System and method for testing an analog-to-digital converter

Abstract

Embodiments of this disclosure relate to systems and methods for testing analog-to-digital converters (ADCs). According to one embodiment, a method for operating an ADC includes: determining a switching point of a comparator of the ADC by applying a first signal having a first slope to the input of the ADC, and monitoring the output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined switching point of the comparator, monitoring the value of an output code of the ADC in response to the second signal, and generating statistics based on the monitored value of the output code, wherein the second signal is a static signal or has a second slope less than the first slope.

Description

Technical Field

[0001] The present invention generally relates to electronic systems, and in particular embodiments to systems and methods for testing analog-to-digital converters (ADCs). Background Technology

[0002] Analog-to-digital converters (ADCs) are used to convert real-world analog signals into the digital domain, applicable to a wide range of systems, from low-frequency systems processing pressure sensor and microphone outputs to high-frequency systems processing received RF signals (such as RF and radar systems). Many such systems rely on high-performance ADCs to meet critical design specifications. A key performance parameter of an ADC is linearity, a measure of how much its transfer function deviates from its ideal transfer function. ADC nonlinearity can be quantified in several different ways, including differential nonlinearity (DNL), integral nonlinearity (INL), and spurious-free dynamic range (SFDR). DNL describes the deviation of a particular code width from the ideal code width of one LSB. When the DNL for a particular code becomes -1 (e.g., the code width becomes zero), code loss occurs. When the DNL for a particular code exceeds 1, the ADC transfer function may become non-monotonic, which can cause problems in systems requiring a monotonic ADC (such as control systems). DNL can also manifest itself as “stuck” output codes. INL describes the deviation of the ADC for a particular code from its ideal output code (assuming an ideal transfer function and gain and offset error corrections), indicating how much the ADC's transfer function deviates from a straight line. Both DNL and INL are represented based on the number of least significant bits (LSBs) that deviate from their ideal value.

[0003] SFDR is a linear metric expressed in the frequency domain and is the amplitude difference between the desired input signal and the maximum spur. SFDR is a useful metric for systems where distortion is a critical parameter, such as in audio systems and RF receivers. In RF communication systems, the presence of spurs reduces the ability of an RF receiver to demodulate signals in the presence of adjacent interfering signals. In radar systems, the presence of spurs can lead to the generation of "false targets" and cause the radar system to indicate the presence of a target or obstacle when it is not actually present. Dynamic range can also be characterized by dBFS, which is the amplitude difference between the full-scale input of an ADC and the maximum spur.

[0004] ADCs contain numerous different error mechanisms that contribute to nonlinearity. For ADCs with pipelined or successive approximation architectures, the mismatch between component values ​​and offset values ​​in the circuitry used to determine the most significant bit of the ADC result is often a major source of nonlinearity. Many techniques can be used to mitigate this nonlinearity, including applying known device matching techniques and error correction through redundancy. Calibration techniques can also be used to improve the linearity of an ADC; however, the linear performance of a calibrated ADC can deteriorate over time as device parameters shift due to voltage, temperature, and other environmental factors. Summary of the Invention

[0005] According to one embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a switching point of a comparator of the ADC by applying a first signal having a first slope to the input of the ADC, and monitoring the output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined switching point of the comparator, monitoring the value of an output code of the ADC in response to the second signal, and generating statistics based on the monitored value of the output code, wherein the second signal is a static signal or has a second slope less than the first slope.

[0006] According to another embodiment, an integrated circuit includes: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator disposed on the integrated circuit and having an output selectively coupled to the input of the ADC, the test signal generator being configured to generate a ramp signal; and a test controller coupled to the output of the at least one comparator and the test signal generator, the test controller being configured to cause the test signal generator to generate a first ramp signal having a first slope, the first ramp signal causing the output state of the at least one comparator to change at a comparator transition point, causing the test signal generator to generate a second ramp signal having a second slope less than the first slope, wherein the second ramp signal alternately increases and decreases between a first upper level and a second lower level, wherein the comparator transition point is between the first upper level and the second lower level, and evaluating the occurrence of independent output codes of the ADC.

[0007] According to another embodiment, an integrated circuit includes: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator having an output coupled to an input of the ADC; and a test controller having a first input coupled to an output of the test signal generator, a first input coupled to the output of the comparator of the ADC, and a second input configured to receive an output code of the ADC, wherein the test controller is configured to determine a switching point of the comparator by causing the test signal generator to apply a first signal having a first slope to the input of the ADC and monitoring the output state of the comparator in response to the first signal, and to cause the test signal generator to apply a second signal having a signal level based on the determined switching point of the comparator, and to compare an accumulation or average of code values ​​generated by a first decision of the comparator with an accumulation or average of code values ​​generated by a second decision of the comparator, wherein the second signal is a static signal or has a second slope less than the first slope. Attached Figure Description

[0008] To gain a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0009] Figure 1A An exemplary ADC system is shown, and Figure 1B An exemplary ADC transfer curve is shown;

[0010] Figure 2A An ADC according to one embodiment is shown, and Figure 2B A schematic diagram of a ramp generator according to one embodiment is shown;

[0011] Figure 3A , Figure 3B and Figure 3C A waveform diagram showing an example voltage profile generated by the ramp generator of the embodiment is shown;

[0012] Figure 4A An ADC according to yet another embodiment is shown, and Figure 4B A waveform diagram is shown, which illustrates the relationship between... Figure 4A The operation of the test system associated with the ADC is shown;

[0013] Figure 5A An ADC output code histogram according to one embodiment is shown, and Figure 5B and Figure 5C A schematic diagram illustrating the implementation of test logic according to an embodiment is shown;

[0014] Figure 6A A pipelined ADC according to one embodiment is shown, and Figure 6B A successive approximation ADC according to one embodiment is shown;

[0015] Figure 7A An RF receiver utilizing an ADC linearity test system according to one embodiment is shown; and Figure 7B A diagram illustrating how linear testing and calibration are scheduled within a radar frame according to one embodiment is shown;

[0016] Figure 8 A block diagram of a method according to one embodiment is shown; and

[0017] Figure 9 A block diagram of a processing system that can be used to implement a partial embodiment of the linear test system is shown.

[0018] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of preferred embodiments and are not necessarily drawn to scale. To illustrate a particular embodiment more clearly, letters indicating variations of the same structure, material, or process step may follow the figure numbers. Detailed Implementation

[0019] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific methods of manufacturing and using the invention and do not limit the scope of the invention.

[0020] The invention will be described with reference to preferred embodiments in the specific context of on-chip calibration systems for pipelined ADCs or successive approximation (SAR) ADCs. However, the invention can be used to provide calibration testing and linearity verification for other types of systems utilizing data converters, and can be used to test data converters of various architectures.

[0021] According to one embodiment of the invention, a method for testing the linearity of an ADC includes applying a test signal with a high slope (e.g., a voltage variation ΔV over a time interval Δt) until the state of the ADC's internal comparator changes. This internal comparator may be associated with a decision threshold within the ADC that directly affects the ADC's linearity. Once the decision threshold is determined, the slope of the test signal decreases (or becomes zero) such that the ADC's input voltage is within an input range representing a finite number of ADC output codes. In some embodiments, a ramp signal that alternately increases and decreases the voltage is applied to the ADC input such that the ADC's input voltage remains close to the transition point of the internal comparator. The ADC output codes and / or the comparator's output state are monitored, and a linearity metric is determined based on the output codes and / or the monitored comparator states. In some embodiments, a histogram of the ADC output codes is obtained relative to the monitored output states of the comparator to obtain the linearity metric. In some embodiments, the linearity metric is the difference between the average ADC output codes when the comparator is in a first state (e.g., high) and a second state (e.g., low).

[0022] Advantageously, by applying an initial fast ramp to the ADC input, the transition point of the internal comparator can be quickly found. By analyzing the ADC's output code within a limited input range, a linearity metric can be obtained using a very small amount of circuitry. Another advantage of the embodiment includes the ability to generate test signals using a very simple ramp generator without the need for a precise digital-to-analog converter. Yet another advantage includes the ability to quickly test and evaluate the linearity of an ADC utilizing redundancy error correction.

[0023] In various embodiments, the test circuitry may be used in combination with calibration circuitry, such as foreground calibration circuitry. In these embodiments, a linearity test of the ADC may be performed periodically to ensure that the ADC's linearity is within a specified range. When the measured linearity deviates from the predetermined range, the ADC may be recalibrated.

[0024] Figure 1A A block diagram of an exemplary ADC system 100 is shown, which includes an ADC 102 that interacts with a calibration circuit 110. The ADC 102 is configured to convert a signal Vin present at its input into a digital signal code. The calibration circuit 110 calibrates the ADC 102 by determining a code correction factor applied to the output of the ADC 102 via a multiplexer 112 and an adder 116 to provide a corrected code.

[0025] As shown in the figure, ADC 102 includes internal circuitry devices 104 and 106 and a comparator 108. Internal circuitry devices 104 and 106 represent various circuitry devices that can be found in an ADC, and comparator 108 represents a comparator or other circuitry configured to apply a decision threshold to the analog input signal Vin or any analog signal within ADC 102. The operation of ADC 102 is divided into two phases: a calibration phase and an operation phase. During the calibration phase, calibration circuitry 110 applies a known analog signal to ADC 102 or its internal nodes while monitoring the operation of ADC 102 to identify instances where the actual output code of ADC 102 deviates from the ideal output code, and to determine correction values ​​to improve the linearity and accuracy of ADC 102.

[0026] Figure 1B The graph shows the relationship between the output code of ADC 102 and the input voltage Vin. Curve 120 represents the uncorrected ADC output code relative to the input voltage, while curve 124 represents the corrected ADC output code relative to the input voltage. It is evident from the graph that curve 120 exhibits a discontinuity or "jump" at the input voltage Vth (which represents the threshold voltage of comparator 108). This discontinuity can be caused by mismatched circuit components within the internal circuitry units 104 and 106 of ADC 102 and / or by a deviation from the ideal threshold voltage Vth of the comparator. For example, in ADC architectures that utilize one or more DACs to continuously estimate the input voltage (such as SAR ADCs or pipelined ADCs), mismatch in the circuitry used to determine the output voltage or output current of the DAC can lead to nonlinearity or "jumps" in the relationship between the input signal and the output code, similar to... Figure 1B Curve 120 in the diagram. By providing a correction factor summed with the uncorrected ADC output, calibration circuit 110 effectively shifts a portion of curve 120 upwards to curve 124 to reduce or eliminate "jumps" or nonlinearities in the ADC transfer function. It should be understood that, although for clarity in Figure 1B Only one jump or nonlinearity is shown, but the transfer function of the ADC 102 can have multiple jumps or nonlinearities. Such nonlinearities can lead to increases in DNL and INL, and can decrease the SFDR of a particular converter. In many cases, these nonlinearities correspond to the ADC's main code transitions, such as those associated with state changes of the most significant bit or the next most significant bit of the ADC output code.

[0027] While calibration circuit 110 improves the linearity of ADC 102, some residual nonlinearity remains after calibration. Furthermore, the quality of calibration can fluctuate due to statistical variations occurring during the calibration phase, or can be offset by changes in supply voltage, temperature, and environmental conditions. Therefore, some calibration cycles may or may not produce calibrations that result in ADC performance meeting predetermined performance requirements. For example, some calibrations may produce residual nonlinearity or jumps that are sufficiently small and / or distributed to allow for meeting linearity requirements applicable to a particular application (such as SFDR), while others may produce excessively large and / or distributed residual nonlinearity or jumps that lead to inadequate ADC performance. In some cases, the quality of calibration may drift during use after the ADC has been manufactured and calibrated.

[0028] In various embodiments of the invention, the linearity of the ADC can be rapidly measured and evaluated after manufacturing. In some embodiments, linearity testing is performed by dedicated test circuitry residing within the ADC system. In some cases, the dedicated test circuitry is located on the same chip or monolithic semiconductor substrate as the ADC. Figure 2A An example of such a system is shown in the figure. Figure 2A An ADC system 200 is shown, comprising an ADC 102 coupled to test logic 202, a ramp generator 204, and a multiplexer 206. During normal operation, the input signal Vin is coupled to the input of the ADC 102 via the multiplexer 206. In some embodiments, as described above... Figure 1A The discussed method uses calibration circuit 110 to correct the output code of 102. Calibration can be achieved using one of many calibration circuits and systems known in the art. For example, a foreground calibration circuit can be used to measure the relative weight of each bit or the relative weight of various components within the ADC, as they relate to the raw output of the ADC. Once these relative weights are determined, the output code is adjusted according to the determined weights. An example of a foreground calibration circuit is described in U.S. Patent No. 4,970,514. Alternatively, other calibration methods can be applied to the embodiments described herein. For example, the embodiment methods can be used to test and verify ADCs that have been trimmed or background-calibrated. The linearity of uncorrected and / or uncalibrated ADCs can also be evaluated according to the embodiment systems and methods.

[0029] During the linear test, test logic 202 asserts the ENABLE signal to activate the ramp generator and couples the output RVin of ramp generator 204 to the input of ADC 102 via a multiplexer. Ramp generator 204 is configured to provide a ramp signal comprising at least one ramp in one direction. Using control signals SLOPE (slope) and DIRECTION (direction), test logic 202 configures the ramp generator to increase the signal level at the input of ADC 102 with a first linear slope until the output CMP of comparator 108 changes state, thereby setting the output of ramp generator 204 to a signal level close to the input level corresponding to the threshold of comparator 108. Next, the test logic causes ramp generator 204 to provide a test signal with a smaller second linear slope, having a reduced input range varying near the input level corresponding to the threshold of comparator 108. For example, when the signal SLOPE is in a first state (e.g., logic "1"), the ramp generator produces a faster first linear slope, while when the signal SLOPE is in a second state (e.g., logic "0"), the ramp generator produces a slower second linear slope. When the signal DIRECTION is in a first state (e.g., logic "1"), the ramp generator produces a ramp with a linearly increasing signal level, while when the signal DIRECTION is in a second state (e.g., logic "0"), the ramp generator produces a ramp with a linearly decreasing signal level. It should be understood that, in alternative embodiments of the invention, other types of test signal generators besides the ramp generator 204 that generates a linear ramp signal may be used to test the linearity of the ADC 102. For example, a test generator that generates more than two ramp rates and / or generates a non-strictly linear ramp may be used.

[0030] During testing, test logic 202 monitors the code output of ADC 102 to evaluate the linearity of ADC 102 within a small code range associated with the input level corresponding to a threshold of comparator 108. In some examples, test logic 202 also monitors the output CMP of comparator 108. In some embodiments, this linearity is evaluated by compiling the output codes of ADC 102 and / or a local histogram of the output code values ​​relative to a measurement state of the comparator output signal CMP. The parameters of the compiled histogram or classification codes are compared with stored parameters, and the linearity of the ADC is determined based on this comparison. In some embodiments, a first set of ADC output codes associated with a first measurement state of the comparator output signal CMP is accumulated or averaged, and a second set of ADC output codes corresponding to a second measurement state of the comparator output signal CMP is measured or averaged. The difference between the two accumulated values ​​or averages is compared with a predetermined range or a predetermined threshold to determine an ADC performance metric. If the determined ADC performance metric is within the predetermined range or the predetermined threshold, the linearity of the ADC is considered to be within acceptable limits. If the determined ADC performance metric is outside the predetermined range above the threshold, corrective actions, such as performing calibration, can be taken to improve the linearity of the ADC. In various embodiments, linearity tests are performed periodically, for example, at predetermined time intervals and / or after predetermined temperature changes, to verify the performance of the ADC 102.

[0031] In some embodiments, a linearity test is performed after foreground calibration to verify the effectiveness of the calibration. Foreground calibration or linearity testing can be performed or scheduled when the ADC has no signal load and would otherwise be idle. In some embodiments, linearity testing can be run periodically to provide continuous verification of the performance of the ADC 102. When a linearity test indicates that the ADC 102 is out of calibration range (e.g., if the ADC performance metric determined by the linearity test is not within a predetermined range or a predetermined threshold), the ADC 102 can be recalibrated, followed by further linearity testing. If the further linearity test indicates that the ADC performance metric is within the predetermined range or threshold, ADC operation continues with a new calibration. On the other hand, if the further linearity test indicates that the ADC performance metric for the new calibration is not within the predetermined range or threshold, and / or indicates that the ADC performance metric associated with the new calibration is worse than the ADC performance metric associated with the previous calibration, the calibration state of the ADC 102 can be restored to its previous calibration state. The above sequence can be repeated multiple times to calibrate the ADC 102.

[0032] In some embodiments, calibration circuit 110 generates calibration data associated with its calibration status. This calibration data may represent relevant calibration values. For example, the calibration data may represent bit weights applied to comparator 108 and other internal comparison circuitry, component trimming settings, or any other calibration variables. If a second calibration attempt is deemed inferior to the first calibration (linearity test results do not meet predetermined criteria), the data associated with the first calibration may be reloaded into the calibration register of ADC 102 and / or calibration circuit 110.

[0033] Figure 2B It shows what can be used for implementation Figure 2A The schematic diagram shows an embodiment of the ramp generator 204. As shown, the ramp generator 204 includes a high-voltage side current source 236, a low-voltage side current source 238, a capacitor 240, a buffer amplifier 242, an optional single-ended to differential converter 244, and inverters 232 and 234.

[0034] During operation, an increasing ramp is generated by charging capacitor 240 with current IH generated by high-side current source 236, and a decreasing ramp is generated by discharging capacitor 240 with current IL generated by low-side current source 238. The slope of the ramp is determined by the amplitude of the currents generated by current sources 238 and 240, such that a higher ramp corresponds to a higher current, and a lower ramp corresponds to a lower current. The voltage across capacitor 240 is buffered by buffer amplifier 242. In an embodiment where ADC 102 has a differential input stage, an optional single-ended to differential converter 244 can be used to convert the single-ended ramp signal at node VR to fully differential signals at nodes VRP and VRN. As shown, the amplitude of each current source can be controlled by signals DIRECTION, ENABLE, and SLOPE generated by test logic 202. In one embodiment, currents IH and IL are set as follows:

[0035] IH = DIRECTION * ENABLE(I SMALL *SLOPE_B+I LARGE *SLOPE)

[0036] IL = DIRECTION_B * ENABLE(I SMALL *SLOPE_B+I LARGE *SLOPE) where DIRECTION_B is the logical inverse of the signal DIRECTION generated by inverter 232, and SLOPE_B is the logical inverse of the signal SLOPE generated by inverter 234. LARGE It is the current corresponding to the faster first slope, and I SMALLIt is the magnitude of the current corresponding to the slower second slope.

[0037] In various embodiments, current sources 236 and 238 may be implemented, for example, using current mirror circuits known in the art; buffer amplifier 242 may be implemented, for example, using source followers; and single-ended to differential converter 244 (amplifier) ​​may be implemented, for example, using single-ended to differential amplifier circuits known in the art. It should be understood that... Figure 2B The circuit shown is just one example of many possible ways to implement the ramp generator in this embodiment. In alternative embodiments of the invention, different circuit arrangements may be used to implement the same or similar functionality.

[0038] Figures 3A-3C A waveform diagram is shown, illustrating an example voltage profile generated by ramp generator 204 during a linear test of the embodiment. Figure 3AA first voltage profile is shown, where trace 302 represents the output voltage of ramp generator 204 and the input voltage of the ADC under test. From time t0 to time t1, the output voltage of ramp generator 204 increases with a first slope. During this time period, it exceeds the threshold 301 of comparator 108 (also called the jump point). For ease of illustration, this threshold is represented by a dashed line 301, as it corresponds to the output voltage of ramp generator 204. However, it should be understood that both the input voltage of ADC 102 and the comparator threshold can be attenuated or amplified by the internal circuitry 104 as the input signal propagates through the circuitry of ADC 102. At time t1, the trajectory of trace 302 changes direction from increasing to decreasing, and the slope of trace 302 decreases to a second slope with an absolute value less than the first slope. The value of trace 302 continues to decrease until time t2, at which point the trajectory of trace 302 reverses direction and increases with the second slope. At times t3, t4, t5, and t6, trace 302 alternately changes direction between decreasing and increasing signal levels with a second slope. Therefore, the second ramp signal represented by trace 302 alternates between increasing and decreasing between a first high level and a second low level. In some embodiments, while maintaining the same manner as the resulting code distribution, the slopes of the increasing and decreasing ramps of the second ramp signal may have different values ​​lower than the first slope. For example, two different slopes, low1 and low2, can be used to achieve the same amplitude (e.g., a first high level and the same low level). These multiple slopes can be applied sequentially using various combinations. In a specific example, decreasing ramps can alternate slopes (e.g., six decreasing ramps using slope low1, followed by six decreasing ramps using slope low2), and increasing ramps can alternate slopes (e.g., six decreasing ramps using slope low1, followed by six decreasing ramps using slope low2). In some embodiments, the second slope may also vary over time. In various embodiments, test logic 202, in conjunction with ramp generator 204, controls the direction of trace 302 by monitoring the output of comparator 108 and / or the output code of ADC 102, and changing the direction of the ramp generated by ramp generator 204 when the output of comparator 108 changes state and / or after the output of ADC 102 exceeds a threshold. In some embodiments, hysteresis is applied while monitoring the output of ADC 102. For example, the direction of the ramp may change from increasing to decreasing when the output of ADC 102 exceeds a first threshold corresponding to a positive threshold offset of comparator 108, and from decreasing to increasing when the output of ADC 102 exceeds a second threshold corresponding to a negative threshold offset of comparator 108. In some embodiments, a hysteresis of approximately 20 to 40 LSBs is applied, although more or less hysteresis may be applied in alternative embodiments.

[0039] Starting at time t1, the output code of ADC 102 is monitored and analyzed by test logic 202 to determine if the linearity of ADC 102 is near the threshold of comparator 108. For example, linearity can be determined by constructing a histogram of the monitored code and analyzing the code density of the output code when a second slope is applied to ADC 102. In some embodiments, the peak region of 302 may deviate from the specified range due to limited bandwidth and other non-ideals. Figure 3A The ideal triangular trajectory is shown. These deviations from the ideal triangular shape affect the observed code density of the code corresponding to these peak regions. Therefore, in some embodiments, when determining the linearity of ADC 102, the output values ​​of ADC 102 corresponding to the regions of maximum and minimum offset or the upper or lower signal levels of trace 302 are omitted or discarded, thus retaining only the code that is not affected by these "edge effects" that occur when the slope of the waveform generated by ramp generator 204 changes direction.

[0040] Figure 3B The second voltage profile is shown, where trace 304 represents the output voltage of ramp generator 204 and the input voltage of the ADC under test. The generation of the second voltage profile is similar to that described above. Figure 3A The generation of the first voltage profile discussed, except that the voltage offset near the comparator switching point is less than the variation of 20 to 40 LSB described above, is achieved, for example, by reducing the magnitude of the second slope and / or by reducing the variation with the generated... Figure 3A The hysteresis used when changing the polarity of the slope, as shown, allows for such a small voltage shift change.

[0041] In some embodiments, the interpeak variation of the trace 304 with respect to the comparator transition point is several LSBs. In these embodiments, test logic 202 may be configured to evaluate the linearity of the ADC 102 in the threshold region of the comparator 108 by comparing the average of the output codes of the ADC 102 calculated when the comparator 108 is in a first state (e.g., the output of the comparator 108 is "1") with the average of the output codes of the ADC 102 when the comparator 108 is in a second state (e.g., the output of the comparator 108 is "1"). In other embodiments, the code used for averaging is recorded only when the output of the comparator 108 transitions from the first state to the second state (e.g., from "1" to "0" or from "0" to "1"). Recording and evaluating the output ADC code in this manner ensures that the evaluated ADC code closely corresponds to the threshold of the comparator 108 and reduces or eliminates the effects associated with moving input signals.

[0042] In some embodiments, the output of the ramp generator 204 remains constant after the first slope is applied, such as Figure 3CThe figure shows trace 306. As shown, the first slope is applied starting at time t0 until the comparator jump point is reached at time t1, at which point the output of ramp generator 204 is frozen at the jump point of comparator 108. For example, this can be achieved by turning off... Figure 2B The current sources 236 and 238 shown prevent capacitor 240 from being charged or discharged to perform the freezing of the output of ramp generator 204. Alternatively, a DAC (not shown) can be used to generate a static input signal. In other embodiments, the input signal level can be set in a closed-loop manner by monitoring the output code of ADC 102 and modifying the input signal via ramp generator 204, DAC (not shown), or other signal generator until the input voltage corresponds to the desired ADC output code value.

[0043] Can be with Figure 3B The linearity of ADC 102 is evaluated in a similar manner to that of other embodiments, for example by comparing the average value of the ADC output associated with a particular state and / or state transition of comparator 108.

[0044] In some embodiments, the decision of comparator 108 can be biased by the input noise present in the input signal of ADC 102. Typically, assuming the noise, static, and input signal are nominally exactly at the comparator's transition point, 50% of comparator decisions are low and 50% are high. However, when a high comparator decision is caused by a voltage that temporarily increases the noise and a low comparator decision is caused by a voltage that temporarily decreases the noise, the average ADC output code caused by a high decision will be higher than the average ADC output code caused by a low decision. For example, a 600 μV Gaussian input noise signal can cause comparator 108 to have a bias of approximately 1 mV. Therefore, Figure 3C The implementation of the ramp trajectory (e.g., the output of the frozen ramp generator 204) is applicable to implementations where the decision of comparator 108 is not easily influenced by input noise bias. On the other hand, Figure 3A and Figure 3B The ramp trajectory of the embodiment may be more suitable for the embodiment ADC, where the decision of comparator 108 is more easily biased by input noise because the ramp signal enables the comparator decision to decorrelate with the input noise. For example, decorrelation can also be affected by designing comparator 108 to have a sufficiently high input reference noise.

[0045] In some embodiments, the relationship between the comparator decision bias and the input noise can be further decorrelated by forcing the comparator output decision according to the pattern, as per [reference to...]. Figure 4A and Figure 4B As shown in the embodiments. Figure 4A The illustrated ADC system 400 includes an ADC 402 coupled to test logic 404, a ramp generator 204, and a multiplexer 206, which, together with... Figure 2A The illustrated ADC system 200 is similar, except that the output of comparator 108 is modified to have a specific pattern. In the illustrated embodiment, multiplexer 406 is coupled between the output of comparator 108 and the input of internal circuitry 106. During normal operation of ADC 402, the output of comparator 108 is coupled to the input of internal circuitry 106. However, during testing, the output M of test logic 404 is applied to the input of internal circuitry 106. In some embodiments, signal M may include a predetermined pattern in which the number of high logic levels is substantially equal to the number of low logic levels. For example, the predetermined pattern may be a periodic pattern that changes state after every N samples, where N => 1. For example, the pattern may change state after each sample (e.g., 10101010…) or after several samples (e.g., 1111000011110000…). In alternative embodiments, other patterns may be used, including random patterns, pseudo-random patterns, and other deterministic patterns. In some embodiments, the above regarding… Figure 3C The described embodiment of the ramp trajectory (e.g., the output of the frozen ramp generator 204) can be used when the comparator output decision is forced according to the pattern, since the applied pattern is used to decorrelate the relationship between the comparator decision bias and the input noise.

[0046] Figure 4B A waveform diagram is shown illustrating the operation of the ADC system during a linear test relative to the output RVin of ramp generator 204, the ramp generator control signals ENABLE, SLOPE, and DIRECTION, the output CMP of comparator 108, the test multiplexer selection signal SEL, and the test input M. At time t1, the ramp generator 204 is enabled to output a positive ramp with a fast slope by asserting the ENABLE control signal, setting the DIRECTION control signal to configure ramp generator 204 to have a positive output ramp, and setting the SLOPE control signal to configure ramp generator 204 to have a fast ramp. At time t2, the output CMP of comparator 108 changes state due to the increase in the input voltage of ADC 402. In response, the SLOPE control signal changes low, which reduces the output ramp of ramp generator 204, and the DIRECTION control signal changes low, which changes the direction of the ramp output signal of ramp generator 204 from increasing ramp to decreasing ramp. Furthermore, the assertion test multiplexer selection signal SEL routes the test signal M to the input of the internal circuitry device 106 and applies a mode to the test signal M. In the illustrated embodiment, an alternating 1-0 mode is shown for the test signal M; however, it should be understood that alternative modes may also be used.

[0047] At time t3, due to the decrease in the input voltage of ADC 402, the output CMP of comparator 108 transitions from a high state to a low state. In response, test logic 404 causes the control signal DIRECTION to transition to a high state at time t4, so that the signal RVin approaches the threshold of comparator 108. In the illustrated embodiment, a "relay-style (bang-bang)" or hysteresis control scheme is used to control the output signal RVin of ramp generator 204 in a closed-loop manner. Hysteresis can be applied by monitoring the output code of ADC 402, and / or by configuring comparator 402 to have hysteresis applied. In other words, test logic 404 controls voltage RVin by decreasing voltage RVin in response to comparator 108 indicating that voltage RVin has exceeded a threshold, and by increasing voltage RVin in response to comparator 108 indicating that voltage RVin has decreased below a threshold.

[0048] It should be understood that Figure 4B A portion of a test for a single comparator threshold is shown. In any of the embodiments disclosed herein, multiple thresholds can be tested by: ramping the signal RVin to a first threshold voltage using a fast ramp, performing a linear test at the first threshold voltage using a slow ramp, then ramping the signal RVin to subsequent threshold voltages, and performing a linear test at each subsequent threshold voltage using a slow ramp.

[0049] Figures 5A-5C A method for analyzing ADC data collected during a linearity test according to an embodiment of the present invention is illustrated. This analysis can be used to indicate the presence of nonlinearity in the ADC's transfer characteristics associated with a comparator jump point, or the level of nonlinearity in the ADC's transfer characteristics associated with a comparator jump point. In some embodiments, code density or statistics associated with a specific output code of the ADC are analyzed to determine the linearity of the ADC near the comparator jump point. Various mathematical and statistical methods can be used to analyze code density. Code density analysis is typically applied to embodiments where the slow-ramp portion of the test cycle traverses an input range corresponding to approximately 20 to approximately 40 ADC output codes, such as... Figure 3AThe illustrated embodiment. However, embodiments with input ranges of higher and lower numbers of ADC output codes can also utilize code density analysis depending on the specific system and its specifications. A large number of samples are collected during the slow ramp portion of the test. The actual number of samples collected can depend on the desired test resolution and the number of output codes through which the signal RVin passes. For example, more samples can be collected in systems with a larger accuracy requirement test range compared to systems with less stringent accuracy requirements. In one specific embodiment, approximately 640 samples are collected for an output code range of 10 codes, achieving approximately 64 samples per code. Of course, more or fewer samples can be collected depending on the specific embodiment and its specifications.

[0050] In some embodiments, test logic 202 or 404 forms a histogram describing the relative frequency of each output code. Figure 5A An example of this is shown, illustrating a histogram of output code counts relative to the output codes. For instance, such a histogram can be formed by recording the received ADC output codes into a first set of register or memory locations and incrementing the count value in a second set of registers or memory locations associated with the first set. Essentially, test logics 202 and 404 are configured to count the number of "hits" for each output code during the time a test signal with a low slope is applied to the ADC.

[0051] Once the histogram is compiled, test logic 202 or 404 can compare the code distribution represented by the histogram with the expected code distribution (e.g., a uniform code distribution). The deviation from the expected code distribution indicates a code "skip" in the ADC. If the measured code distribution differs from the expected distribution by a predetermined amount, test logic 202 or 404 can provide an indication that the ADC is not calibrated. This indication can be used as a trigger to start a new calibration cycle. The histogram can be evaluated and / or quantized in several different ways by test logic 202 or 404.

[0052] In some embodiments, the shape of the histogram can also be used to determine whether the ADC is calibrated. This determination is achieved by analyzing the histogram to derive an ADC performance metric, and then comparing the derived performance metric to an expected value, a range of expected values, or a threshold. For example, in embodiments where a uniform distribution of ADC output codes is expected (such as in the case of a linear ramp input), the difference (or squared difference) between the sizes of each histogram bin (e.g., the number of counted "clicks") can be compared to the expected size of each histogram bin, and this difference can be compared to a predetermined threshold. Figure 5AIn the example, the expected number of clicks is represented by a dashed line 550 representing the baseline value, which can be determined by calculating the average count of the recorded ADC output codes, or it can be a predetermined value. For example, in many cases, the baseline value 550 is not known prior and is calculated based on a histogram. For example, if 1000 clicks are distributed across 10 units (after eliminating outer units 556 and 558), the baseline value 500 would be 100. As shown, some output codes have counts exceeding the baseline value 550, while others have counts below it. In one embodiment, the maximum peak deviation 552 between the count of a particular output code and the baseline value can be determined by test logic 202 or 404 and a value compared to a predetermined threshold. In another embodiment, a maximum inter-peak deviation 554 can be determined and compared to a predetermined threshold. This inter-peak deviation 554 can be evaluated for adjacent codes and / or for all codes. The evaluation of the inter-peak deviation for adjacent codes provides an indication of the DNL. In some cases, this maximum inter-peak deviation may occur at the major code transition of the ADC.

[0053] In other embodiments, an error metric that takes into account the deviation of the output codes across all records may also be used. For example, the peak or interpeak deviation of each histogram cell may be calculated and summed to provide an error metric. In some cases, the square or other function may be applied to each individual deviation to obtain a mean square error, root mean square error, or other metric.

[0054] In some embodiments, one or more ADC output code or histogram entries of minimum 556 and maximum 558 records may be omitted from the code density analysis so that only the code that is not affected by these “edge effects” that occur when the slope of the waveform generated by the ramp generator 204 changes direction is retained.

[0055] In various embodiments, ADC performance metrics determined based on code density analysis are compared to thresholds to provide an indication of whether the ADC has been adequately calibrated. In such embodiments, comparators (such as...) can be used. Figure 5B The digital comparator 502 shown compares the error metric with a threshold.

[0056] In some embodiments, the linearity of the ADC can be determined by performing a code comparison of the ADC's output code within a region of the comparator threshold. For example, this can be achieved by comparing the code generated by the ADC when the output of comparator 108 is in a first state with the code generated by the ADC when the output of comparator 108 is in a second state. Code comparison analysis is typically applied to embodiments where the slow-ramp portion of the test loop traverses a small input range (such as those mentioned above). Figure 3B The embodiments described above), or embodiments where the input signal is static during linear analysis (such as those described above). Figure 3C (As described in the embodiments). During the time that the corresponding test signal portion (slow ramp / static signal) is applied to the input of the ADC, a count of the codes used for comparison is provided. Instead of code density analysis according to a specific system and its specifications, or in addition to code density analysis, code comparison analysis can also be applied. Figure 3A This particular embodiment is well-suited for ADCs with error correction or redundancy architectures (also known as “redundant ADCs”), such as error-correcting pipelined ADCs or redundant SAR ADCs, where input signals near the transition points of comparator 108 are mapped to the same output code, regardless of the output of comparator 108.

[0057] In one embodiment, as shown in the computing unit 530 Figure 5C As shown, the collected ADC output codes can be averaged or accumulated based on the output CMP of comparator 108. Calculation unit 530 includes: an averaging circuit 532 configured to average the output codes when the output of comparator 108 is in a first state (e.g., CMP = 1); and an averaging circuit 534 configured to accumulate the output codes when the output of comparator 108 is in a second state (e.g., CMP = 0). At the end of a test cycle for a specific threshold, the difference ΔAVG between the outputs of averaging circuit 532 and averaging circuit 534 is calculated by subtractor 536. Window comparator 538 determines whether the difference ΔAVG falls between thresholds PTHRESH and NTHRESH. If the difference ΔAVG is not within the window, an assertion signal RECALIBRATE indicates that the ADC is not calibrated.

[0058] In one embodiment, averaging circuits 532 and 534 are implemented using an accumulator 540 and a subsequent divider 542. The accumulator 540 is configured to accumulate the ADC output code when the output of comparator 108 is in its respective predetermined state, and the divider 542 is configured to divide the output of accumulator 540 by the number of accumulated samples to form an average. In some cases, the divider 542 can be omitted, and linear evaluation can be based on the difference between the outputs of the accumulators. In such embodiments, the number of counts performed for each comparator state can be fixed. Furthermore, thresholds PTHRESH and NTHRESH can be scaled according to the number of counts performed for each comparator. In embodiments where the count value is a power of 2, a shifter can be used to implement the divider 542 to right- or left-shift the output of accumulator 540 according to the divisor. The accumulator 540, divider 542, subtractor 536, and window comparator can be implemented using digital logic circuits known in the art.

[0059] Although Figure 5CThe embodiments are designed to evaluate the ADC output code based on the comparator output state (e.g., CMP = 1 or CMP = 0), but it should be understood that histograms and accumulated values ​​regarding comparator output modes (e.g., CMP 1→0 or 0→1 output transitions) can also be collected. It should also be understood that... Figures 5A-5C The embodiments illustrate some specific examples of how the output code of a processable ADC can be determined to determine the linearity of the ADC according to embodiments of the present invention.

[0060] Figure 6A and Figure 6B Two example ADC systems configured to utilize a linear test system and method according to embodiments of the present invention are shown. Figure 6A For pipelined ADC systems, and Figure 6B For successive approximation ADC systems. Figure 6A The illustrated pipelined ADC system 600 includes a total of k pipeline stages 602, 604, and 608. The first pipeline stage includes an ADC 620, a DAC 622, and a subtractor 624. During operation, the first pipeline stage 602 converts the input voltage Vin into a digital value MSB representing one or more most significant bits of the conversion. The DAC 622 converts the converted value back to the analog domain, and the subtractor 624 subtracts the DAC output from the analog input to form a residual signal. This residual signal is passed to the next pipeline stage 604, which amplifies the residual signal in a manner similar to pipeline stage 602 to form further digital outputs and further residual signals. In some embodiments, such as using a multiplicative DAC (MDAC), residual amplification is performed before passing the residual to the next stage. Each corresponding residual is processed in a similar manner through each of the first k-1 stages to form multiple digital outputs and a final residual, which is digitized by the k-th stage to produce a digital value LSB representing one or more least significant bits of the conversion. In various embodiments, one or more pipeline stages may have a redundant bit range to facilitate pipelined ADC error correction methods known in the art. In the illustrated embodiment, the ADC 620 of the first pipeline stage 602 uses two comparators 632 and 634 (instead of a single comparator) to perform a 1.5-bit conversion, which provides an additional 0.5 bits of redundancy on top of the single bit.

[0061] Data alignment and error correction circuitry 610 receives the results of each partial conversion from each pipeline stage 602, 604, and 608 and forms the ADC output code OUT passed over these partial conversions. Data alignment and error correction circuitry 610 may be implemented using data alignment and error correction techniques known in the art. For example, in some embodiments, data alignment and error correction circuitry 610 may form a weighted average of each partial conversion to form the final output value. In some embodiments, calibration logic 614 performs foreground calibration of the ADC system 600 using foreground calibration techniques known in the art. In some embodiments, calibration logic 614 performs digital foreground calibration, which adjusts the weights applied to the partial conversions at each stage. In alternative embodiments, calibration logic 614 may facilitate analog foreground calibration, wherein the gain and / or threshold levels of one or more pipeline stages 602, 604, and / or 608 are adjusted.

[0062] In various embodiments, test logic 612 and ramp generator 204 are based on the above regarding... Figure 2A-2B , Figures 3A-3C , Figures 4A-4B and Figures 5A-5C The described embodiment method performs a linearity test on the ADC system 600. In some embodiments, the test logic 612 may be related to... Figure 2A The test logic 202 shown is implemented and functions in a similar manner. For example, test logic 612 can monitor the outputs of one or more comparators located within one or more pipeline stages 602, 604, and 608 of the ADC. Although Figure 6A The illustrated embodiment shows test logic 612 monitoring the output of a single comparator 634 located within the ADC 620 of the first pipeline stage 602. However, it should be understood that test logic 612 can also be configured to monitor comparator 632 and / or can be configured to monitor comparators in other stages. In a configuration where the ADC 620 has more than two comparators, test logic 612 can also be configured to monitor additional comparators. In such an embodiment, test logic 612 can serially perform multiple linear tests corresponding to the input voltage level of each individual comparator. Between each linear test, test logic 612 can cause ramp generator 204 to increase the ramp signal RVin to the next input signal level (corresponding to the next comparator being tested) using the fast ramp rate described above, thereby reducing the total test time for all input signal levels corresponding to all tested comparator threshold levels.

[0063] In some embodiments, test logic 612 can be connected with... Figure 4AThe test logic 404 shown is implemented in a similar manner, wherein the test signal M is replaced by the output of the monitored comparator. These embodiments may utilize a multiplexer 406, coupled to the output of comparator 634 and the test outputs M and SEL generated by test logic 612, as described above. Figure 4A and Figure 4B The embodiments described herein. The multiplexer 406 and the signals M and S generated by the test logic 612 are shown in dashed lines to indicate that this is an optional feature.

[0064] Figure 6B The illustrated successive approximation register (SAR) ADC system 650 is configured to perform successive approximation of an input voltage Vin. During operation, the input voltage Vin is sampled via a sample-and-hold circuit 662. In multiple successive approximation cycles, the successive approximation register 654 provides a digital input to the DAC 652 and compares the output of the DAC 652 with the sampled input voltage generated by the sample-and-hold circuit 662. At the end of each successive approximation cycle, the contents of the successive approximation register 654 are updated based on the output of the comparator 660. The DAC 652 can be implemented using various DAC architectures known in the art. In one example, the DAC 652 can be implemented using a charge redistribution switched capacitor array, which also incorporates the functionality of the sample-and-hold circuit 662. In such an embodiment, as is known in the art, the input voltage Vin can be sampled on the bottom plate of the capacitor array, while the DAC function is implemented by redistributing charge on the top plate of the capacitors in the capacitor array.

[0065] In one example embodiment, the successive approximation is initialized with a word where the MSB is set high and the remaining bits are set low (e.g., 100…00) to produce a half-scale output. If the DAC voltage is greater than the sampled input voltage, comparator 660 produces a "0" output, and the successive approximation register is updated such that the MSB is set low, the next most significant bit is set high, and the remaining bits are set low (e.g., 010…00), thus producing a quarter-scale output. Conversely, if the DAC voltage is less than the sampled input voltage, comparator 660 produces a "1" output, and the successive approximation register is updated such that the MSB is set high, the next most significant bit is set high, and the remaining bits are set low (e.g., 110…00), thus producing a three-quarter-scale output. Subsequent successive approximation loops are executed in a similar manner until every bit has been tested, and the resulting contents of the successive approximation register represent the digitized value of the sampled input.

[0066] In some embodiments, DAC 652 may be a redundant DAC with a sub-binary base. In such embodiments, errors arising from comparator offset and / or capacitor mismatch in earlier successive approximation cycles can be corrected using redundant SAR ADC techniques known in the art during later approximation cycles. In such embodiments, code mapping circuitry 656 may be used to convert the non-binary output of successive approximation register 654 into a binary word, for example, by performing a weighted summation of each bit of successive approximation register 654. In some embodiments, calibration logic 658 may be used to calibrate the linearity of SAR ADC system 650 using foreground calibration techniques known in the art. Foreground calibration techniques and / or redundant SAR-ADC systems and methods described in U.S. Patent No. 4,970,514 may be applied to embodiments of the present invention. In some embodiments, calibration logic 658 performs digital foreground calibration, which adjusts the weights applied by code mapping circuitry 656 to the output of successive approximation register 654. In alternative embodiments, calibration logic 658 may facilitate analog foreground calibration, wherein elements of DAC 652 are adjusted.

[0067] In various embodiments, test logic 612 and ramp generator 204 are based on the above regarding... Figure 2A-2B , Figures 3A-3C , Figures 4A-4B and Figures 5A-5C The described embodiment method performs a linearity test on the SAR ADC system 650. In some embodiments, the test logic 612 may be related to... Figure 2A The test logic 202 shown is implemented and functions in a similar manner. For example, as shown, test logic 612 can monitor the output of comparator 660. In some embodiments, the test logic monitors the output CMP of comparator 660 during a predetermined successive approximation loop. Test logic 612 can monitor the output of comparator 660 during a first approximation loop used for comparisons corresponding to half-scale DAC values, and can monitor the output of comparator 660 during a second successive approximation loop used for comparisons corresponding to quarter-scale or three-quarter-scale DAC values ​​or other DAC values ​​associated with the primary code transition. Non-binary radix DACs may differ from these values.

[0068] although Figure 6B The illustrated embodiment shows test logic 612 monitoring the output of a single comparator 660 located within the SAR ADC system 650. However, it should be understood that in embodiments performing multi-stage comparisons, test logic 612 may also be configured to monitor multiple comparators. In embodiments where the SAR ADC system 650 has two or more comparators (not shown), test logic 612 may also be configured to monitor these additional comparators.

[0069] Test logic 612 can be configured to test multiple comparisons performed during different successive approximation cycles. In such an embodiment, test logic 612 is configured to perform multiple linear tests serially during the same or different successive approximation cycles at input voltages corresponding to different DAC output levels. Between each linear test, test logic 612 can cause ramp generator 204 to increase the ramp signal RVin to the next input signal level (corresponding to the next DAC level being tested) using a fast ramp as described above, thereby reducing the total test time.

[0070] In some embodiments, test logic 612 can be connected with... Figure 4A The test logic 404 shown is implemented in a similar manner, where the test signal M is replaced by the output of the monitored comparator. This embodiment may utilize a multiplexer 406, which is coupled to the output of comparator 660 and, as described above, the output of the comparator 660. Figure 4A and Figure 4B The test outputs M and SEL generated by the test logic 612 described in the embodiment are shown. The multiplexer 406 and the signals M and S generated by the test logic 612 are represented by dashed lines to indicate that the inclusion of the multiplexer 406 is optional.

[0071] The ADC, incorporating the test system and method described in the embodiments, can be applied to a variety of different systems and applications. An example of such a system is a radio frequency receiver, such as... Figure 7A The RF receiver 700 is shown. As illustrated, the RF receiver 700 includes an RF signal path having an antenna 702, a low-noise amplifier 704, a mixer 706, a programmable gain amplifier 708, a filter 710, an ADC 712 (as described above), and a processor 714. During operation, the RF signal received by the antenna 702 is amplified by the low-noise amplifier 704. The mixer 706 performs down-conversion, converting the frequency of the received RF signal to an intermediate frequency or baseband frequency. The output of the mixer 706 is amplified by the programmable gain amplifier 708, and the output of the programmable gain amplifier 708 is filtered by the filter 710. The filtering provided by the filter 710 can be used to reject out-of-band frequency content and / or as an anti-aliasing filter for the ADC 712, which includes an ADC with associated test circuitry, as described above. Figure 2A , Figure 2B , Figure 3A and Figure 3B The embodiments described above test the controller and ramp generator. In some embodiments, the ADC 712 also includes, as described above... Figure 1A , Figure 1B , Figure 2A , Figure 4A , Figure 6A and Figure 6BThe calibration circuit arrangement discussed. ADC 712 may be implemented, for example, using a pipelined ADC, a SAR ADC, or other ADC architectures known in the art. The ADC architecture may include redundancy. Processor 714 may perform signal processing on the output of ADC 712. However, it should be understood that... Figure 7A The architecture of the RF receiver 700 shown is just one example of many possible RF receiver implementations that can be implemented using the ADC implementations of the embodiment test system and methods.

[0072] In various embodiments, the radio frequency receiver 700 can be used in a variety of radio frequency-based systems. For example, the radio frequency receiver 700 can be used as a signal receiving path for cellular phones or other wireless devices. The radio frequency receiver 700 can also be used, for example, in radar systems. The embodiment test system and method are particularly suitable for use in radar systems that utilize periodic radar signals, such as frequency modulated continuous wave (FMCW) radar systems. In such embodiments, the radar transceiver transmits a series of increasing or decreasing frequencies. The radar receiver then receives the reflections from the transmitted radar chip and determines the frequency difference between the reflected signal and the currently transmitted signal. This frequency difference is proportional to the distance between the radar transceiver and the detected target.

[0073] In embodiments of the present invention, calibration and / or linearity testing can be performed as follows: Figure 7B The waveform diagram shows the execution within the time period between the linear frequency modulation signals. Figure 7B The relationship between the calibration and testing cycles and the FMCW radar frame is illustrated. As shown, the FMCW radar frame comprises n linear frequency modulated (LFM) signal cycles, where the LFM signal frequency 724 increases linearly between a minimum frequency fmin and a maximum frequency fmax. Once the LFM signal frequency 724 reaches the maximum frequency fmax at the end of the LFM signal cycle, the LFM signal frequency 724 is reset to the minimum frequency fmin. Although Figure 7B A linear frequency modulated (LFM) signal with increasing frequency is illustrated, but it should be understood that in some embodiments, the LFM signal frequency 724 may linearly decrease from a maximum frequency fmax at the beginning of each LFM signal period to a minimum frequency fmin at the end of each LFM signal period. In other embodiments, LFM signal periods with linearly increasing LFM signal frequency 724 alternate with LFM signal periods with linearly decreasing LFM signal frequency 724. In other embodiments, various frequencies, LFM signal periods, and frame lengths may be used, depending on the specific embodiment and its specifications.

[0074] like Figure 7B As shown in the example above, based on the information provided... Figure 1A , Figure 1B , Figure 2A , Figure 4A , Figure 6A and Figure 6B The described test and calibration method calibrates and / or tests the ADC 712 between each frame. Although Figure 7B The tests and / or calibrations performed before and after a single radar frame are shown as illustrative examples, but it should be understood that the ADC 712 can be calibrated and / or tested after any number of consecutive radar frames. It should be further understood that... Figure 7A and Figure 7B The system examples provided are merely non-limiting examples that illustrate how to integrate the ADC test and calibration systems and methods of the embodiments into practical system applications.

[0075] In some embodiments, the various ADC systems described herein may be disposed on a single monolithic semiconductor integrated circuit (such as a single semiconductor substrate), and / or the digital components may be on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0076] Figure 8 A block diagram of an embodiment method 800 for performing a linearity test on an ADC is shown. The ADC under test and the test system configured to perform the test can correspond to... Figure 2A-2B , Figures 3A-3C , Figures 4A-4B , Figures 5A-5C , Figures 6A-6B and Figures 7A-7B One of the embodiments described above. In step 802, a comparator associated with the comparator switching point or the input level used for testing is selected. Next, in steps 804 to 816, a linearity test is performed on the selected comparator or input level according to the embodiments disclosed above. In step 804, a first signal is applied to the input of the ADC to quickly obtain the input level associated with the selected input level associated with the comparator switching point. In various embodiments, the first signal is a ramp signal with a first slope, and the output of the selected comparator is monitored when the first signal is applied to the ADC. In some embodiments, as described in the embodiments above, the first signal may be generated by ramp generator 204.

[0077] When the system detects a change in state of the monitored selected comparator in step 806, a second signal is applied to the input of the ADC in step 808. In various embodiments, the initial value of the second signal level corresponds to the most recent value of the first signal level. The second signal may include a static signal (as described above regarding...). Figure 3C (as described above), or may include at least one ramp segment in at least one direction (as mentioned above). Figure 3A and Figure 3B (as described above). In some embodiments, as mentioned above... Figure 4BAs described in the embodiments, in step 810, a switching mode is applied to the comparator's logic output, causing the comparator's logic output to begin switching. In step 812, the ADC's code output is monitored while a second signal is applied until the completion of the second signal segment is determined in step 814. In various embodiments, the second signal is applied for a predetermined time period and / or a sufficiently long time period to collect enough data points to determine the linearity of the ADC for the input range associated with the selected input level. The duration may depend on the required test resolution, the characteristics of the second signal, and the type of post-processing used to determine the ADC performance metric.

[0078] In step 820, it is determined whether any remaining input test points exist. If so, the next comparator input level is selected, and steps 804-816 are repeated for the next test point. In some embodiments, ramp generator 204 ramps the ADC input signal from the signal level associated with the previously selected comparator transition point to the signal level associated with the next selected comparator transition point. Once all test points have been evaluated (as determined in step 820), then according to the above regarding... Figures 5A-5C The algorithm determines the linearity of the ADC. In some embodiments, the linearity of the ADC is determined point-by-point for each test prior to step 820. The linearity results for all test points can be evaluated during step 824 to determine whether the overall linearity of the ADC meets a predetermined performance criterion. In some embodiments, the predetermined performance criterion can be as simple as ensuring that all measured test points meet a predetermined ADC performance metric. Alternatively, the results for each individual test point can be weighted and summed to obtain the overall ADC performance metric.

[0079] Now for reference Figure 9 A block diagram of a processing system 900 according to an embodiment of the present invention is provided. The processing system 900 illustrates a general platform, as well as general components and functions, that can be used to implement portions of and / or interact with an external computer or processing device of the radar system of the embodiments. For example, the processing system 900 can be used to implement some or all of the processing performed by the test logic and foreground calibration logic disclosed in the above embodiments, and can be used to track and post-process ADC output codes to determine ADC performance metrics, such as referring to… Figures 5A-5C As described.

[0080] For example, the processing system 900 may include a central processing unit (CPU) 902 connected to a bus 908 and a memory 904, and may be configured to perform the processing discussed above according to programming instructions stored in the memory 904 or other non-transitory computer-readable medium. If desired or required, the processing system 900 may further include: a display adapter 910 for providing connection to a local display 912; and an input / output (I / O) adapter 914 for providing input / output interfaces for one or more input / output devices 916, such as a mouse, keyboard, flash drive, etc.

[0081] The processing system 900 may also include a network interface 918, which may be implemented using a network adapter and is configured to couple to a wired link (such as a network cable, USB interface, etc.) and / or a wireless / cellular link to communicate with the network 920. The network interface 918 may also include suitable receivers and transmitters for wireless communication. It should be noted that the processing system 900 may include other components. For example, if implemented externally, the processing system 900 may include hardware components such as power supplies, cables, motherboards, removable storage media, chassis, etc. These other components (although not shown) are considered part of the processing system 900. In some embodiments, the processing system 900 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0082] Embodiments of the invention are summarized herein. Other embodiments may also be understood in light of the overall description and claims submitted herein.

[0083] Example 1. A method for operating an analog-to-digital converter (ADC) including a comparator, the method comprising: determining a switching point of the comparator by applying a first signal having a first slope to the input of the ADC, and monitoring the output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined switching point of the comparator, monitoring the value of an output code of the ADC in response to the second signal, and generating statistics based on the monitored output code value, wherein the second signal is a static signal or has a second slope less than the first slope.

[0084] Example 2. The method according to Example 1 further includes: analyzing statistical information to determine at least one of the following: the occurrence of nonlinearity in the ADC transfer characteristics associated with the comparator's jump point, or the level of nonlinearity in the ADC transfer characteristics associated with the comparator's jump point.

[0085] Example 3. The method according to Example 1 or 2 further includes: performing a first calibration of the ADC before determining the jump point of the comparator; analyzing statistics; selectively performing a second calibration based on whether the statistics meet predetermined criteria; and repeatedly applying the second signal, monitoring the ADC output code value and generating statistics.

[0086] Example 4. Following the method of Example 3, where the first calibration and the second calibration are foreground calibrations.

[0087] Example 5. According to the method of Example 3 or 4, wherein performing the second calibration includes: providing second calibration data in response to the second calibration, and replacing the first calibration data associated with the first calibration of the ADC before determining the transition point with the second calibration data, the method further includes: scheduling the second calibration based on the signal load of the ADC.

[0088] Example 6. According to the method of Example 3 or 4, wherein performing the second calibration includes: providing second calibration data in response to the second calibration, and selectively replacing the first calibration data associated with the first calibration of the ADC before determining the jump point with the second calibration data based on whether statistical information meets a predetermined criterion.

[0089] Example 7. Following the method of Example 6, where the predetermined criteria are based on the level of the jump.

[0090] Example 8. According to one of Examples 1 to 7, wherein the second signal has a second slope that is less than the first slope, and the statistics include information from a histogram indicating the monitored output code values.

[0091] Example 9. According to the method of Example 8, the application of the first signal includes: applying the first signal until the output state of the comparator changes in response to the first signal to achieve a first signal level, and then applying a second signal having an initial value of the first signal level.

[0092] Example 10. According to the method of Example 8, the application of the second signal further includes: alternately increasing the second signal level to a first upper level and decreasing the second signal level to a second lower level according to a second slope within a predetermined range, said predetermined range including signal levels corresponding to the switching points of the comparator.

[0093] Example 11. The method according to Example 10 further includes generating a second signal, wherein generating the second signal includes: generating a ramp signal having a second slope in a first direction when the level of the second signal is increased, and generating a ramp signal having a second slope in a second direction opposite to the first direction when the level of the second signal is decreased.

[0094] Example 12. According to the method of Example 10, the information for generating the indicator histogram includes: omitting histogram entries of the ADC output code associated with the first high level and the second low level of the second signal.

[0095] Example 13. A method according to one of Examples 1 to 12, wherein the statistical information includes first statistical information indicating the average of code values ​​generated by a first decision of the comparator and second statistical information indicating the average of code values ​​generated by a second decision of the comparator, wherein the method further includes comparing the first statistical information with the second statistical information.

[0096] Example 14. According to the method of Example 13, the application of the second signal includes: applying a static signal having a signal level based on the determined transition point.

[0097] Example 15. According to the method of Example 13, it further includes: generating first and second statistics based on a first set of output codes associated with the transition of the compiler and comparator's output state from the first state to the second state, and a second set of output codes associated with the transition of the compiler and comparator's output state from the second state to the first state.

[0098] Example 16. According to the method of Example 15, wherein the first set of output codes is further associated with an increase in the second signal level, and the second set of output codes is further associated with a decrease in the second signal level.

[0099] Example 17. Following the method of Example 15 or 16, wherein compiling the first set of output codes includes averaging or summing the values ​​of the first set of output codes, and compiling the second set of output codes includes averaging or summing the values ​​of the second set of output codes.

[0100] Example 18. According to the method of Example 13, it further includes: when the output state of the comparator has a first state, generating first statistics based on averaging or accumulating a first set of output codes, and when the output state of the comparator has a second state, generating second statistics based on averaging or accumulating a second set of output codes.

[0101] Example 19. The method according to Example 13 further includes: alternatingly modifying the output state of the comparator while applying the second signal.

[0102] Example 20. According to one of Examples 1 to 19, wherein the ADC includes a redundant ADC.

[0103] Example 21. An integrated circuit comprising: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator disposed on the integrated circuit and having an output selectively coupled to an input of the ADC, the test signal generator being configured to generate a ramp signal; and a test controller coupled to the output of the at least one comparator and the test signal generator, the test controller being configured to cause the test signal generator to generate a first ramp signal having a first slope, the first ramp signal causing the output state of the at least one comparator to change at a comparator transition point, causing the test signal generator to generate a second ramp signal, the second ramp signal having a second slope less than the first slope, wherein the second ramp signal alternately increases and decreases between a first upper level and a second lower level, wherein the comparator transition point is between the first upper level and the second lower level, and the occurrence of an independent output code for evaluating the ADC.

[0104] Example 22. An integrated circuit according to Example 21, wherein the test controller is configured to evaluate the occurrence of an independent output code by counting the number of clicks on at least one independent output code.

[0105] Example 23. According to the integrated circuit of Example 22, wherein the test controller is further configured to analyze the distribution of the number of counted clicks to determine an ADC performance metric based on the analyzed distribution of the number of counted clicks, and compare the ADC performance metric with a predetermined threshold.

[0106] Example 24. An integrated circuit based on Example 22 or 23, wherein the test controller is further configured to compare the counted clicks with the expected clicks.

[0107] Example 25. An integrated circuit according to one of Examples 21 to 24 further includes a calibration circuit coupled to and disposed on the ADC, wherein a test controller is configured to test the ADC after the calibration circuit calibrates the ADC.

[0108] Example 26. An integrated circuit according to Example 25, wherein the calibration circuit is configured to calibrate the ADC based on an evaluation of the independent ADC output code meeting a predetermined criterion.

[0109] Example 27. An integrated circuit, comprising: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator having an output coupled to an input of the ADC; and a test controller having an output coupled to the test signal generator, a first input coupled to the output of the comparator of the ADC, and a second input configured to receive an output code of the ADC, wherein the test controller is configured to: determine a transition point of the comparator by causing the test signal generator to apply a first signal having a first slope to the input of the ADC and monitoring the output state of the comparator in response to the first signal; and cause the test signal generator to apply a second signal having a signal level based on the determined transition point of the comparator, and compare an accumulation or average of code values ​​generated by a first decision of the comparator with an accumulation or average of code values ​​generated by a second decision of the comparator, wherein the second signal is a static signal or has a second slope less than the first slope.

[0110] Example 28. An integrated circuit according to Example 27, wherein the test controller further includes an output coupled to a comparator, and the test controller is further configured to modify the output state of at least one comparator according to a mode.

[0111] Example 29. An integrated circuit according to Example 27 or 28, wherein the ADC includes a redundant ADC.

[0112] Example 30. An integrated circuit according to Example 26, wherein the redundant ADC is a pipelined ADC, and at least one comparator is disposed within the pipeline stage of the pipelined ADC.

[0113] While the invention has been described with reference to exemplary embodiments, this specification is not intended to be limiting. Those skilled in the art will appreciate, based on the specification, various modifications and combinations of illustrative embodiments and other embodiments of the invention. Therefore, it is expected that the appended claims will encompass any such modifications or embodiments.

Claims

1. A method for operating an analog-to-digital converter (ADC) comprising a comparator, the method comprising: determining a trip point of the comparator by applying a first signal having a first slope to an input of the ADC and monitoring an output state of the comparator in response to the first signal; and applying a second signal having a second signal level based on the determined trip point of the comparator after applying the first signal, monitoring an output code value of the ADC in response to the second signal, and generating statistics based on the monitored output code value, wherein the second signal is a static signal or the second signal has a second slope less than the first slope and alternately changes direction between a decreasing signal level and an increasing signal level at the second slope. analyzing the statistics to determine at least one of:

2. The method of claim 1, further comprising: an occurrence of non-linearity in a transfer characteristic of the ADC associated with the trip point of the comparator; or a level of non-linearity in a transfer characteristic of the ADC associated with the trip point of the comparator. performing a first calibration of the ADC prior to determining the trip point of the comparator; analyzing the statistics; 3. The method of claim 1, further comprising: selectively performing a second calibration based on whether the statistics meet a predetermined criterion; and repeating the applying of the second signal, the monitoring of the output code value of the ADC and the generating of the statistics.

4. The method of claim 3, wherein the first calibration and the second calibration are foreground calibrations. providing second calibration data in response to the second calibration and replacing first calibration data associated with the first calibration of the ADC prior to determining the trip point with the second calibration data, the method further comprising scheduling the second calibration based on a signal load of the ADC. providing second calibration data in response to the second calibration and selectively replacing first calibration data associated with the first calibration of the ADC prior to determining the trip point with the second calibration data based on whether the statistics meet a predetermined criterion.

5. The method of claim 3, wherein performing the second calibration comprises:

7. The method of claim 6, wherein the predetermined criterion is based on a level of a jump.

6. The method of claim 3, wherein performing the second calibration comprises:

8. The method of claim 1, wherein the second signal has the second slope less than the first slope, and wherein the statistics comprise information indicative of a histogram of the monitored output code value. applying the first signal until the output state of the comparator changes in response to the first signal to achieve a first signal level, and then applying the second signal having an initial value of the first signal level. alternately increasing the second signal level to a first upper level and decreasing the second signal level to a second lower level in accordance with the second slope within a predetermined range, the predetermined range including the signal level corresponding to the trip point of the comparator.

9. The method of claim 8, wherein applying the first signal comprises:

9. The method of claim 1, wherein the first signal is a ramp signal.

10. The method of claim 8, wherein applying the second signal further comprises: ​ 11. The method of claim 10, further comprising generating the second signal, wherein generating the second signal comprises: generating a ramp signal having the second slope in a first direction when the second signal level is increasing, and generating a ramp signal having the second slope in a second direction opposite the first direction when the second signal level is decreasing.

12. The method of claim 10, wherein generating information indicative of the histogram comprises: omitting a histogram entry for an output code of the ADC associated with the first upper level and the second lower level of the second signal.

13. The method of claim 1, wherein the statistical information includes first statistical information indicative of an average of code values resulting from first decisions of the comparator, and second statistical information indicative of an average of code values resulting from second decisions of the comparator, wherein the method further comprises comparing the first statistical information to the second statistical information.

14. The method of claim 13, wherein applying the second signal comprises: applying a static signal having a signal level based on the determined trip point.

15. The method of claim 13, further comprising: generating the first statistical information and the second statistical information based on compiling a first set of output codes associated with transitions of the output state of the comparator from a first state to a second state, and compiling a second set of output codes associated with transitions of the output state of the comparator from the second state to the first state.

16. The method of claim 15, wherein the first set of output codes is further associated with an increase in the second signal level, and the second set of output codes is further associated with a decrease in the second signal level.

17. The method of claim 15, wherein compiling the first set of output codes includes averaging or accumulating values of the first set of output codes, and compiling the second set of output codes includes averaging or accumulating values of the second set of output codes.

18. The method of claim 13, further comprising: generating the first statistical information based on averaging or accumulating a first set of output codes when the output state of the comparator has a first state, and generating the second statistical information based on averaging or accumulating a second set of output codes when the output state of the comparator has a second state.

19. The method of claim 13, further comprising: alternating modifying an output state of the comparator while applying the second signal.

20. The method of claim 13, wherein the ADC includes a redundant ADC.

21. An integrated circuit comprising: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator disposed on the integrated circuit and having an output selectively couplable to an input of the ADC, the test signal generator configured to produce a ramp signal; and a test controller coupled to an output of the at least one comparator and the test signal generator, the test controller configured to: cause the test signal generator to produce a first ramp signal having a first slope, the first ramp signal causing an output state of the at least one comparator to change at a comparator trip point; causing the test signal generator to generate a second ramp signal having a second slope smaller than the first slope, wherein the second ramp signal alternately increases and decreases between a first upper level and a second lower level, wherein the comparator trip point is between the first upper level and the second lower level; and evaluating occurrences of independent output codes of the ADC.

22. The integrated circuit of claim 21, wherein the test controller is configured to evaluate occurrences of the independent output codes by counting a number of hits of at least one independent output code.

23. The integrated circuit of claim 22, wherein the test controller is further configured to analyze a distribution of the counted number of hits to determine an ADC performance metric from the analyzed distribution of the counted number of hits, and compare the ADC performance metric to a predetermined threshold.

24. The integrated circuit of claim 22, wherein the test controller is further configured to compare the counted number of hits to an expected number of hits.

25. The integrated circuit of claim 21, further comprising a calibration circuit coupled to the ADC and disposed on the integrated circuit, wherein the test controller is configured to test the ADC after the calibration circuit calibrates the ADC.

26. The integrated circuit of claim 25, wherein the calibration circuit is configured to calibrate the ADC based on the evaluated occurrences of whether independent output codes of the ADC meet predetermined criteria.

27. An integrated circuit, comprising: an analog-to-digital converter (ADC) including at least one comparator disposed on the integrated circuit; a test signal generator having an output coupled to an input of the ADC; and a test controller having a first input coupled to an output of the comparator of the ADC, a second input configured to receive output codes of the ADC, and an output coupled to an output of the test signal generator, wherein the test controller is configured to: determine a trip point of the comparator by causing the test signal generator to apply a first signal having a first slope to the input of the ADC and monitor an output state of the comparator in response to the first signal, and cause the test signal generator to apply a second signal having a signal level based on the determined trip point of the comparator and compare an accumulation or average of code values resulting from first decisions of the comparator to an accumulation or average of code values resulting from second decisions of the comparator, wherein the second signal is a static signal or the second signal has a second slope smaller than the first slope and alternately changes direction between a decreasing signal level and an increasing signal level at the second slope.

28. The integrated circuit of claim 27, wherein the test controller further includes an output coupled to the comparator, and the test controller is further configured to modify the output state of the at least one comparator according to a mode.

29. The integrated circuit of claim 27, wherein the ADC comprises a redundant ADC.

30. The integrated circuit of claim 29, wherein the redundant ADC is a pipeline ADC, and wherein the at least one comparator is disposed within a pipeline stage of the pipeline ADC.

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