Time phase mismatch calibration method for multi-channel interleaved adc based on autocorrelation of multiple channels in binary output tree

Abstract

A N-channel interleaved analog-to-digital converter (ADC) adds a variable delay to the input sampling clock of each ADC. During calibration, each variable delay is edited by a successive approximation register (SAR) to minimize the time phase mismatch between channels. An autocorrelator generates a sign of a correlation error for a pair of ADC digital outputs. The SAR bits are tested using the correlation sign to determine when to add or subtract the SAR bits. Calibration is first performed in a binary tree first layer of a multiplexed correlator. Then, the deviation between more distant pairs and groups is calibrated in higher layers of the binary tree using an autocorrelator whose inputs are multiplexed from the ADC output groups to the binary tree of the multiplexed correlator. The binary tree of the multiplexed correlator can include bypassers for odd non-binary values of N. The sampling clock and component time phase mismatch between two adjacent channels and more distant channels is reduced to 1 LSB.

Description

Technical Field

[0001] This invention relates to analog-to-digital converters (ADCs), and more particularly to a calibration method for alternating ADCs. Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used to convert analog signals into digital values. Multi-bit ADCs offer high resolution, and their accuracy can be improved through calibration. Higher sampling rates can be achieved by alternating between two ADCs, with each operating at half the sampling rate.

[0003] Figure 1 An alternating ADC of the prior art is shown. ADC 10 and ADC 12 alternate, wherein ADC 10 samples the analog input AIN when the clock CLK turns off switch 20, and ADC 12 samples the analog input AIN when the inverting clock CLKB turns off switch 22. While ADC 10 has sufficient time to sample and hold AIN and convert it into a digital value, multiplexer 18 selects the digital output Y1 from ADC 10 when CLK is high. When CLK is low relative to multiplexer 18, the digital output DOUT is Y2. Therefore, each of ADC 10 and ADC 12 operates at half the data rate of the final output DOUT.

[0004] Figure 2 This diagram illustrates the simulation of sampling and clock skew. AIN is sampled into ADC 10 to generate Y1[K-1] and Y1[K] on the falling edge of CLK, while AIN is sampled into ADC 12 to generate Y2[K-1] and Y2[K] on the falling edge of CLKB, where K is the sample or timing exponent. The sampling time or period of AIN is Ts. Ideally, there is no clock skew in CLK, and all samples are separated by Ts. However, CLK may not have a pulse width that is exactly 50% of the 2*Ts period, causing sampling pulse width mismatch and nonlinearity. Channel Y2 sampling can be delayed by Ts+ΔT / 2 relative to channel Y1 sampling, while channel Y1 sampling can be delayed by Ts-ΔT / 2 relative to channel Y2 sampling. Ideally, ΔT = 0, and there is no sampling mismatch. However, in reality, ΔT is finite. For more than two channels, it is desirable to reduce ΔT to a minimum acceptable level.

[0005] ADCs 10 and 12 and switches 20 and 22 may not be precisely matched, resulting in a limited bandwidth mismatch between the two channels Y1 and Y2. Therefore, sampling pulse mismatch and ADC component mismatch can lead to nonlinearity.

[0006] Figure 3This is a graph showing the clutter in the spectrum of a prior art alternating ADC. Sampling pulse width mismatch and component mismatch can cause nonlinearity or errors leading to clutter 302. These clutters can be generated in integer multiples of Fs / N, K*Fs / N±F, where K is an integer, Fs is the sampling frequency (period Ts = 1 / Fs), and N is the number of alternating channels. Because these clutters limit the dynamic range of high-speed ADCs and are proportional to the amplitude and frequency of the analog input signal, they are undesirable.

[0007] The desired architecture is a highly alternating ADC with at least four ADC channels alternating together, operating at a higher sampling rate. It is desirable to introduce variable, programmable delays for each of the channel inputs to calibrate for time-phase mismatches caused by sampling pulse width mismatches, clock mismatches, and component mismatches among the four or more channels alternating together. A calibration method is desired to test various values ​​of these delays to program them thereby minimizing deviations between the multiple channels. Fast foreground calibration methods and background calibration methods for adjusting for gradual temperature deviations are both desired. Attached Figure Description

[0008] Figure 1 This illustrates an alternative ADC from the prior art.

[0009] Figure 2 A graph simulating sampling and clock skew.

[0010] Figure 3 This is a graph showing clutter in the spectrum of an existing alternating ADC.

[0011] Figure 4 Block diagram of a 4-channel alternating ADC with autocorrelator for calibration based on editable input delay.

[0012] Figure 5 A diagram of a SAR delay element with binary weighted capacitors.

[0013] Figure 6 The autocorrelator is shown in more detail.

[0014] Figures 7A-7C The autocorrelation of samples during calibration is highlighted.

[0015] Figures 8A-8D A flowchart for foreground calibration of four alternating ADC channels.

[0016] Figure 9 A graph showing how to reduce spectral clutter for an alternating ADC with channel input delay calibrated by an autocorrelator.

[0017] Figure 10The diagram shows the binary tree of the autocorrelator and the multiplexing of the alternating outputs.

[0018] Figure 11A-11B A flowchart is shown showing the calibration process for any layer in the binary tree of the autocorrelator.

[0019] Figure 12 The back-end processor that triggers the background calibration of the alternating ADC is shown.

[0020] Figures 13A-13B A flowchart illustrating the background calibration process is shown.

[0021] Figure 14 Show the non-binary tree of autocorrelators and multiplexers.

[0022] Figure 15 Show the non-binary odd tree of autocorrelators and multiplexers.

[0023] Figure 16 This shows the FIR filtering of the ADC output.

[0024] Figure 17 The model of an alternating ADC is shown. Detailed Implementation

[0025] This invention relates to an improvement in alternating ADC calibration. The following description enables those skilled in the art to make and use the invention in the context of a particular application and its requirements. It will be apparent to those skilled in the art that various modifications can be made to the preferred embodiments, and that the general principles described can be applied to other embodiments. Therefore, the invention is not intended to limit the specific embodiments shown and described, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0026] Figure 4 This is a block diagram of a 4-channel alternating ADC with an autocorrelator calibrated based on an editable input delay. The analog input AIN is buffered by analog buffer 30, sampled by switch 20 into ADC 10 generating digital value Y1, and sampled by switch 23 into ADC 13 generating digital value Y3. The analog input AIN is buffered by analog buffer 32, sampled by switch 22 into ADC 12 generating digital value Y2, and sampled by switch 24 into ADC 14 generating digital value Y4.

[0027] Odd channels Y1 and Y3 are multiplexed together and alternately output to YM13 via multiplexer (MUX) 60. Simultaneously, even channels Y2 and Y4 are multiplexed and alternately output to YM24 via multiplexer 62. Finally, multiplexer 64 alternately selects YM13 and YM24 to generate the final data output DOUT. Multiplexer 64 operates at double speed with clock TSX2, while multiplexers 60 and 62 receive the sampling clock TS.

[0028] The sampling clock TS or its inverted clock TSB is delayed by variable delays to generate clocks T1, T2, T3, and T4. Clocks T1, T2, T3, and T4 control switches 20, 22, 23, and 24, respectively, that sample the AIN to ADCs 10, 12, 13, and 14. ADCs 10, 12, 13, and 14 generate channel digital outputs Y1, Y2, Y3, and Y3, respectively, with corresponding sampling phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. These variable delays are edited during calibration using digital values, which are stored in a successive approximation register (SAR). The successive approximation register (SAR) enables and disables binary weighted capacitor delay elements. Calibration uses a successive approximation method to first test the larger most significant bit (MSB) capacitor, then successively tests smaller capacitors until the least significant bit (LSB) capacitor is tested.

[0029] SAR delay device 40 delays the sampling clock TS to generate T1 for switch 20, while SAR delay device 43 delays the inverted sampling clock TSB to generate T3 for switch 23. By adjusting the delay values ​​written to SAR delay devices 40 and 43, the time phase mismatch between odd channels Y1 and Y3 can be compensated and matched using the 0-degree clock and 180-degree clock for T1 and T3, respectively, within the delay of one LSB capacitor in SAR delay devices 40 and 43.

[0030] Similarly, SAR delay device 42 delays the sampling clock TS to generate T2 for switch 22, while SAR delay device 44 delays the inverted sampling clock TSB to generate T4 for switch 24. By adjusting the delay values ​​programmed into SAR delay devices 42 and 44, the time phase mismatch between channels Y2 and Y4 can be compensated and matched using 90-degree and 270-degree clocks for T2 and T4, respectively, within the delay of one LSB capacitor in SAR delay devices 42 and 43.

[0031] The autocorrelator 50 compares the digital values ​​Y1 and Y3 and generates a sign bit SIGNA for the correlation result. This sign bit indicates which value of Y1 and Y2 is larger, thus enabling the calibration process to determine whether to set or clear the bit being tested for SAR delay device 40 or SAR delay device 43.

[0032] Autocorrelator 52 compares the digital values ​​Y2 and Y4 and generates a sign bit SIGNB for the correlation result. This sign bit indicates which value of Y2 and Y4 is larger, thus enabling the calibration process to determine whether to set or clear the bit being tested for SAR delay device 42 or SAR delay device 44.

[0033] Autocorrelator 54 compares the multiplexed digital values ​​YM13 and YM24 and generates a sign bit SIGNC for the correlation result. This sign bit indicates which value of YM13 and YM24 is larger, allowing the calibration process to determine whether to set or clear the bit being tested for SAR delay devices 40, 43 or SAR delay devices 42, 44. Autocorrelator 54 receives clock TSX2 and operates at twice the frequency of autocorrelators 50 and 52 that receive clock TS.

[0034] The calibrator 55 receives the sign bit SIGNA from autocorrelator 50, the sign bit SIGNB from autocorrelator 52, and the sign bit SIGNC from autocorrelator 54. Because smaller bit positions are tested consecutively, the calibrator 55 can use these sign bits during successive approximation sequencing to determine when to keep the test bit set in SAR delay devices 40, 42, 43, and 44 and when to reset the test bit. SIGNA is initially used to select one of SAR delay devices 40 and 41 to add a test bit. SIGNB is initially used to select one of SAR delay devices 42 and 44 to add a test bit. For the second layer, SIGNC is used to select either SAR delay devices 40 and 43 or SAR delay devices 42 and 44 to add a test bit during the second layer sequencing.

[0035] Figure 5 This is a diagram of a SAR delay element with binary weighted capacitors. The SAR delay device 40 has an input inverter 92 and an output inverter 94. The input inverter 92 inverts the input sampling clock TS to drive the delay node D, and the output inverter 94 drives the local sampling clock T1 for channel 1.

[0036] A series of binary weighted capacitors 110, 108, 106, 104...102 have capacitance values ​​or weights that are 64, 32, 16, 8, 4, 2, and 1 times the minimum capacitance value C, respectively. This minimum capacitance value can be the capacitance value C1 of capacitor 102. All of the binary weighted capacitors 110, 108, 106, 104...102 have one terminal connected to the delay node D between inverters 92 and 94, and another terminal grounded via startup transistors 120, 118, 116, 114...112. Bits in SAR register 130 drive the gates of startup transistors 120, 118, 116, 114...112. When a bit in SAR register 130 is high, the startup transistors are closed, grounding the lower terminal of the capacitor, enabling the capacitor, and increasing the capacitance and delay of delay node D.

[0037] For example, the binary value 1010000 of SAR register 130 enables transistors 120 and 116 and capacitors 110 and 106, thereby increasing the capacitance at delay node D by 64C+16C or 80C. MSB capacitor 110 increases the delay by 64C, while capacitor 116 increases the delay by 16C. Other SAR delay devices 42, 43, and 44 operate in a similar manner, and each of them can be programmed with different SAR delay device values.

[0038] Figure 6 The autocorrelator is shown in more detail. The autocorrelator 50 receives Y1 from ADC 10 at time point K, which is used as Y1[K], and receives Y3 from ADC 13 at time point K, which is used as Y3[K]. Y1[K] is delayed by sampling delay device 146 to generate Y1[K-1], while Y3[K] is delayed by sampling delay device 148 to generate Y3[K-1].

[0039] Multiplier 140 multiplies Y1[K] by Y3[K-1], while multiplier 142 multiplies Y1[K-1] by Y3[K-1]. Finally, adder 144 generates the sign bit SIGN of the correlation error Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1].

[0040] When ΔT is positive ( Figure 2Since Y1[K]*Y3[K-1] is less than Y1[K-1]*Y3[K-1], Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] is negative and its sign bit is 1. A delay should be added to SAR delay device 40 to reduce ΔT. When ΔT is negative, Y1[K]*Y3[K-1] is greater than Y1[K-1]*Y3[K-1], so Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] is positive and its sign bit is 0. A delay should be added to SAR delay device 43 to increase ΔT. Other autocorrelators 52 and 54 should be operated in a similar manner.

[0041] Figures 7A-7C The autocorrelation of samples during calibration is highlighted. Figure 7A In the first step of the highlighting process, the autocorrelator 50 compares Y1 and Y3 to generate the sign of Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1]. When ΔT(Y1,Y3) is positive, Y1[K]*Y3[K-1] is less than Y1[K-1]*Y3[K-1], so Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] is negative, and the sign bit is set to 1. A delay should be added to the SAR delay device 40 to reduce ΔT(Y1,Y3). When ΔT(Y1,Y3) is negative, Y1[K]*Y3[K-1] is greater than Y1[K-1]*Y3[K-1], so Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] is positive, and the sign bit is set to 0. The delay should be added to the SAR delay device 43 to increase ΔT(Y1,Y3).

[0042] exist Figure 7B In the second step of the highlighting, the autocorrelator 52 compares Y2 and Y4 to generate the sign of Y2[K]*Y4[K-1] – Y2[K-1]*Y4[K-1]. When ΔT(Y2,Y4) is positive, Y2[K]*Y4[K-1] is less than Y2[K-1]*Y4[K-1], so Y2[K]*Y4[K-1]-Y2[K-1]*Y4[K-1] is negative, and the sign bit is set to 1. A delay should be added to the SAR delay device 42 to reduce ΔT(Y2,Y4). When ΔT(Y2,Y4) is negative, Y2[K]*Y4[K-1] is greater than Y2[K-1]*Y4[K-1], so Y2[K]*Y4[K-1]-Y2[K-1]*Y4[K-1] is positive, and the sign bit is set to 0. The delay should be added to the SAR delay device 44 to increase ΔT(Y2,Y4).

[0043] exist Figure 7BIn the final third step of the highlighted display, the autocorrelator 54 compares YM13, which is multiplexed by Y1 and Y3, with YM24, which is multiplexed by Y2 and Y4, to generate the sign of YM12[K]*YM24[K-1]-YM13[K-1]*YM24[K-1]. When ΔT(YM13,YM24) is positive, YM13[K]*YM24[K-1] is less than YM13[K-1]*YM24[K-1], so YM13[K]*YM24[K-1]-YM13[K-1]*YM24[K-1] is negative, and the sign bit is set to 1. Delay should be added to SAR delay devices 40 and SAR delay devices 43 to reduce ΔT(YM13,YM24). When ΔT(YM13,YM24) is negative, YM13[K]*YM24[K-1] is greater than YM13[K-1]*YM24[K-1], so YM13[K]*YM24[K-1]-YM13[K-1]*YM24[K-1] is positive, and the sign bit is set to 0. The delay should be added to SAR delay devices 42 and 44 to increase ΔT(YM13,YM24).

[0044] Figures 8A-8D A flowchart illustrating the foreground calibration of four alternating ADC channels. This process can be used for initial calibration. Figure 4 The system features a 4-channel alternating ADC. Figures 8A-8B In the first pass, autocorrelators 50 are used to calibrate the odd-pair channels Y1 and Y3. Then, starting from step 236, ... Figures 8A-8B In steps 204-232, an autocorrelator 52 is used to perform a second-pass calibration on the even-numbered channels Y2 and Y4. This is referred to as the first layer, where each adjacent pair of ADC outputs is correlated. Finally, in Figure 8C-8D In the second layer, autocorrelator 54 is used to calibrate the multi-channel multiplexed outputs YM13 and YM24.

[0045] exist Figure 8A In step 202, clear all bits in all SAR delay devices 40, 42, 42, 44. This operation disconnects all binary weighted capacitors 110, 108, 106, 104...102 from all SAR delay elements. Calculate the average value S1 of the sign bit SIGN from autocorrelator 50 over M samples of the analog input AIN, in step 204. M can be a large number of samples, such as 2^22, which can still be acquired at high frequency over a short period of time.

[0046] When the averaged sign bit S1 is 1, in step 210, the average value of Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] over the M sample range is negative. Because the sign is negative, ΔT(Y1,Y3) is positive. Regarding the average value, Y1[K]*Y3[K-1] is less than Y1[K-1]*Y3[K-1]. The delay should be added to the SAR delay device 40 to reduce ΔT(Y1,Y3). Channel selection CS is set to 1, in step 216.

[0047] When the averaged sign bit S1 is 0, in step 210, the average value of Y1[K]*Y3[K-1]-Y1[K-1]*Y3[K-1] over the M sample range is positive. Because the sign is positive, ΔT(Y1,Y3) is negative. Regarding the average value, Y1[K]*Y3[K-1] is greater than Y1[K-1]*Y3[K-1]. The delay should be added to the SAR delay device 43 to increase ΔT(Y1,Y3). The channel selection CS is set to 3, in step 206.

[0048] The bit position Q is set to the MSB of the first layer, step 212. When CS = 1, Q is the bit position in SAR delay device 40, or when CS = 3, Q is the bit position in SAR delay device 43. This MSB of the first layer can be smaller than the overall MSB of SAR delay device 40, thus allowing overflow to higher layers. For example, the MSB of the second layer might be Q = 6, thus matching the C64 binary weighted capacitor 110 ( Figure 5 Corresponding to this, the MSB of the first layer may be Q=5, thus corresponding to the C32 binary weighted capacitor 108 ( Figure 5 Corresponding to.

[0049] exist Figure 8B In step 220, among the selected SAR delay elements, the bit at the current position Q is set to high. For the initial iteration Q = MSB = 5, when CS = 1, SAR delay device 40 is set to 0100000, while SAR delay device 43 remains at 0000000. When CS = 3, SAR delay device 43 is set to 0100000, while SAR delay device 40 remains at 0000000. When CS = 1, the delay element is selected as SAR delay device 40, or when CS = 3, the delay element is selected as SAR delay device 43.

[0050] The average value S2 is calculated from the 50 sign bit SIGN of the autocorrelator on the M samples of the analog input AIN, step 224. When the averaged sign bit S2 is the same as S1, the additional capacitance added in step 220 is insufficient to change the sign of the correlation error and the polarity of ΔT, step 230. The additional capacitance and delay added in step 220 should remain enabled during further testing.

[0051] When the averaged sign bit S2 is opposite to S1, excessive additional capacitance is added in step 220, step 230. The added capacitance and delay change the sign and polarity of the associated error ΔT. The additional capacitance and delay added in step 220 are removed by clearing the bit Q added in SAR delay device 40 (CS=1) or SAR delay device 43 (CS=3), step 226. Step 226 cancels step 220.

[0052] If Q has not yet reached the LSB, proceed to step 232, then subtract Q, proceed to step 234, and set the next valid bit Q in SAR delay device 40 (CS=1) or SAR delay device 43 (CS=3), proceed to step 220. Average the new symbol bit S2 with the new setting of SAR delay device 40 or SAR delay device 43, proceed to step 224, and if S2 is not equal to the original symbol bit S1, clear the added bit, proceed to steps 230 and 226.

[0053] This process is repeated for consecutive small Q-bit positions and the small additions of capacitance in steps 220-234 until Q reaches the LSB, step 232. Then, for any other channel pair (e.g., Y2, Y4), the process is repeated starting from step 204, where step 216 is modified to set CS=2, thereby setting and clearing the bits in SAR delay device 42, and step 206 is modified to set CS=4, thereby setting and clearing the bits in SAR delay device 44. When processing Y2, Y4, the sign bits S1 and S2 are averaged using autocorrelator 52 instead of autocorrelator 50.

[0054] Once all adjacent channel pairs in the first layer have been processed, step 236, then calibration continues for the second layer. Figure 8C .exist Figures 8A-8B In this process, the values ​​set in SAR delay devices 40, 42, 43, and 44 introduce input delay into the sampling clocks at the inputs of ADCs 10, 12, 13, and 14, thereby compensating for skew or deviations in the LSB capacitor delay of each of these pairs. Figures 8B-8C In this study, the pair-to-pair skew between odd pairs Y1, Y3 and even pairs Y2, Y4 was tested and compensated.

[0055] The output Y1 of ADC 10 and the output Y3 of ADC 13 are multiplexed together by multiplexer 60 to form YM13, which is identified by channel selection CS=13. Similarly, the output Y2 of ADC 12 and the output Y4 of ADC 14 are multiplexed together by multiplexer 62 to form YM24, which is identified by channel selection CS=24, step 242.

[0056] exist Figure 8C In step 244, the sign bit SIGN from the second-layer autocorrelator 54 is averaged S2 over M samples of the analog input AIN. When the averaged sign bit S1 is 1, in step 250, the average of YM13[K]*YM24[K-1]-YM13[K-1]*YM24[K-1] over M samples is negative. Because the sign is negative, ΔT(YM13,YM24) is positive. Delay should be added to both SAR delay device 40 and SAR delay device 43 to reduce ΔT(YM13,YM24). Channel selection CS is set to 13, in step 256.

[0057] When the averaged sign bit S1 is 0, in step 250, the average value of YM13[K]*YM24[K-1]-YM13[K-1]*YM24[K-1] over the M sample range is positive. Because the sign is positive, ΔT(YM13,YM24) is negative. Delay should be added to both SAR delay device 42 and SAR delay device 44 to increase ΔT(YM13,YM24). Channel selection CS is set to 24, step 246.

[0058] Bit position Q is set to the MSB of the second layer, step 252. When CS = 13, Q is the bit position of either SAR delay devices 40 or 43, or when CS = 24, Q is the bit position of either SAR delay devices 42 or 44. This MSB of the second layer can be greater than the MSB of the first layer. For example, the MSB of the second layer may be Q = 6, thus matching the C64 binary weighted capacitor 110 ( Figure 5 Corresponding to this, the MSB of the first layer may be Q=5, thus corresponding to the C32 binary weighted capacitor 108 ( Figure 5 Corresponding to.

[0059] exist Figure 8DIn step 260, the current position Q is set to high and added to the existing value of both the selected SAR delay element and the current position Q. For example, for the initial iteration Q = MSB = 6, when CS = 13, when SAR delay device 40 is 0010101 and SAR delay device 43 is 0000000, adding Q = 6 generates 1010101 in SAR delay device 40 and 1000000 in SAR delay device 43.

[0060] Calculate the average value S2 from the 54-sign bit SIGN of the autocorrelator over M samples of the analog input AIN, step 264. When the averaged sign bit S2 is the same as S1, proceed to step 270. The additional capacitance added in step 260 is insufficient to change the sign of the correlation error and the polarity of ΔT. The additional capacitance and delay added in step 260 should remain enabled during further testing.

[0061] When the averaged sign bit S2 is opposite to S1, step 270, the extra capacitance added in step 260 is excessive. The added capacitance and delay change the sign and polarity of the associated error ΔT. The extra capacitance and delay added in step 260 are removed by subtracting the bit Q added in either SAR delay devices 40 and 43 (CS=13) or SAR delay devices 42 and 44 (CS=24), step 266. Step 266 cancels step 260.

[0062] If Q has not yet reached the LSB, proceed to step 272, then subtract Q, proceed to step 274, and add the next valid bit Q from SAR delay devices 40, 43 (CS = 13) or SAR delay devices 42, 44 (CS = 24), proceed to step 260. Average the new symbol bit S2 using the new settings of SAR delay devices 40, 43 or SAR delay devices 43, 44, proceed to step 264, and if S2 is not equal to the original symbol bit S1, subtract the added bit, proceed to steps 270, 266.

[0063] When the calibration is complete, repeat the process for consecutive smaller Q bit positions and smaller added capacitors in steps 260-274 until Q reaches the LSB, step 272.

[0064] Figure 9 A graph showing the reduction of spectral clutter in an interleaved ADC with channel input delays calibrated by an autocorrelator. This is achieved by adjusting... Figure 4 The programmable delays in the SAR delay devices 40, 42, 43, and 44 of the alternating ADC shown are... Figures 8A-8DA calibration routine is used to compensate for sampling pulse width mismatch and component mismatch that cause nonlinearity or error. This calibration reduces the amplitude of clutter 303. This clutter is still generated in integer multiples of Fs / N / K*Fs / N±Fin, where Fs is the sampling frequency (period Ts = 1 / Fs) and N is the number of interleaved channels. However, when compared with... Figure 3 When compared with existing clutter 302, the amplitude of clutter 303 is reduced.

[0065] Figure 10 The diagram illustrates an autocorrelator and a multiplexed binary tree on the output of an alternating ADC. Autocorrelators 50, 52, 54, and 56 can be configured in a binary tree that matches the binary tree of multiplexers 60, 62, 64, and 66, which multiplex the outputs Y1, Y2...Y(N) of the alternating ADC on the first level of the binary tree. Each channel pair has one of the multiplexed correlators 700, 702, 704, and 706 in the first level, one of which receives two digital inputs from two ADCs. For example, multiplexed correlator 700 receives Y1(N) from ADC 10. Figure 4 Y5, Y1, and Y5 from ADC 5 are input to multiplexer 60 and autocorrelator 50 of multiplexer correlator 700. Multiplexer 60 generates multiplexed output YM15, while autocorrelator 50 generates correlation symbol SIGN.

[0066] When there are N ADC channels, and N is a binary integer, the first layer has N / 2 multiplexed correlators 700, 702, 704, and 706, the second layer has N / 4 multiplexed correlators 708 and 710, the third layer has N / 8 multiplexed correlators 700, and the final layer R has only one multiplexed correlator 712. Multiplexed correlator 712 generates the final data output DOUT to form its multiplexer 66. This final multiplexer 66 and the final autocorrelator 56 operate at the highest sampling frequency Fs. Lower layers L in the binary tree operate at a lower frequency Fs / (2*(R-1)), where L is the current layer, R is the total number of layers (log2(N) of the full binary tree), and L and R are integers. The multiplexing and correlation frequencies are twice that of each consecutive layer in the binary tree.

[0067] Figure 11A-11B This diagram illustrates the calibration process for any layer in a binary tree of the autocorrelation function. For any layer L in the binary tree, such as... Figure 10As shown, each autocorrelator in layer L>1 has two inputs YM(U) and YM(V) from the preceding multiplexer. In the first layer L=1, each autocorrelator has two inputs Y(U) and Y(V) directly from the ADC.

[0068] All ADC channels Y(Ui) fed into the multiplexer that generates YM(U) are in group U, while all ADC channels Y(Vi) fed into the multiplexer that generates YM(V) are in group V. Layer L may have several autocorrelators, each with a different set of channels in its group U and another set of channels in its group V. Channels in group U are identified by channel selection CS=U, and the channels have multiplexed ADC outputs as the first input of the group-pair autocorrelator; while channels in group V are identified by channel selection CS=V, and the channels have multiplexed ADC outputs as the second input of the autocorrelator, step 342.

[0069] exist Figure 11A In step 344, the sign bit SIGN from the layer R autocorrelator of group-UV is averaged S1 over M samples of the analog input AIN. When the averaged sign bit S1 is 1, in step 350, the average of YM(U)[K]*YM(V)[K-1]–YM(U)[K-1]*YM(V)[K-1] over M samples is negative. Because the sign is negative, ΔT(YM(U),YM(V)) is positive. Delay should be added to each SAR delay element (SAR delay device 40, etc.) SAR(U) in each channel of group U to reduce ΔT(YM(U),YM(V)). Channel selection CS is set to U, in step 356.

[0070] When the averaged sign bit S1 is 0, in step 350, the average value of YM(U)[K]*YM(V)[K-1]–YM(U)[K-1]*YM(V)[K-1] over the M sample range is positive. Because the sign is positive, ΔT(YM(U),YM(V)) is negative. The delay should be added to each SAR delay device SAR(V) in each channel of group V to increase ΔT(YM(U),YM(V)). Channel selection CS is set to V, in step 346.

[0071] Bit position Q is set to the MSB of layer L, step 352. When CS = U, Q is the bit position in each SAR(U), or when CS = V, Q is the bit position in each SAR(V). This MSB of layer L can be greater than the MSB of the first layer.

[0072] exist Figure 11BIn step 360, the current position Q is set high and added to the existing value of the SAR (CS) of each SAR delay device for each channel in the selected group U or V. The sign bit SIGN from the current autocorrelator is averaged S2 over M samples of the analog input AIN. When the averaged sign bit S2 is the same as S1, in step 370, the additional capacitance added in step 360 is insufficient to change the sign and polarity of the correlation error ΔT. The additional capacitance and delay added in step 360 should remain enabled during further testing.

[0073] When the averaged sign bit S2 is opposite to S1, step 370, the extra capacitance added in step 360 is excessive. The added capacitance and delay change the sign and polarity of the associated error ΔT. The extra capacitance and delay added in step 360 are removed by subtracting the added bit Q in all SAR (CS) of the selected channel group U or V, step 366. Step 366 cancels step 360.

[0074] If Q has not yet reached the LSB, proceed to step 372, then subtract Q, proceed to step 374, and add the next valid bit Q of all SAR(CS) in the selected channel CS, U, or V, proceed to step 360. Average the new symbol bit S2 with the new SAR(CS) setting, proceed to step 364, and if S2 is not equal to the original symbol bit S1, subtract the added bit, proceed to steps 370 and 366.

[0075] This process is repeated for consecutive small Q-bit positions and the small added capacitances in steps 360-374 until Q reaches the LSB, step 372. Then, for any other pair U, V, this process is repeated starting from step 342, step 376. Once all possible pair U, V in layer L have been processed, the next layer L+1 in the autocorrelator binary tree can be processed by repeating the process starting from step 342 for layer L = L+1. Finally, layer L has only one pair and one autocorrelator.

[0076] Figure 12 The back-end processor that triggers background calibration of the alternating ADC is shown. Foreground calibration, such as... Figures 8A-8D As shown, it can be triggered by power-on, initialization, or reset. This foreground calibration uses an autocorrelator to perform a successive approximation search, which loads a delay value into the SAR delay device register 744 in the alternating ADC 730 to compensate for the time phase mismatch between the ADC channels in the alternating ADC 730.

[0077] Temperature and voltage conditions can drift over time. Switches, delay devices, ADCs, and other components, along with their errors, can exhibit temperature and voltage dependence. The circuitry in the Alternating ADC 730 is sensitive to temperature and voltage. Over time, changes in temperature and supply voltage, due to system heating or environmental changes, can lead to increased time-phase mismatch in the Alternating ADC 730. Because of this condition drift, the calibrated delay may need to be updated to compensate for this drift. Background calibration can be periodically triggered to compensate for these drifts.

[0078] The downstream device 732 may be a baseband modem, a digital signal processor (DSP), a field-programmable array (FPGA), or other device using the digital output DOUT from the alternating ADC 730. The downstream device 732 may include logic that detects when temperature, voltage, or other conditions change and triggers the alternating ADC 730 to perform background calibration. The downstream device 732 may have a timer and trigger background calibration after a period of time, such as hourly or daily. The downstream device 732 may detect idle time or periods when the analog input AIN has the appropriate signal strength and frequency for calibration. Pattern generation logic integrated with the alternating ADC 730 may also be enabled to generate the appropriate analog input AIN signal for calibration.

[0079] Figures 13A-13B A flowchart of the background calibration process is shown. After the foreground calibration is completed and the calibrated delay is applied to all SAR delay devices 40, 42, 43, 44..., background calibration is performed.

[0080] exist Figure 13A In this process, any layer L can have several autocorrelators, each of which has a different set of channels in its group U and another set of channels in its group V. Channels in group U are identified by channel selection CS=U, and each channel has its corresponding multiplexed ADC output as the first input of the group-pair autocorrelator; while channels in group V are identified by channel selection CS=V, and each channel has its corresponding multiplexed ADC output as the second input of the autocorrelator, step 342.

[0081] The sign bit SIGN from the group-to-UV layer R autocorrelator is averaged S1 over M samples of the analog input AIN, step 444. When the averaged sign bit S1 is 1, step 450, the average of YM(U)[K]*YM(V)[K-1]–YM(U)[K-1]*YM(V)[K-1] over M samples is negative. Because the sign is negative, ΔT(YM(U),YM(V)) is positive. Delay should be added to each SAR delay element (SAR delay device 40, etc.) SAR(U) in each channel of group U to reduce ΔT(YM(U),YM(V)). Channel selection CS is set to U, step 456.

[0082] When the averaged sign bit S1 is 0, in step 450, the average value of YM(U)[K]*YM(V)[K-1]–YM(U)[K-1]*YM(V)[K-1] over the M sample range is positive. Because the sign is positive, ΔT(YM(U),YM(V)) is negative. The delay should be added to each SAR delay device SAR(V) in each channel of group V to increase ΔT(YM(U),YM(V)). Channel selection CS is set to V, in step 446.

[0083] Bit position Q is set to the least significant bit (LSB) of layer L, step 452. When CS = U, Q is the bit position in each SAR(U), or when CS = V, Q is the bit position in each SAR(V). MSB is used for foreground calibration when larger delay changes are expected to converge more quickly to the calibration results. However, LSB is used for background calibration because larger drift is not desired, so slower adjustments are preferred for background calibration.

[0084] exist Figure 13B In step 460, the bit (LSB) of the current position Q is set high and added to the existing value of the SAR (CS) of each SAR delay device for each channel in the selected group U or V. The sign bit SIGN from the current autocorrelator is averaged S2 over M samples of the analog input AIN. When the averaged sign bit S2 is the same as S1, in step 470, the additional capacitance added in step 460 is insufficient to change the sign and polarity of the correlation error ΔT. The additional capacitance and delay added in step 460 should remain enabled during further testing. The inverted indicator F is cleared.

[0085] When the averaged sign bit S2 is opposite to S1, step 470, the extra capacitance added in step 460 is excessive. The added capacitance and delay change the sign and polarity of the associated error ΔT. The extra capacitance and delay added in step 460 are removed by subtracting the added LSB bit Q in all SAR (CS) of the selected channel group U or V, step 466. Step 466 cancels step 460. The inversion indicator F is incremented.

[0086] When the inversion indicator F is less than the inversion limit FL, step 472, then add another LSB to all SAR(CS) in the selected channel CS, U or V, step 460. Average the new symbol bit S2 with the new SAR(CS) setting, step 464, and if S2 is not equal to the original symbol bit S1, subtract the added LSB bits, steps 470, 466.

[0087] This process is repeated by adding 1 LSB in steps 460-472 until F reaches the inversion limit FL, step 472. The inversion limit FL can be set to a value as small as 1 or larger for better robustness.

[0088] Then, for any other pair U, V, repeat the process from step 442 to step 476. Once all possible pair U, V in layer L have been processed, the next layer L+1 in the autocorrelator binary tree can be processed by repeating the process from step 442 for layer L = L+1. Finally, layer L has only one pair and one autocorrelator.

[0089] Figure 14 The diagram shows a non-binary tree for the autocorrelator and multiplexer. While binary trees are very efficient, there may be a non-binary number of ADC channels N. For example, there may be N = 6 ADC channels that generate outputs Y1, Y2, Y3...Y6.

[0090] For N=6 channels, there are N / 2=3 multiplexer correlators 700, 702, and 704 in the first layer of the non-binary tree. The second layer has a single multiplexer correlator 708, which receives the multiplexed output YM14 from the first-layer multiplexer correlator 700 and the multiplexed output YM25 from the first-layer multiplexer correlator 702.

[0091] The first-level multiplexed output YM36 from the multiplexer 704 is bypassed and executed in the second level, and is directly input to the third-level multiplexer 712. The third-level multiplexer 712 also receives YM1425 from the multiplexer 708 in the second level.

[0092] The third-level multiplexer correlator 712 operates at Fs, the second-level multiplexer correlator 708 operates at Fs / 2, and the first-level multiplexer correlators 700, 702, and 704 operate at Fs / 4. Other non-binary even values ​​N can be replaced if needed, and the non-binary tree can be adjusted.

[0093] Figure 15 The diagram shows a non-binary odd-numbered tree of autocorrelators and multiplexers. In this alternative, there are an odd number (N=7) of ADC channels that generate outputs Y1, Y2, Y3...Y7.

[0094] For 6 out of N=7 channels, there are N / 2=3 multiplexer correlators 700, 702, and 704 in the first level of the non-binary tree. The second level has two multiplexer correlators 708 and 710. Multiplexer correlator 708 receives the multiplexed output YM15 from the first-level multiplexer correlator 700 and the multiplexed output YM26 from the first-level multiplexer correlator 702.

[0095] Multiplexer 710 receives multiplexed output YM37 from multiplexer 704 and Y4 directly from ADC 4, which is bypassed in the first layer.

[0096] The third-layer multiplexer correlator 712 receives YM1526 from the second-layer multiplexer correlator 708 and YM374 from the second-layer multiplexer correlator 710.

[0097] The third-level multiplexer correlator 712 operates at Fs, the second-level multiplexer correlators 708 and 710 operate at Fs / 2, and the first-level multiplexer correlators 700, 702, and 704 operate at Fs / 4. Other non-binary odd values ​​N can be replaced if needed, and the non-binary tree can be adjusted.

[0098] Figure 16 The diagram illustrates FIR filtering of the ADC outputs. A Finite Impulse Reaction (FIR) filter 740 can be input to each ADC output Y(J) before it is input to the autocorrelator 50. Without FIR filtering, multiplexing is performed directly on the ADC output Y(J). The FIR filter 740 can also be added to the multiplexed input of the autocorrelator 50 on a second layer or any other autocorrelator on a higher layer.

[0099] As long as the autocorrelation derivative of the FIR filter 740 is known, the FIR filter 740 can act as a low-pass or band-pass filter for calibration. FIR filtering helps to constrain the polarity of its autocorrelation derivative to a well-defined value or reduction for calibrating alternating ADCs within a known frequency range. Because the autocorrelation derivative is frequency-dependent, FIR filtering can prevent any potential convergence problems during calibration.

[0100] Theoretical model of alternating ADC

[0101] Figure 17 The model of an alternating ADC is shown. A first sampler 152 samples the analog input X(S) as a function H1(S). The function H1(S) is multiplied by a first multiplier 158 by a first delay 156D1(T) to generate X, which is input to the first ADC 154. S1 (S). In the second channel, the analog input X(S) is also sampled by the second sampler 162 and used as a function H2(S). The function H2(S) is multiplied by the second multiplier 168 by the second delay 166D2(T) to generate X, which is input to the second ADC 164. S2 (S). The digital outputs of the first DC154 and the second ADC 164 are multiplexed together by a multiplexer 150 to generate output Y(S).

[0102] The following equations and discussions are provided as theoretical background and are not intended to limit the invention or its claims, but are intended for illustrative purposes.

[0103] Assuming a single-pole sampling system, the sampled analog signals (odd) and (even) are given by the following equations:

[0104]

[0105]

[0106] Therefore, the numerical output Y(s) is given by the following equation:

[0107]

[0108] Ideally, if H1(s) = H2(s) = H(s) and ΔT = 0, then

[0109]

[0110] H1(s) effectively eliminates the odd image copy from H2(s), in other words, the bandwidth of X(s) can be doubled as desired due to the reciprocating sampling system. However, since H1(s) ≠ H2(s) if ΔT ≠ 0, an error image (i.e., an uncorrected odd image copy) actually exists.

[0111] Here, due to the following bandwidth mismatch and time phase mismatch, we hope to approximate the error:

[0112]

[0113] Where m is an odd number.

[0114] This provides a basic analysis of the impact of "dynamic error" in the proposed ADC system. Our goal is to evaluate the frequency response of E(s), which, broadly speaking, can be summarized by the exponential term as:

[0115]

[0116] Therefore, the equivalent frequency response of the two sampling systems converges as follows:

[0117] E(s) = H′1(s) - H′2(s)

[0118] Considering the case of reciprocating sampling with mismatch, the following equation is proposed:

[0119]

[0120]

[0121] (Where, Δt represents the time phase mismatch in channel 2 relative to channel 1, and Δω represents the finite bandwidth mismatch in channel 2 relative to channel 1.)

[0122] Equivalently, the equation is proposed as follows:

[0123]

[0124] and

[0125]

[0126] Here, since the cross-product term is negligible compared to the fundamental frequency term, it is not input frequency dependent, so we exclude the effect of gain mismatch on H1'(s) and H2'(s).

[0127] Considering the "dynamic error" E(s), i.e.

[0128] E(s) = H′1(s) - H′2(s)

[0129] Equivalently, neglecting the cross-product term, the equation is as follows:

[0130]

[0131] E bw(s) and E sk (s) Consider the effects of finite bandwidth mismatch and time phase mismatch respectively.

[0132] Obviously, if Δω = 0 and ΔT = 0, then the dynamic errors caused by finite bandwidth mismatch and time phase mismatch are zero.

[0133] However, dynamic errors are frequent, thus requiring calibration to meet the target performance. Therefore, in our case, we need to focus on the time derivative of the dynamic error. Consider the following equation:

[0134]

[0135]

[0136] By restoring the inverse Laplace transform to the time domain, we obtain:

[0137]

[0138]

[0139] From the above equation, we can see that Y(s) = Y ideal (s)·H(s)=X(s)·H(s) (that is, the filtered analog input signal).

[0140] Since H(s) is the desired response of the loop filter typically used in reciprocating channels, the above equation is also the same as the following equation:

[0141]

[0142]

[0143] It should be noted that, depending on the input signal frequency, the effect of H(s) causes finite gain error and phase shift. The input signal frequency does not benefit the odd image replica but will cause mismatch in the two sampling systems.

[0144] In the time domain, the previous equations converge linearly to the following equations:

[0145] y(t)=y ideal (t)+e(t)=x(t)+e bw (t)+e sk (t)

[0146] Considering the absolute value of the dynamic error signal e(t),

[0147]

[0148] For example, if ΔT = + / - 1ps, τSAMP =1 / (2*π*5G)=32ps, and Δω / ω o =1%, then the first-order error term is limited by + / -1.064ps (in modern multi-GS / s ADCs).

[0149] From the above equations, we can see that ΔT and Δω / ω o Both are somewhat related to signal / clock / component mismatch, which can be reduced through proper layout and physical component size, while τ SAMP These are circuit design parameters (PVTvar.).

[0150] To mitigate the impact of dynamic errors, a wider sampling bandwidth (lower τ) can be designed. SAMP To reduce linearity, a wider sampling bandwidth is fundamentally a trade-off with noise, power, and other circuit design physical constraints.

[0151] From the above equations, we can see that the error signal can be summarized as a Taylor series expansion:

[0152]

[0153] Considering the single-carrier signal x(t) = Asin(ωt), the odd and even time derivatives are given by the following equations:

[0154]

[0155] The error signal is proportional to the signal amplitude A and the frequency.

[0156] Error signals appear at angles of 90 degrees, 180 degrees, 270 degrees, etc. (i.e., integers * Fs / 2 ± Fin) -> noise. Both sampling pulses and finite bandwidth mismatch appear as inter-channel pulse width difference errors. Therefore, it is possible to eliminate pulse width difference errors by adjusting the sampling pulse widths with variable delay elements before the sampler to align their effective sampling pulse widths.

[0157] E ΔT [k]=y1[k]y2[k-1]-y1[k-1]y2[k-1]

[0158]

[0159] It is important to note that time-series correlation equals autocorrelation.

[0160]

[0161] With the help of a large number of samples (e.g., 2^20 samples), the polar average value indicates the direction of the variable delay element when the delay should increase or decrease like the comparator of a SAR ADC.

[0162] Alternative embodiments

[0163] The inventors envisioned several other embodiments. For example, the clock can be obtained from other clocks and thus synchronized with them. The clock can be buffered, enabled, and verified via logic. Analog input signals can be buffered in various ways using buffer devices or trees. Although the initial clearing of all bits in the entire SAR has been described, SAR bits can still be initially cleared to a high state instead of a low state. Low-state active bits can be used instead of high-state active bits.

[0164] The binary weighted capacitors 110, 108, 106, 104...102 can be connected to a power supply or some other voltage instead of ground. These capacitors can be powered by p-channel or n-channel transistors, and the bits stored in the SAR delay device 40 can be active high or active low, and these bits can be encoded in various ways and need to be decoded by the decoder in the SAR delay device 40. Although binary weighted capacitors 110, 108, 106, 104...102 have been shown, these capacitors can still have other weight sequences, such as 1C, 1C, 2C, 5C, 11C, 15C, etc., and successive approximation register (SAR) programming can be adjusted for these non-binary weight sequences. The SAR delay device 40 can employ other weighted delay elements (such as resistors, transistors, or buffers of various sizes or weights) instead of having binary weighted capacitors 110, 108, 106, 104...102. Although binary weighted capacitors have been described, other weighting methods, such as decimal weighting, prime weighting, linear weighting, or octal weighting, can be substituted. Digital delay values ​​in SAR can exist in these other number systems, such as octal numbers instead of binary numbers. Other types of delay elements can be substituted, such as parallel current sources, resistors, or various combinations thereof, as well as parallel, series, or combined network devices. Values ​​can be shifted, transformed, or manipulated in various ways.

[0165] Although autocorrelator 50 has been shown for a specific correlation, other autocorrelation functions can be substituted, and autocorrelator 50 can be adjusted to perform these alternative correlation functions. Inversion and complement can be added at various locations. Switches 20, 22, 23, and 24 can be simple transistor switches, transfer transistors, transfer gates, or other types of switches. Sample delay device 146 is implemented as a latch, other memory element, or a delay device with combinational logic including NAND gates, NOR gates, XOR gates, and XNOR gates. The p-channel or n-channel driven to power or ground can be used as a delay element instead of using capacitors for delay elements, MOSFETs, FinFETs, or other devices.

[0166] Although a tree of autocorrelators 50 has been shown, the autocorrelators 50 can still be reused or operated in various series and parallel arrangements. For example, when performing calibration for the first layer, all the autocorrelators 50 of the first layer can operate in parallel; however, then, when performing calibration for the first layer, the multiplexed output from the first-layer multiplexer can be fed back to half of the inputs of the first-layer autocorrelators 50 to generate the second-layer sign bits for the second-layer calibration. Therefore, a hardware instance of the first-layer autocorrelators 50 can be used for all-layer calibration, where the first-layer autocorrelators 50 serve as the second-layer autocorrelators 54.

[0167] Although the operation has been described serially for ease of understanding, parallel operation is still possible. Calibration can be performed serially, one channel pair at a time, or in parallel, where for each channel pair, each ADC channel pair with a different autocorrelation 50 is executed in parallel. Figures 8A-8B Steps 204-234. When executed serially, a single instance of autocorrelator 50 can be used in the hardware, rather than a separate instance of autocorrelator 50.

[0168] It can execute process steps serially or in parallel. The order can be adjusted or modified. Higher-level operations, such as SAR testing and decision logic, can be performed in software or firmware, while lower-level functions, such as generating error sign bits using an autocorrelator 50, can be performed in hardware. It can replace some or all of the calibration routines with hardware, such as programmable logic, FPGAs, or other logic gates on integrated circuits (ICs) or other chips. Various combinations of hardware, software, firmware, etc., can be replaced.

[0169] While a 2-input 1-output multiplexer with two inputs has been shown, larger multiplexers, such as a 4-input 1-output multiplexer with four inputs, can be substituted, where the clock is changed by a larger factor, such as 4. Autocorrelation can be performed on more than two inputs as another alternative. Analog input buffers can be rearranged so that one analog input buffer drives four ADCs instead of two, or a tree structure with multiple layers of analog input buffers can be stored. Higher-order multiplexers can be considered to include multiple 2-input 1-output multiplexers, thus representing a special case of 2-input 1-output multiplexer implementations.

[0170] The average number of samples (M) can be different for foreground and background calibration, and even for different levels of binary trees or for other reasons (such as changing voltage or temperature conditions).

[0171] The analog input signal AIN does not necessarily have to be a sine wave signal, but can be other forms of AC signal, such as a triangular wave, superimposed sine waves of different frequencies, or any wireless baseband signal. These signals can be used as input signals for calibration when the polarity of the autocorrelation derivative can be determined.

[0172] The sign bit can be averaged by setting a trigger for each 1 sign bit and clearing the trigger for each 0 sign bit.

[0173] When the LSB is incremented to maintain the autocorrelation sign inversion by more than FL times, the inversion limit FL can be used to end background calibration. Optionally, background calibration can be ended when the autocorrelation sign inverts for the first time.

[0174] The number of channels N can be binary, non-binary, even, or odd, depending on the tree structure of the multiplexer and autocorrelator. While a 4-channel interleaving has been shown in detail, 8-channel, 7-channel, 6-channel, 16-channel, 32-channel, or N-channel interleaving ADCs are also possible. The channel alternation order can be varied. The alternation can be nested or a long loop on the first layer.

[0175] Additional components can be added to various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also exist. Circuit enabling and disabling can be accomplished by adding transistors or other methods. Transmission gate transistors or transmission gates can be added for isolation. Inverters or additional buffers can be added. Capacitors can be connected in parallel to form a larger capacitor, which has the same edge or perimeter effect across several capacitor sizes. Switches can be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors, or more complex circuits, active or passive, amplifying or non-amplifying.

[0176] The number of digital bits in the ADC can be adjusted. For example, a 15-bit ADC, or an 8-bit ADC, a 6-bit ADC, a 22-bit ADC, or an 18-bit ADC can be used. Different numbers of bits can be swapped for different levels of precision, and the number of bits can be fixed or changed.

[0177] The background section of this invention may include background information about the problem or environment of the invention, rather than a description of prior art by others. Therefore, the material included in the background section is not prior art acknowledged by the applicant.

[0178] Any methods or processes described herein are implemented by machines or computers and are intended to be performed by machines, computers, or other devices, rather than by humans alone without such machine assistance. Tangible results may include reports or displays generated by other machines on display devices (such as computer monitors, projection devices, audio generating devices, and related media devices), and may include hard-copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0179] Any advantages and benefits described may not apply to all embodiments of the invention. When the word "device" is mentioned in a claim element, the applicant intends the claim element to comply with paragraph 6 of section 112 of 35 USC. Typically, one or more words precede the word "device." Words appearing before the word "device" are intended to simplify the reference to the claim element and are not intended to convey structural limitations. Such device-plus-function claims are intended to cover not only the structures described herein for performing functions and their structural equivalents, but also equivalent structures. For example, although nails and screws have different structures, they are equivalent structures because they both perform the function of fastening. Claims that do not apply the word "device" are not intended to comply with paragraph 6 of section 112 of 35 USC. Signals are typically electrical signals, but can be optical signals, such as signals capable of being transmitted over fiber optic lines.

[0180] The foregoing description of embodiments of the invention has been provided for purposes of illustration and description. Extensiveness is not guaranteed, and the embodiments are not intended to be limited to the precise forms disclosed. Numerous modifications and variations can be made based on the foregoing teachings. The scope of the invention is not limited by this detailed description, but is defined by the appended claims.

Claims

1. An alternating analog-to-digital converter (ADC), comprising: There are N channels, where N is an integer of at least 4, and each of the channels includes: An ADC is used to convert a sampled analog input into a digital output with a digital value representing the sampled analog input. Analog switch that samples analog input in response to a delayed clock; The successive approximation register (SAR) is programmed with a delay value during calibration; A variable delay element having a variable delay controlled by the delay value stored in the SAR, the variable delay element delaying the input sampling clock through the variable delay to generate a delayed clock for the analog switch; Multiplexed correlator output tree, each multiplexed correlator includes: A multiplexer receives a tree clock, a first tree input, and a second tree input. The multiplexer generates a tree output by using the tree clock, thereby alternately selecting the first tree input and the second tree input as the output tree for output. An autocorrelation unit receives the first tree input and the second tree input, and the autocorrelation unit generates a correlation symbol for the correlation between the first tree input and the second tree input. The output tree further includes several layers of multiplexed correlators, which include: Each of the first layer multiplexed correlators receives the digital output of the ADC from the first channel of a pair of channels as the first tree input, and each of the first layer multiplexed correlators receives the digital output of the ADC from the second channel of the pair of channels as the second tree input; Each of the second-layer multiplexed correlators receives the tree output from the first multiplexed correlator in the first-layer multiplexed correlator as the first tree input, and each of the second-layer multiplexed correlators receives the tree output from the second multiplexed correlator in the first-layer multiplexed correlator as the second tree input; and The final layer multiplexed correlator has a single multiplexed correlator that receives the tree output from a first multiplexed correlator in the preceding layer as a first tree input, and receives the tree output from a second multiplexed correlator in the preceding layer as a second tree input. The single multiplexed correlator outputs the tree output as the final digital value representing the analog input. The SAR is programmed with a delay value to compensate for time phase mismatch between channels using a successive approximation calibration process, which examines the correlation symbols generated by the autocorrelator to determine the timing for accepting or rejecting test bits in the SAR input to the channels of the autocorrelator.

2. The alternating ADC according to claim 1, wherein, The autocorrelator includes: The first sample delay device delays the first tree input by one pulse of the tree clock to generate a first delayed sample; The second sample delay device delays the second tree input by one pulse of the tree clock to generate a second delayed sample; The first multiplier multiplies the first tree input by the first delayed sample to generate the first product; The second multiplier multiplies the second tree input by the second delayed sample to generate the second product; An adder subtracts the second product from the first product to generate a correlation value, and selects the most significant bit (MSB) of the correlation value as the correlation symbol.

3. The alternating ADC according to claim 2, wherein, The variable delay element includes a plurality of binary weighted capacitors, each of which is enabled by a bit in the SAR.

4. The alternating ADC according to claim 2, wherein, The autocorrelator in each multiplexer in the first layer further includes: A first finite impulse response (FIR) filter is used to filter the first tree input before the first tree input is input to the autocorrelator; A second FIR filter is used to filter the second tree input before it is input to the autocorrelator.

5. The alternating ADC according to claim 2, wherein, The first layer multiplexing correlator includes N / 2 multiplexing correlators; The second-layer multiplexing correlator includes N / 4 multiplexing correlators, wherein when N / 4 is not an integer, N / 4 is rounded down to the nearest integer; The final layer multiplexing correlator includes one multiplexing correlator; The number of layers in the multiplexing correlator is log2(N), rounded up to the nearest integer. The multiplexed correlators form a tree structure.

6. The alternating ADC according to claim 5, wherein, N is a non-binary number; The multiplexed correlator forms a non-binary tree structure.

7. The alternating ADC according to claim 6, wherein, N is an odd number; When N is odd, N / 2 is rounded down to the nearest integer. The multiplexed correlator forms a non-binary odd tree structure.

8. The alternating ADC according to claim 2, further comprising: A successive approximation calibrator used to operate each autocorrelator in the output tree; The successive approximation calibrator averages the correlation symbols from the autocorrelator over M analog input sample ranges, where M is an integer, to generate averaged symbol bits. These averaged symbol bits are used to select a chosen group of SARs. The selected group of SARs adjusts the input delay of the ADC for all channels fed into either the first tree input or the second tree input. (a) Test bit positions are added to the SAR of the selected group, and multiple test averaged symbol bits are generated over the analog input sample range. When the test averaged symbol bits are not equal to the averaged symbol bits, the test bit positions are subtracted, and this process is repeated from (a) for consecutive smaller bit positions in the SAR. Therefore, the average value of the correlation symbol of each autocorrelator in each layer of the output tree is added or subtracted from the consecutive bit positions in the SAR of all channels in the selected group, and all channels in the selected group are fed into the first tree input or the second tree input to the autocorrelator.

9. The alternating ADC according to claim 8, wherein, The tree clock applied to the final layer has a final frequency; Wherein, the frequency of the tree clock applied to the previous layer is the final frequency divided by 2; Wherein, the frequency of the tree clock applied to the first layer is the final frequency divided by N.

10. The alternating ADC according to claim 9, wherein, The frequency of the tree clock applied to the intermediate layer L is the final frequency divided by 2 and multiplied by [log2(N)–L], where L is an integer less than log2(N)–L.

11. The alternating ADC according to claim 8, wherein, The input sampling clock is the tree clock divided by 2 and multiplied by [log2(N)–1].

12. The alternating ADC according to claim 8, wherein, The digital output from the ADC is at least 6 bits.

13. A calibration method for reducing time-phase mismatch between channels in an alternating analog-to-digital converter (ADC), comprising: Clear all bits in the successive approximation register (SAR), which sets a variable input delay between the analog input and the alternating ADCs, each of which samples the analog input and generates an ADC digital output; Each channel has a SAR, an ADC, and an input delay element, wherein the input delay element has a variable input delay set by the SAR. For each pair of channels in the first layer: The ADC digital output is fed from two ADC inputs in a pair of channels into an autocorrelator, and the sign is averaged over multiple sample ranges of the analog input to generate an averaged sign. The autocorrelator generates the sign of the autocorrelation function of the ADC digital output. Check the averaging symbol to select the first or second channel in the channel pair as the selected channel; Set the current bit position to the position of the most significant bit (MSB) of the first layer in the SAR; (a) Set a test bit at the current bit position in the SAR of the selected channel to adjust the variable input delay, and average the symbols generated by the autocorrelator over multiple sample ranges of the analog input to generate test symbols; When the test symbol does not match the averaging symbol, the test bit is cleared; Decrease the current bit position, and repeat from (a) until the current bit position is the least significant bit (LSB) in the SAR; Each autocorrelator in the second layer has a first input and a second input, the first input alternately receiving the ADC digital output from a first pair of channels, and the second input alternately receiving the ADC digital output from a second pair of channels; Among them, the first pair of channels is the first group of channels; The second pair of channels is the second group of channels; Each autocorrelator in the higher layers above the second layer has a first input and a second input, the first input alternately receiving the ADC digital output from a first set of channels, and the second input alternately receiving the ADC digital output from a second set of channels; For each autocorrelator in the second layer and the higher layers: The autocorrelation function is used to generate a sign of the autocorrelation function of the ADC digital output, which is multiplexed together to the first input and the second input, and the sign is averaged over multiple sample ranges of the analog input to generate an averaged sign. The averaging symbol is checked to select either the first group of channels or the second group of channels as the selected group of channels; For the current layer, set the current bit position to the position of the most significant bit (MSB) of the current layer in the SAR; (b) The test bit at the current bit position is added to the previous delay setting in the SAR of each channel in the selected group of channels to adjust the variable input delay, and the symbols generated by the autocorrelator are averaged over multiple sample ranges of the analog input to generate the test symbol; When the test symbol does not match the averaged symbol, the test bit in the SAR is subtracted for each channel in the selected group of channels; Decrease the current bit position, and repeat from (b) until the current bit position is the least significant bit (LSB) in the SAR; and Calibration ends when all autocorrelators in all layers have been used to adjust the settings in the SAR, thereby adjusting the variable input delay to minimize time phase mismatch between all channels.

14. The calibration method according to claim 13, wherein, For the autocorrelator in the first layer, the first input is the ADC digital output input from the first ADC in the channel pair to the autocorrelator, and the second input is the ADC digital output input from the second ADC in the channel pair to the autocorrelator. The first group of channels is the first channel with the first ADC in the channel pair, and the second group of channels is the second channel with the second ADC in the channel pair. The calibration method further includes: Initiate a background calibration process to adjust the settings in the SAR, which were pre-set through calibration; for each autocorrelator, the background calibration process includes: The autocorrelation function is used to generate the sign of the autocorrelation function of the first input and the second input, and the sign is averaged over multiple sample ranges of the simulated input to generate an averaged sign. The averaging symbol is checked to select either the first group of channels or the second group of channels as the selected group of channels; Set the current bit position to the least significant bit (LSB) position in the SAR; (b) The test bit at the current bit position is added to the previous delay setting in the SAR for each channel in the selected group of channels to adjust the variable input delay, and the symbols generated by the autocorrelator are averaged over multiple sample ranges of the analog input to generate the test symbol. When the test symbol matches the averaged symbol, repeat from (b); and When the test symbol does not match the averaged symbol, the test bit in the SAR is subtracted for each channel in the selected group of channels, and the calibration of the autocorrelator is terminated; and Background calibration ends when all autocorrelators in all layers have been used to adjust the settings in the SAR, thereby adjusting the variable input delay to minimize time phase mismatch between all channels.

15. The calibration method according to claim 13, wherein, All autocorrelators in a layer are calibrated in parallel.

16. The calibration method according to claim 13, wherein, A single physical autocorrelation is reused to process multiple layers of the autocorrelation in sequence.

17. The calibration method according to claim 13, wherein, The autocorrelators are arranged in a tree structure, wherein there are N / 2 autocorrelators in the first layer, N / 4 autocorrelators in the second layer, and 1 autocorrelator in the final layer, where N is an integer greater than or equal to 4.

18. The calibration method according to claim 17, wherein, N is a non-binary integer, and N / 4 and N / 2 are rounded down to the nearest integer.

19. A calibrated alternating analog-to-digital converter (ADC), comprising: There are N channels, where N is an integer of at least 4, and each channel includes: An ADC has a sampled analog input and a digital output; A sampling switch is located between the analog input and the sampled analog input, and the sampling switch responds to a delayed clock. Successive Approximation Register (SAR) stores delay settings; A delay element generates a variable delay between the input clock and the delayed clock, wherein the variable delay is determined by a delay setting in the SAR; The output tree of the multiplexed correlator, each multiplexed correlator includes: First input and second input; The multiplexer outputs the first input as a tree output when the layer clock is in the first state, and outputs the second input as the tree output when the layer clock is not in the first state. An autocorrelation generator generates a symbol for an autocorrelation function, the symbol being received by the first input and the second input of the multiplexer; The output tree has N / 2 multiplexed correlators in the first layer, wherein each of the N / 2 multiplexed correlators in the first layer receives the digital output of the ADC in the first channel of one of the N channels as the first input, and each receives the digital output of the ADC in the second channel of one of the N channels as the second input. The output tree has N / 4 multiplexed correlators in the second layer, wherein each of the N / 4 multiplexed correlators in the second layer receives the tree output from the first multiplexed correlator in the first layer as the first input, and each receives the tree output from the second multiplexed correlator in the first layer as the second input; The output tree has a single multiplexed correlator in the final layer, wherein the single multiplexed correlator in the final layer receives the tree output from a first multiplexed correlator in the previous layer as the first input, and receives the tree output from a second multiplexed correlator in the previous layer as the second input. The multiplexed correlator outputs the tree output as the final digital output for calibrating the alternating ADC. The calibrator uses the symbols from each autocorrelator to determine the time to add a test bit to the SAR and the time to remove the test bit from the SAR, wherein all channels of the SAR are input to either the first or second input of the autocorrelator.

20. The alternating ADC according to claim 19, wherein, The calibrator also includes: An averager is used to average the sign bit from the autocorrelator over a range of M analog input samples to generate an averaged sign bit, where M is an integer; The selector uses the averaged sign bit to select a selected group of SARs, which adjusts the delay settings in the SAR for all channels, which are fed into the first input or the second input; A tester is configured to add test bit positions to the selected group of SARs, generate test averaged symbol bits over a range of multiple analog input samples, and subtract the test bit positions when the test averaged symbol bits are not equal to the averaged symbol bits, repeating this process for consecutive smaller bit positions in the SAR. Thus, the sign bit of each autocorrelator in each layer of the output tree is added or subtracted from the consecutive bit positions in the SAR for all channels in the selected group, all channels of the selected group being fed into the first or second input to the autocorrelator.

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