An abnormality processing method and device suitable for echo cancellation equipment
By building a data storage module in the echo cancellation device and establishing data storage and reading rules, the problem of data processing abnormalities in the abnormal situation of the device is solved, ensuring the stable operation of the device and the improvement of communication quality.
Patent Information
- Application Number
- CN202210224600.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-09
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2042-03-09
AI Technical Summary
Existing echo cancellation devices may experience abnormal data processing flow when handling abnormal situations, resulting in a decline in communication quality, especially when device clock differences and voice acquisition devices are damaged or downtime.
By building a data storage module and establishing data storage and reading rules, data storage and exception processing in the echo cancellation data processing process is realized. Specific measures include preset data reading threshold, adding clock generation modules, using FIFO data storage modules, and operating data synchronization modules to ensure that the device can still operate normally under abnormal conditions.
It effectively solves the problem of data processing abnormalities of the echo cancellation equipment in abnormal situations, ensures that the equipment works normally and continuously within 7×24 hours, and improves communication quality.
Smart Images
Figure CN114584661B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an abnormality processing method and device applicable to echo cancellation equipment, and in particular to the technical field of satellite communication. Background Art
[0002] In a telephone conference scenario, in addition to conventional noise interference, there is usually interference from delayed and distorted echoes. This is especially true for long-distance communication scenarios with long delays, such as a satellite telephone conference between two parties communicating over long distances. The echo is so severe that normal conversations cannot be made, so echo cancellation devices are widely used in such scenarios.
[0003] In the prior art, the echo cancellation device needs to be equipped with two voice devices in the actual working process to realize the processing of dual-channel signals. At this time, the difference in the working clocks between the devices will introduce deviations in the data processing process. At the same time, in the actual use process, there is also the possibility that the data processing of the echo cancellation device will be abnormal due to damage or sudden shutdown of the voice collection device. Summary of the invention
[0004] Purpose of the invention: To propose an abnormality handling method and device applicable to echo cancellation equipment to solve the above problems existing in the prior art, so that the echo cancellation equipment can ensure normal operation 24 hours a day, 7 days a week, regardless of any abnormality.
[0005] Technical solution: In the first aspect, a method for handling an abnormality applicable to an echo cancellation device is proposed, and the method specifically comprises the following steps:
[0006] Constructing a data storage module for storing data in the echo cancellation data processing process;
[0007] Establish data storage and reading rules based on the constructed data storage module;
[0008] The data storage and reading rules are called according to the requirements to complete the echo cancellation data processing.
[0009] In some possible implementations of the first aspect, the data storage and reading rules include: a preset data reading threshold. When the read clock is faster than the write clock, if the amount of readable data in the data storage module is less than the threshold, the data storage module is cleared and the output data of the previous level of the current module in the echo cancellation data processing process is re-read.
[0010] The data storage and reading rules also include: presetting a data reading threshold. When the reading clock is slower than the writing clock, if the amount of readable data in the data storage module is greater than the threshold, the data storage module is cleared and the output data of the previous level of the current module in the echo cancellation data processing process is re-read.
[0011] The data storage and reading rules also include: after the communication signal in the echo cancellation data processing process completes synchronization, if it is detected that the synchronization header of the communication signal data frame is lost, the data in the current data storage module is cleared and the synchronization search is restarted.
[0012] In some implementable embodiments of the first aspect, a clock generation module is added to generate the clock required in the echo cancellation data processing process; further, based on a development platform for implementing echo cancellation, a clock of the required rate is generated by using a direct integer multiple frequency division method and a shift register cycle method.
[0013] In some implementation methods of the first aspect, during the echo cancellation data processing, communication signals from different directions are received through the data storage module and the rate is adjusted; further, a storage threshold space of the data storage module is preset, and when the data written into the data storage module exceeds the threshold, the reading operation of the next level process of the current module is started.
[0014] In some implementations of the first aspect, during the communication process, the echo cancellation processing data processing process based on the data storage module further includes the following steps:
[0015] Step 1, obtain the analog signal and convert it into a digital signal that conforms to the frame structure;
[0016] Step 2: adjusting and synchronizing the digital signal rate;
[0017] Step 3: Put the synchronized data into the data storage module for storage;
[0018] Step 4, reading the data in the data storage module and sending it to the echo cancellation device;
[0019] Step 5: Convert the output signal of the echo cancellation device into an analog signal through signal conversion.
[0020] In a second aspect, an abnormality handling device applicable to an echo cancellation device is proposed, and the device specifically comprises:
[0021] A signal conversion module is configured to complete the conversion between digital signals and analog signals;
[0022] A FIFO data storage module is configured to store received data;
[0023] A data synchronization module, configured to read the data in the FIFO data storage module and perform synchronization operations;
[0024] An echo cancellation device is configured to achieve echo cancellation by estimating an echo value during communication;
[0025] The clock generation module is configured to generate clocks of different rates according to requirements.
[0026] The FIFO data storage module further includes: a first FIFO data storage module, a second FIFO data storage module, a third FIFO data storage module and a fourth FIFO data storage module.
[0027] In some implementations of the second aspect, the first FIFO data storage module is configured to receive and store communication data from the near end during the communication process; the second FIFO data storage module is configured to receive and store communication data from the far end during the communication process; the third FIFO data storage module is configured to receive and store communication data after synchronization with the near end during the communication process; and the fourth FIFO data storage module is configured to receive and store communication data after synchronization with the far end during the communication process.
[0028] In some possible implementations of the second aspect, during the communication process, the communication signal is converted from an analog signal into a digital signal that conforms to the E1 frame structure through the signal conversion module, and the FIFO data storage module and the data synchronization module are used to perform rate adjustment and synchronization; the synchronized data is then echo-cancelled using an echo cancellation device, and the processed output data is passed to the signal conversion module to convert the digital signal into an analog signal, thereby completing the communication after echo cancellation.
[0029] Beneficial effects: The present invention proposes an abnormality handling method and device applicable to echo cancellation equipment, which reduces the poor communication quality caused by echoes during communication by adding an echo cancellation device. At the same time, for abnormal problems generated during the use of the echo cancellation equipment, the data processing flow abnormality is effectively solved by adding a data storage module and reading and writing rules. In addition, the present invention can also ensure that the echo cancellation equipment can work normally 24 hours a day, 7 days a week, regardless of any abnormality. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a schematic diagram of the echo cancellation principle in the prior art.
[0031] Figure 2 It is a schematic diagram of the echo cancellation data transmission process of the present invention.
[0032] Figure 3 This is a schematic diagram of 4.096MHz and 2.048MHz clock generation according to the present invention.
[0033] Figure 4 This is a schematic diagram of 8KHz clock generation according to the present invention.
[0034] Figure 5Schematic diagram of the rate adjustment scheme of the present invention.
[0035] Figure 6 This is a schematic diagram of the interface of the E1 data synchronization module of the present invention.
[0036] Figure 7 This is a schematic diagram of the output after E1 data synchronization is completed in the present invention.
[0037] Figure 8 This is a block diagram of the working mechanism of FIFO3 and FIFO4 of the present invention.
[0038] Fig. 9 This is a block diagram of the exception handling mechanism of the present invention. DETAILED DESCRIPTION
[0039] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.
[0040] The applicant believes that the echo cancellation principle in the prior art is as follows Figure 1 As shown in the figure, the near-end speech signal x1(t) will generate an echo d(t) at the far end, and then the far-end transmission signal becomes x2(t)+d(t), where x2(t) is the far-end useful speech signal. Adding echo cancellation equipment in the transmission link will generate an echo estimate based on the near-end signal adaptively adjusted. The far-end signal is transmitted to the near-end after passing through the echo cancellation device. At this time, the signal received by the near-end is In order to achieve the above echo cancellation, two voice devices are required in actual applications to process dual-channel signals. The difference in the working clocks between the devices will introduce deviations in the data processing process. At the same time, in actual use, there is also the possibility of damage or sudden shutdown of the voice acquisition device, which will lead to abnormal data processing of the echo cancellation device.
[0041] Based on the demand for group echo cancellation and to address the problems existing in the prior art, this application proposes an exception handling method and device suitable for echo cancellation equipment, which converts analog signals and data signals through E1 telephones, and proposes a corresponding exception handling method by analyzing the causes of abnormal data.
[0042] Embodiment 1
[0043] In one embodiment, a method for handling an abnormality applicable to an echo cancellation device is provided, the method specifically comprising the following steps:
[0044] Step 1, obtain the analog signal and convert it into a digital signal that conforms to the frame structure;
[0045] Step 2: adjusting and synchronizing the digital signal rate;
[0046] Step 3: Put the synchronized data into the FIFO module for storage;
[0047] Step 4, read the data in the FIFO module and send it to the echo cancellation device;
[0048] Step 5: Convert the output signal of the echo cancellation device into an analog signal through signal conversion.
[0049] In a preferred embodiment, Figure 2 As shown in the figure, when developing based on the FPGA platform, the chip IDT82V2081 is used for E1 data collection, and the chip ZL50232 is used for echo cancellation processing. The entire data processing process is: converting the analog signal into a digital signal that conforms to the E1 frame structure for rate adjustment, synchronization and other operations; then sending the synchronized E1 data to the echo cancellation device; finally, transmitting the output data of the echo cancellation device to the input end of the E1 device, and the E1 device converts the E1 data that has completed echo cancellation into an analog signal. Specifically, the meanings of the characters involved in the accompanying drawings are as follows: MCLK_P1 represents the working clock of the proximal driver chip, MCLK_P2 represents the working clock of the distal driver chip, TCLK_P1 represents the proximal data acquisition clock, TCLK_P2 represents the distal data acquisition clock, RCLK_P1 represents the proximal data output clock, RCLK_P2 represents the distal data output clock, RD_P1 represents the proximal write data signal, RD_P2 represents the distal write data signal, C4i represents the working clock of the echo cancellation device, F0i represents the frame header indication signal of the E1 data, TD_P1 represents the proximal receiving end, TD_P2 represents the distal receiving end, FIFO1 represents the first FIFO data storage module, FIFO2 represents the second FIFO data storage module, FIFO3 represents the third FIFO data storage module, FIFO4 represents the fourth FIFO data storage module, Sin represents the proximal input interface of the echo cancellation device, Rin represents the distal input interface of the echo cancellation device, Rout represents the output interface corresponding to Rin, and Sout represents the output interface corresponding to Sin.
[0050] Embodiment 2
[0051] In a further embodiment based on the first embodiment, since a plurality of devices are involved in the process of implementing echo cancellation, clocks of a plurality of rates need to be generated according to requirements during the processing.
[0052] Specifically, based on the overall clock rate of the system, a direct integer multiple frequency division method and a shift register are used for generation.
[0053] In the preferred embodiment, for E1 equipment, according to the three purposes of driver chip operation, data collection and data output, there will be three clocks: MCLK, TCLK and RCLK, and the rates of these three clocks are all 2.048MHz. For echo cancellation equipment, two clocks, C4i and F0i, are required, where C4i is the working clock of the echo cancellation equipment, under which the echo cancellation equipment reads and outputs data, and its rate is 4.096MHz; F0i is the frame header indication signal of E1 data, provided by the outside world, and its rate is 8KHz.
[0054] When developing based on the FPGA platform, the FPGA platform is EP3C16F484I7 and the system clock is 16.384MHz. Figure 3 As shown, the clocks with the required rates of 4.096MHz and 2.048MHz can be generated by direct integer multiple division. Figure 4 As shown, for an 8KHz clock, its waveform characteristics are utilized to generate it cyclically using a shift register, and the array Syn[1-511] is set to {0, 1, 1, ..., 1}, and the following operations are performed under a 4.096MHz clock.
[0055]
[0056] Embodiment 3
[0057] In a further embodiment based on the first embodiment, the communication process involves receiving voice signals from two directions, so two E1 chips are required. Although the main clocks of the two chips are of the same source, due to the differences in actual work, the output clocks of the two E1 chips are not strictly synchronized. In order to improve the convenience of subsequent data processing, the output data of the two E1 chips are adjusted at a rate.
[0058] Specifically, Figure 5 As shown, in order to improve the convenience of subsequent data processing, the output data of the two E1 chips are adjusted by FIFO. In the process of data reading, for FIFO1 and FIFO2, when the device is turned on, data is obtained from the E1 device. When the data written in both exceeds the preset 2560 bits, the data reading operation is allowed.
[0059] In the preferred embodiment, it is assumed that the received E1 data is stable, that is, the relative positions of the frame header, data, and possible signaling do not change within a period of time. Figure 6As shown, the frame synchronization module Syn_for_E1 obtains E1 data, corresponding timing signals and corresponding enable signals from the previous module. At this time, the position of the obtained E1 data in the frame structure is unknown and random, and then outputs the enable signal and the corresponding synchronization data. Figure 7 As shown, the function of the frame synchronization module Syn_for_E1 is to output the frame header indication and the E1 data aligned with the frame header after finding the frame header position.
[0060] Embodiment 4
[0061] In a further embodiment based on the first embodiment, when the echo cancellation module receives data, in order to ensure that the frame header position of the data is aligned with the input signal, a new storage module is inserted between the synchronization data and the echo cancellation module.
[0062] Specifically, Figure 8 As shown, FIFO3 and FIFO4 storage modules are inserted between the synchronization data and echo cancellation modules. These two FIFO storage modules use the "Frame_start" generated by the previous level E1 data synchronization module as a write indication, which can ensure that the stored data are all synchronized data.
[0063] In a preferred embodiment, when the number of data written by the two FIFO storage modules is greater than 1024, the read enable "Ena_for_rd" is pulled high to realize data reading. Since "CLK_2048" and "CLK_4096" are of the same source, FIFO3 and FIFO4 can use the same read enable without deviation in data collection.
[0064] The output interfaces of the echo cancellation module ZL50232 are "Sout" and "Rout", and its working clock rate is 4.096MHz. Each valid data lasts for two clock cycles, which is equivalent to an effective data rate of 2.048MHz. Therefore, it can be directly connected to the input interface of the E1 chip IDT82V8021.
[0065] Embodiment 5
[0066] In a further embodiment based on the first embodiment, a clock module is introduced to synchronize the working frequencies between devices. However, although the speeds of multiple clocks are consistent, their phases are different, which leads to differences in the pace of data reading and writing, and thus causes empty reading or full writing, resulting in abnormal data processing flow. In addition, when the execution device in the echo cancellation process crashes or works abnormally, abnormal data processing flow may also occur.
[0067] Specifically, Figure 2As shown in the figure, in the process of echo cancellation, although the clocks RCLK_P1, RCLK_P2 and CLK_2048 have the same speed, their phases are different, that is, the reading and writing pace of FIFO1 and FIFO2 are different, which will cause one of them to read empty or write full, and then cause the whole data processing flow to be abnormal. In addition, if the near-end or far-end signal transmission equipment crashes or works abnormally, the E1 data synchronization module will be in the synchronization search stage and "Frame_start" will be in a low level, which will cause FIFO3 or FIFO4 to read empty or write full, and then cause the whole data processing flow to be abnormal.
[0068] In response to abnormal situations in the data processing flow, this embodiment implements abnormal processing by adding a reset operation on the FIFO module. When reading E1 frame data, a threshold value of the amount of data that can be read by the FIFO is preset. When the threshold condition is met, the FIFO module is cleared and data reading starts again.
[0069] In a preferred embodiment, the specific implementation process is as follows Fig. 9 As shown, FIFO1 and FIFO2 are used to store the output data of the E1 module. Combining various factors, the present invention sets the depth of FIFO1 and FIFO2 to 16384, and the bit width of the input and output data is 1 bit, so that the maximum storage depth of FIFO is 64 E1 frames. For the case where the read clock is faster than the write clock, in order to prevent abnormalities caused by FIFO1 or FIFO2 reading empty, it is set that when the readable data volume of FIFO1 / FIFO2 is less than 24 after starting data reading, FIFO1 and FIFO2 are cleared, and the output data of the E1 module is restarted; for the case where the read clock is slower than the write clock, in order to prevent abnormalities caused by FIFO1 or FIFO2 being full, it is set that when the written data exceeds 16000, FIFO1 and FIFO2 are cleared, and the output data of the E1 module is restarted.
[0070] In case of sudden downtime or abnormal operation of input devices, the E1 data synchronization module is set to maintain synchronization. If the E1 data synchronization header is detected to be lost, the synchronization indication "Frame_start" is pulled down, and FIFO3 and FIFO4 are cleared at the same time and the synchronization search is restarted. Since both input signals need to be synchronized before writing, it will not cause one side to be full; since the read and write clocks of FIFO3 and FIFO4 are kept in the same phase, there will be no situation where one side is read empty.
[0071] Embodiment 6
[0072] In one embodiment, an abnormality handling device applicable to an echo cancellation device is provided. The device is used to implement an abnormality handling method applicable to the echo cancellation device, specifically comprising:
[0073] A signal conversion module is configured to complete the conversion between digital signals and analog signals;
[0074] A FIFO data storage module is configured to store received data;
[0075] A data synchronization module, configured to read the data in the FIFO data storage module and perform synchronization operations;
[0076] An echo cancellation device is configured to achieve echo cancellation by estimating an echo value during communication;
[0077] The clock generation module is configured to generate clocks of different rates according to requirements.
[0078] The FIFO data storage module further includes: a first FIFO data storage module, a second FIFO data storage module, a third FIFO data storage module and a fourth FIFO data storage module. The first FIFO data storage module is configured to receive and store communication data from the near end during the communication process; the second FIFO data storage module is configured to receive and store communication data from the far end during the communication process; the third FIFO data storage module is configured to receive and store communication data after synchronization with the near end during the communication process; and the fourth FIFO data storage module is configured to receive and store communication data after synchronization with the far end during the communication process.
[0079] In a further embodiment, during the communication process, when a communication request is sent from the near end to the far end, the communication signal generated by the near end is first converted into a digital signal that conforms to the E1 frame structure through a signal conversion module, and transmitted to the first FIFO data storage module for storage; secondly, the data in the first FIFO data storage module is read according to a preset reading rule, and the digital signal is synchronized using a data synchronization module; thirdly, the synchronized digital signal is stored using a third FIFO data storage module; from this, the echo cancellation device reads the data in the third FIFO data storage module according to a preset data reading rule to perform echo cancellation; finally, the output data of the echo cancellation device is transmitted to the signal conversion module at the far end to convert the digital signal into an analog signal, thereby completing the communication after echo cancellation.
[0080] In a further embodiment, during the communication process, when a communication request is sent from the far end to the near end, the communication signal generated by the far end is first converted into a digital signal that conforms to the E1 frame structure through the signal conversion module, and transmitted to the second FIFO data storage module for storage; secondly, the data in the second FIFO data storage module is read according to a preset reading rule, and the digital signal is synchronized using the data synchronization module; thirdly, the synchronized digital signal is stored using the fourth FIFO data storage module; from this, the echo cancellation device reads the data in the fourth FIFO data storage module according to the preset data reading rule to perform echo cancellation; finally, the output data of the echo cancellation device is transmitted to the signal conversion module at the near end to convert the digital signal into an analog signal, thereby completing the communication after echo cancellation.
[0081] In a further embodiment, the clock generation module is used to generate the clock required in the entire communication process. Based on the FPGA platform EP3C16F484I7, the required clock is generated by direct integer multiple frequency division or shift register cycle operation according to different requirements.
[0082] In a further embodiment, when a FIFO data storage module is used to adjust the communication signal rate, for the first FIFO data storage module and the second FIFO data storage module, data is obtained from the signal conversion module when the device is turned on, and data reading operations are allowed to be started when the data written in both modules exceeds a threshold.
[0083] In a further embodiment, if the received E1 data is stable, that is, the relative positions of the frame header, data, and possible signaling do not change within a period of time, the data synchronization module obtains the communication signal, the corresponding timing signal, and the corresponding enable signal from the previous module, and the position of the acquired communication data in the frame structure is unknown and random. The function of the synchronization module is to output the frame header indication and the communication data aligned with the frame header after finding the frame header position.
[0084] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes may be made to it in form and detail without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims
1. An abnormality handling method applicable to an echo cancellation device, characterized in that: The specific steps include: Constructing a data storage module for storing data in the echo cancellation data processing process; Data storage and reading rules are established based on the constructed data storage module; the data storage and reading rules include: A data reading threshold is preset, and when the reading clock is faster than the writing clock, if the amount of readable data in the data storage module is less than the threshold, the data storage module is cleared, and the output data of the previous level of the current module in the echo cancellation data processing process is re-read; A data reading threshold is preset, and when the reading clock is slower than the writing clock, if the amount of readable data in the data storage module is greater than the threshold, the data storage module is cleared, and the output data of the previous level of the current module in the echo cancellation data processing process is re-read; After the communication signal in the echo cancellation data processing process completes synchronization, if it is detected that the synchronization header of the communication signal data frame is lost, the data in the current data storage module is cleared and the synchronization search is restarted; Calling the data storage and reading rules according to the requirements to complete the echo cancellation data processing; in the echo cancellation data processing process, receiving the communication signals from different directions through the data storage module and adjusting the rate; Furthermore, a storage threshold space of the data storage module is preset, and when the data written into the data storage module exceeds the threshold, the read operation of the next level process of the current module is started.
2. The abnormality handling method applicable to the echo cancellation device according to claim 1, characterized in that: Generate the clock required in the echo cancellation data processing process by adding a clock generation module; Furthermore, based on the development platform for implementing echo cancellation, a clock of a required rate is generated by using a direct integer multiple frequency division method and a shift register cycle method.
3. An application method of the abnormality handling method applicable to echo cancellation equipment according to claim 1, characterized in that: During the communication process, the echo cancellation processing data processing process based on the data storage module further includes the following steps: Step 1, obtain the analog signal and convert it into a digital signal that conforms to the frame structure; Step 2: adjusting and synchronizing the digital signal rate; Step 3: Put the synchronized data into the data storage module for storage; Step 4, reading the data in the data storage module and sending it to the echo cancellation device; Step 5: Convert the output signal of the echo cancellation device into an analog signal through signal conversion.
4. An abnormality handling device applicable to an echo cancellation device, used to implement any one of the methods of claims 1-3, characterized in that: Specifically include: A signal conversion module is configured to complete the conversion between digital signals and analog signals; A FIFO data storage module is configured to store received data; A data synchronization module, configured to read the data in the FIFO data storage module and perform synchronization operations; An echo cancellation device is configured to achieve echo cancellation by estimating an echo value during communication; A clock generation module is configured to generate clocks of different rates according to requirements; The FIFO data storage module further includes: a first FIFO data storage module, a second FIFO data storage module, a third FIFO data storage module and a fourth FIFO data storage module.
5. The abnormality processing device applicable to the echo cancellation device according to claim 4, characterized in that: The first FIFO data storage module is configured to receive and store communication data from the near end during the communication process; The second FIFO data storage module is configured to receive and store remote communication data during the communication process; The third FIFO data storage module is configured to receive and store the communication data after near-end synchronization during the communication process; The fourth FIFO data storage module is configured to receive and store the communication data after remote synchronization during the communication process.
6. The abnormality processing device applicable to the echo cancellation device according to claim 4, characterized in that: During the communication process, the communication signal is converted into a digital signal conforming to the E1 frame structure by the signal conversion module, and the FIFO data storage module and the data synchronization module are used for rate adjustment and synchronization; The synchronized data is then echo-cancelled using an echo cancellation device, and the processed output data is passed to a signal conversion module to convert digital signals into analog signals, thereby completing communication after echo cancellation.
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