Shift register and driving method, light emitting control driving circuit, and display device

Abstract

A shift register comprises: an input circuit, which transmits the first signal of the first signal input terminal to the first node in response to a first clock signal of the first clock signal terminal and a second signal of the second signal input terminal, and transmits the second signal to the first node in response to the first clock signal and the first signal; a first control circuit, which transmits the first clock signal to the second node in response to the voltage of the first node, and transmits the first voltage of the first voltage terminal to the second node in response to the first clock signal; a second control circuit, which transmits the second voltage of the second voltage terminal to the third node in response to the voltage of the first node, and transmits the second clock signal to the third node in response to the voltage of the second node and the second clock signal; an output circuit, which transmits the first voltage to the signal output terminal in response to the voltage of the first node, and transmits the second voltage to the signal output terminal in response to the voltage of the third node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method, a light emitting control driving circuit, and a display device. Background Art

[0002] Self-luminous devices have the advantages of high brightness, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, and high luminous efficiency. They are widely used in various terminal display products with high-resolution color screens. Summary of the invention

[0003] In one aspect, a shift register is provided. The shift register comprises an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is coupled to a first signal input terminal, a second signal input terminal, a first clock signal terminal and a first node. The first control circuit is coupled to the first node, the first clock signal terminal, a first voltage terminal and a second node. The second control circuit is coupled to the first node, the second node, the second voltage terminal, the second clock signal terminal and a third node. The output circuit is coupled to the first node, the third node, the first voltage terminal, the second voltage terminal and a signal output terminal.

[0004] The input circuit is configured to transmit a first signal received at the first signal input terminal to the first node in response to a first clock signal received at the first clock signal terminal and a second signal received at the second signal input terminal, and to transmit a second signal received at the second signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal and the first signal received at the first signal input terminal.

[0005] The first control circuit is configured to transmit a first clock signal received at the first clock signal terminal to the second node in response to a voltage of the first node, and to transmit a first voltage of the first voltage terminal to the second node in response to the first clock signal.

[0006] The second control circuit is configured to transmit the second voltage of the second voltage terminal to the third node in response to the voltage of the first node, and to transmit the second clock signal to the third node in response to the voltage of the second node and a second clock signal received at the second clock signal terminal.

[0007] The output circuit is configured to transmit a first voltage at the first voltage terminal to the signal output terminal in response to a voltage at the first node, and to transmit a second voltage at the second voltage terminal to the signal output terminal in response to a voltage at the third node.

[0008] In some embodiments, the input circuit includes: a first input subcircuit, a second input subcircuit and a third input subcircuit. The first input subcircuit is coupled to the first signal input terminal, the second signal input terminal and the third input subcircuit. The second input subcircuit is coupled to the first signal input terminal, the second signal input terminal and the third input subcircuit. The third input subcircuit is also coupled to the first clock signal terminal and the first node.

[0009] The first input subcircuit is configured to transmit the second signal to the third input subcircuit in response to the first signal. The second input subcircuit is configured to transmit the first signal to the third input subcircuit in response to the second signal. The third input subcircuit is configured to transmit the signal from the first input subcircuit to the first node and transmit the signal from the second input subcircuit to the first node in response to the first clock signal.

[0010] In some embodiments, the first input subcircuit includes a first transistor, a control electrode of the first transistor is coupled to the first signal input terminal, a first electrode of the first transistor is coupled to the second signal input terminal, and a second electrode of the first transistor is coupled to the third input subcircuit.

[0011] In some embodiments, the second input subcircuit includes a second transistor. A control electrode of the second transistor is coupled to the second signal input terminal, a first electrode of the second transistor is coupled to the first signal input terminal, and a second electrode of the second transistor is coupled to the third input subcircuit.

[0012] In some embodiments, the third input subcircuit includes a third transistor. A control electrode of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the first input subcircuit and the second input subcircuit, and a second electrode of the third transistor is coupled to the first node.

[0013] In some embodiments, the third input subcircuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the first clock signal terminal, the first electrode of the fourth transistor is coupled to the first input subcircuit, and the second electrode of the fourth transistor is coupled to the first node. The control electrode of the fifth transistor is coupled to the first clock signal terminal, the first electrode of the fifth transistor is coupled to the second input subcircuit, and the second electrode of the fifth transistor is coupled to the first node.

[0014] In some embodiments, the output circuit includes a first output subcircuit and a second output subcircuit. The first output subcircuit is coupled to the third node, the second voltage terminal, and the signal output terminal. The second output subcircuit is coupled to the first node, the first voltage terminal, and the signal output terminal. The first output subcircuit is configured to transmit the second voltage to the signal output terminal in response to the voltage of the third node. The second output subcircuit is configured to transmit the first voltage to the signal output terminal in response to the voltage of the first node.

[0015] In some embodiments, the first output subcircuit includes a sixth transistor and a first capacitor. The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the signal output terminal. The first terminal of the first capacitor is coupled to the second node, and the second terminal of the first capacitor is coupled to the first voltage terminal.

[0016] In some embodiments, the second output subcircuit includes a seventh transistor, wherein a control electrode of the seventh transistor is coupled to the first node, a first electrode of the seventh transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the signal output terminal.

[0017] In some embodiments, the first control circuit includes a first control subcircuit and a second control subcircuit. The first control subcircuit is coupled to the first clock signal terminal, the first voltage terminal and the second node. The second control subcircuit is coupled to the first node, the first clock signal terminal and the second node. The first control subcircuit is configured to transmit the first voltage to the second node in response to the first clock signal. The second control subcircuit is configured to transmit the first clock signal to the second node in response to the voltage of the first node.

[0018] In some embodiments, the first control subcircuit includes an eighth transistor. A control electrode of the eighth transistor is coupled to the first clock signal terminal, a first electrode of the eighth transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the second node.

[0019] In some embodiments, the second control subcircuit includes a ninth transistor. A control electrode of the ninth transistor is coupled to the first node, a first electrode of the ninth transistor is coupled to the first clock signal terminal, and a second electrode of the ninth transistor is coupled to the second node.

[0020] In some embodiments, the second control circuit includes: a third control subcircuit and a fourth control subcircuit. The third control subcircuit is coupled to the first node, the third node and the second voltage terminal. The fourth control subcircuit is coupled to the second node, the second clock signal terminal and the third node.

[0021] The third control subcircuit is configured to transmit the second voltage to the third node in response to the voltage of the first node. The fourth control subcircuit is configured to transmit the second clock signal to the third node in response to the voltage of the second node and the second clock signal.

[0022] In some embodiments, the third control subcircuit includes a tenth transistor. A control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the second voltage terminal, and a second electrode of the tenth transistor is coupled to the third node.

[0023] In some embodiments, the fourth control subcircuit includes: an eleventh transistor, a twelfth transistor, and a second capacitor. The control electrode of the eleventh transistor is coupled to the second node, and the first electrode of the eleventh transistor is coupled to the second clock signal terminal. The control electrode of the twelfth transistor is coupled to the second clock signal terminal, the first electrode of the twelfth transistor is coupled to the second electrode of the eleventh transistor, and the second electrode of the twelfth transistor is coupled to the third node. The first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the second electrode of the eleventh transistor and the first electrode of the twelfth transistor.

[0024] In some embodiments, the shift register further comprises a third control circuit. The third control circuit is coupled to the second node, the second voltage terminal, the first node, and the second clock signal terminal. The third control circuit is configured to transmit the second voltage of the second voltage terminal to the first node in response to the voltage of the second node and the second clock signal received at the second clock signal terminal.

[0025] In some embodiments, the third control circuit includes a thirteenth transistor and a fourteenth transistor. The control electrode of the thirteenth transistor is coupled to the second node, the first electrode of the thirteenth transistor is coupled to the second voltage terminal, the control electrode of the fourteenth transistor is coupled to the second clock signal terminal, the first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor, and the second electrode of the fourteenth transistor is coupled to the first node.

[0026] In some embodiments, the shift register further includes a fourth control circuit coupled to the first node and the second clock signal terminal and configured to control the voltage of the first node according to the second clock signal received at the second clock signal terminal.

[0027] In some embodiments, the fourth control circuit includes a third capacitor. A first terminal of the third capacitor is coupled to the second clock signal terminal, and a second terminal of the third capacitor is coupled to the first node.

[0028] In another aspect, a light emitting control driving circuit is provided. The light emitting control driving circuit comprises: a plurality of cascaded shift registers, wherein the first stage shift register of the plurality of cascaded shift registers is the shift register as described in any of the above embodiments.

[0029] In another aspect, a display device is provided, wherein the display device comprises the light emitting control driving circuit as described in the above embodiment.

[0030] In some embodiments, the display device further comprises a processor and a controller. The processor is coupled to the controller. The controller is also coupled to the light emitting control driving circuit. The processor is configured to output a first control signal and a second control signal to the controller.

[0031] The controller is configured to transmit a first signal and a second signal to the light emitting control driving circuit in response to the first control signal, wherein, within a frame period, the first signal has a plurality of first pulses, the second signal has a plurality of second pulses, and the first pulses do not overlap with the second pulses at the same time.

[0032] The controller is also configured to transmit a first signal and a second signal to the light emitting control driving circuit in response to the second control signal, wherein within a frame period, the first signal has a plurality of first pulses and the second signal is a DC signal.

[0033] In some embodiments, the processor is configured to, in response to a startup operation on a specific application, output a first control signal to the controller if the specific application belongs to a preset set; and output a second control signal to the controller if the specific application does not belong to the preset set. The preset set includes at least one application.

[0034] On the other hand, a driving method of a shift register is provided. The shift register includes: an input circuit, a first control circuit and a first output circuit. The input circuit is coupled to a first signal input terminal, a second signal input terminal, a first clock signal terminal and a first node. The first control circuit is coupled to the first node, the first clock signal terminal, a first voltage terminal and a second node. The second control circuit is coupled to the first node, the second node, the second voltage terminal, the second clock signal terminal and a third node. The output circuit is coupled to the first node, the third node, the first voltage terminal, the second voltage terminal and a signal output terminal.

[0035] The driving method comprises:

[0036] The input circuit transmits a first signal received at the first signal input terminal to the first node in response to a first clock signal received at the first clock signal terminal and a second signal received at the second signal input terminal, and transmits a second signal received at the second signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal and the first signal received at the first signal input terminal;

[0037] The first control circuit transmits the first clock signal received at the first clock signal terminal to the second node in response to the voltage of the first node, and transmits the first voltage of the first voltage terminal to the second node in response to the first clock signal;

[0038] The second control circuit transmits the second voltage of the second voltage terminal to the third node in response to the voltage of the first node, and transmits the second clock signal to the third node in response to the voltage of the second node and the second clock signal received at the second clock signal terminal;

[0039] The output circuit transmits a first voltage at the first voltage terminal to the signal output terminal in response to the voltage of the first node, and transmits a second voltage at the second voltage terminal to the signal output terminal in response to the voltage of the third node.

[0040] Wherein, within one frame period, the first signal has a plurality of first pulses, and the second signal has a plurality of second pulses; the first pulses and the second pulses do not overlap at the same time.

[0041] In some embodiments, the plurality of first pulses and the plurality of second pulses are arranged periodically, and the interval between a second pulse and a first pulse is approximately half the interval between two adjacent first pulses.

[0042] In some embodiments, within one frame period, the number of the plurality of first pulses and the number of the plurality of second pulses are both 4; and the interval between a second pulse and a first pulse is approximately 1 / 8 of the length of one frame period. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0044] Figure 1A is a structural diagram of a display device according to some embodiments;

[0045] Figure 1B is another structural diagram of a display device according to some embodiments;

[0046] Figure 2 is a structural diagram of a sub-pixel according to some embodiments;

[0047] Figure 3 is a structural diagram of a pixel circuit according to some embodiments;

[0048] Figure 4 is a signal timing diagram of a driving pixel circuit according to some embodiments;

[0049] Figure 5 is a structural diagram of a light emitting device according to some embodiments;

[0050] Fig. 6A is a structural diagram of a shift register according to some embodiments;

[0051] Figure 6B is another structural diagram of a shift register according to some embodiments;

[0052] Figure 7is another structural diagram of a shift register according to some embodiments;

[0053] Figure 8 is another structural diagram of a shift register according to some embodiments;

[0054] Fig. 9 is a signal timing diagram for driving a shift register according to some embodiments;

[0055] Fig.10 is another signal timing diagram for driving a shift register according to some embodiments;

[0056] Fig.11 is a structural diagram of a light emitting control driving circuit according to some embodiments;

[0057] Fig.12 is another structural diagram of a shift register according to some embodiments;

[0058] Fig.13A is another structural diagram of a shift register according to some embodiments;

[0059] Fig. 13B is another structural diagram of a shift register according to some embodiments;

[0060] Fig.14 is another structural diagram of a display device according to some embodiments;

[0061] Fig.15A is a schematic diagram of an application scenario of a display device according to some embodiments;

[0062] Fig. 15B FIG. 4 is a schematic diagram of another application scenario of a display device according to some embodiments. DETAILED DESCRIPTION

[0063] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0064] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0065] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0066] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0067] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0068] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0069] Embodiments of the present disclosure provide a display device. Exemplarily, the display device may be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, the display device may be one of a variety of electronic devices, and the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of the present disclosure do not impose any special restrictions on the specific form of the above-mentioned display device.

[0070] For example, Figure 1A and Figure 1B As shown, the display device 200 includes a display panel 100. The display panel 100 has an active area (AA) and a peripheral area S at least located on one side of the AA area.

[0071] like Figure 1A and Figure 1B As shown, the display panel 100 includes a plurality of sub-pixels P disposed in the AA region. Figure 2 As shown, at least one sub-pixel P (eg, each sub-pixel P) includes a pixel circuit 20 and a light emitting device L. The pixel circuit 20 is coupled to the light emitting device L. The pixel circuit 20 is configured to drive the light emitting device L to emit light.

[0072] It should be noted that the arrangement of sub-pixels can be designed according to actual conditions and is not limited here. Figure 1A and Figure 1B As shown, a plurality of sub-pixels P are arranged in an array, wherein sub-pixels P arranged in a row along the X direction are called sub-pixels in the same row, and sub-pixels P arranged in a row along the Y direction are called sub-pixels in the same column.

[0073] Furthermore, the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, and can be designed according to actual conditions. Exemplarily, the pixel circuit is composed of electronic devices such as thin film transistors (TFT), capacitors (C), etc. For example, the pixel circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two thin film transistors (multiple switching transistors and a driving transistor) and at least one capacitor, for example, refer to Figure 3 The pixel circuit 20 may include a capacitor Cst and seven transistors (six switch transistors M1, M2, M3, M5, M6 and M7 and one driving transistor M4) to form a 7T1C structure.

[0074] For example, Figure 3 As shown, the control electrode (gate) of a portion of the switch transistors (eg, M1, M7) is used to receive Figure 4 The control electrodes of the other switching transistors (eg, M2, M3) are used to receive the reset signal Reset. Figure 4 The control electrodes of another part of the switch transistors (eg, M5, M6) are used to receive the gate drive signal Gate. Figure 4 The light emitting control signal EM is shown. Figure 3 The working process of the pixel circuit shown includes Figure 4 The three stages shown are the first stage ①, the second stage ② and the third stage ③. For example, in the first stage ①, in response to the reset signal Reset, the transistors M1 and M7 are turned on. The initial signal Initial is transmitted to the control electrode (g) of the driving transistor M4 and the anode of the light-emitting device L through the transistor M1 and the transistor M7, respectively, so as to reset the anode of the light-emitting device L and the control electrode of the driving transistor M4. In the second stage ②, under the control of the gate drive signal Gate, the transistor M2 is turned on, the control electrode g of the driving transistor M4 is coupled to the drain (d), and the driving transistor M4 is in a diode conduction state. At this time, the data signal Data is written to the source (s) of the driving transistor M4 through the transistor M2, and the threshold voltage (Vth) of the driving transistor M4 is compensated. In the third stage ③, under the control of the light-emitting control signal EM, the transistors M5 and M6 are turned on, and the current path between the first power supply signal VDD and the second power supply signal VSS is turned on. The driving current (I sd ) is transmitted to the light-emitting device L through the above-mentioned current path to drive the light-emitting device L to emit light.

[0075] For example, the light emitting device may be a current driven light emitting device such as an LED (light emitting diode) or an OLED (organic light emitting diode). Figure 5 As shown, the light-emitting device L includes a cathode 1202 and an anode 1201, and a light-emitting functional layer 1203 located between the cathode 1202 and the anode 1201. The light-emitting functional layer 1203 may include, for example, a light-emitting layer E, a hole transport layer (HTL) located between the light-emitting layer E and the anode 1201, and an electron transport layer (ETL) located between the light-emitting layer E and the cathode 1202. Of course, in some embodiments, a hole injection layer (HIL) may be provided between the hole transport layer HTL and the anode, and an electron injection layer (EIL) may be provided between the electron transport layer ETL and the cathode 1202 as required.

[0076] Exemplarily, the anode may be formed of a transparent conductive material with a high work function, and its electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum zinc oxide (AZO) and carbon nanotubes, etc.; the cathode may be formed of a material with high conductivity and low work function, and its electrode material may include alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl) or metal single substances such as magnesium (Mg), aluminum (Al), lithium (Li) and silver (Ag). The material of the light-emitting layer can be selected according to the different colors of the light emitted. For example, the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material. For example, in at least one embodiment of the present disclosure, the light-emitting layer may adopt a doping system, that is, a doping material is mixed into the main light-emitting material to obtain a usable light-emitting material. For example, the main light-emitting material may adopt a metal compound material, anthracene derivatives, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, benzene diamine derivatives and triarylamine polymers, etc.

[0077] Since the brightness of the environment in which the display device is located is different under different external conditions, the display device needs to adjust the display brightness to ensure that the user can view the display content normally. For example, the display device can adopt a dimming method of pulse width modulation (PWM) dimming, and by controlling the screen to alternate between light and dark, the screen can display different brightness and adjust the display brightness. That is, the screen is inserted into black multiple times, and the brightness of the display is changed by adjusting the time of black insertion. For example, by pulse width modulation of the light control signal, the light-emitting device is inserted into black multiple times within a frame period, and the light-emitting duration of the light-emitting device is controlled to change the brightness of the screen. However, due to the limitations of the internal circuit of the display device, such as the limited number of black insertions that the IC (Integrated Circuit) can support, the number of black insertions of the display device is small, and it is difficult to achieve a higher refresh rate (for example, 1KHz). In this way, in some application scenarios, such as scanning codes or taking pictures, the display device is prone to recognition abnormalities due to the small number of black insertions.

[0078] The embodiment of the present disclosure provides a shift register SR, such as Fig. 6A As shown, the shift register SR includes: an input circuit 11, a first control circuit 12, a second control circuit 13 and an output circuit 14.

[0079] The input circuit 11 is coupled to the first signal input terminal Iput1, the second signal input terminal Iput2, the first clock signal terminal CLK1 and the first node N1. The first control circuit 12 is coupled to the first node N1, the first clock signal terminal CLK1, the first voltage terminal V1 and the second node N2. The second control circuit 13 is coupled to the first node N1, the second node N2, the second voltage terminal V2, the second clock signal terminal CLK2 and the third node N3. The output circuit 14 is coupled to the first node N1, the third node N3, the first voltage terminal V1, the second voltage terminal V2 and the signal output terminal Oput.

[0080] The input circuit 11 is configured to transmit the first signal received at the first signal input terminal Iput1 to the first node N1 in response to the first clock signal received at the first clock signal terminal CLK1 and the second signal received at the second signal input terminal Iput2; and, in response to the first clock signal received at the first clock signal terminal CLK1 and the first signal received at the first signal input terminal Iput1, transmit the second signal received at the second signal input terminal Iput2 to the first node N1.

[0081] The output circuit 14 is configured to transmit a first voltage of the first voltage terminal V1 to the signal output terminal Oput in response to a voltage of the first node N1, and to transmit a second voltage of the second voltage terminal V2 to the signal output terminal Oput in response to a voltage of the third node N3.

[0082] The first control circuit 12 is configured to transmit the first clock signal received at the first clock signal terminal CLK1 to the second node N2 in response to the voltage of the first node N1, and transmit the first voltage of the first voltage terminal V1 to the second node N2 in response to the first clock signal. In this way, the first control circuit 12 can control the voltage of the second node N2.

[0083] The second control circuit 13 is configured to transmit the second voltage of the second voltage terminal V2 to the third node N3 in response to the voltage of the first node N1, and transmit the second clock signal to the third node N3 in response to the voltage of the second node N2 and the second clock signal received at the second clock signal terminal CLK2. In this way, the second control circuit 13 can control the voltage of the third node N3 so that the output circuit 14 can stably output the second voltage, thereby ensuring the stability and reliability of the signal output by the signal output terminal Oput.

[0084] Exemplarily, the first voltage of the first voltage terminal V1 is a DC voltage, such as a DC low voltage (VGL). For example, the first voltage is (-7) V. Exemplarily, the first voltage of the second voltage terminal V2 is a DC voltage, such as a DC high voltage (VGH). For example, the second voltage is 7V.

[0085] Among them, at different times, the output circuit 14 transmits the first voltage and the second voltage to the signal output terminal Oput, and the signal output terminal Oput outputs the first voltage and the second voltage to the pixel circuit, and the voltages of the corresponding light-emitting control signal are the first voltage and the second voltage, respectively. For example, the shift register SR transmits the low-level first voltage to the signal output terminal Oput, and at this time, the output signal of the signal output terminal Oput is a low-level signal, that is, the light-emitting control signal EM is a low-level signal, for example, the voltage of the light-emitting control signal EM is the first voltage. In this way, reference Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are in a conducting state in response to the low-level light-emitting control signal EM, and transmit the driving signal to the light-emitting device L to drive the light-emitting device L to emit light. For example, the shift register SR transmits the high-level second voltage to the signal output terminal Oput. At this time, the output signal of the signal output terminal Oput is a high-level signal, that is, the light-emitting control signal EM is a high-level signal, for example, the voltage of the light-emitting control signal EM is the second voltage. In this way, reference Figure 3, the transistors M5 and M6 in the pixel circuit 20 are in a cut-off state in response to the high-level light-emitting control signal EM, and will not transmit the driving signal to the light-emitting device L, and the light-emitting device L will not emit light.

[0086] Exemplarily, the duty cycles of the first signal received at the first signal input terminal Iput1 and the second signal received at the second signal input terminal Iput2 are approximately the same. Exemplarily, the first signal and the second signal have a phase difference.

[0087] Exemplarily, the second clock signal and the first clock signal are inverted signals. For example, the phase difference between the second clock signal and the first clock signal is 180°. For example, when the first clock signal is a low-level signal, the second clock signal is a high-level signal; when the first clock signal is a high-level signal, the second clock signal is a low-level signal. For example, the first signal and the second signal will not be high-level signals at the same time.

[0088] For example, within a frame period, the first signal has a plurality of first pulses, and the second signal has a plurality of second pulses. The first pulse and the second pulse do not overlap at the same time. For example, the second pulse is delayed from the first pulse. For example, the number of first pulses of the first signal is equal to the number of second pulses of the second signal. For example, the first pulse and the second pulse are arranged periodically; the time interval between two adjacent first pulses of the first signal is approximately equal to the time interval between two adjacent second pulses of the second signal; the interval between a second pulse and a first pulse is approximately half the interval between two adjacent first pulses. For example, the time interval between two adjacent first pulses of the first signal is approximately u, and the time interval between the first pulse of the first signal and the second pulse of the second signal is approximately (u / 2), that is, the second pulse of the second signal is delayed by approximately (u / 2) compared to the first pulse of the first signal. For example, the phase difference between the first signal and the second signal is approximately half the time interval between two adjacent first pulses of the first signal. For example, within one frame period, when the number of first pulses of the first signal and the number of second pulses of the second signal are both 4, the duration of one frame period is approximately t, the time interval between two adjacent first pulses of the first signal (i.e., the duration of the period of the first signal) is approximately (t / 4), the time interval between two adjacent second pulses of the second signal (i.e., the duration of the period of the second signal) is approximately (t / 4), and the time delay of the second pulse of the second signal compared with the first pulse of the first signal is approximately (t / 8), that is, the phase of the second signal is delayed by approximately (t / 8) compared with the phase of the first signal.

[0089] It can be understood that the input circuit transmits the first signal to the first node, and after a preset time, the input circuit transmits the second signal to the first node. The above-mentioned preset time refers to the time when the phase of the second signal is delayed from the phase of the first signal. For example, if the time length of the phase delay of the second signal compared with the phase of the first signal is about (t / 8), then the preset time is (t / 8).

[0090] In this case, the input circuit in the shift register can transmit the first signal and the second signal to the first node at different times, control the voltage of the second node through the first control circuit, and control the voltage of the third node through the second control circuit, so that the output circuit transmits the first voltage to the signal output terminal, and the signal output terminal outputs a light control signal to make the light-emitting device emit light normally and display a bright state, and the output circuit transmits the second voltage to the signal output terminal so that the light-emitting device does not emit light and displays a dark state, that is, inserts black, so that the display panel alternates between light and dark, and adjusts the overall brightness of the display panel. In addition, the shift register in the embodiment of the present disclosure receives the first signal and the second signal, and can transmit the second voltage to the signal output terminal at different times. Compared with the case where the second voltage is transmitted to the signal output terminal after receiving the first signal, the number of times the second voltage is transmitted to the signal output terminal is increased, so that the number of times the signal output terminal outputs the black insertion signal increases, and the number of times the display panel inserts black according to the output signal increases. In this way, the signal output by the signal output terminal is frequency-multiplied, and the refresh frequency of the display panel is increased.

[0091] Therefore, an embodiment of the present disclosure provides a shift register, wherein the input circuit transmits the first signal to the first node in response to the first clock signal and the second signal; and, in response to the first clock signal and the first signal, transmits the second signal to the first node. The first control circuit transmits the first voltage to the second node in response to the first clock signal, and, in response to the voltage of the first node, transmits the second voltage to the second node. The second control circuit transmits the second clock signal to the third node in response to the voltage of the second node and the second clock signal, and, in response to the voltage of the first node, transmits the second voltage to the third node. The output circuit transmits the first voltage to the signal output terminal in response to the voltage of the first node, and, in response to the voltage of the third node, transmits the second voltage to the signal output terminal. In this way, the shift register receives the first signal and the second signal, and can transmit the second voltage to the signal output terminal at different times, which increases the number of times the second voltage is transmitted to the signal output terminal, so that the number of times the signal output terminal outputs the black insertion signal increases, and the number of times the display panel inserts black according to the output signal increases. In this way, the signal output from the signal output terminal is frequency-multiplied, which increases the refresh frequency of the display panel.

[0092] In some embodiments, Figure 6BAs shown, the input circuit 11 includes a first input subcircuit 111, a second input subcircuit 112 and a third input subcircuit 113. The first input subcircuit 111 is coupled to the first signal input terminal Iput1, the second signal input terminal Iput2 and the third input subcircuit 113. The second input subcircuit 112 is coupled to the first signal input terminal Iput1, the second signal input terminal Iput2 and the third input subcircuit 113. The third input subcircuit 113 is also coupled to the first clock signal terminal CLK1 and the first node N1.

[0093] The first input subcircuit 111 is configured to transmit the second signal to the third input subcircuit 113 in response to the first signal. The second input subcircuit 112 is configured to transmit the first signal to the third input subcircuit 113 in response to the second signal. The third input subcircuit 113 is configured to transmit the signal from the first input subcircuit 111 to the first node N1 and transmit the signal from the second input subcircuit 112 to the first node N1 in response to the first clock signal.

[0094] For example, Figure 7 As shown, the first input subcircuit 111 includes a first transistor T1. The control electrode of the first transistor T1 is coupled to the first signal input terminal Iput1, the first electrode of the first transistor T1 is coupled to the second signal input terminal Iput2, and the second electrode of the first transistor T1 is coupled to the third input subcircuit 113.

[0095] For example, Figure 7 As shown, the second input subcircuit 112 includes a second transistor T2 . A control electrode of the second transistor T2 is coupled to the second signal input terminal Iput2 , a first electrode of the second transistor T2 is coupled to the first signal input terminal Iput1 , and a second electrode of the second transistor T2 is coupled to the third input subcircuit 113 .

[0096] For example, Figure 7 As shown, the third input subcircuit 113 includes a third transistor T3. The control electrode of the third transistor T3 is coupled to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is coupled to the first input subcircuit 111 and the second input subcircuit 112, and the second electrode of the third transistor T3 is coupled to the first node N1.

[0097] When the first input subcircuit 111 includes the first transistor T1 and the second input subcircuit 112 includes the second transistor T2 , the first electrode of the third transistor T3 is coupled to the second electrode of the first transistor T1 and the second electrode of the second transistor T2 .

[0098] For example, Figure 8 As shown, the third input sub-circuit 113 includes a fourth transistor T4 and a fifth transistor T5.

[0099] A control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CLK1 , a first electrode of the fourth transistor T4 is coupled to the first input sub-circuit 111 , and a second electrode of the fourth transistor T4 is coupled to the first node N1 .

[0100] A control electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1 , a first electrode of the fifth transistor T5 is coupled to the second input sub-circuit 112 , and a second electrode of the fifth transistor T5 is coupled to the first node N1 .

[0101] When the first input subcircuit 111 includes the first transistor T1, the first electrode of the fourth transistor T4 is coupled to the second electrode of the first transistor T1. When the second input subcircuit 112 includes the second transistor T2, the first electrode of the fifth transistor T5 is coupled to the second electrode of the second transistor T2.

[0102] In some embodiments, Figure 6B As shown, the output circuit 14 includes a first output subcircuit 141 and a second output subcircuit 142. The first output subcircuit 141 is coupled to the third node N3, the second voltage terminal V2 and the signal output terminal Oput. The second output subcircuit 142 is coupled to the first node N1, the first voltage terminal V1 and the signal output terminal Oput.

[0103] The first output sub-circuit 141 is configured to transmit the second voltage to the signal output terminal Oput in response to the voltage of the third node N3. The second output sub-circuit 142 is configured to transmit the first voltage to the signal output terminal Oput in response to the voltage of the first node N1.

[0104] For example, Figure 7 and Figure 8 As shown, the first output sub-circuit 141 includes a sixth transistor T6 and a first capacitor C1.

[0105] A control electrode of the sixth transistor T6 is coupled to the third node N3 , a first electrode of the sixth transistor T6 is coupled to the second voltage terminal V2 , and a second electrode of the sixth transistor T6 is coupled to the signal output terminal Oput.

[0106] A first terminal of the first capacitor C1 is coupled to the third node N3 , and a second terminal of the first capacitor C1 is coupled to the second voltage terminal V2 .

[0107] For example, Figure 7 and Figure 8 As shown, the second output sub-circuit 142 includes a seventh transistor T7.

[0108] A control electrode of the seventh transistor T7 is coupled to the first node N1 , a first electrode of the seventh transistor T7 is coupled to the first voltage terminal V1 , and a second electrode of the seventh transistor T7 is coupled to the signal output terminal Oput.

[0109] In some embodiments, Figure 6B As shown, the first control circuit 12 includes a first control subcircuit 121 and a second control subcircuit 122. The first control subcircuit 121 is coupled to the first clock signal terminal CLK1, the first voltage terminal V1 and the second node N2. The second control subcircuit 122 is coupled to the first node N1, the first clock signal terminal CLK1 and the second node N2.

[0110] The first control subcircuit 121 is configured to transmit the first voltage to the second node N2 in response to the first clock signal. The second control subcircuit 122 transmits the first clock signal to the second node N2 in response to the voltage of the first node N1.

[0111] For example, Figure 7 and Figure 8 As shown, the first control subcircuit 121 includes an eighth transistor T8. A control electrode of the eighth transistor T8 is coupled to the first clock signal terminal CLK1, a first electrode of the eighth transistor T8 is coupled to the first voltage terminal V1, and a second electrode of the eighth transistor T8 is coupled to the second node N2.

[0112] For example, Figure 7 and Figure 8 As shown, the second control subcircuit 122 includes a ninth transistor T9. A control electrode of the ninth transistor T9 is coupled to the first node N1, a first electrode of the ninth transistor T9 is coupled to the first clock signal terminal CLK1, and a second electrode of the ninth transistor T9 is coupled to the second node N2.

[0113] In some embodiments, Figure 6B As shown, the second control circuit 13 includes a third control subcircuit 131 and a fourth control subcircuit 132. The third control subcircuit 131 is coupled to the first node N1, the third node N3 and the second voltage terminal V2. The fourth control subcircuit 132 is coupled to the second node N2, the second clock signal terminal CLK2 and the third node N3.

[0114] The third control sub-circuit 131 is configured to transmit the second voltage to the third node N3 in response to the voltage of the first node N1 .

[0115] The fourth control sub-circuit 132 is configured to transmit the second clock signal to the third node N3 in response to the voltage of the second node N2 and the second clock signal.

[0116] For example, Figure 7 and Figure 8As shown, the third control subcircuit 131 includes a tenth transistor T10.

[0117] A control electrode of the tenth transistor T10 is coupled to the first node N1 , a first electrode of the tenth transistor T10 is coupled to the second voltage terminal V2 , and a second electrode of the tenth transistor T10 is coupled to the third node N3 .

[0118] For example, Figure 7 As shown, the fourth control subcircuit 132 includes an eleventh transistor T11, a twelfth transistor T12 and a second capacitor C2.

[0119] A control electrode of the eleventh transistor T11 is coupled to the second node N2 , and a first electrode of the eleventh transistor T11 is coupled to the second clock signal terminal CLK2 .

[0120] A control electrode of the twelfth transistor T12 is coupled to the second clock signal terminal CLK2 , a first electrode of the twelfth transistor T12 is coupled to the second electrode of the eleventh transistor T11 , and a second electrode of the twelfth transistor T12 is coupled to the third node N3 .

[0121] A first terminal of the second capacitor C2 is coupled to the second node N2 , and a second terminal of the second capacitor C2 is coupled to the second electrode of the eleventh transistor T11 and the first electrode of the twelfth transistor T12 .

[0122] Among them, Figure 7 and Figure 8 As shown, the second electrode of the eleventh transistor T11, the first electrode of the twelfth transistor T12 and the second end of the second capacitor C2 are coupled to each other at the fourth node N4.

[0123] In some embodiments, Fig. 6A and Figure 6B As shown, the shift register SR further includes a third control circuit 15. The third control circuit 15 is coupled to the second node N2, the second voltage terminal V2, the first node N1 and the second clock signal terminal CLK2.

[0124] The third control circuit 15 is configured to transmit the first voltage of the second voltage terminal V2 to the first node N1 in response to the voltage of the second node N2 and the second clock signal received at the second clock signal terminal CLK2. In this way, the third control circuit 15 can control the voltage of the first node N1.

[0125] For example, Figure 7 and Figure 8 As shown, the third control circuit 15 includes a thirteenth transistor T13 and a fourteenth transistor T14.

[0126] A control electrode of the thirteenth transistor T13 is coupled to the second node N2 , and a first electrode of the thirteenth transistor T13 is coupled to the second voltage terminal V2 .

[0127] A control electrode of the fourteenth transistor T14 is coupled to the second clock signal terminal CLK2 , a first electrode of the fourteenth transistor T14 is coupled to the second electrode of the thirteenth transistor T13 , and a second electrode of the fourteenth transistor T14 is coupled to the first node N1 .

[0128] In some embodiments, Fig. 6A and Figure 6B As shown, the shift register SR further includes a fourth control circuit 16. The fourth control circuit 16 is coupled to the first node N1 and the second clock signal terminal CLK2.

[0129] The fourth control circuit 16 is configured to control the voltage of the first node N1 according to the second clock signal received at the second clock signal terminal CLK2. Thus, the fourth control circuit 16 can stabilize the voltage of the first node N1 when the voltage of the first node N1 is in a floating state.

[0130] For example, Figure 7 and Figure 8 As shown, the fourth control circuit 16 includes a third capacitor C3. A first terminal of the third capacitor C3 is coupled to the second clock signal terminal CLK2, and a second terminal of the third capacitor C3 is coupled to the first node N1.

[0131] It should be noted that the transistors used in the shift register SR provided in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (FET) or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited to this.

[0132] In some embodiments, the control electrode of each transistor used in the shift register SR is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0133] In the circuit provided by the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not represent actually existing components, but represent the meeting points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent meeting points of related electrical connections in the circuit diagram.

[0134] In the shift register SR provided in the embodiment of the present disclosure, the specific implementation of each circuit and sub-circuit is not limited to the above-described method, and it can be any implementation method used, such as a conventional connection method well known to those skilled in the art, as long as the corresponding functions are achieved. The above examples do not limit the protection scope of the present disclosure. In practical applications, technicians can choose to use or not use one or more of the above circuits according to the situation. Various combinations and variations based on the above circuits do not deviate from the principles of the present disclosure, and will not be described in detail.

[0135] In the following, taking the case where all the transistors are P-type transistors as an example, the working conditions of the transistors in the shift register SR at different stages of a frame period are described in detail.

[0136] It should be noted that the shift register may have m working stages (S1 to Sm) in one frame period, where m is an integer greater than or equal to 1. The specific value of m may be set according to actual conditions, and the present disclosure does not limit this. For example, m may be 4 or 8. For example, when the refresh rate of the display panel (screen) is 60 Hz, m may be 4. At this time, reference Fig. 9 , the first signal ESTV1 can have 4 high levels (ie, 4 pulses) within one frame period, and the second signal ESTV2 can have 4 high levels (ie, 4 pulses) within one frame period.

[0137] like Fig. 9 As shown, the shift register has four working stages (S1 to S4) in one frame period (F). The working conditions of the circuits and sub-circuits in the shift register in each working stage are similar. The first working stage (S1) is described below, and the remaining working stages can refer to the description of the first working stage and will not be repeated here.

[0138] like Fig. 9 In the first time period (P1) of the first working phase (S1) shown, the input circuit 11 responds to the first clock signal CK received at the first clock signal terminal CLK1 and the second signal ESTV2 received at the second signal input terminal Iput2, and the input circuit 101 transmits the first signal ESTV1 received at the first signal input terminal Iput1 to the first node N1.

[0139] For example, refer to Figure 6BThe second input subcircuit 112 transmits the first signal ESTV1 to the third input subcircuit 113 in response to the second signal ESTV2. The third input subcircuit 113 transmits the signal from the second input subcircuit 112 (ie, the first signal ESTV1) to the first node N1 in response to the first clock signal CK.

[0140] For example, Figure 7 As shown, the third transistor T3 is turned on in response to the low-level first clock signal CK received at the first clock signal terminal CLK1. The second transistor T2 is turned on in response to the low-level second signal ESTV2. In addition, since the first signal ESTV1 is at a high level, the first transistor T1 is turned off, and a conductive path is not formed with the third transistor T3, and the low-level second signal ESTV2 is not transmitted to the first node N1. In this case, the second transistor T2 forms a conductive path with the third transistor T3, and the high-level first signal ESTV1 is transmitted to the first node N1. At this time, the voltage of the first node N1 is at a high level.

[0141] For example, Figure 8 As shown, the fourth transistor T4 and the fifth transistor T5 both respond to the low-level first clock signal CK, and the fourth transistor T4 and the fifth transistor T5 are both turned on. The second transistor T2 responds to the low-level second signal ESTV2, and the second transistor T2 is turned on. In addition, since the first signal ESTV1 is at a high level, the first transistor T1 is turned off, and a conductive path is not formed with the fourth transistor T4, and the low-level second signal ESTV2 is not transmitted to the first node N1. In this case, the second transistor T2 and the fifth transistor T5 form a conductive loop, and the high-level first signal received at the first signal input terminal Iput1 is transmitted to the first node N1. At this time, the voltage of the first node N1 is at a high level.

[0142] The first control circuit 12 transmits the first voltage of the first voltage terminal V1 to the second node N2 in response to the first clock signal CK. Figure 6B , the first control sub-circuit 121 transmits the first voltage to the second node N2 in response to the first clock signal CK. Figure 7 As shown, the eighth transistor T8 responds to the low-level first clock signal CK, the eighth transistor T8 is turned on, and the low-level first voltage VGL is transmitted to the second node N2. At this time, the voltage of the second node N2 is at a low level. In addition, the ninth transistor T9 responds to the high-level voltage of the first node N1, the ninth transistor T9 is turned off, and the first clock signal CK is not transmitted to the second node N2.

[0143] In addition, for the third control subcircuit 131 in the second control circuit 13, the tenth transistor T10 therein responds to the high-level voltage of the first node N1, the tenth transistor T10 is turned off, and the second voltage will not be transmitted to the third node N3. For the fourth control subcircuit 132, the eleventh transistor T11 therein responds to the low-level voltage of the second node N2, the eleventh transistor T11 is turned on, and the high-level second clock signal CB is transmitted to the first electrode of the twelfth transistor T12 and the second end of the second capacitor C2, that is, transmitted to the fourth node N4, so that the voltage of the fourth node N4 is at a high level. The twelfth transistor T12 responds to the high-level second clock signal CB, the twelfth transistor T12 is turned off, and the high-level voltage will not be transmitted to the third node N3. In addition, the thirteenth transistor T13 in the third control circuit 15 is turned on in response to the low-level voltage of the second node N2, and the fourteenth transistor T14 is turned off in response to the high-level second clock signal CB, so the high-level second voltage VGH of the second voltage terminal V2 will not be transmitted to the first node N1.

[0144] In the output circuit 14, the seventh transistor T7 in the second output subcircuit 142 responds to the high-level voltage of the first node N1, and the seventh transistor T7 is turned off, and the low-level first voltage of the first voltage terminal V1 will not be transmitted to the signal output terminal Oput. At this time, the third node N3 is in a floating state (Floating), and the first end of the first capacitor C1 in the first output subcircuit 141 receives the high-level second voltage of the second voltage terminal V2. Due to the storage function of the first capacitor C1, the voltage of the third node N3 can be controlled to be a high level. The sixth transistor T6 responds to the high-level voltage of the third node N3, and the sixth transistor T6 is turned off and the second voltage of the second voltage terminal V2 will not be transmitted to the signal output terminal Oput. In this case, since the seventh transistor T7 and the sixth transistor T6 are both in the off state, the signal (i.e., the light emitting control signal) output by the signal output terminal Oput of the shift register SR maintains the previous low level.

[0145] In such Fig. 9 The second period (P2) of the first working phase (S1) shown in FIG. Figure 7As shown, the second transistor T2 in the second input subcircuit 112 of the input circuit 11 is turned on in response to the low-level second signal ESTV2 received at the second signal input terminal Iput2, and the first transistor T1 in the first input subcircuit 111 is turned off in response to the high-level first signal ESTV1 received at the first signal input terminal Iput1. Since the third transistor T3 in the third input subcircuit 113 of the input circuit 11 is turned off in response to the high-level first clock signal CK received at the first clock signal terminal CLK1, the second transistor T2 and the first transistor T1 will not form a conductive path with the third transistor T3, and therefore, the input circuit 11 will not transmit the signal to the first node N1. At this time, the voltage of the first node N1 is at a high level in the previous stage.

[0146] For example, Figure 8 As shown, the fourth transistor T4 and the fifth transistor T5 in the third input subcircuit 113 both respond to the high-level first clock signal CK received at the first clock signal terminal CLK1, and the fourth transistor T4 and the fifth transistor T5 are both turned off. The first transistor T1 in the first input subcircuit 111 responds to the low-level first signal ESTV1 received at the first signal input terminal Iput1, and the first transistor T1 is turned on. The second transistor T2 in the second input subcircuit 112 responds to the low-level second signal ESTV2 received at the second signal input terminal Iput2, and the second transistor T2 is turned on. At this time, the fourth transistor T4 and the first transistor T1 will not form a conductive path, the second transistor T2 and the fifth transistor T5 will not form a conductive path, and the second signal ESTV2 and the first signal ESTV1 will not be transmitted to the first node N1. At this time, the voltage of the first node N1 is at a high level in the previous stage.

[0147] For example, Figure 7 As shown, the eighth transistor T8 in the first control subcircuit 121 of the first control circuit 12 responds to the high-level first clock signal CK, the eighth transistor T8 is turned off, and the low-level first voltage VGL is not transmitted to the second node N2. The ninth transistor T9 in the second control subcircuit 122 responds to the high-level voltage of the first node N1, the ninth transistor T9 is turned off, and the first clock signal CK is not transmitted to the second node N2.

[0148] In this case, the thirteenth transistor T13 in the third control circuit 15 transmits the first voltage VGH of the first voltage terminal V1 to the first node N1 in response to the voltage of the third node N3 and the second clock signal CB received at the second clock signal terminal CLK2. Figure 7As shown, the eleventh transistor T11 in the fourth control circuit 107 responds to the low-level voltage of the third node N3, the eleventh transistor T11 is turned on, the twelfth transistor T12 responds to the low-level second clock signal CB, the twelfth transistor T12 is turned on, and the high-level first voltage VGH of the first voltage terminal V1 is transmitted to the first node N1 through the eleventh transistor T11 and the twelfth transistor T12, so that the voltage of the first node N1 is a high level.

[0149] Due to the storage function of the second capacitor C2 in the fourth control subcircuit 132 of the second control circuit 13, the voltage of the second node N2 can maintain the low level of the previous stage.

[0150] At this time, the eleventh transistor T11 in the fourth control subcircuit 132 of the second control circuit 13 responds to the low-level voltage of the second node N2, and the eleventh transistor T11 is turned on, transmitting the low-level second clock signal CB to the fourth node N4, and the twelfth transistor T12 responds to the low-level second clock signal CB, and the twelfth transistor T12 is turned on. The second control circuit 13 transmits the low-level second clock signal CB to the third node N2, and at this time, the voltage of the third node N2 is a low level.

[0151] In this case, the first output sub-circuit 141 in the output circuit 14 transmits the second voltage VGH of the second voltage terminal V2 to the signal output terminal Oput in response to the voltage of the third node N3. For example, the sixth transistor T6 in the first output sub-circuit 141 responds to the low-level voltage of the third node N3, and the sixth transistor T6 is turned on, and the high-level second voltage VGH of the second voltage terminal V2 is transmitted to the signal output terminal Oput, so that the signal outputted by the signal output terminal Oput is high level, that is, the light emitting control signal EM is high level.

[0152] Furthermore, due to the bootstrap effect of the second capacitor C2, the eleventh transistor T11 can be fully turned on, thereby reducing the signal loss caused by the threshold voltage of the eleventh transistor T11 and improving the stability and reliability of the output signal of the signal output terminal Oput.

[0153] In addition, the thirteenth transistor T13 in the third control circuit 15 is turned on in response to the low-level voltage of the second node N2, and the fourteenth transistor T14 transmits the second voltage to the first node N1 in response to the low-level second clock signal CB, so that the voltage obtained at the first node N1 is a high level. Since the voltage of the first node N1 is a high level, the seventh transistor T7 in the second output sub-circuit 142 is turned off, and the tenth transistor T10 in the third control sub-circuit 131 is turned off.

[0154] In this case, refer to Figure 3Under the control of the high-level light-emitting control signal EM, the transistors M5 and M6 in the pixel circuit 20 are turned off, the light-emitting device L does not emit light, and the display panel (ie, the screen) is blacked out.

[0155] In such Fig. 9 In the third time period (P3) of the first working stage (S1) shown, the input circuit 11 transmits the first signal ESTV1 received at the first signal input terminal Iput1 to the first node N1 in response to the first clock signal CK received at the first clock signal terminal CLK1 and the second signal ESTV2 received at the second signal input terminal Iput2; and, the input circuit 11 transmits the second signal ESTV2 received at the second signal input terminal Iput2 to the first node N1 in response to the first clock signal CK received at the first clock signal terminal CLK1 and the first signal ESTV1 received at the first signal input terminal Iput1.

[0156] For example, Figure 7 As shown, the third transistor T3 in the third input subcircuit 113 of the input circuit 11 is turned on in response to the low-level first clock signal CK received at the first clock signal terminal CLK1, the second transistor T2 in the second input subcircuit 112 is turned on in response to the low-level second signal ESTV2 received at the second signal input terminal Iput2, and the first transistor T1 in the first input subcircuit 111 is turned on in response to the low-level first signal ESTV1 received at the first signal input terminal Iput1. Therefore, the low-level second signal ESTV2 is transmitted to the first node N1 through the first transistor T1 and the third transistor T3, and the low-level first signal ESTV1 is transmitted to the first node N1 through the second transistor T2 and the third transistor T3. At this time, the voltage of the first node N1 is low.

[0157] For example, Figure 8As shown, the fourth transistor T4 and the fifth transistor T5 in the third input subcircuit 113 are both turned on in response to the low-level first clock signal CK received at the first clock signal terminal CLK1. The first transistor T1 in the first input subcircuit 111 is turned on in response to the low-level first signal ESTV1 received at the first signal input terminal Iput1. At this time, the low-level second signal ESTV2 received at the second signal input terminal Iput2 is transmitted to the first node N1 through the first transistor T1 and the fourth transistor T4. In addition, the second transistor T2 in the second input subcircuit 112 is turned on in response to the low-level second signal ESTV2 received at the second signal input terminal Iput2, and the low-level first signal ESTV1 is transmitted to the first node N1. At this time, the voltage of the first node N1 is low.

[0158] The first control circuit 12 transmits the first clock signal CK received at the first clock signal terminal CLK1 to the second node N2 in response to the voltage of the first node N1, and transmits the first voltage of the first voltage terminal V1 to the second node N2 in response to the first clock signal CK. For example, the first control subcircuit 121 transmits the first voltage of the first voltage terminal V1 to the second node N2 in response to the first clock signal CK; the second control subcircuit 122 transmits the first clock signal CK to the second node N2 in response to the voltage of the first node N1.

[0159] For example, the eighth transistor T8 in the first control subcircuit 121 transmits the first voltage of the first voltage terminal V1 to the second node N2 in response to the low-level first clock signal CK. The ninth transistor T9 in the second control subcircuit 122 transmits the low-level first clock signal CK to the second node N2 in response to the low-level voltage of the first node N1. At this time, the voltage of the second node N2 is at a low level.

[0160] The third control subcircuit 131 of the second control circuit 13 transmits the second voltage of the second voltage terminal V2 to the third node N3 in response to the voltage of the first node N1. For example, the tenth transistor T10 is turned on in response to the low voltage of the first node N1, and transmits the high-level second voltage of the second voltage terminal V2 to the third node N3. At this time, the voltage of the third node N3 is at a high level. In addition, the eleventh transistor T11 in the fourth control subcircuit 132 of the second control circuit 13 transmits the high-level second clock signal CB to the fourth node N4 in response to the voltage of the second node N2, and the twelfth transistor T12 is turned off in response to the high-level second clock signal CB, and does not transmit the high-level second clock signal CB to the third node N3. Therefore, the voltage of the third node N3 is at a high level.

[0161] The sixth transistor T6 in the first output subcircuit 141 of the output circuit 14 responds to the voltage of the third node N3 at a high level, and the sixth transistor T6 is turned off, and the second voltage of the second voltage terminal V2 is not transmitted to the signal output terminal Oput. The second output subcircuit 142 responds to the voltage of the first node N1, and transmits the first voltage of the first voltage terminal V1 to the signal output terminal Oput. For example, the seventh transistor T7 in the second output subcircuit 142 responds to the voltage of the first node N1 at a low level, and the seventh transistor T7 is turned on, and the first voltage is transmitted to the signal output terminal Oput. At this time, the signal outputted by the signal output terminal Oput is at a low level, that is, the light emitting control signal EM is at a low level.

[0162] In this case, refer to Figure 3 In response to the low-level light emission control signal EM, the transistors M5 and M6 in the pixel circuit 20 are turned on, and the pixel circuit 20 can enter Figure 4 In the third stage ③, the pixel circuit 20 transmits the driving signal to the light-emitting device L to drive the light-emitting device L to emit light.

[0163] In addition, if Figure 7 As shown, the thirteenth transistor T13 in the third control circuit 15 responds to the low-level voltage of the second node N2, and the thirteenth transistor T13 is turned on, and the fourteenth transistor T14 responds to the high-level second clock signal CB received at the second clock signal terminal CLK2, and the fourteenth transistor T14 is turned off. In this way, the second voltage of the second voltage terminal V2 will not be transmitted to the first node N1 by the third control circuit 15, and the voltage of the first node N1 remains at a low level.

[0164] It should be noted that in the third time period (P3), due to the influence of the threshold voltage of the transistors in the input circuit 11 (for example, the third input sub-circuit 113 and the second input sub-circuit 112) and the output circuit 14 (for example, the second output sub-circuit 142), the voltage of the low-level signal output by the signal output terminal Oput is different from the voltage of the first voltage terminal V1. For example, the voltage of the first voltage terminal V1 (for example, (-7) V) is higher than the voltage of the low-level signal output by the signal output terminal Oput (for example, (-2) V).

[0165] In such Fig. 9In the fourth period (P4) of the first working stage (S1) shown in the figure, during a portion of the time, the second transistor T2 is turned on in response to the second signal ESTV2 of low level, and the first transistor T1 is turned on in response to the first signal ESTV1 of low level. The third transistor T3 is turned off in response to the first clock signal CK of high level, and the second transistor T2 and the first transistor T1 do not form a conductive path with the third transistor T3, and the first signal ESTV1 and the second signal ESTV2 are not transmitted to the first node N1. For another example, Figure 8 As shown, the fourth transistor T4 and the fifth transistor T5 both respond to the high-level first clock signal CK, and the fourth transistor T4 and the fifth transistor T5 are both turned off. At this time, the second signal ESTV2 will not be transmitted to the first node N1 through the first transistor T1 and the fourth transistor T4, and the first signal ESTV1 will not be transmitted to the first node N1 through the second transistor T2 and the fifth transistor T5. At this time, the first node N1 is in a floating state. The fourth control circuit 16 controls the voltage of the first node N1 according to the second clock signal CB received at the second clock signal terminal CLK2. For example, Figure 7 As shown, the third capacitor C3 in the fourth control circuit 16 has a storage function. The third capacitor C3 can control the voltage of the first node N1 to maintain a low level in the previous stage according to the low-level second clock signal CB received at the second clock signal terminal CLK2.

[0166] In this case, the tenth transistor T10 is turned on in response to the tenth transistor T10, and the high-level second voltage of the second voltage terminal V2 is transmitted to the third node N3, at which time, the voltage of the third node N3 is high. In this case, the sixth transistor T6 is turned off in response to the voltage of the third node N3 at a high level. The seventh transistor T7 is turned on in response to the voltage of the first node N1 at a low level, and the first voltage of the low level of the first voltage terminal V1 is transmitted to the signal output terminal Oput. At this time, the signal output terminal Oput outputs a low-level signal. In addition, the voltage of the low-level signal output by the signal output terminal Oput in the fourth period (P4) is lower than the voltage of the low-level signal output by the signal output terminal Oput in the third period (P3). For example, the voltage of the low-level signal output by the signal output terminal Oput in the fourth period (P4) is equal to the first voltage (e.g., (-7)V).

[0167] In this case, refer to Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are turned on, and the pixel circuit 20 drives the light-emitting device L to emit light.

[0168] In addition, the ninth transistor T9 responds to the low-level voltage of the first node N1, the ninth transistor T9 is turned on, and the high-level first clock signal CK is transmitted to the second node N2, so that the voltage of the second node N2 is high. The eighth transistor T8 responds to the high-level first clock signal CK, the eighth transistor T8 is turned off, and the low-level second voltage is not transmitted to the second node N2. At this time, the voltage of the second node N2 is high.

[0169] The thirteenth transistor T13 is turned off in response to the high voltage of the second node N2, and the fourteenth transistor T14 is turned on in response to the low second clock signal CB. At this time, the second voltage of the second voltage terminal V1 is not transmitted to the first node N1, and the voltage of the first node N1 remains low.

[0170] The eleventh transistor T11 is turned off in response to the high voltage of the second node N2, and the twelfth transistor T12 is turned on in response to the low second clock signal CB. At this time, the second clock signal CB is not transmitted to the third node N3.

[0171] During another part of the fourth period (P4), the second transistor T2 is turned on in response to the low-level second signal ESTV2, and the first transistor T1 is turned on in response to the low-level first signal ESTV1. Figure 7 The third transistor T3 in the circuit is turned on in response to the low-level first clock signal CK received at the first clock signal terminal CLK1, or, Figure 8 The fourth transistor T4 and the fifth transistor T5 in the circuit both respond to the low-level first clock signal CK, and are both turned on. At this time, the first signal ESTV1 and the second signal ESTV2 can be transmitted to the first node N1. The voltage of the first node N1 is at a low level.

[0172] In this case, the tenth transistor T10 is turned on in response to the tenth transistor T10, and the high-level second voltage of the second voltage terminal V2 is transmitted to the third node N3, at which time, the voltage of the third node N3 is high. In this case, the sixth transistor T6 is turned off in response to the voltage of the third node N3 at a high level. The seventh transistor T7 is turned on in response to the voltage of the first node N1 at a low level, and the first voltage of the low level of the first voltage terminal V1 is transmitted to the signal output terminal Oput. At this time, the signal output terminal Oput outputs a low-level signal. In addition, the voltage of the low-level signal output by the signal output terminal Oput in the fourth period (P4) is lower than the voltage of the low-level signal output by the signal output terminal Oput in the third period (P3). For example, the voltage of the low-level signal output by the signal output terminal Oput in the fourth period (P4) is equal to the first voltage (e.g., (-7)V).

[0173] In this case, refer to Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are turned on, and the pixel circuit 20 drives the light-emitting device L to emit light.

[0174] In addition, the ninth transistor T9 is turned on in response to the low-level voltage of the first node N1, and the low-level first clock signal CK is transmitted to the second node N2, so that the voltage of the second node N2 is low. The eighth transistor T8 is turned on in response to the low-level first clock signal CK, and the low-level second voltage is transmitted to the second node N2. At this time, the voltage of the second node N2 is low.

[0175] The thirteenth transistor T13 is turned on in response to the low voltage of the second node N2, and the fourteenth transistor T14 is turned off in response to the high second clock signal CB. At this time, the second voltage of the second voltage terminal V1 is not transmitted to the first node N1, and the voltage of the first node N1 remains low.

[0176] The eleventh transistor T11 is turned on in response to the low voltage of the second node N2, and the twelfth transistor T12 is turned off in response to the high second clock signal CB. At this time, the second clock signal CB is not transmitted to the third node N3.

[0177] After the preset time, Fig. 9In the fifth period (P5) of the first working stage (S1) shown, the input circuit 11 transmits the second signal ESTV2 received at the second signal input terminal Iput2 to the first node N1 in response to the first clock signal CK received at the first clock signal terminal CLK1 and the first signal ESTV1 received at the first signal input terminal Iput1. For example, the first input subcircuit 111 transmits the second signal ESTV2 received at the second signal input terminal Iput2 to the third input subcircuit 113 in response to the first signal ESTV1 received at the first signal input terminal Iput1, and the third input subcircuit 113 transmits the signal from the first input subcircuit 111 to the first node N1 in response to the first clock signal CK received at the first clock signal terminal CLK1.

[0178] For example, Figure 7 As shown, the third transistor T3 is turned on in response to the low-level first clock signal CK. The first transistor T1 is turned on in response to the low-level first signal ESTV1. In addition, since the second signal ESTV2 received at the second signal input terminal Iput2 is at a high level, the second transistor T2 is turned off, and a conductive path is not formed with the third transistor T3, and the low-level first signal ESTV1 is not transmitted to the first node N1. In this case, the first transistor T1 forms a conductive path with the third transistor T3, and the high-level second signal ESTV2 received at the second signal input terminal Iput2 is transmitted to the first node N1. At this time, the voltage of the first node N1 is at a high level.

[0179] For example, Figure 8 As shown, the fourth transistor T4 and the fifth transistor T5 are both turned on in response to the low-level first clock signal CK received at the first clock signal terminal CLK1. The first transistor T1 is turned on in response to the low-level first signal ESTV1. In addition, since the second signal ESTV2 received at the second signal input terminal Iput2 is at a high level, the second transistor T2 is turned off, and a conductive path is not formed with the fourth transistor T4, and the low-level first signal ESTV1 is not transmitted to the first node N1. In this case, the first transistor T1 forms a conductive loop with the fourth transistor T4, and the high-level second signal ESTV2 received at the second signal input terminal Iput2 is transmitted to the first node N1. At this time, the voltage of the first node N1 is at a high level.

[0180] It should be noted that the operation of the other circuits in the shift register SR except the input circuit 11 is similar to the operation of the first period (P1) described above, and the description of the first period (P1) can be referred to above, and will not be repeated here. At this time, the signal outputted by the signal output terminal Oput of the shift register SR is a low level.

[0181] In such Fig. 9 In the sixth period (P6) of the first working stage (S1) shown in FIG. 1 , the working conditions of each circuit in the shift register SR are similar to those of the second period (P2) described above. You can refer to the description of the second period (P2) described above, and will not repeat them here. At this time, the signal outputted by the signal output terminal Oput is at a high level. In this case, refer to Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are turned off, the light emitting device L does not emit light, and the display panel is blacked out.

[0182] In addition, in Fig. 9 In the seventh period (P7) of the first working stage (S1) shown, the working conditions of each circuit in the shift register SR are similar to those of the third period (P3) described above, and the description of the third period (P3) can be referred to above, which will not be repeated here. At this time, the signal output by the signal output terminal Oput is a low level, and due to the influence of the threshold voltage of each transistor in the input circuit 11 (for example, the third input subcircuit 113 and the first input subcircuit 111) and the output circuit 14 (for example, the second output subcircuit 142), the voltage of the low level signal output by the signal output terminal Oput is different from the first voltage of the first voltage terminal V1. In this case, refer to Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are turned on, and the pixel circuit 20 can enter the state as shown in FIG. Figure 4 In the third stage ③, the light-emitting device L is driven to emit light.

[0183] In such Fig. 9 In the eighth period (P8) of the first working stage (S1) shown, the working conditions of each circuit in the shift register SR are similar to those of the fourth period (P4) described above. You can refer to the description of the fourth period (P4) described above and will not repeat it here. At this time, the signal output terminal Oput still outputs a low-level signal, and the voltage of the low-level signal output by the signal output terminal Oput in the fourth period (P4) is lower than the voltage of the low-level signal output by the signal output terminal Oput in the third period (P3). In this case, refer to Figure 3 , the transistors M5 and M6 in the pixel circuit 20 are turned on, and the pixel circuit 20 drives the light-emitting device L to emit light.

[0184] On this basis, compared to the situation where the input circuit in the shift register receives an input signal (for example, the first signal ESTV1), so that the shift register outputs a high-level signal only once in one working phase, and in the four working phases within a frame period, the shift register outputs a high-level signal four times, so that the screen is inserted black four times, the input circuit in the shift register in the embodiment of the present disclosure receives the input of two signals (for example, the first signal ESTV1 and the second signal ESTV2), and in one working phase, the shift register can output a high-level signal twice, so that the screen can be inserted black twice. In this way, in the four working phases within a frame period, the shift register can output a high-level signal eight times, so that the display panel can be inserted black eight times. Therefore, the shift register in the embodiment of the present disclosure can output at a double frequency in one working phase to realize a double frequency function, so that the number of times the screen is inserted black is increased, and the refresh frequency of the screen is improved.

[0185] For example, for a screen driven with a frame period of 60Hz, the display device inserts black four times in one frame period, and the refresh frequency of the screen is 60Hz×4=240Hz, which is difficult to meet the use requirements of the display device in application scenarios such as scanning codes or taking photos. However, the embodiments of the present disclosure can increase the number of black insertions, so that the number of black insertions of the display device in one frame period is increased to eight times, and the refresh frequency of the screen is 60Hz×8=480Hz, which increases the refresh frequency of the screen. Moreover, in the case where the IC in the display device can support a maximum of 16 black insertions, for a screen driven with a frame period of 60Hz, the frequency of the screen after frequency doubling is 60Hz×16×2=1920Hz, so that the display device can meet the use requirements of application scenarios such as scanning codes or taking photos.

[0186] In some embodiments, the signal output by the shift register SR may not be frequency-multiplied. For example, in a working phase, the shift register SR outputs a high-level signal. For example, referring to Figure 7 and Figure 8 The input circuit 11 transmits the first signal received at the first signal input terminal Iput1 to the first node N1 in response to the first clock signal received at the first clock signal terminal CLK1, and transmits the second signal received at the second signal input terminal Iput2 to the first node N1 in response to the first clock signal received at the first clock signal terminal CLK1 and the first signal received at the first signal input terminal Iput1.

[0187] Wherein, the second signal is a DC signal, for example, the second signal is a DC low level signal. For example, the second signal is the same as the first voltage of the first voltage terminal V1; the voltage of the second signal is equal to the first voltage of the first voltage terminal V1. For example, the voltage of the second signal is a DC low voltage. For example, the second signal input terminal Iput2 and the first voltage terminal V1 are the same signal terminal.

[0188] For example, in Fig.10 In the frame period (F) shown in FIG. Figure 7 and Figure 8 The second transistor T2 shown responds to the second signal of low level, and the second transistor T2 is always in the on state. Figure 7 The first electrode of the third transistor T3 is coupled to the first signal input terminal Iput1, so that when the third transistor T3 is turned on in response to the first clock signal, the third transistor T3 transmits the first signal to the first node N1. Figure 8 The first electrode of the fifth transistor T5 is coupled to the first signal input terminal Iput1, so that when the fifth transistor T5 is turned on in response to the first clock signal, the fifth transistor T5 transmits the first signal to the first node N1.

[0189] In such Fig.10 The first period (P1) of the first working phase (S1) shown, Figure 7 The third transistor T3 and the second transistor T2 are turned on, the first transistor T1 is turned off, and the input circuit 101 transmits the high-level first signal ESTV1 to the first node N1, so that the voltage of the first node N1 is at a high level. Figure 8 The fourth transistor T4, the fifth transistor T5 and the second transistor T2 are turned on, and the first transistor T1 is turned off, and the high-level first signal ESTV1 is transmitted to the first node N1, so that the voltage of the first node N1 is at a high level.

[0190] The operation of the other circuits in the shift register SR except the input circuit 11 can refer to the above-mentioned shift register SR. Fig. 9 The working condition of the first period (P1) of the first working stage (S1) in the embodiment will not be described here. At this time, the signal outputted by the signal output terminal Oput is a low level signal.

[0191] In such Fig.10 The second period (P2) of the first working phase (S1) shown, Figure 7 The first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 is turned off, and the high-level first signal ESTV1 and the second signal ESTV2 are not transmitted to the first node N1, and the voltage of the first node N1 is at a high level in the previous stage. Figure 8The fourth transistor T4 and the fifth transistor T5 are turned off, the first transistor T1 and the second transistor T2 are turned on, and the voltage of the first node N1 is at a high level in the previous stage.

[0192] The operation of the other circuits in the shift register SR except the input circuit 11 can refer to the above-mentioned shift register SR in Fig. 9 The working conditions of the second period (P2) of the first working stage (S1) in the embodiment will not be described here. At this time, the signal outputted by the signal output terminal Oput is a high level signal. During this period, the screen is blacked out.

[0193] In such Fig.10 In the third period (P3) and the fourth period (P4) of the first working stage (S1) shown in FIG. 1 , the working conditions of each circuit in the shift register SR are the same as those of the shift register SR in the above-mentioned Fig. 9 The working conditions of the third period (P3) and the fourth period (P4) of the first working stage (S1) are the same and will not be described in detail here.

[0194] In such Fig.10 In the fifth period (P5) of the first working phase (S1) shown in FIG. 1 , the working conditions of each circuit in the shift register SR are the same as those of the shift register SR in the above-mentioned Fig. 9 The working conditions of the third period (P3) of the first working stage (S1) are the same as those of the first working stage (S1), which will not be described here. At this time, the signal outputted by the signal output terminal Oput is a low level signal. Fig.10 In the sixth period (P6) of the first working stage (S1) shown in FIG. 1 , the working conditions of each circuit in the shift register SR are the same as those of the shift register SR in the above-mentioned Fig. 9 The working conditions of the fourth period (P4) of the first working stage (S1) in FIG. 1 are the same and will not be described here. At this time, the signal outputted by the signal output terminal Oput is a low level signal. Fig.10 In the seventh period (P7) and the eighth period (P8) of the first working stage (S1) shown in FIG. 1 , the working conditions of each circuit in the shift register SR are the same as those of the shift register SR in the above-mentioned Fig. 9 The working conditions of the seventh period (P7) and the eighth period (P8) of the first working stage (S1) are the same and will not be described in detail here.

[0195] In this case, in one working stage, the shift register outputs a high-level signal once, and in four working stages within one frame period, the shift register outputs a high-level signal four times, so that the screen is blacked out four times, and the signal output by the shift register may not be frequency-multiplied. Therefore, the signal output by the signal output end of the shift register provided in the embodiment of the present disclosure may not be frequency-multiplied, so that the screen can achieve both a low number of black insertions and a high number of black insertions, thereby adjusting the refresh frequency of the screen in different application scenarios, for example, in the normal display state, the signal output by the shift register is not frequency-multiplied, and in the code scanning state, the signal output by the shift register is frequency-multiplied, so as to meet the needs of different display devices and save power consumption.

[0196] It should be noted that the duty ratio of the first signal and the second signal can be adjusted according to actual conditions and is not limited here. Fig. 9 , the duration of a pulse (ie, a high level) of the first signal ESTV1 and the second signal ESTV2 can be lengthened. Fig. 9 In the first working stage, the first signal ESTV1 can maintain a high level from the first period (P1) to the third period (P3), and the second signal ESTV2 can maintain a high level from the fifth period (P5) to the seventh period (P7); accordingly, the duration of the high level of the light-emitting control signal EM is the same as the duration of the high level of the first signal ESTV1, that is, the time of each black insertion is extended.

[0197] The light emission control driving circuit provided by the embodiments of the present disclosure is configured to provide a light emission control signal to a pixel circuit, for example.

[0198] For example, Figure 1A and Figure 1B As shown, the display device 200 includes a light emitting control driving circuit 10. The light emitting control driving circuit 10 may be disposed on a substrate of the display panel 100. Figure 1A and Figure 1B As shown, the display panel 100 further includes a plurality of light emitting signal lines (EL(1), EL(2), EL(3) . . . ), and a shift register is coupled to a light emitting signal line. The light emitting signal line is configured to transmit a light emitting control signal EM. For example, the plurality of light emitting signal lines Figure 1A and Figure 1B The in extends along the X direction. Figure 1A and Figure 1B As shown, the light emitting control driving circuit 10 includes a plurality of shift registers (R(1), R(2), R(3)...), which are cascaded in sequence. The first stage shift register R(1) among the plurality of shift registers is the shift register SR in any of the above embodiments.

[0199] For example, a plurality of sub-pixels are divided into n rows of sub-pixels, and a light emitting signal line is coupled to a row of sub-pixels (refer to Figure 1A ), the i-th row of sub-pixels is coupled to the i-th stage shift register R(i), and the i-th stage shift register R(i) is configured to provide a light-emitting control signal to the i-th row of sub-pixels, n is a positive integer, 1≤i≤n, and i is an integer. For example, one light-emitting signal line is coupled to two rows of sub-pixels (refer to Figure 1B ), the i-th row of sub-pixels and the i+1-th row of sub-pixels are coupled to the i-th stage shift register R(i). Exemplarily, the signal output end of each shift register can be connected to at least one transistor (e.g. Figure 3 The control electrodes of transistors M5 and M6 in the pixel circuit provide a light emitting control signal.

[0200] In the case where multiple shift registers are cascaded in sequence, for example, Fig.11 As shown, the signal output terminal Oput of the first-stage shift register R(1) is coupled to the input terminal IN of the second-stage shift register R(2). The second-stage shift register R(2) is adjacent to the first-stage shift register R(1). The signal output terminal Oput of the second-stage shift register R(2) is coupled to the input terminal IN of the third-stage shift register R(3). The third-stage shift register R(3) is adjacent to the second-stage shift register R(2). In addition, the cascade connection method of the remaining shift registers is the same as described above.

[0201] The first-stage shift register R(1) works in the same manner as the above-mentioned shift register SR, which will not be described here. For example, the first-stage shift register R(1) provides a light-emitting control signal to the control electrode of the transistor coupled to the first-stage shift register R(1) in the first row of sub-pixels. The signal output terminal Oput of the above-mentioned first-stage shift register R(1) provides the output signal to the input terminal IN of the second-stage shift register R(2) as the input signal of the second-stage shift register R(2), so that the second-stage shift register R(2) provides a light-emitting control signal to the control electrode of the transistor connected to the signal output terminal Oput of the second-stage shift register R(2) in the second row of sub-pixels. The signal output terminal Oput of the second-stage shift register R(2) provides the output signal to the input terminal IN of the third-stage shift register R(3) as the input signal of the third-stage shift register R(3), so that the third-stage shift register R(3) provides a light-emitting control signal to the control electrode of the transistor connected to the signal output terminal Oput of the third-stage shift register R(3) in the third row of sub-pixels. In this way, through the multiple cascaded shift registers R, multiple rows of sequentially arranged sub-pixels can be scanned row by row.

[0202] For example, in the light emitting control driving circuit, except for the first stage shift register, other shift registers may adopt the following Fig.12 The shift register SRA shown in FIG. Fig.12 As shown, the input circuit 11A in the shift register SRA is coupled to the first clock signal terminal CLK1, the input terminal IN and the first node N1. The input circuit 11A transmits the signal received at the input terminal IN to the first node N1 in response to the first clock signal received at the first clock signal terminal CLK1.

[0203] It should be noted that other circuits in the shift register SRA (such as reference Fig.13A and Fig. 13B The first control circuit 12A, the second control circuit 13A, the output circuit 14A, the third control circuit 15A and the fourth control circuit 16A) are all the same in structure and function as the corresponding circuits in the above-mentioned shift register SR, and will not be described again here.

[0204] For example, Fig.13A and Fig. 13B As shown, the input circuit 11A in the shift register SRA includes a first transistor T1A, a control electrode of the first transistor T1A is coupled to the first clock signal terminal CLK1, a first electrode of the first transistor T1A is coupled to the input terminal IN, and a second electrode of the first transistor T1A is coupled to the first node N1.

[0205] In this case, in the light emitting control driving circuit 10, the first transistor T1A in the input circuit 11A in the second-stage shift register R(2) is turned on in response to the first clock signal, and transmits the signal received at the input terminal IN to the first node N1, so that the signal output terminal Oput of the second-stage shift register R(2) outputs a signal. The signal received at the input terminal IN of the second-stage shift register R(2) is the signal outputted by the signal output terminal Oput of the first-stage shift register R(1). For example, the signal outputted by the signal output terminal Oput of the first-stage shift register R(1) is the frequency-multiplied signal outputted by the above-mentioned shift register SR (for example, reference 1). Fig. 9 In this case, the signal outputted by the signal output terminal Oput of the second-stage shift register R(2) may be a frequency-doubled signal.

[0206] Correspondingly, the first transistor T1A in the input circuit 11A in the third-stage shift register R(3) is turned on in response to the first clock signal, and transmits the signal received at the input terminal IN to the first node N1, so that the signal output terminal Oput of the third-stage shift register R(3) outputs a signal. The signal received at the input terminal IN of the third-stage shift register R(3) is the signal outputted by the signal output terminal Oput of the second-stage shift register R(2). In the case where the signal outputted by the signal output terminal Oput of the second-stage shift register R(2) can be a frequency-doubled signal, the signal outputted by the signal output terminal Oput of the third-stage shift register R(3) can also be a frequency-doubled signal. In this way, the output signals of other shift registers can also be frequency-doubled signals accordingly.

[0207] In this case, the light emitting control driving circuit can output a frequency-doubled signal row by row through a plurality of cascaded shift registers, thereby increasing the number of black insertions of the display panel and the refresh frequency of the display panel.

[0208] It should be noted that the above description is based on an example in which a primary shift register in a light emitting control driving circuit controls a row (or column) of sub-pixels for display. In other embodiments, the primary shift register may also control at least two rows (or columns) of sub-pixels for display. In addition, the light emitting control driving circuit may adopt a gate driver on array (GOA) technology to arrange the light emitting control driving circuit on a substrate of a display panel.

[0209] For the light emitting control driving circuit, Figure 1A and Figure 1B It is only for illustration, and the description is made by taking single-sided driving (i.e., setting a light-emitting control driving circuit on a single side of the peripheral area of ​​the display panel, and driving row by row from the single side) as an example. In other embodiments, dual-sided simultaneous driving may be adopted (i.e., light-emitting control driving circuits are respectively set on two sides along the extension direction of the signal line transmitting the light-emitting control signal in the peripheral area of ​​the display panel, and the two light-emitting control driving circuits are used to drive row by row from both sides at the same time). In other embodiments, the display panel may adopt dual-sided cross driving (i.e., light-emitting control driving circuits are respectively set on two sides along the extension direction of the signal line transmitting the light-emitting control signal in the peripheral area of ​​the display panel, and the two light-emitting control driving circuits are used to drive row by row alternately from both sides). The embodiment of the present disclosure takes single-sided driving as an example to illustrate the light-emitting control driving circuit 10 provided in the embodiment.

[0210] Exemplarily, the first clock signal terminal and the second clock signal terminal in any two adjacent cascaded shift registers are respectively coupled to different first clock signal lines and second clock signal lines. Fig.11 As shown, the first clock signal terminal CLK1 of the odd-numbered shift register is coupled to the first clock signal line CLKA, the second clock signal terminal CLK2 of the odd-numbered shift register is coupled to the second clock signal line CLKB, the first clock signal terminal CLK1 of the even-numbered shift register is coupled to the second clock signal line CLKB, and the second clock signal terminal CLK2 of the even-numbered shift register is coupled to the first clock signal line CLKA.

[0211] It should be noted that, for the convenience of description, the embodiments of the present disclosure use the same symbols to represent some signal terminals, signals transmitted by some signal terminals, and signal lines coupled to some signal terminals, but their properties are different.

[0212] In some embodiments, Fig.14 As shown, the display device 200 further includes a processor 210 and a controller 220. The processor 210 is coupled to the controller 220, and the controller 220 is also coupled to the light emitting control driving circuit 10.

[0213] For example, the processor 210 may include a central processing unit (CPU), a microprocessor or an application specific integrated circuit (ASIC), etc. The controller 220 may include a timing controller (TCON) or a driver IC, etc.

[0214] Among them, reference Fig.15A and Fig. 15B , the processor 210 is configured to output a first control signal and a second control signal to the controller 220.

[0215] refer to Fig.15A , the controller 220 is configured to transmit the first signal and the second signal to the light emitting control driving circuit 10 in response to the first control signal. In one frame period, the first signal has a plurality of first pulses, the second signal has a plurality of second pulses, and the first pulses and the second pulses do not overlap at the same time. For example, referring to Fig. 9 In one frame period (F), the first signal ESTV1 has four first pulses, the second signal ESTV2 has four second pulses, and each first pulse and each second pulse have a certain time interval.

[0216] refer to Fig. 15B , the controller 220 is further configured to transmit the first signal and the second signal to the light emitting control driving circuit 10 in response to the second control signal. In one frame period, the first signal has a plurality of first pulses, and the second signal is a DC signal. For example, referring to Fig.10 In one frame period (F), the first signal ESTV1 has four first pulses, and the second signal ESTV2 is a DC low voltage signal.

[0217] Exemplarily, the processor 210 is configured to, in response to a startup operation on a specific application, output a first control signal to the controller 220 when the specific application belongs to a preset set; and output a second control signal to the controller 220 when the specific application does not belong to the preset set.

[0218] The preset set includes at least one application.

[0219] It should be noted that the preset set can be pre-set according to the actual usage of the product. Exemplarily, the application described in the text can be software, such as mobile phone software (Application, APP). For example, the display device can be pre-configured with at least one application, or at least one application can be obtained from a third-party application platform. The at least one application can include a camera program, a code scanning program, a video shooting program, or a screen recording program.

[0220] The display device is configured with a specific application. Exemplarily, the specific application may be at least one application in a preset set, for example, the specific application includes a camera application, a barcode scanning application, a video shooting application, or a screen recording application, etc. Alternatively, the specific application may not be an application in the preset set, for example, the specific application may be a clock application, a weather forecast application, or a text messaging application, etc.

[0221] For example, reference Fig.15A and Fig. 15B , the user interaction interface displayed by the display device has an icon of a specific application, and the startup operation of the specific application can be a user clicking the icon of the specific application. For example, in the case where the specific application is a camera program, refer to Fig.15A There is a camera icon on the user interaction interface, and a specific application is started. The user clicks on the camera icon, and the specific application is started. At this time, the display device is in a state of taking pictures. The processor responds to the start-up operation of the specific application (i.e., the operation of clicking the icon), and when the camera application belongs to the preset set, the processor outputs a first control signal to the controller.

[0222] For example, in the case where the specific application is a text messaging application, reference Fig. 15B, there is a text message icon on the user interaction interface, the user clicks the text message icon, the specific application is started, at this time, the display device is in the state of editing text messages, that is, the display device is in the state of normal display, the processor responds to the start operation of the specific application, and outputs a second control signal to the controller when the text message sending program does not belong to the preset set. The embodiment of the present disclosure provides a driving method of a shift register, and the shift register can adopt the shift register RS ​​in any of the above embodiments.

[0223] refer to Fig. 6A , the shift register RS ​​includes an input circuit 11, a first control circuit 12, a second control circuit 13 and an output circuit 14. The input circuit 11 is coupled to the first signal input terminal Iput1, the second signal input terminal Iput2, the first clock signal terminal CLK1 and the first node N1. The first control circuit 12 is coupled to the first node N1, the first clock signal terminal CLK1, the first voltage terminal V1 and the second node N2. The second control circuit 13 is coupled to the first node N1, the second node N2, the second voltage terminal V2, the second clock signal terminal CLK2 and the third node N3. The output circuit 14 is coupled to the first node N1, the third node N3, the first voltage terminal V1, the second voltage terminal V2 and the signal output terminal Oput.

[0224] In this case, the driving method includes:

[0225] The input circuit transmits a first signal received at a first signal input terminal to a first node in response to a first clock signal received at the first clock signal terminal and a second signal received at a second signal input terminal, and transmits a second signal received at a second signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal and the first signal received at the first signal input terminal.

[0226] The first control circuit transmits a first clock signal received at the first clock signal terminal to the second node in response to the voltage of the first node; and transmits a first voltage at the first voltage terminal to the second node in response to the first clock signal.

[0227] The second control circuit transmits the second voltage of the second voltage terminal to the third node in response to the voltage of the first node, and transmits the second clock signal to the third node in response to the voltage of the second node and the second clock signal received at the second clock signal terminal.

[0228] The output circuit transmits a first voltage at the first voltage terminal to the signal output terminal in response to a voltage at the first node, and transmits a second voltage at the second voltage terminal to the signal output terminal in response to a voltage at the third node.

[0229] In one frame period, the first signal has a plurality of first pulses, and the second signal has a plurality of second pulses. The first pulses and the second pulses do not overlap at the same time.

[0230] Exemplarily, the plurality of first pulses and the plurality of second pulses are arranged periodically, and the interval between a second pulse and a first pulse is approximately half the interval between two adjacent first pulses.

[0231] For example, in one frame period, the number of the plurality of first pulses and the number of the plurality of second pulses are both 4. The interval between one second pulse and one first pulse is about 1 / 8 of the length of one frame period. Fig. 9 , within a frame period (F), the duration of the frame period (F) is V, and the interval duration (W) between a first pulse in the first signal ESTV1 and a second pulse in the second signal ESTV2 is approximately 1 / 8 of the duration V of the frame period (F), that is, W=V / 8. For example, within a frame period (F), the phase of a second pulse in the second signal ESTV2 is delayed by a time period of approximately 1 / 8 of the duration V of the frame period (F) compared to the phase of a first pulse in the first signal ESTV1.

[0232] It should be noted that the driving method of the shift register described above has the same beneficial effects as the shift register described above, and therefore will not be described in detail.

[0233] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, comprising: An input circuit coupled to the first signal input terminal, the second signal input terminal, the first clock signal terminal and the first node; The input circuit is configured to transmit a first signal received at the first signal input terminal to the first node in response to a first clock signal received at the first clock signal terminal and a second signal received at the second signal input terminal, and to transmit a second signal received at the second signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal and the first signal received at the first signal input terminal; a first control circuit coupled to the first node, the first clock signal terminal, the first voltage terminal and the second node; the first control circuit being configured to transmit a first clock signal received at the first clock signal terminal to the second node in response to a voltage of the first node, and to transmit a first voltage at the first voltage terminal to the second node in response to the first clock signal; a second control circuit coupled to the first node, the second node, a second voltage terminal, a second clock signal terminal and a third node; the second control circuit being configured to transmit a second voltage at the second voltage terminal to the third node in response to a voltage at the first node, and to transmit the second clock signal to the third node in response to a voltage at the second node and a second clock signal received at the second clock signal terminal; and An output circuit is coupled to the first node, the third node, the first voltage terminal, the second voltage terminal and the signal output terminal; the output circuit is configured to transmit the first voltage of the first voltage terminal to the signal output terminal in response to the voltage of the first node, and to transmit the second voltage of the second voltage terminal to the signal output terminal in response to the voltage of the third node.

2. The shift register according to claim 1, wherein: The input circuit comprises: a first input subcircuit, a second input subcircuit and a third input subcircuit; The first input subcircuit is coupled to the first signal input terminal, the second signal input terminal and the third input subcircuit; the first input subcircuit is configured to transmit the second signal to the third input subcircuit in response to the first signal; The second input subcircuit is coupled to the first signal input terminal, the second signal input terminal and the third input subcircuit; the second input subcircuit is configured to transmit the first signal to the third input subcircuit in response to the second signal; The third input sub-circuit is also coupled to the first clock signal terminal and the first node; the third input sub-circuit is configured to transmit the signal from the first input sub-circuit to the first node and to transmit the signal from the second input sub-circuit to the first node in response to the first clock signal.

3. The shift register according to claim 2, wherein: The first input subcircuit comprises: a first transistor, wherein a control electrode of the first transistor is coupled to the first signal input terminal, a first electrode of the first transistor is coupled to the second signal input terminal, and a second electrode of the first transistor is coupled to the third input sub-circuit; The second input subcircuit comprises: A second transistor, wherein a control electrode of the second transistor is coupled to the second signal input terminal, a first electrode of the second transistor is coupled to the first signal input terminal, and a second electrode of the second transistor is coupled to the third input sub-circuit.

4. The shift register according to claim 2 or 3, wherein: The third input sub-circuit comprises: A third transistor, wherein a control electrode of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the first input subcircuit and the second input subcircuit, and a second electrode of the third transistor is coupled to the first node.

5. The shift register according to claim 2 or 3, wherein: The third input sub-circuit comprises: a fourth transistor, wherein a control electrode of the fourth transistor is coupled to the first clock signal terminal, a first electrode of the fourth transistor is coupled to the first input subcircuit, and a second electrode of the fourth transistor is coupled to the first node; and A fifth transistor, wherein a control electrode of the fifth transistor is coupled to the first clock signal terminal, a first electrode of the fifth transistor is coupled to the second input sub-circuit, and a second electrode of the fifth transistor is coupled to the first node.

6. The shift register according to claim 1, wherein: The output circuit comprises: a first output subcircuit coupled to the third node, the second voltage terminal and the signal output terminal; the first output subcircuit is configured to transmit the second voltage to the signal output terminal in response to the voltage of the third node; and The second output sub-circuit is coupled to the first node, the first voltage terminal and the signal output terminal; the second output sub-circuit is configured to transmit the first voltage to the signal output terminal in response to the voltage of the first node.

7. The shift register according to claim 6, wherein: The first output sub-circuit comprises: a sixth transistor, a control electrode of the sixth transistor being coupled to the second node, a first electrode of the sixth transistor being coupled to the first voltage terminal, and a second electrode of the sixth transistor being coupled to the signal output terminal; and A first capacitor, wherein a first terminal of the first capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the first voltage terminal.

8. The shift register according to claim 6 or 7, wherein: The second output sub-circuit comprises: A seventh transistor, wherein a control electrode of the seventh transistor is coupled to the first node, a first electrode of the seventh transistor is coupled to the first voltage terminal, and a second electrode of the seventh transistor is coupled to the signal output terminal.

9. The shift register according to claim 1, wherein: The first control circuit comprises: a first control subcircuit coupled to the first clock signal terminal, the first voltage terminal and the second node; the first control subcircuit being configured to transmit the first voltage to the second node in response to the first clock signal; and The second control subcircuit is coupled to the first node, the first clock signal terminal and the second node; the second control subcircuit is configured to transmit the first clock signal to the second node in response to the voltage of the first node.

10. The shift register according to claim 9, wherein: The first control subcircuit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is coupled to the first clock signal terminal, a first electrode of the eighth transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the second node; The second control subcircuit comprises: A ninth transistor, wherein a control electrode of the ninth transistor is coupled to the first node, a first electrode of the ninth transistor is coupled to the first clock signal terminal, and a second electrode of the ninth transistor is coupled to the second node.

11. The shift register according to claim 1, wherein: The second control circuit comprises: a third control subcircuit coupled to the first node, the third node and the second voltage terminal; the third control subcircuit is configured to transmit the second voltage to the third node in response to the voltage of the first node; and A fourth control subcircuit is coupled to the second node, the second clock signal terminal and the third node; the fourth control subcircuit is configured to transmit the second clock signal to the third node in response to the voltage of the second node and the second clock signal.

12. The shift register according to claim 11, wherein: The third control subcircuit comprises: a tenth transistor, wherein a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the second voltage terminal, and a second electrode of the tenth transistor is coupled to the third node; The fourth control subcircuit comprises: an eleventh transistor, a control electrode of the eleventh transistor being coupled to the second node, and a first electrode of the eleventh transistor being coupled to the second clock signal terminal; a twelfth transistor, wherein a control electrode of the twelfth transistor is coupled to the second clock signal terminal, a first electrode of the twelfth transistor is coupled to the second electrode of the eleventh transistor, and a second electrode of the twelfth transistor is coupled to the third node; and A second capacitor, wherein a first terminal of the second capacitor is coupled to the second node, and a second terminal of the second capacitor is coupled to the second electrode of the eleventh transistor and the first electrode of the twelfth transistor.

13. The shift register according to claim 1, further comprising: a third control circuit coupled to the second node, the second voltage terminal, the first node and a second clock signal terminal; The third control circuit is configured to transmit a second voltage at the second voltage terminal to the first node in response to the voltage at the second node and a second clock signal received at the second clock signal terminal.

14. The shift register according to claim 13, wherein: The third control circuit comprises: a thirteenth transistor, a control electrode of the thirteenth transistor being coupled to the second node, and a first electrode of the thirteenth transistor being coupled to the second voltage terminal; and A fourteenth transistor, wherein a control electrode of the fourteenth transistor is coupled to the second clock signal terminal, a first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor, and a second electrode of the fourteenth transistor is coupled to the first node.

15. The shift register according to claim 1, further comprising: A fourth control circuit is coupled to the first node and the second clock signal terminal; the fourth control circuit is configured to control the voltage of the first node according to the second clock signal received at the second clock signal terminal.

16. The shift register according to claim 15, wherein: The fourth control circuit comprises: A third capacitor, wherein a first terminal of the third capacitor is coupled to the second clock signal terminal, and a second terminal of the third capacitor is coupled to the first node.

17. A light emitting control driving circuit, comprising: Multiple cascaded shift registers; Wherein, the first stage shift register in the plurality of cascaded shift registers is the shift register according to any one of claims 1 to 16.

18. A display device comprising: The light emitting control driving circuit as claimed in claim 17.

19. The display device according to claim 18, further comprising: Processors and controllers; The processor is coupled to the controller; The processor is configured to output a first control signal and a second control signal to the controller; The controller is also coupled to the light emitting control driving circuit; The controller is configured to transmit a first signal and a second signal to the light emitting control driving circuit in response to the first control signal, wherein within a frame period, the first signal has a plurality of first pulses, the second signal has a plurality of second pulses, and the first pulses and the second pulses do not overlap at the same time; The controller is also configured to transmit a first signal and a second signal to the light emitting control driving circuit in response to the second control signal, wherein within a frame period, the first signal has a plurality of first pulses and the second signal is a DC signal.

20. The display device according to claim 19, wherein: The processor is configured to, in response to a startup operation on a specific application, output a first control signal to the controller if the specific application belongs to a preset set; and output a second control signal to the controller if the specific application does not belong to the preset set; The preset set includes at least one application.

21. A shift register driving method, wherein: The shift register comprises: an input circuit, a first control circuit, a second control circuit and an output circuit; the input circuit is coupled to a first signal input terminal, a second signal input terminal, a first clock signal terminal and a first node; the first control circuit is coupled to the first node, the first clock signal terminal, a first voltage terminal and a second node; the second control circuit is coupled to the first node, the second node, the second voltage terminal, the second clock signal terminal and a third node; the output circuit is coupled to the first node, the third node, the first voltage terminal, the second voltage terminal and a signal output terminal; The driving method comprises: The input circuit transmits a first signal received at the first signal input terminal to the first node in response to a first clock signal received at the first clock signal terminal and a second signal received at the second signal input terminal, and transmits a second signal received at the second signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal and the first signal received at the first signal input terminal; The first control circuit transmits the first clock signal received at the first clock signal terminal to the second node in response to the voltage of the first node, and transmits the first voltage of the first voltage terminal to the second node in response to the first clock signal; The second control circuit transmits the second voltage of the second voltage terminal to the third node in response to the voltage of the first node, and transmits the second clock signal to the third node in response to the voltage of the second node and the second clock signal received at the second clock signal terminal; The output circuit transmits the first voltage of the first voltage terminal to the signal output terminal in response to the voltage of the first node, and transmits the second voltage of the second voltage terminal to the signal output terminal in response to the voltage of the third node; Wherein, within one frame period, the first signal has a plurality of first pulses, and the second signal has a plurality of second pulses; the first pulses and the second pulses do not overlap at the same time.

22. The driving method according to claim 21, wherein: The plurality of first pulses and the plurality of second pulses are arranged periodically; The interval between a second pulse and a first pulse is approximately half the interval between two adjacent first pulses.

23. The driving method according to claim 21 or 22, wherein: In one frame period, the number of the plurality of first pulses and the number of the plurality of second pulses are both 4; The interval between a second pulse and a first pulse is approximately 1 / 8 of the duration of a frame period.

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