Vertical field effect transistor and method for its construction

Abstract

A vertical field effect transistor (200) is provided, having a drift region (204) with a first conductivity type, a semiconductor fin (206) on or above the drift region (204), and a source / drain electrode (214, 216) on or above the semiconductor fin (206), wherein the semiconductor fin (206) has an electrically conductive region (208) electrically conductively connecting the source / drain electrode (214, 216) with the drift region (204), and a confinement structure (210) laterally configured next to the electrically conductive region (208) and extending from the source / drain electrode (214, 216) to the drift region (204), wherein the confinement structure (210) is arranged for confining an electrically conductive channel of the vertical field effect transistor in the semiconductor fin (206) to a region of the electrically conductive region (208).

Description

Technical Field

[0001] The present invention relates to a vertical field-effect transistor and a method for constructing it. Background Technology

[0002] In conventional transistors (such as MOSFETs or MISFETs), the active switching component is provided by a reverse channel, for example by a p-region in an npn junction, where an electron path is constructed by applying a gate voltage. For applications of semiconductors with wide bandgap (such as silicon carbide (SiC) or gallium nitride (GaN)) in power electronic components, the use of so-called power FinFETs (Fin = Finne, FET = Feldeffekttransistor, field-effect transistor) can be advantageous. The structure of a conventional power FinFET 100 is as follows... Figure 1 This is illustrated intuitively. A conventional power FinFET 100 has an n-type doped drift region 104, a drain electrode 106, a source electrode 108, a gate electrode 110, a semiconductor fin 112, a gate dielectric 114, and an insulating layer 116 on a substrate 102. The semiconductor fin 112 is connected to the source electrode 108 by means of n+ doping 118. In the power FinFET 100, the switchable component consists of a narrow semiconductor fin 112, which is switchable due to the matching of its geometry and the gate metallization 110. The channel resistance of the power FinFET 100 is much smaller than that of conventional MOSFETs or MISFETs based on SiC or GaN. This results in a smaller on-resistance for the entire component. The power FinFET 100, in its current form, requires a narrow semiconductor fin, the lateral width of which determines the transistor's on-state voltage. To achieve a positive turn-on voltage (threshold voltage) for a normally closed transistor (typically required, especially in safety-related applications), a width of at least 100 nm to less than 100 nm is necessary for the semiconductor fins. The width of the semiconductor fins depends particularly on the semiconductor material used and the work function of the gate metal. Such narrow semiconductor fins may no longer be manufacturable using conventional photolithography techniques, as they are typically used in the mass production of power transistors. Summary of the Invention

[0003] The objective of this invention is to provide a vertical field-effect transistor and a method for manufacturing the same, wherein the vertical field-effect transistor / method realizes a vertical field-effect transistor having a positive turn-on voltage and a wide semiconductor fin.

[0004] According to one aspect of the invention, this task is solved by a vertical field-effect transistor (VFET). The VFET has: a drift region with a first conductivity type; a semiconductor fin on or above the drift region; and a source / drain electrode on or above the semiconductor fin, wherein the semiconductor fin has a conductive region and a confining structure, the conductive region conductively connecting the source / drain electrode to the drift region, and the confining structure laterally constructed next to the conductive region and extending from the source / drain electrode to the drift region, wherein the confining structure is configured to confine the conductive path of the VFET in the semiconductor fin to the region of the conductive region. This achieves a VFET with a structurally wider semiconductor fin and a positive turn-on voltage (threshold voltage). The positive threshold voltage is achieved by a relatively narrow, conductive semiconductor fin. Here, the decisive factor is not the structural width of the semiconductor fin, but the width of the conductive region of the semiconductor fin. Correspondingly, when a portion of the width of a semiconductor fin is non-conductive or non-conductive, a higher threshold voltage can also be achieved in a wider semiconductor fin. For example, a confinement structure can be constructed in the form of a p-doped region within a portion of the semiconductor fin, where the p-doped region functions as a non-conductive region within the fin during transistor operation. The width of the semiconductor fin that determines the threshold voltage is given by the width of the always-conductive region of the semiconductor fin.

[0005] According to another aspect of the invention, the task is solved by a method for constructing a vertical field-effect transistor (VFET). The method comprises: constructing a drift region having a first conductivity type; constructing a semiconductor fin on or above the drift region; and constructing a source / drain electrode on or above the semiconductor fin, wherein the semiconductor fin has a conductive region and a confining structure, the conductive region conductively connecting the source / drain electrode to the drift region, the confining structure being laterally constructed adjacent to the conductive region and extending laterally from the source / drain electrode to the drift region, wherein the confining structure is configured to confine the conductive path of the VFET in the semiconductor fin to the region of the conductive region. This reduces the photolithographic requirements for the structuring or structural width of the semiconductor fin. Attached Figure Description

[0006] Extensions to these aspects are set forth in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and explained in more detail below. The drawings show:

[0007] Figure 1 A schematic cross-sectional view of the transistor structure of the technology involved is shown;

[0008] Figure 2A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0009] Figure 3 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0010] Figure 4 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0011] Figure 5 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0012] Figure 6 A schematic view showing a vertical field-effect transistor according to different implementations;

[0013] Figure 7 A schematic view showing a vertical field-effect transistor according to different implementations;

[0014] Figure 8 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0015] Figure 9 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0016] Figure 10 A flowchart illustrating a method for constructing a vertical field-effect transistor according to different implementations is shown;

[0017] Figure 11 A schematic cross-sectional view of a vertical field-effect transistor during its construction, according to different implementations;

[0018] Figure 12 Schematic cross-sectional views of vertical field-effect transistors during their construction, according to different embodiments; and

[0019] Figures 13A-13F A schematic cross-sectional view of a vertical field-effect transistor during its construction is shown according to different implementations. Detailed Implementation

[0020] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, and in which specific embodiments are shown for visual illustration, in which the invention can be practiced. It is self-evident that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of protection of the invention. It is self-evident that features of the different embodiments described herein can be combined with each other unless specifically indicated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of protection of the invention is defined by the supplementary claims. In the drawings, the same or similar elements are given the same reference numerals, as is appropriate for the purpose.

[0021] Figures 2 to 9Schematic views of vertical field-effect transistors (VFETs) according to different embodiments are shown. In different embodiments, VFETs 200, 300, 400, 500, 600, and 700 have a drift region 204 on a semiconductor substrate 202; a semiconductor fin 206 (extending longitudinally perpendicular to the view) on or above the drift region 204; a confinement structure 210; a first source / drain electrode (e.g., source electrode 214); and a second source / drain electrode (e.g., drain electrode 216). Hereinafter, it is exemplarily assumed that the first source / drain electrode 214 is the source electrode and the second source / drain electrode 216 is the drain electrode. Furthermore, VFET 200 has a gate electrode 212 next to at least one sidewall of the semiconductor fin 206, wherein the gate electrode 212 is electrically insulated from the source electrode 214 by means of an insulator 218. A gate dielectric 222 is disposed between the gate electrode 212 and the semiconductor fin 206. The highly doped connection region 220 can electrically connect the semiconductor fin 206 to the source electrode 214. The source electrode 214 may additionally be laterally constructed next to at least one sidewall of the semiconductor fin 206 on or above the drift region 204. The semiconductor fin 206 has a confinement structure 210 next to the conductive region 208. The confinement structure 210 laterally confines the conductivity and structural extension of the conductive region 208. The conductive region 208 has a first conductivity type and the confinement structure 210 has a second conductivity type different from the first conductivity type. In other words, the vertical field-effect transistors 200, 300, 400, 500, 600, and 700 may have a drift region 204 with a first conductivity type; a semiconductor fin 206 on or above the drift region 204; and a source electrode 214 or drain electrode 216 on or above the semiconductor fin 206. Semiconductor fin 206 has a conductive region 208 that conductively connects the source electrode 214 or drain electrode 216 to the drift region 204, and further has a limiting structure 210 that is laterally constructed next to the conductive region 208 and extends from the source electrode 214 or drain electrode 216 to the drift region 204. The limiting structure 210 is configured to confine the conductive path of the vertical field-effect transistor (VFET) within the semiconductor fin 206 to the region of the conductive region 208. By means of the limiting structure, the lateral extension of the conductive region within the semiconductor fin is reduced. The conductive region is more strongly depleted, and the threshold voltage of the VFET is increased. Furthermore, in different embodiments, the limiting structure may be configured to shield the semiconductor fin and, in particular, the gate oxide relative to field spikes. This can improve the blocking strength and reliability of the VFET.

[0022] The semiconductor substrate 202 can be, for example, a GaN substrate 202 or a SiC substrate 202. A weakly n-type conductive semiconductor drift region 204 (also called a drift region 204), such as a GaN drift region 204 or a SiC drift region 204, can be formed (e.g., applied) on the semiconductor substrate 202. The n-type conductive semiconductor region can be formed above the drift region 204 in the form of a semiconductor fin 206, for example, a GaN fin or a SiC fin 206. An n+ type conductive connection region 220 can be formed on the semiconductor fin 206 or in a portion above the fin 206, and the source electrode 214 is connected to the semiconductor fin 206 via the n+ type conductive connection region. The source electrode 214 can be connected not only to the confinement structure 210 but also to the semiconductor fin 206. The drain electrode 216 can be located on the back side of the substrate 202. During operation, a space charge region can be formed between the region of the confinement structure 210 and the drift region 204. This reduces the area where current can flow, thereby increasing resistance. Due to the introduction of the confinement structure 210, the total resistance of field-effect transistors 200, 300, 400, 500, 600, and 700 is reduced compared to the variant without the confinement structure. Figure 1 Compared to the previous case, this is an improvement. The potential acting at the drain electrode 216 under blocking conditions results in an electric field that has its maximum value directly below the confinement structure 210, rather than as it would be without the confinement structure 210 (see...). Figure 1 The source fin 208 has its maximum value near the bottom of the semiconductor fin 206. This prevents, for example, premature electrical breakdown of the field-effect transistor or voltage applied at the drain electrode 216 from streaming to the gate electrode 212. The semiconductor fin 208 is depleted in the region adjacent to the gate electrode 212. The field-effect transistor can be latched up without a gate voltage applied because the electron gas can be depleted in the drift region below the semiconductor fin 206. Due to the application of a positive voltage at the gate electrode 210, electrons can accumulate in the region of the semiconductor fin 208 adjacent to the gate electrode 212. Electrons can flow from the source electrode 214 through the semiconductor fin 206 to the bottom of the semiconductor fin 206 and from there through the drift region 204 and through the substrate 202 to the drain electrode 216.

[0023] The confinement structure 210 may extend into the drift region 204. In other words, the confinement structure 210 may have a region arranged in the drift region 204 that extends laterally toward the gate electrode 212, such as, for example, in... Figure 2 As can be intuitively illustrated, the confinement structure 210 can function as a shielding structure in the drift region, reducing or shifting field spikes in the electric field below or near the gate electrode 212 into the drift region 204, for example, compared to a field-effect transistor without a shielding structure.

[0024] The confinement structure 210 can be completely surrounded laterally by the conductive region 208. The confinement structure 210 and the conductive region can be constructed coaxially, such as, for example, in... Figure 3 This is illustrated intuitively. Alternatively, the limiting structure 210 can be constructed at at least one sidewall of the semiconductor fin 206, such as, for example, in... Figure 2 , Figure 6 and Figure 7 This is explained intuitively in the text.

[0025] In the first section 404, which is laterally arranged next to the gate electrode 212, the confinement structure 210 may have a greater lateral extension than in the second section, so that the conductive region of the semiconductor fin 206 corresponding to the first section 404 of the confinement structure 210 has a contracted section 402, such as, for example, in Figure 4 This is explained intuitively in the text.

[0026] The first and second conductivity types can be opposite conductivity types. The drift region 204 can be, for example, n-type conductive and the confinement structure 210 can have at least one p-type conductive region. Alternatively or additionally, the confinement structure 210 can have a non-conductive second confinement structure 502, such as, for example in… Figure 5 This is explained intuitively in the text.

[0027] In different implementations, the current flow in the semiconductor fins can also occur partially in the horizontal direction, such as in... Figure 8 and Figure 9 This is illustrated intuitively. For this purpose, additional layers or structures of the first or second conductivity type can be provided, which spatially restrict current flow. For example, conductive regions 804, 806, 808 of the first conductivity type can be provided in fin 206, and the restricting structure, in addition to region 210, can have an additional layer or structure 802 that restricts current flow. Current flow occurs, for example, from source electrode 214 through regions 806, 804, 808 through drift region 204 and substrate 202 to drain electrode 216. Vertical restriction of the current path is achieved through region 802 of the second conductivity type. This implementation can be combined with features of the embodiments described above, such as, for example, in... Figure 9 As intuitively illustrated in the text, the aforementioned Figure 9 An additional restraint structure 502 is shown on the upper side of the fin.

[0028] Furthermore, in different embodiments, the confinement structure 210 may be configured to provide a body diode via a pn junction connected to the source electrode. For example, in different embodiments, the conductive region 208 of the semiconductor fin 206 is n-type doped and the confinement structure 210 is p-type doped or non-conductive. The non-conductive confinement structure 210 may be constructed, for example, by anti-doping or by introducing an inactive ion species (e.g., argon). In embodiments with a non-conductive confinement structure, a body diode is not implemented because the confinement structure is non-conductive.

[0029] Figure 10 A flowchart illustrating a method for constructing a vertical field-effect transistor (VFET) according to various embodiments is shown. Method 1000 includes: constructing 1010 a drift region 204 with a first conductivity type; constructing 1020 a semiconductor fin 206 on or above the drift region 204; and constructing 1030 source / drain electrodes 214, 216 on or above the semiconductor fin 206. The semiconductor fin 206 has a conductive region 208 that conductively connects the source / drain electrodes 214, 216 to the drift region 204 and has a limiting structure 210 laterally constructed adjacent to the conductive region 208 and extending laterally from the source / drain electrodes 214, 216 to the drift region 204. The limiting structure 210 is configured to limit the conductive path of the VFET in the semiconductor fin 206 to the region of the conductive region 208.

[0030] All the embodiments shown can also be implemented using a non-conductive confinement structure 210.

[0031] Figure 11 , Figure 12 and Figures 13A to 13F A schematic cross-sectional view of a vertical field-effect transistor during its construction is shown according to different embodiments. The confinement structure 210 can be constructed by means of ion implantation after the semiconductor fin geometry has been provided. Here, this can be achieved, for example, by a strong incident angle of the ions to be implanted. Figure 11 The outline shown is illustrated. Here, a mask 1120 is constructed on the surface of the drift region 204 and the semiconductor fin 208, wherein a portion of the semiconductor fin 208 is exposed. The exposed portion of the semiconductor fin 208 is irradiated with an ion beam 1110 to construct the confinement structure 210. Due to the rotation of the substrate 202 during implantation (such as, for example, in...), Figure 12(As illustrated intuitively in the diagram), different sides of the semiconductor fin 206 can be, for example, p-type doped to form the confinement structure 210. Alternatively, ion implantation can also be performed before the semiconductor fin is formed. In this case, the semiconductor fin can be shaped, for example, after p-type implantation, by removing a portion of the p-type doped region again. Alternative implementations involve the shape of the confinement structure 210, for example, the shape of the p-type doped confinement structure 210. Thus, this can also be centrally constructed in the semiconductor fin, see... Figure 4 This allows for the avoidance of narrow spacers that are technically difficult to manufacture. The lower end of the limiting structure 210 can be higher than, and lower than, the bottom of the semiconductor fin, and can also be at the same height as it. Furthermore, the limiting structure 210 can be shown with different widths at different depths, as in... Figure 4 and Figures 13A to 13F As shown, by varying the width of the limiting structure 210, the on-resistance in regions with larger spacing between the limiting structure 210 and the semiconductor fin sidewalls can be reduced, while stronger depletion can be achieved in regions with smaller spacing (parallel to the gate dielectric). Figures 13A-13F The diagram shows a method for constructing in Figure 4 An embodiment of the method with the structure shown is described. This method features the structuring of the semiconductor fin 208 within the n-type doped drift region 204. Figure 13A The confinement structure 210 is constructed with ion implantation of a first p-type doped region. Figure 13B ) and ion implantation in the second p-type doped region ( Figure 13C ), so as to construct in Figure 4 The contracted region 402 is illustrated visually. Furthermore, the method may include ion implantation of the n+ connection region 220 for the source electrode 214. Additionally, the method involves the deposition and structuring of the gate dielectric, gate electrode 212, and insulator 218. Furthermore, the method may include the deposition and structuring of the source electrode 214 and drain electrode 216. This has the advantage that the critical dimension of the width of the semiconductor fin 208 is defined, for example, by the vertical extension of the n-type doped layer 208, which can be more precisely controlled by epitaxy or implantation. The conductive region of the semiconductor fin may, but does not need to, be doped in the same way as the drift region 204. In other words, the conductive region of the fin may have the same doping concentration as the drift region or a different doping concentration. The confinement structure 210 can be connected via the source electrode 214 or via a supercell (not visually illustrated) contact. Optionally, a higher n-type doped region 808 may be provided for current bifurcation (see...). Figure 8 and Figure 9In one embodiment, the interface between the semiconductor material (e.g., SiC) and the gate dielectric (e.g., gate oxide) of the fin is neutralized, for example by partially counteracting the n-type doping of the semiconductor material (e.g., SiC). This can be achieved, for example, by reverse implantation or alternatively by dead implantation with an electrochemically inactive ion species (e.g., argon). Conductive channels are thus moved from the semiconductor / dielectric interface toward the neutralized / unneutralized semiconductor interface (e.g., a neutral SiC / n-SiC interface) due to this implantation. If this interface has a low defect density, the channel mobility is thereby increased. If the neutral region is fabricated by means of implantation, the implantation can be performed before constructing the semiconductor fin. In a subsequent process, in this case, the neutral region can be partially removed and the semiconductor fin 208 constructed. The shape of the conductive region of the semiconductor fin is determined by the lateral spacing of the conductive region and the doping ratio of the confining structure. Therefore, with appropriate selection, the formation of conductive channels can be laid from the interface of drift region 204 to the gate dielectric within the semiconductor fin, thus resulting in higher channel mobility. Alternatively, the neutral region 502 can be—similar to the fabrication of the p-type doped region 210—after the semiconductor fin geometry has been provided. In another embodiment, the semiconductor fin is constructed with a structure constrained in two lateral directions. For example, a square or hexagonal structure. The p-type doped regions serving as the constraining structure can be provided at one or more interfaces, for example, by directional implantation (see also...). Figure 6 and Figure 7 ).

[0032] The embodiments described and shown in the accompanying drawings are merely exemplary selections. Different embodiments may be combined with each other entirely or in individual features. One embodiment may also be supplemented by features of another embodiment. Furthermore, the described method steps may be repeated and performed in a sequence different from that described. In particular, the invention is not limited to a particular method.

Claims

1. A vertical field-effect transistor (200, 300, 400, 500, 600, 700), comprising: Drift region (204) having a first type of conductivity; Semiconductor fins (206) on or above the drift region (204); The source / drain electrodes (214, 216) on or above the semiconductor fin (206); and A gate electrode (212) is configured next to at least one sidewall of the semiconductor fin (206). in, The semiconductor fin (206) has a conductive region (208) and a confinement structure (210). The conductive region conductively connects the source / drain electrodes (214, 216) to the drift region (204). The confinement structure is laterally constructed next to the conductive region (208) and extends from the source / drain electrodes (214, 216) toward the drift region (204). The confinement structure (210) is configured to confine the conductive path of the vertical field-effect transistor in the semiconductor fin (206) to the region of the conductive region (208). The limiting structure (210) has a greater lateral extension in a first section (404) arranged laterally next to the gate electrode (212) than in other sections of the limiting structure (210), thereby having a contracted section (402) in the conductive region of the semiconductor fin (206) corresponding to the first section (404) of the limiting structure (210).

2. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1, wherein, The limiting structure (210) extends into the drift region (204).

3. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The confinement structure (210) has a second conductivity type that is opposite to the first conductivity type.

4. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The confinement structure (210) is non-conductive.

5. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2. in, The limiting structure (210) has the following region arranged in the drift region (204): the region extends laterally toward the gate electrode (212).

6. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The drift region (204) is n-type conductive, wherein the confinement structure (210) has at least one p-type conductive region.

7. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The confinement structure (210) is completely surrounded laterally by the conductive region (208).

8. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The confinement structure (210) and the conductive region are constructed coaxially.

9. The vertical field-effect transistor (200, 300, 400, 500, 600, 700) according to claim 1 or 2, wherein, The limiting structure (210) is constructed at at least one sidewall of the semiconductor fin (206).

10. A method for constructing a vertical field-effect transistor, the method comprising: Construct a drift region (204) with a first type of conductivity; Semiconductor fins (206) are constructed on or above the drift region (204); Source / drain electrodes (214, 216) are constructed on or above the semiconductor fin (206); and A gate electrode (212) is constructed next to at least one sidewall of the semiconductor fin (206). in, The semiconductor fin (206) has a conductive region (208) and a confinement structure (210). The conductive region conductively connects the source / drain electrodes (214, 216) to the drift region (204). The confinement structure is laterally constructed next to the conductive region (208) and extends from the source / drain electrodes (214, 216) toward the drift region (204). The confinement structure (210) is configured to confine the conductive path of the vertical field-effect transistor in the semiconductor fin (206) to the region of the conductive region (208). The limiting structure (210) has a greater lateral extension in a first section (404) arranged laterally next to the gate electrode (212) than in other sections of the limiting structure (210), thereby having a contracted section (402) in the conductive region of the semiconductor fin (206) corresponding to the first section (404) of the limiting structure (210).

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