An oscillator circuit

Abstract

An oscillator circuit relates to the field of electronic technology and is used to improve the performance of the oscillator. The oscillator circuit includes: a first amplifier (Am1) and a second amplifier (Am2) having switches that can be switched, and the oscillator circuit can be operated in an inductive feedback mode or a negative resistance mode respectively by switching; a resonator including a capacitive element and an inductive element, the inductive element including a tapped inductor, and the tapped inductor including four terminals (V1, V2, V3, V4), two of the four terminals being coupled to the differential input terminal of the first amplifier (Am1) and the differential output terminal of the second amplifier (Am2), and the other two terminals being coupled to the differential output terminal of the first amplifier (Am1).

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an oscillator circuit. Background Art

[0002] With the development of wireless communication systems such as cellular, wireless local area networks (WLAN), satellite communications, and global positioning systems (GPS), the demand for small, low-cost, and high-frequency products is also increasing. In this regard, voltage-controlled oscillators (VCOs) play a key role in communication systems, providing the periodic signals required for timing in digital circuits and frequency conversion in radio frequency (RF) circuits. VCOs can be implemented as standalone modules separated from other circuits or integrated into application-specific integrated circuits (ASICs) for use in devices such as, but not limited to, mobile phones, base stations, and nearly every communication device. As RF frequencies increase and power supply voltages decrease, it becomes increasingly difficult to design a VCO that meets both system noise and power requirements while also meeting product requirements for small size, low cost, and high frequency.

[0003] The noise performance of an LC resonant VCO is directly related to its signal power, which is proportional to the energy stored in the resonant inductor-capacitor (LC) tank circuit. In traditional VCO designs, the energy stored in the LC circuit is proportional to the size of the inductor and the square of the power supply voltage of the amplifier in the VCO. As the geometry of semiconductor devices shrinks, the power supply voltage of the amplifier needs to be reduced. To compensate for the voltage drop, the size of the inductor used in the LC tank circuit must also be reduced so that the noise performance generated by the VCO remains unchanged. Increasing the required frequency also requires reducing the size of the inductor. However, reducing the size of the inductor is extremely challenging because as the size of the inductor continues to shrink, the quality factor (Q) of the inductor also decreases, further increasing the thermal noise of the VCO. Summary of the Invention

[0004] The present application provides an oscillator circuit for improving the performance of the oscillator. To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0005] In a first aspect, an oscillator circuit is provided, comprising: a first amplifier and a second amplifier having switches that can be switched, and by switching, the oscillator circuit can operate in an inductive feedback mode or a negative resistance mode, respectively; a resonator, comprising a capacitive element and an inductive element, the inductive element comprising a tapped inductor, the tapped inductor comprising four terminals, namely a first terminal, a second terminal, a third terminal, and a fourth terminal, two of the four terminals being coupled to the differential input of the first amplifier and the differential output of the second amplifier, and the other two terminals being coupled to the differential output of the first amplifier. In the above technical solution, by switching the first amplifier to operate, the oscillator circuit can operate in the inductive feedback mode, and by switching the second amplifier to operate, the oscillator circuit can operate in the negative resistance mode, thereby meeting the noise and power consumption requirements in different scenarios and improving the performance of the oscillator circuit.

[0006] In a possible implementation of the first aspect, the first amplifier includes two groups of first coupling transistors with gates and drains coupled in the same polarity, and the sources of the two groups of first coupling transistors are coupled to a positive power rail and a negative power rail, respectively, via switches. Optionally, the first amplifier includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first switch, a second switch, a third switch, and a fourth switch; wherein the gate of the first NMOS transistor and the gate of the first PMOS transistor are both coupled to a first terminal, the drain of the first NMOS transistor and the drain of the first PMOS transistor are both coupled to a third terminal, the drain of the second NMOS transistor and the drain of the second PMOS transistor are both coupled to a second terminal, the gate of the second NMOS transistor and the gate of the second PMOS transistor are both coupled to a fourth terminal, the source of the first NMOS transistor and the source of the second NMOS transistor are coupled to the positive power rail via the first switch and the second switch, respectively, and the source of the first PMOS transistor and the source of the second PMOS transistor are coupled to the negative power rail via the third switch and the fourth switch. In the above possible implementation manner, the gate of the coupling tube in the first amplifier has a larger oscillation amplitude, thereby reducing the nonlinearity of the drain, so that the oscillator circuit has better phase noise.

[0007] In a possible implementation of the first aspect, the first amplifier includes a first MOS transistor, a second MOS transistor, a first switch, and a second switch, wherein the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors; wherein the gate of the first MOS transistor is coupled to the first terminal, the drain of the first MOS transistor is coupled to the third terminal, the drain of the second MOS transistor is coupled to the second terminal, the gate of the second MOS transistor is coupled to the fourth terminal, and the sources of the first MOS transistor and the second MOS transistor are coupled to a positive power rail or a negative power rail respectively via the first switch and the second switch. In the above possible implementation, the first amplifier has the advantages of a simple structure and is easy to implement and control.

[0008] In a possible implementation of the first aspect, the second amplifier is used to enable the oscillator circuit to operate in a single-ended negative resistance mode. Optionally, the second amplifier includes: a third MOS transistor, a fourth MOS transistor, a fifth switch, and a sixth switch, wherein the third MOS transistor and the fourth MOS transistor are both PMOS transistors or NMOS transistors; wherein the drain of the third MOS transistor is coupled to the first terminal via the fifth switch and the gate of the fourth MOS transistor, the drain of the fourth MOS transistor is coupled to the fourth terminal via the sixth switch and the gate of the third MOS transistor, and the source of the third MOS transistor and the source of the fourth MOS transistor are both coupled to a positive power rail or a negative power rail. In the above possible implementation, when the oscillator circuit operates in the single-ended negative resistance mode, the oscillator circuit has low noise performance, and the structure of the second amplifier is relatively simple.

[0009] In a possible implementation of the first aspect, the second amplifier is configured to enable the oscillator circuit to operate in a complementary negative-resistance mode. In the above possible implementation, when the oscillator circuit operates in the complementary negative-resistance mode, the oscillator circuit has low power consumption, which is lower than the power consumption when operating in the single-ended negative-resistance mode.

[0010] In a possible implementation of the first aspect, the second amplifier includes two groups of second coupling transistors with cross-coupled gates and drains, the drains of which are coupled via switches, and the sources of the two groups of second coupling transistors are coupled to a positive power rail and a negative power rail, respectively. Optionally, the second amplifier includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; wherein the drain of the third NMOS transistor is coupled to the first terminal via the fifth switch and the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor is coupled to the fourth terminal via the sixth switch and the gate of the third NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are both coupled to the positive power rail, the drain of the third PMOS transistor is coupled to the first terminal via the seventh switch and the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor is coupled to the fourth terminal via the eighth switch and the gate of the third PMOS transistor, and the source of the third PMOS transistor and the source of the fourth PMOS transistor are both coupled to the negative power rail. In the above possible implementation, the coupling tube in the second amplifier has the effect of negative resistance compensation, so that the oscillator circuit has the characteristic of low power consumption.

[0011] In one possible implementation of the first aspect, for the first amplifier, a first impedance is formed between the first terminal and the fourth terminal, a second impedance is formed between the second terminal and the third terminal, an input voltage at the input of the first amplifier is greater than an output voltage determined by a voltage divider, and the voltage divider is formed by the first impedance and the second impedance. Optionally, the input voltage exceeds the power supply voltage of the first amplifier. In this possible implementation, the gain of the oscillator circuit can be increased.

[0012] In one possible implementation of the first aspect, the tapped inductor includes two tapped sections, the two tapped sections being located at the second terminal and the fourth terminal, respectively, and the two tapped sections being routed in the middle of the tapped inductor. In this possible implementation, changing the positions of the two tapped sections can be used to adjust the power consumption, output amplitude, and phase noise of the oscillator circuit, thereby improving the performance of the oscillator circuit.

[0013] In a second aspect, a non-transitory computer-readable medium for use with a computer having software for creating an integrated circuit is provided, wherein the computer-readable medium has one or more computer-readable data structures stored thereon, the one or more computer-readable data structures having photomask data for manufacturing the oscillator circuit provided by the first aspect or any possible implementation of the first aspect.

[0014] It can be understood that any of the non-transitory computer-readable media provided above for use with a computer includes the oscillator circuit provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the oscillator circuit provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a differential LC tank circuit provided in an embodiment of the present application;

[0016] Figure 2 An example layout of a differential tapped inductor provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of a differential tapped LC tank circuit provided in an embodiment of the present application;

[0018] Figure 4 A block diagram of a differential VCO provided in an embodiment of the present application;

[0019] Figure 5 A schematic diagram of a first differential VCO provided in an embodiment of the present application;

[0020] Figure 6 A schematic diagram of a second differential VCO provided in an embodiment of the present application;

[0021] Figure 7 A schematic diagram of a third differential VCO provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of a first amplifier provided in an embodiment of the present application;

[0023] Figure 9 A schematic diagram of a second amplifier provided in an embodiment of the present application;

[0024] Figure 10 A design flow chart of an ASIC provided in an embodiment of the present application;

[0025] Figure 11 An illustrative example of a computing device is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0027] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0028] Various circuits or other components may be described or referred to as being "configured" to perform one or more tasks. In this case, "configured" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured" include hardware, such as circuitry that performs an operation, etc. Stating that a circuit / component is "configured" to perform one or more tasks explicitly states that 35 U.S.C. § 112(f) will not be invoked.

[0029] Throughout this specification, references to "one embodiment," "an embodiment," "a specific embodiment," or "a particular embodiment" indicate that a particular feature, structure, or characteristic described in connection with the particular embodiment is included in at least one embodiment, but not necessarily in all of the specific embodiments. Thus, each appearance of the phrases "in a specific embodiment," "in one embodiment," or "in a specific embodiment" in different places throughout this specification does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment may be combined with one or more other specific embodiments in any suitable manner. It should be understood that other variations and modifications of the specific embodiments described and illustrated herein are possible in light of the teachings herein and are considered part of the spirit and scope of this application.

[0030] Figure 1 shows the parasitic resistance R c and R l Schematic diagram of an LC tank circuit 100 for use in a differential voltage controlled oscillator (VCO). The LC tank circuit 100 may also be referred to as an LC resonant circuit, LC resonator, or resonator. The VCO amplifier provides current to the input impedance of the LC tank circuit 100. The voltage across the LC circuit generated by the LC tank circuit 100 is equal to the voltage at the amplifier input. In a conventional single inductor VCO (e.g., a Pierce configuration), the amplifier drives the impedance Z2 (ω o ), and the voltage at the amplifier input is expressed as o ) voltage.

[0031] In this application, a single inductor is tapped (eg, divided into at least two parts) according to a coefficient K. The amplifier drives the resistor Z1 (ω o ) is defined by the inductor tap, and the voltage at the amplifier input comes from the impedance Z2 (ω o ) defines the signal at the inductor tap. Theoretically, inductor segments KL and (1-K) / 2*L can be treated as separate inductors due to their small inductance and very high frequency. However, separate inductors are impractical due to physical size requirements and mutual coupling.

[0032] Because the amplifier input and output are located at different points in the LC tank circuit 100 (i.e., Z2 and Z1), the input voltage of the amplifier in the VCO can be much greater than the amplifier output voltage determined by the voltage divider measurement of the tapped inductor. This arrangement has many advantages.

[0033] The amplifier's hot carrier injection (HCI) voltage limit is limited to the output. HCI is a phenomenon in which charge carriers become trapped in the gate dielectric of a MOS transistor and permanently alter its switching characteristics. This allows input signals exceeding the amplifier's supply voltage limits. Because the input voltage represents the energy stored in the LC tank circuit 100, the VCO noise is lower compared to a VCO with a conventional resonator for the same total inductance due to the higher voltage of the LC tank circuit 100. Furthermore, the inductor does not have to be reduced in size to meet noise requirements, allowing for higher inductor Q when integrated into an integrated circuit (e.g., as part of an ASIC).

[0034] Since the voltage input to the amplifier exceeds the supply rails, the amplifier gain is higher than the given power dissipation. The amplifier output current is the product of the input voltage to Z2 and its transconductance g. m As the input voltage increases, the amplifier has more gain for the same current, which reduces the power requirements of the system.

[0035] from Figure 1 It can be seen from the following equations (1) to (5) that Z1 (ω o ) at the impedance ratio Z2(ω o ) is lower by a factor K 2 Under large signal conditions, the linearity of the amplifier is determined by the linearity of its output rather than the linearity of its input. The low impedance at the output of the VCO reduces the nonlinear mixing of flicker noise with the VCO frequency, thereby improving the spectral utilization of the sideband noise near it. Those skilled in the art will recognize that flicker noise at baseband frequency is a type of electronic noise with a 1 / ω density spectrum, but mixed through nonlinear elements, which produces a 1 / ω phase noise of the VCO single sideband. 3 part.

[0036] Resonance value And ω o L=X o (1)

[0037]

[0038]

[0039]

[0040]

[0041] Where: o is the oscillation frequency (radians per second);

[0042] L is the inductance;

[0043] C is the capacitance;

[0044] R l is the parasitic resistance of the inductor;

[0045] R c is the parasitic resistance of the capacitor;

[0046] K is a constant relating Z1 to Z2;

[0047] X o The resonant frequency is ω o The reactance of the inductor L.

[0048] Reference Figure 2 , shows an example of an LC tank circuit (e.g. Figure 1 An example layout of a differential tapped inductor 200 for integration into an integrated circuit is shown in FIG. Figure 3 shows an idealized schematic diagram of a differential tapped LC tank circuit 302, including Figure 2 , which is a representation of the equivalent inductance 200' of the tapped inductor 200 coupled in parallel with the capacitor C. Note that Figure 2 The segments V1-V5a, V2-V5a, V3-V5b, V4-V5b and V5a-V5b in the Figure 3 Inductors L1, L2, L3, L4 and L5 in the schematic diagram.

[0049] The differential tapped inductor 200 includes one or more conductive segments (e.g., V1-V5a, V4-V5b, and V5a-V5b) that form a physical loop 201. As used herein, the term "physical loop" refers to a closed or nearly closed geometric shape having a co-located or immediately adjacent start and end point and including at least one distinct convex portion, wherein the convex portion defines an interior space within the convex portion (e.g., a ring-shaped polygon or a ring-shaped polygon segment). Thus, a physical loop is distinct from an "electrical loop," which generally refers to a closed path of any shape through which current may flow.

[0050] Physical loop 201 is preferably symmetrical and is shown as being generally octagonal when within inductor 200. Those skilled in the art will recognize that physical loop 201 may include other symmetrical and asymmetrical shapes (e.g., rectangular, square, hexagonal, etc.) without departing from the scope of the present application. Inductor 200 is electrically connected to segments V2-V5a and V3-V5b at V5a and V5b via electrical connections to form electrical loops (L2 and L3), which are disposed within the interior space formed by physical loop 21 (including L1, L5, and L4).

[0051] The capacitive element C of the differential tapped LC tank circuit 302 can be embodied as a PMOS varactor, an NMOS varactor, a metal-insulator-metal (MIM) device, or any other suitable capacitive element. In silicon technology, two types of varactor diodes can be used, namely a reverse biased pn junction diode or a MOS capacitor varactor. The MOS capacitor varactor can be composed of a MOS transistor, the drain, source, and body terminals of which are coupled together, and the capacitance is adjusted based on the voltage applied between the body and the gate terminal. Without departing from the scope of the present application, those skilled in the art will recognize that other alternative elements to the capacitive element C of the LC tank circuit can be used.

[0052] The quality factor (Q) of the differential tapped LC tank circuit 302 depends on the inductor 200 having a low resistance. The resistance of the inductor 200 is minimized by using thick / wide metallization processes such as, but not limited to, aluminum, copper, gold, or other suitable materials to reduce series resistance. The inductor 200 is preferably constructed of a high dielectric substrate material such as silicon, gallium arsenide, or other suitable materials. Surface micromachining techniques can be used to create an air gap between the inductor and the substrate to further improve dielectric performance.

[0053] The inductor tap segments V2-V5a and V3-V5b (L2 and L3) are coupled to the amplifier output and are not part of the LC resonant circuit. Therefore, their parasitic resistance is not as important as the parasitic resistance of the inductor segments L1, L4 and L5. Therefore, segments L2 and L3 can be connected using Figure 2 The thinner metal material shown is constructed.

[0054] A practical problem involved when using multiple inductors (e.g., L1 to L5) is the mutual inductance in any connection from the amplifier output to the tap points V5a and V5b. The inductor current in the resonant LC circuit is typically much higher than the current supplied from the amplifier by the circuit factor Q. When the mutual inductance is high, the induced current from the resonant LC circuit becomes high enough in the leads from the amplifier output to the tap points that the input impedance to the taps becomes so high that the amplifier cannot supply any current. To overcome this problem, the tap sections V2-V5a (L2) and V3-V5b (L3) are directed upward in the middle of the inductor 200 (e.g., Figure 2 As shown), the induced currents from the two symmetrical halves of the inductor 200 cancel each other out.

[0055] Tap locations V5a and V5b can be adjusted on the metal to change power consumption, VCO output swing, and phase noise performance. This can be used to fine-tune the design of the metal, as shown by V5a' and V5b'. To minimize parasitic effects on the substrate, the substrate can be doped with additives to have a high resistivity, and / or the distance between the metal layer and the substrate can be increased through etching or micromachining.

[0056] Figure 4 FIG. 4 is a block diagram of a differential VCO 400 according to the principles of the present application. Figure 3 4 (shown in detail in FIG4 ), has terminals V1, V2, V3, and V4. Terminals V1 and V4 are coupled to the input of amplifier 404, and terminals V2 and V3 are coupled to the output of amplifier 404. Amplifier 404 preferably has a CMOS topology, however, those skilled in the art will recognize other suitable amplifier topologies, such as PMOS, NMOS, and bipolar, without departing from the scope of the present application.

[0057] refer to Figure 5 , shows a schematic diagram of an example differential CMOS VCO 500 using a differential tapped LC tank circuit 302 practiced according to the principles of the present application. The CMOS amplifier is composed of PMOS transistors 504 and 506 and NMOS transistors 508 and 510. The sources of the PMOS transistors 504 and 506 are coupled to the positive power rail (VDD), and their gates are coupled to the gates of the NMOS transistors 508 and 510. The gates of the PMOS transistors 504 and 508 are coupled to the tap V1 of the differential tapped LC tank circuit 302. The gates of the PMOS transistors 506 and NMOS transistors 510 are coupled to the tap V4 of the differential tapped LC tank circuit 302. The sources of the NMOS transistors 508 and 510 are coupled to the negative power rail (ground), and their drains are coupled to the drains of the PMOS transistors 504 and 506.

[0058] Taps V2 and V3 of the differential LC tank resonator circuit 302 are coupled to the normally coupled drains of the PMOS transistor 504 and the NMOS transistor 508 , and to the normally coupled drains of the PMOS transistor 506 and the NMOS transistor 510 , respectively.

[0059] like Figure 6 FIG. 1 shows a circuit diagram of a differential CMOS VCO 500 according to the principles of the present application. Figure 6 The first amplifier pair gm1 corresponds to Figure 5 The PMOS tube 504 and NMOS tube 508 in the second amplifier pair gm2 correspond to Figure 5 It should be noted that the equivalent inductors L1-L5 in the differential tapped LC tank circuit 302 can be used in practical applications. Figure 6 The inductors shown in L11-L14 are designed, and L11-L14 are only exemplary and do not limit the embodiments of the present application.

[0060] exist Figure 6 In the figure, L11-L14 and capacitor C are connected in parallel to form an oscillator tank. The PMOS and NMOS transistors in the CMOS amplifier form a negative resistance through cross-positive feedback, offsetting the loss of the tank to form a class AB mode oscillator. For PMOS transistor 504 and NMOS transistor 508, the amplitude of the AC signal seen by gate A and drain B is different. This is because the impedance seen by end B is smaller than the impedance seen by end A. According to small signal linear analysis, the proportional relationship is approximately (L14+L11+L12) / (L11+L12+L13+L14). Therefore, by selecting different ratios of L3 and L4 to improve the impedance seen by drain B of the first amplifier pair gm1, the first amplifier pair gm1 can operate in the linear region of the class AB mode. Compared with traditional CMOS oscillators, Figure 6 The gate of the class AB oscillator formed by the inductive feedback shown has a larger oscillation amplitude, reduces the nonlinearity of the drain, and thus has better phase noise.

[0061] Currently, communications equipment is often used to run a variety of different services, and these different services often have different requirements for oscillator performance, such as power consumption and noise. For example, voice call services generally require low oscillator noise, which results in higher oscillator power consumption. Internet access services have lower noise requirements than voice call services, and thus require lower oscillator power consumption. The differential CMOS VCO provided above can be used in low-noise, high-power scenarios, but it will result in wasted power in low-power scenarios. Based on this, the following provides a VCO with switchable amplifiers to meet the different power consumption and noise requirements in different scenarios, as shown below.

[0062] Now transfer to Figure 7 , shows a circuit diagram of an example VCO 700 using a differential tapped LC tank circuit 302 practiced according to the principles of the present application. The amplifiers in the VCO include a first amplifier Am1 having a differential input and a differential output, and a second amplifier Am2 having a differential output. The first amplifier Am1 and the second amplifier are switchable, and by switching, the oscillator circuit can operate in an inductive feedback mode (also known as a class AB mode) or a negative resistance mode, respectively.

[0063] The signals at the differential input and differential output terminals are differential signals with a phase difference of 180 degrees. The inductive feedback mode may refer to a situation where both the differential input and differential output terminals of the amplifier in the VCO are coupled to a tapped inductor, and changes in the amplifier's output voltage will cause changes in the amplifier's input voltage. The negative resistance mode refers to a situation where the amplifier in the VCO utilizes a cross-coupled CMOS transistor pair architecture, resulting in a two-terminal device with only an output terminal. Therefore, only the differential output terminal of the amplifier is coupled to the tapped inductor.

[0064] In the oscillator circuit provided in the embodiment of the present application, when the oscillator circuit operates at Figure 7 In the inductive feedback mode, the oscillator circuit has the characteristics of low noise. Figure 7 In the negative resistance mode, the oscillator circuit has the characteristics of low power consumption, thereby meeting the requirements for noise and power consumption in different scenarios and improving the performance of the oscillator circuit.

[0065] Optionally, the first amplifier Am1 may include the following three different structures, which are described in detail below.

[0066] The first amplifier Am1 includes two sets of first coupling transistors with gates and drains coupled in the same polarity, and the sources of the two sets of first coupling transistors are coupled to the positive power rail (VDD) and the negative power rail (ground) respectively through switches. Specifically, Figure 7 As shown, the first amplifier Am1 includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; wherein, the gate of the first NMOS transistor M1 and the gate of the first PMOS transistor M3 are both coupled to the first terminal V1, the drain of the first NMOS transistor M1 and the drain of the first PMOS transistor M3 are both coupled to the third terminal V3, the gate of the second NMOS transistor M2 and the gate of the second PMOS transistor M4 are both coupled to the fourth terminal V4, the drain of the second NMOS transistor M2 and the drain of the second PMOS transistor M4 are both coupled to the second terminal V2, the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are coupled to the positive power rail (VDD) through the first switch S1 and the second switch S2, respectively, and the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are coupled to the negative power rail (ground) through the third switch S3 and the fourth switch S4, respectively. It should be noted that the first switch S1 and the second switch S2 may also be replaced by one switch, and the sources of the first NMOS transistor M1 and the second NMOS transistor M2 may be multiplexed with this one switch; similarly, the third switch S3 and the fourth switch S4 may also be replaced by one switch, and the sources of the first PMOS transistor M3 and the second PMOS transistor M4 may be multiplexed with this one switch.

[0067] The second type, such as Figure 8 As shown in (a) of FIG, the first amplifier Am1 includes a first NMOS transistor M1, a second NMOS transistor M2, a first switch S1, and a second switch S2. The gate of the first NMOS transistor M1 is coupled to the first terminal V1, the drain of the first NMOS transistor M1 is coupled to the third terminal V3, the drain of the second NMOS transistor M2 is coupled to the second terminal V2, the gate of the second NMOS transistor M2 is coupled to the fourth terminal V4, and the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are coupled to the positive power rail (VDD) via the first switch S1 and the second switch S2, respectively. It should be noted that the first switch S1 and the second switch S2 can also be replaced by a single switch, with the sources of the first PMOS transistor M1 and the second PMOS transistor M3 sharing this single switch.

[0068] The third type, such as Figure 8 As shown in (b), the first amplifier Am1 includes a first PMOS transistor M3, a second PMOS transistor M4, a third switch S3, and a fourth switch S4. The gate of the first PMOS transistor M3 is coupled to the first terminal V1, the drain of the first PMOS transistor M3 is coupled to the third terminal V3, the drain of the second PMOS transistor M4 is coupled to the second terminal V2, the gate of the second PMOS transistor M4 is coupled to the fourth terminal V4, and the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are coupled to the negative power rail (ground) via the third switch S3 and the fourth switch S4, respectively. It should be noted that the third switch S3 and the fourth switch S4 can also be replaced by a single switch, with the sources of the first NMOS transistor M2 and the second NMOS transistor M4 sharing this single switch.

[0069] The second and third types are both single-ended structures, which have greater power consumption than the first type, but better noise performance.

[0070] Optionally, the second amplifier Am1 may also include the following three different structures, which are described in detail below.

[0071] The first type, the second amplifier, is used to make the oscillator circuit operate in a complementary negative resistance mode. The second amplifier Am2 includes two sets of second coupling transistors with gates and drains cross-coupled, and the drains are coupled through switches. The sources of the two sets of second coupling transistors are respectively coupled to the positive power rail (VDD) and the negative power rail (ground). Specifically, Figure 7As shown, the second amplifier Am2 includes a third NMOS transistor M5, a fourth NMOS transistor M6, a third PMOS transistor M7, a fourth PMOS transistor M8, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8; wherein, the drain of the third NMOS transistor M5 is coupled to the first terminal V1 through the fifth switch S5 and the gate of the fourth NMOS transistor M6, the drain of the fourth NMOS transistor M6 is coupled to the fourth terminal V4 through the sixth switch S6 and the gate of the third NMOS transistor M5, the source of the third NMOS transistor M5 and the source of the fourth NMOS transistor M6 are both coupled to the positive power rail (VDD), the drain of the third PMOS transistor M7 is coupled to the first terminal V1 through the seventh switch S7 and the gate of the fourth PMOS transistor M8, the drain of the fourth PMOS transistor M8 is coupled to the fourth terminal V4 through the eighth switch S8 and the gate of the third PMOS transistor M7, and the source of the third PMOS transistor M7 and the source of the fourth PMOS transistor M8 are both coupled to the negative power rail (ground).

[0072] Type II, the second amplifier is used to make the oscillator circuit work in single-ended negative resistance mode. Figure 9 As shown in (a) of FIG. 1 , the second amplifier Am2 includes: a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth switch S5, and a sixth switch S6; wherein the drain of the third NMOS transistor M5 is coupled to the first terminal V1 through the fifth switch S5 and the gate of the fourth NMOS transistor M6, the drain of the fourth NMOS transistor M6 is coupled to the fourth terminal V4 through the sixth switch S6 and the gate of the third NMOS transistor M5, and the source of the third NMOS transistor M5 and the source of the fourth NMOS transistor M6 are both coupled to the positive power rail (VDD).

[0073] Type III, the second amplifier is used to make the oscillator circuit work in single-ended negative resistance mode. Figure 9 As shown in (b), the second amplifier Am2 includes: a third PMOS transistor M7, a fourth PMOS transistor M8, a seventh switch S7, and an eighth switch S8; wherein, the drain of the third PMOS transistor M7 is coupled to the first terminal V1 through the seventh switch S7 and the gate of the fourth PMOS transistor M8, the drain of the fourth PMOS transistor M8 is coupled to the fourth terminal V4 through the eighth switch S8 and the gate of the third PMOS transistor M7, and the source of the third PMOS transistor M7 and the source of the fourth PMOS transistor M8 are both coupled to the negative power rail (ground).

[0074] Similarly, Types II and III are also single-ended architectures, which have better noise performance than Type I, but consume more power.

[0075] Specifically, Figure 7Taking the oscillator circuit shown as an example, the switching states of the first amplifier Am1 and the second amplifier Am2 in the oscillator are illustrated. When the first switch S1 to the fourth switch S4 are closed and the fifth switch S5 to the eighth switch S8 are opened, the first amplifier Am1 is in the working state, and the working mode of the oscillator circuit is switched to the inductive feedback mode. At this time, the oscillator circuit has the characteristics of low noise and is suitable for scenarios with high noise requirements such as voice call services. When the first switch S1 to the fourth switch S4 and the fifth switch S5 to the eighth switch S8 are closed, the second amplifier Am2 is in the working state, and the working mode of the oscillator circuit is switched to the negative resistance mode. At this time, the oscillator circuit has the characteristics of low power consumption and is suitable for scenarios with high noise requirements such as Internet services. Therefore, the oscillator circuit can be applied to different requirements for power consumption and noise in different scenarios. When the oscillator circuit includes Figure 8 The first amplifier or Figure 9 When the second amplifier is provided, the specific switching process is similar to the above switching process, and the embodiment of the present application will not be repeated here.

[0076] When the oscillator circuit operates in different modes and structures, the oscillator's power consumption and noise performance vary, thereby meeting the needs of different application scenarios. Specifically, the oscillator circuit's power consumption when operating in single-ended mode is greater than when operating in complementary mode, and the oscillator circuit's power consumption when operating in inductive feedback mode is greater than when operating in negative resistance mode. However, the noise performance is also improved accordingly due to the increased power consumption.

[0077] It should be noted that the above Figure 7-Figure 9 The specific structures of the first amplifier Am1 and the second amplifier Am2 shown are only exemplary. In actual applications, the first amplifier Am1 and the second amplifier Am2 can also be amplifiers of other topologies with the same functions, such as PMOS, NMOS and bipolar, etc., which will not be repeated in the embodiments of the present application.

[0078] Modern integrated circuit design and manufacturing are typically automated using Electronic Design Automation (EDA) tools. Example tools can be found from companies such as, but not limited to, Synopsys, Cadence, and Mentor Graphics. Details of these EDA tools are not required for this application.

[0079] Reference Figure 10, shows a simplified general ASIC design flow for producing an ASIC with an embodiment of the present application using (EDA) tools. At step 1000, a functional design of an ASIC is created that may include a VCO having a tapped inductor 200 according to the principles of the present application.

[0080] In practice, for these ASICs, the functional design is typically represented by writing register transfer level (RTL) code in a hardware description language (HDL), such as, but not limited to, VHDL or Verilog. Functional verification (behavioral simulation) is then preferably performed on the HDL data structures to ensure that the RTL design meets the logic specifications. Alternatively, a schematic capture program can be used to capture the schematic of the digital logic.

[0081] For the actual simulated portion of the ASIC (e.g., a VCO with a tapped inductor of the present application), the simulated functional design is typically represented by capturing the schematic using a schematic capture program. The output of the schematic capture program is then converted (synthesized) into a gate / transistor level netlist data structure.

[0082] At step 1002, the data structure is simulated by a simulation program within integrated circuits emphasis (SPICE). At step 1004, the data structure obtained from step 1002 is instantiated by its geometric representation and a physical layout of the ASIC is performed.

[0083] The first step in physical layout is typically what is called "floorplanning," in which the total area on the integrated circuit chip is allocated and the input / output (I / O) pins are defined. Hard cores (e.g., arrays, analog blocks, inductors, etc.) are placed within the total area based on design constraints (e.g., trace length, timing, etc.). Clock routing (often called a clock tree) is placed and guides the connections between gates / analog blocks. When all components are placed, global and detailed routing is run to connect all components together. Post-routing optimization is preferably performed to improve performance (timing closure), noise (signal integrity), and yield. The layout is modified where possible while remaining consistent with the design rules dictated by the selected in-house or external semiconductor manufacturing foundry to improve production efficiency. Such modifications may include adding additional vias or dummy metal / diffusion / polymer layers.

[0084] At step 1006, the physical design is verified. A design rule check (DRC) is performed to determine whether the physical layout of the ASIC meets a set of recommended parameters, namely the foundry's design rules. Design rules are a set of parameters provided by the foundry for a specific semiconductor manufacturing process. Design rules specify certain geometric and connectivity constraints to ensure that there is sufficient margin to account for variability in the semiconductor manufacturing process and to ensure that the ASIC functions properly. A layout versus schematic (LVS) check is preferably performed to verify that the physical layout corresponds to the original schematic or circuit diagram of the design. A full simulation is then preferably performed to ensure that the layout stage was completed correctly.

[0085] After the layout is verified in step 1006, the mask generation design data, typically in the form of a GDSII data structure, is said to be "taped out" for use in preparing the photomask at step 1008. The GDSII data structure is transferred from the circuit designer to the photomask supplier / manufacturer or directly to the semiconductor foundry via a communication medium (e.g., memory or a network).

[0086] At step 1010, a photomask is created and used to fabricate an ASIC according to the principles of the present application.

[0087] Some of the techniques described herein can be implemented by software stored on one or more computer-readable storage media and executed on a computer. The selected techniques can be executed on a single computer or on a computer networked with one or more other computers. For clarity, only those aspects of the tools or computers that are closely related to the disclosed techniques are described. Details of products well known in the art may be omitted.

[0088] Figure 11 Shown for practice Figure 11 1 is an illustrative example of a computing device 1101 for designing a flow. Figure 11 As shown, computing device 1101 includes a computing unit 1103 having a processing unit 1105 and a system memory 1107. Processing unit 1105 can be any type of programmable electronic device for executing software instructions, but is typically a microprocessor. System memory 1107 can include both read-only memory (ROM) 1109 and random access memory (RAM) 1111. Those skilled in the art will appreciate that both read-only memory 1109 and random access memory 1111 can store software instructions executed by processing unit 1105.

[0089] The processing unit 1105 and system memory 1107 are directly or indirectly connected to one or more peripheral devices via bus 1113 or an alternative communication structure. For example, the processing unit 1105 or system memory 1107 can be directly or indirectly connected to one or more additional storage devices 1115. Storage devices 1115 can include, for example, "hard" disk drives, solid-state disk drives, optical disk drives, and removable disk drives. The processing unit 1105 and system memory 1107 can also be directly or indirectly connected to one or more input devices 1117 and one or more output devices 1119. Input devices 1117 can include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, navigation ball, or joystick), a scanner, a camera, and a microphone. Output devices 1119 can include, for example, a display device, a printer, and speakers. For various examples of computing device 1101, one or more of peripheral devices 1115 through 1119 can be internally provided with the computing unit 1103. Alternatively, one or more of the peripheral devices 1115 to 1119 may be external to the housing of the computing unit 1103 and connected to the bus 1113 via a Universal Serial Bus (USB) connector or a Digital Visual Interface (DVI) connector, etc.

[0090] In some embodiments, the computing unit 1103 may also be directly or indirectly connected to one or more network interface cards (NICs) 1121 for communicating with other devices comprising the network. The NICs 1121 convert data and control signals from the computing unit 1103 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). Furthermore, the NICs 1121 may utilize any suitable connection agent (or combination of agents) for connecting to a network, including a wireless transceiver, a modem, or an Ethernet connection.

[0091] It should be understood that the computing device 1101 is shown only as an example and is not limiting. One or more computing devices may be used to implement the various embodiments of the present application, including one or more computing devices. Figure 11 The components of the computing device 1101 shown or including components (including those not shown) Figure 11 For example, the embodiments of the present application may be implemented using a multi-processor computer, multiple single and / or multi-processor computers arranged in a network, or some combination of the two.

[0092] In one embodiment, in a resonator device having an inductive element and a capacitive element, the inductive element comprises a tapped inductor, the tapped inductor comprises four terminals, two of the four terminals are coupled to the differential input of a first amplifier and the differential output of a second amplifier, and the other two terminals are coupled to the differential output of the first amplifier; the first amplifier and the second amplifier have switches that can be switched, and by switching, the oscillator circuit can operate in an inductive feedback mode or a negative resistance mode, respectively.

[0093] In another embodiment, a computer device includes a storage device for storing computer instructions including photomask data, for manufacturing an oscillator including a resonator device. The resonator device includes an inductive element and a capacitive element, wherein the inductive element includes a tapped inductor having four terminals, two of which are coupled to the differential input of a first amplifier and the differential output of a second amplifier, and the remaining two terminals are coupled to the differential output of the first amplifier. The first amplifier and the second amplifier have switches that can be switched to operate the oscillator circuit in an inductive feedback mode or a negative resistance mode, respectively.

[0094] In yet another embodiment, a floorplanning device includes logic for defining or allocating a total area on an integrated circuit and for defining input / output (I / O) pins. The floorplanning device includes a hard core placement device (e.g., arrays, analog blocks, inductors, etc.) for placement within the total area based on design constraints (e.g., trace length, timing, etc.). A clock routing placement device (often referred to as a clock tree) is used to place connections between the clock tree and the gates / analog blocks. Global and detailed guidance devices are used to design connections to connect all components together.

[0095] Physical design verification equipment, including design rule checking equipment, is used to verify that the physical design of a circuit (e.g., an ASIC) satisfies one or more design rules. Design rules specify certain geometric and connectivity constraints to ensure that there is sufficient margin to account for variability in the semiconductor manufacturing process, thereby ensuring that the ASIC functions properly. Layout versus schematic (LVS) equipment is used to verify that the physical layout corresponds to the original schematic or circuit diagram of the design. Simulation equipment is used to perform full simulations to ensure that the layout stage was completed correctly.

[0096] The tapeout apparatus is used to generate mask generation design data, typically in the form of a GDSII data structure, for use in preparing a photomask. The GDSII data structure is transmitted from the circuit designer to the photomask supplier / manufacturer or directly to the semiconductor foundry via a communication medium (e.g., a memory or a network). The photomask creation apparatus creates a photomask for manufacturing an ASIC according to the principles of the present application. Among other features, it should be understood that the apparatus described above is optionally used to produce a resonator device and an amplifier device as described and claimed herein.

[0097] Some of the techniques described herein can be implemented by software stored on one or more computer-readable storage media and executed on a computer. The selected techniques can be executed on a single computer or on a computer networked with one or more other computers. For clarity, only those aspects of the tools or computers that are closely related to the disclosed techniques are described. Details of products well known in the art may be omitted.

[0098] Although features and elements are described above in specific combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements. Examples of computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, optical media such as CD-ROMs, and digital versatile disks (DVDs).

[0099] Although the present application has been described with respect to certain embodiments and generally related methods, variations and permutations of these embodiments and methods will be apparent to those skilled in the art. In particular, it should be noted that although the present application has been described in the context of CMOS amplifiers, those skilled in the art will recognize the application of PMOS and NMOS amplifiers, bipolar amplifiers, and other suitable topologies without departing from the scope of the present application. The present application is applicable to almost all communication systems. For example, the present application can be used in cellular transceivers, two-way radio communications, Wi-Fi applications, satellite receivers, and any application using voltage-controlled oscillators.

[0100] It should be noted that the embodiments and drawings of the present application are merely examples. Each MOS transistor in any embodiment or drawing may be a single MOS transistor that meets the required startup gain or required conduction current, or may be a combination of MOS transistors that meet the required startup gain or required conduction current formed by connecting multiple MOS transistors in parallel, that is, the sum of the startup gains corresponding to each of the multiple MOS transistors is greater than or equal to the required startup gain; each capacitor in the embodiment of the present application may be a single capacitor that meets the required capacitance value, or may be a combination of multiple capacitors that meet the required capacitance value by connecting multiple capacitors in parallel or in series, that is, the capacitance value corresponding to the multiple capacitors after being connected in series or in parallel is equal to the required capacitance value; each inductor in the embodiment of the present application may be a single inductor that meets the required inductance value, or may be a combination of multiple inductors that meet the required inductance value by connecting multiple inductors in series or in parallel; each resistor in the embodiment of the present application may be a single resistor that meets the required resistance value, or may be a combination of multiple resistors that meet the required resistance value by connecting multiple resistors in parallel or in series, that is, the resistance value corresponding to the multiple resistors after being connected in series or in parallel is equal to the required resistance value.

[0101] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An oscillator circuit, characterized in that: include: The first amplifier and the second amplifier are provided with switches, and the oscillator circuit can be operated in an inductive feedback mode or a negative resistance mode respectively by switching; a resonator comprising a capacitive element and an inductive element, wherein the inductive element comprises a tapped inductor, and the tapped inductor comprises four terminals, namely, a first terminal, a second terminal, a third terminal, and a fourth terminal; The first amplifier is used to make the oscillator circuit operate in the inductive feedback mode, the differential input terminals of the first amplifier are coupled to the first terminal and the fourth terminal respectively, and the differential output terminals of the first amplifier are coupled to the second terminal and the third terminal respectively; The second amplifier is used to enable the oscillator circuit to operate in the negative resistance mode, and the differential output terminals of the second amplifier are coupled to the first terminal and the fourth terminal respectively.

2. The circuit according to claim 1, wherein: The first amplifier includes two groups of first coupling tubes whose gates and drains are coupled in the same polarity, and the sources of the two groups of first coupling tubes are respectively coupled to a positive power rail and a negative power rail through switches.

3. The circuit according to claim 2, characterized in that The first amplifier includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first switch, a second switch, a third switch and a fourth switch; The gate of the first NMOS transistor and the gate of the first PMOS transistor are both coupled to the first terminal, the drain of the first NMOS transistor and the drain of the first PMOS transistor are both coupled to the third terminal, the drain of the second NMOS transistor and the drain of the second PMOS transistor are both coupled to the second terminal, the gate of the second NMOS transistor and the gate of the second PMOS transistor are both coupled to the fourth terminal, the source of the first PMOS transistor and the source of the second PMOS transistor are respectively coupled to the positive power rail through the first switch and the second switch, and the source of the first NMOS transistor and the source of the second NMOS transistor are respectively coupled to the negative power rail through the third switch and the fourth switch.

4. The circuit according to claim 1, wherein: The first amplifier includes a first MOS transistor, a second MOS transistor, a first switch and a second switch, and the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors; The gate of the first MOS transistor is coupled to the first terminal, the drain of the first MOS transistor is coupled to the third terminal, the drain of the second MOS transistor is coupled to the second terminal, the gate of the second MOS transistor is coupled to the fourth terminal, and the sources of the first MOS transistor and the second MOS transistor are coupled to the positive power rail or the negative power rail through the first switch and the second switch respectively.

5. The circuit according to any one of claims 1 to 4, characterized in that: The second amplifier is used to enable the oscillator circuit to operate in a single-ended negative resistance mode.

6. The circuit according to claim 5, characterized in that The second amplifier includes: a third MOS transistor, a fourth MOS transistor, a fifth switch and a sixth switch, wherein the third MOS transistor and the fourth MOS transistor are both PMOS transistors or NMOS transistors; The drain of the third MOS transistor is coupled to the first terminal through the fifth switch and the gate of the fourth MOS transistor, the drain of the fourth MOS transistor is coupled to the fourth terminal through the sixth switch and the gate of the third MOS transistor, and the source of the third MOS transistor and the source of the fourth MOS transistor are both coupled to a positive power rail or a negative power rail.

7. The circuit according to any one of claims 1 to 4, characterized in that: The second amplifier is used to enable the oscillator circuit to operate in a complementary negative resistance mode.

8. The circuit according to claim 7, characterized in that The second amplifier includes two groups of second coupling transistors with cross-coupled gates and drains, and the drains are coupled through switches. The sources of the two groups of second coupling transistors are coupled to a positive power rail and a negative power rail, respectively.

9. The circuit according to claim 8, characterized in that The second amplifier includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth switch, a sixth switch, a seventh switch and an eighth switch; The drain of the third PMOS transistor is coupled to the first terminal through the fifth switch and the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor is coupled to the fourth terminal through the sixth switch and the gate of the third PMOS transistor, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both coupled to the positive power rail, the drain of the third NMOS transistor is coupled to the first terminal through the seventh switch and the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor is coupled to the fourth terminal through the eighth switch and the gate of the third NMOS transistor, and the source of the third NMOS transistor and the source of the fourth NMOS transistor are both coupled to the negative power rail.

10. The circuit according to claim 1, wherein: For the first amplifier, a first impedance is formed between the first terminal and the fourth terminal, a second impedance is formed between the second terminal and the third terminal, an input voltage at the input end of the first amplifier is greater than an output voltage determined by a voltage divider, and the voltage divider is formed by the first impedance and the second impedance.

11. The circuit according to claim 10, characterized in that The input voltage exceeds a supply voltage of the first amplifier.

12. The circuit according to claim 1, wherein: The tapped inductor includes two tap sections, the two tap sections are respectively located at the second terminal and the fourth terminal, and the two tap sections are wired in the middle of the tapped inductor.

13. A non-transitory computer-readable medium for use with a computer, characterized in that The computer has software for creating an integrated circuit, and the computer-readable medium has stored thereon one or more computer-readable data structures having photomask data for fabricating the oscillator circuit according to any one of claims 1-12.

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