A pipeline data transmission method and a data pipeline device

Abstract

The present invention proposes a pipeline data transmission method and a data pipeline device. The data pipeline device includes a front-stage module, a rear-stage module and a buffer coupled between the front-stage module and the rear-stage module. The buffer includes a plurality of storage units. The pipeline data transmission method includes: performing a plurality of write-read rounds; in each write-read round, the front-stage module performs a write operation on each storage unit in sequence according to a write sequence; and in each write-read round, the rear-stage module performs a read operation on each storage unit in sequence according to a read sequence; wherein, in two consecutive write-read rounds, the write sequence in the latter write-read round is the same as the read sequence in the former write-read round.

Description

Technical Field

[0001] The present invention relates to a data transmission technology, and in particular to a pipeline data transmission method and a data pipeline device. Background Art

[0002] In order to avoid power consumption caused by frequent storage and reading of memory, data transmission between two electronic components can be done by connecting a buffer in series between the two to allow the data transmitter to store the data to be transmitted and the data receiver to read the data stored in the buffer. However, when two electronic components store and read the same buffer at the same time, data loss is inevitable. For example, data is written to a certain area of ​​the buffer, and new data is written to the area before it can be read. In particular, this problem is particularly prone to occur when the two electronic components have different access orders to the buffer.

[0003] In order to overcome this problem, there is a method of using two buffers, where the data transmitter alternately writes data to the two buffers for the data reader to read. In this way, although the problem of data loss can be solved, it requires twice the buffer cost. Summary of the invention

[0004] In view of the above problems, the present invention proposes a pipeline data transmission method, which is applied to a data pipeline device. The data pipeline device includes a front-stage module, a rear-stage module and a buffer coupled between the front-stage module and the rear-stage module. The buffer includes a plurality of storage units. The pipeline data transmission method includes: performing a plurality of write-read rounds; in each write-read round, the front-stage module performs a write operation on each storage unit in sequence according to a write order; and in each write-read round, the rear-stage module performs a read operation on each storage unit in sequence according to a read order; wherein, in two consecutive write-read rounds, the write order in the later write-read round is the same as the read order in the previous write-read round.

[0005] One embodiment of the present invention further proposes a data pipeline device, comprising a front-stage module, a rear-stage module and a buffer. The buffer is coupled between the front-stage module and the rear-stage module, and comprises a plurality of storage units. The front-stage module and the rear-stage module perform a plurality of write-read rounds. In each write-read round, the front-stage module performs a write operation on each storage unit in sequence according to a write sequence, and the rear-stage module performs a read operation on each storage unit in sequence according to a read sequence. In two consecutive write-read rounds, the write sequence in the latter write-read round is the same as the read sequence in the former write-read round.

[0006] According to the data pipeline device and pipeline data transmission method proposed in the embodiment of the present invention, when using a single buffer, the front-stage module and the back-stage module can each use their own write order and read order to access the buffer, and at the same time avoid the data loss problem caused by the overwriting of unread data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0008] Figure 1 It is a schematic diagram of the structure of a data pipeline device according to an embodiment of the present invention;

[0009] Figure 2 A flowchart of a pipeline data transmission method according to an embodiment of the present invention;

[0010] Figure 3 A schematic diagram of performing a write operation on a buffer according to an embodiment of the present invention;

[0011] Figure 4 A schematic diagram of performing a read operation on a buffer according to an embodiment of the present invention; and

[0012] Figure 5 FIG. 4 is a detailed flow chart of a pipeline data transmission method according to an embodiment of the present invention.

[0013]

Explanation of symbols

[0014] 100: Data pipeline device

[0015] 110:Pre-stage module

[0016] 120: Post-stage module

[0017] 130: Buffer

[0018] 131: Storage unit

[0019] S210, S220, S230: Steps

[0020] S510, S520, S530, S540, S550, S560: Steps DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0023] Reference Figure 1 , is a schematic diagram of the architecture of a data pipeline device according to an embodiment of the present invention. The data pipeline device 100 includes a front-stage module 110, a back-stage module 120, and a buffer 130 coupled between the front-stage module 110 and the back-stage module 120. The front-stage module 110 and the back-stage module 120 are two independent electronic devices. In some embodiments, the front-stage module 110 is an image sensor, the back-stage module 120 is an image encoder, and the transmitted data is image data. For ease of explanation, this application scenario will be used as an example for explanation below, but the present invention is not limited to this application scenario. In some embodiments, the back-stage module 120 is an image encoder that complies with the High Efficiency Video Coding (HEVC) architecture.

[0024] Reference Figure 2 , is a flow chart of a pipeline data transmission method according to an embodiment of the present invention. The pipeline data transmission method is applied to the aforementioned data pipeline device 100 , so that the front-stage module 110 can transmit data to the back-stage module 120 .

[0025] In step S210, a plurality of write-read rounds are performed. That is, after completing a write-read round, the next write-read round is continued. In other words, before completing a write-read round, the next write-read round will not be entered. A write-read round means that the front-stage module 110 completely writes a piece of data into the buffer 130, and the back-stage module 120 reads the data completely from the buffer 130. The piece of data, taking image data as an example, may be, for example, an image, a certain strip (Slice) of an image, etc. In some embodiments, during the process of the front-stage module 110 writing data (the data has not been completely written), the back-stage module 120 starts to read the data. In some embodiments, within a write / read round, the read operation starts after the write operation is completed. Between two consecutive write / read rounds, the next round of write operation can start before the previous round of read operation is completed.

[0026] Reference Figure 3, is a schematic diagram of performing a write operation on a buffer 130 according to an embodiment of the present invention. The buffer 130 includes a plurality of storage units 131. The storage unit 131 is the minimum unit for performing a write operation or a read operation. The storage unit 131 includes one or more storage units (not shown). The storage unit is the minimum memory unit in the buffer 130. For example, the storage capacity of a storage unit is one byte, and the storage capacity of a storage unit 131 is four bytes (i.e., a storage unit 131 has four storage units). For the convenience of explanation, here only the buffer 130 having 20 storage units 131 is taken as an example, but the present invention is not limited to this number and should include fewer or more storage units 131. Here, the storage units 131 are arranged in a two-dimensional manner of four rows and five columns. In some embodiments, the number of storage units 131 in a row (here five) is positively correlated with the stride of the image data. Specifically, a row of storage units 131 can store a plurality of rows of pixel data of the image. In some embodiments, the number of storage units 131 in a row (here, four) is positively correlated with the height of the image data, that is, a storage unit 131 in a row can store multiple rows of pixel data of the image. In some embodiments, one storage unit 131 can store one Coding Tree Unit (CTU).

[0027] In step S220, in each write-read round, the front-stage module 110 performs a write operation on each storage unit 131 in sequence according to a write sequence. Figure 3 As shown in FIG. 1 , the numbers marked in the storage unit 131 are the ordinal numbers of the storage units 131 for performing the write operation. The number "1" represents the first storage unit 131 for performing the write operation, the number "2" represents the second storage unit 131 for performing the write operation, and so on. Figure 3 In the illustrated embodiment, the storage cells 131 in the first column are written from left to right, and then the storage cells 131 in the second column are written from left to right, and then the storage cells 131 in the third column are written from left to right, and finally the storage cells 131 in the fourth column are written from left to right. This order is generally referred to as raster order.

[0028] In step S230, in each write-read round, the subsequent module 120 performs a read operation on each storage unit 131 in sequence according to a read order. Figure 4 , is a schematic diagram of performing a read operation on a buffer 130 according to an embodiment of the present invention. The numbers marked in the storage units 131 are the ordinal numbers of the storage units 131 performing the read operation. The number "1" represents the first storage unit 131 performing the read operation, the number "2" represents the second storage unit 131 performing the read operation, and so on. Figure 4 In the example shown, the storage cells 131 in the first row from the left are read from top to bottom, and then the storage cells 131 in the second row from the left are read from top to bottom, then the storage cells 131 in the third row from the left are read from top to bottom, and then the storage cells 131 in the fourth row from the left are read from top to bottom, and finally the storage cells 131 in the fifth row from the left are read from top to bottom. This order is generally referred to as a tile order.

[0029] For the convenience of explanation, the following embodiment defines the address of the storage unit 131 as follows: Figure 3 The ordinal number shown. That is, the address of the storage unit 131 in the first column and the first row is "1", the address of the storage unit 131 in the first column and the second row is "2", and so on. The aforementioned write sequence refers to the sequence formed by arranging the addresses of the corresponding storage units 131 in the order in which the write operation is performed. The aforementioned read sequence refers to the sequence formed by arranging the addresses of the corresponding storage units 131 in the order in which the read operation is performed.

[0030] Referring to Table 1, the writing sequence and reading sequence of multiple writing and reading rounds of an embodiment of the present invention are shown. It can be seen that in two consecutive writing and reading rounds, the writing sequence in the later writing and reading round is the same as the reading sequence in the previous writing and reading round. For example, the writing sequence of the second writing and reading round is the same as the reading sequence of the first writing and reading round, and the writing sequence of the third writing and reading round is the same as the reading sequence of the second writing and reading round. In this way, in two consecutive writing and reading rounds, if the execution sequence number of the writing sequence in the later writing and reading round is less than the execution sequence number of the reading sequence in the previous writing and reading round, the storage unit 131 that has not been read will not be written with new data and cause data loss. For example, when the execution sequence number of the reading sequence is "5", the execution sequence number of the writing sequence can be "1", "2", "3", "4", but cannot be "5" or a sequence number thereafter. The execution sequence number refers to the sequence number of the address of the storage unit 131 to which the writing action is currently to be performed, which is located in the writing sequence. For example, in the write sequence in the second write-read round, if the current write operation is to be performed on the storage unit 131 with the address "16", the execution sequence number is "4".

[0031] Table 1

[0032]

[0033] Referring to Table 1, the writing order and reading order in the same writing and reading round are different. Therefore, the front-stage module 110 and the back-stage module 120 can be written and read respectively according to their needs. For example, the front-stage module 110 as an image sensor writes the image data to the buffer 130 column by column, and the back-stage module 120 as an image encoder needs to read the image data from the buffer 130 block by block for encoding.

[0034] Referring to Table 1, there is a mapping relationship between the write order and the read order in the same write-read round, and the mapping relationship of each write-read round is the same. That is to say, in the same write-read round, there is a mapping relationship between the two addresses of the same ordinal number in the write order and the read order; in each write-read round, the address in the write order is mapped to the address in the read order in the same way. For example, in the first write-read round, the address with ordinal number "2" in the write order is "2", and the address with ordinal number "2" in the read order is "6", while in other write-read rounds, the address "2" in the write order is mapped to the address "6" in the read order (for example, ordinal number "5" in the second write-read round). Table 2 shows the mapping relationship between the addresses in the write order and the addresses in the read order in one embodiment of the present invention.

[0035] Table 2

[0036]

[0037] Reference Figure 5 , is a detailed flow chart of a pipeline data transmission method according to an embodiment of the present invention. First, in step S510, the initial value of the parameter is set. The parameter is the parameter used in the calculation formula described below, which will be described later.

[0038] In step S520, the front-stage module 110 performs a write operation on the storage unit 131 at the current address; the rear-stage module 120 performs an operation on the storage unit 131 at the current address. For the front-stage module 110, the current address is the address corresponding to the current execution sequence number in the write sequence; for the rear-stage module 120, the current address is the address corresponding to the current execution sequence number in the read sequence. The current execution sequence number of the front-stage module 110 and the current execution sequence number of the rear-stage module 120 may be different.

[0039] After completing step S520, proceed to step S530 to obtain the address of the next execution sequence number as the current address for the next write or read operation. The calculation formula is shown in formula (1). Add(n) is the write address or read address of the current sequence number, and Add(n+1) is the write address or read address of the next sequence number. n is the current sequence number. p is the displacement between the current address and the next address. If Add(n+1) obtained by formula (1) is greater than z, then Add(n+1) is updated according to formula (2). z is the number of storage units 131. In this example, z is 20. n, p, and z are positive integers. Herein, the initial values ​​of the parameters set in the aforementioned step S510 are supplemented: n is 1, Add(1) is 1, the initial value of p of the previous module 110 is 1, and the initial value of p of the next module 120 is 5.

[0040] Add(n+1)=Add(n)+p Formula (1)

[0041] Add(n+1)=Add(n+1)-z+1 Formula (2)

[0042] In step S540, it is determined whether the image data has been written or read. If so, the process proceeds to step S550; if not, the process returns to step S520 to continue the next writing or reading operation.

[0043] In step S550, determine whether to execute the next write-read round (that is, determine whether the write order or read order of this write-read round is completed). If so, enter step S560 to update the parameter value, and the calculation formula is shown in formula (3); if not, end the process. Formula (3) is the product of p and s divided by z and then taking the largest integer less than or equal to it (or called "rounding down"), plus the product of p and s divided by the remainder of z, as the p value of the next read-write round. s is a positive integer. In this example, s is positively correlated with the span of the image data. Specifically, s is the number of storage units 131 in a row (here 5), but the embodiments of the present invention are not limited to this, and s can also be set to other values. The p values ​​corresponding to the write order and the read order in each write-read round are shown in Table 1.

[0044]

[0045] In another embodiment, instead of using formula (3), the parameter value is updated through formula (3-1) to formula (3-3), which can avoid multiplication and division calculations, improve computing performance or reduce hardware costs. Before executing formula (3-1), execute formula (3-2) p times to obtain the q value. In the process of executing formula (3-2) p times, check the result after each execution of formula (3-2). If the calculated q value is greater than z, update the q value according to formula (3-3), and then continue the next calculation of formula (3-2). Finally, use the calculated final q value as the new p value (i.e., formula (3-1)), and reset the q value to 0. It is supplemented here that in the aforementioned step S510, the initial value of the parameter set also includes: the initial value of q is 0.

[0046] p=q Formula (3-1)

[0047] q=q+s Formula (3-2)

[0048] q=q-z+1 Formula (3-3)

[0049] In summary, according to the data pipeline device 100 and the pipeline data transmission method proposed in the embodiment of the present invention, when using a single buffer 130, the front-stage module 110 and the back-stage module 120 can each use their own write order and read order to access the buffer 130, and at the same time avoid the problem of data loss caused by overwriting of unread data.

[0050] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A pipeline data transmission method is applied to a data pipeline device, the data pipeline device comprises a front-stage module, a rear-stage module and a buffer coupled between the front-stage module and the rear-stage module, the buffer comprises a plurality of storage units, the pipeline data transmission method comprises: Perform multiple write and read rounds; In each of the write-read rounds, the front-stage module sequentially performs a write operation on each of the storage units according to a write sequence; and In each of the write-read rounds, the post-stage module sequentially performs a read operation on each of the storage units according to a read sequence; in, In two consecutive write-read rounds, the writing order in the latter write-read round is the same as the reading order in the former write-read round; Among them, in two consecutive write-read rounds, the execution sequence number of the write sequence in the later write-read round is smaller than the execution sequence number of the read sequence in the previous write-read round. 2 . The pipeline data transmission method as claimed in claim 1 , wherein the writing order and the reading order in the same writing and reading round are different. 3 . The pipeline data transmission method as claimed in claim 2 , wherein there is a mapping relationship between the write order and the read order in the same write-read round, and the mapping relationship of each write-read round is the same.

4. The pipeline data transmission method of claim 1, wherein at least one of the write sequence and the read sequence is a sequence formed by arranging an address corresponding to each storage unit in the order of executing the related action, which is expressed as formula (1), if Add(n+1) obtained by formula (1) is greater than z, then Add(n+1) is updated according to formula (2), wherein Add(n) is the write address of the current sequence number, Add(n+1) is the write address of the next sequence number, z is the number of the storage units, n is the current sequence number, and n, p, and z are positive integers; Add(n+1)=Add(n)+p Formula (1) Add(n+1)=Add(n+1)-z+1 Formula (2).

5. The pipeline data transmission method as claimed in claim 1, wherein after the write-read round is completed, the p value is calculated according to formula (3); in, p, s, z are positive integers.

6. The pipeline data transmission method as claimed in claim 4, wherein after the write-read round is completed, the value of p is updated according to formula (3-1); p=q Formula (3-1) q=q+s Formula (3-2) q=q-z+1 Formula (3-3) in, Before executing formula (3-1), execute formula (3-2) p times to obtain the q value. If the q value after each execution of formula (3-2) is greater than z, the q value is updated according to formula (3-3). q is a positive integer and the initial value of q is 0. 7 . The pipeline data transmission method according to claim 4 , wherein each of the write-read rounds is to write an image data into the buffer and read the image data from the buffer, wherein s is positively correlated with the span of the image data.

8. A data pipeline device, comprising: A preamplifier module; a post-stage module; and A buffer zone is coupled between the front-stage module and the rear-stage module and includes a plurality of storage units; in, The front-stage module and the rear-stage module perform a plurality of write-read rounds. In each of the write-read rounds, the front-stage module performs a write operation on each storage unit in sequence according to a write sequence, and the rear-stage module performs a read operation on each storage unit in sequence according to a read sequence; wherein, in two consecutive write-read rounds, the write order in the later write-read round is the same as the read order in the previous write-read round; Among them, in two consecutive write-read rounds, the execution sequence number of the write sequence in the later write-read round is smaller than the execution sequence number of the read sequence in the previous write-read round. 9 . The data pipeline device as claimed in claim 8 , wherein the write order and the read order in the same write-read round are different. 10 . The data pipeline device as claimed in claim 9 , wherein there is a mapping relationship between the write sequence and the read sequence in the same write-read round, and the mapping relationship of each write-read round is the same.

11. The data pipeline device of claim 8, wherein at least one of the write sequence and the read sequence is a sequence formed by arranging an address corresponding to each storage unit in the order of executing the related action, which is expressed as formula (1), if Add(n+1) obtained by formula (1) is greater than z, then Add(n+1) is updated according to formula (2), wherein Add(n) is the write address of the current sequence number, Add(n+1) is the write address of the next sequence number, z is the number of the storage units, n is the current sequence number, and n, p, and z are positive integers; Add(n+1)=Add(n)+p Formula (1) Add(n+1)=Add(n+1)-z+1 Formula (2).

12. The data pipeline device as claimed in claim 11, wherein after the write-read round is completed, the p value is updated according to formula (3); in, p, s, z are positive integers.

13. The data pipeline device as claimed in claim 11, wherein after the write-read round is completed, the p value is updated according to formula (3-1); p=q Formula (3-1) q=q+s Formula (3-2) q=q-z+1 Formula (3-3) in, Before executing formula (3-1), execute formula (3-2) p times to obtain the q value. If the q value after each execution of formula (3-2) is greater than z, the q value is updated according to formula (3-3). q is a positive integer and the initial value of q is 0. 14 . The data pipeline device according to claim 11 , wherein s is positively correlated with a span of data.

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