A multi-CPU system and communication method thereof

Abstract

The present application discloses a multi-CPU system and a communication method thereof. The system comprises at least one group of CPU groups, wherein the group comprises a protocol proxy chip and 2 N CPUs, each CPU is directly connected to a protocol proxy chip and some CPUs in the same group; the mapping configuration information of the CPU includes the identification IDs of the directly connected CPU and the protocol proxy chip; the mapping configuration information of the protocol proxy chip includes the identification IDs of each CPU in the same group, and the protocol proxy chip is used to send the data packet to the target CPU when receiving the data packet sent by the CPU in the same group and determining that the data packet is sent to the target CPU in the same group. The technical solution disclosed in the present application configures the identification ID of the CPU that is not directly connected in the same group to the protocol proxy chip, and the protocol proxy chip acts as a proxy for the CPU in the group so that the group contains the maximum number of CPUs, thereby improving the utilization rate of the number of CPUs in the group and the CPU identification ID.

Description

Technical Field

[0001] The present application relates to the technical field of system design, and more specifically, to a multi-CPU system and a communication method thereof. Background Art

[0002] As the performance improvement of a single CPU continues to slow down, more systems choose to increase the number of CPUs to meet performance and power requirements. In the same system, the interconnection between multiple CPUs is limited by two conditions: the maximum number of transmission ports on a single CPU that can be used for interconnection and the ID design of the CPU in the data transmission protocol.

[0003] At present, in order to increase the maximum number of CPUs that can be accommodated in a single system under the above two conditions, it is generally implemented through a protocol proxy chip. Specifically, the CPUs are grouped, and each group contains a number of CPUs that can be distinguished by an identification ID and a corresponding protocol proxy chip. The CPUs in the group recognize and communicate with each other, and the CPUs outside the group are accessed through the protocol proxy chip, that is, the protocol proxy chip is responsible for the external agent. Obviously, the data transmission delay between different groups will be higher than the data transmission within the group. Therefore, the number of CPUs in the group is generally increased as much as possible. However, in the existing system, because a fixed identification ID must be assigned to the protocol proxy chip, it will result in only 2 CPUs in each group. n -1 CPU (n is the bit width of the identification ID), that is, 3, 7, 15..., which will reduce the number of CPUs in the same group, that is, the utilization rate of the identification ID cannot be maximized. At the same time, in order to design the circuit around the CPU symmetrically, it will tend to set 2, 4, 8 CPUs in each group, which will further reduce the number of CPUs in the same CPU group.

[0004] In summary, how to increase the number of CPUs in a group so that the system can include more CPUs is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a multi-CPU system and a communication method thereof, which are used to increase the number of CPUs in a group so that a larger number of CPUs can be included in the system.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] A multi-CPU system includes at least one group of CPU groups, wherein the CPU group includes a protocol proxy chip and 2 NCPUs, each of the CPUs in the CPU group is directly connected to the protocol proxy chip and some CPUs in the same CPU group according to the number of its ports; N is the number of bits of the bit width of the identification ID of the CPU;

[0008] The mapping configuration information of each of the CPUs in the same CPU group includes the identification ID of the directly connected CPU and the identification ID of the protocol proxy chip, so as to send a data packet to the corresponding directly connected CPU or protocol proxy chip according to the identification ID;

[0009] The mapping configuration information of the protocol proxy chip includes the identification ID of each CPU in the same CPU group. The protocol proxy chip is used to send the data packet to the target CPU when it receives a data packet sent by a CPU in the same CPU group and determines that the data packet is sent to the target CPU in the same CPU group based on the data packet and the identification ID of each CPU.

[0010] Preferably, the protocol proxy chip is used to send the data packet to the protocol proxy chip in the other CPU group when it is determined that the data packet is sent to other CPU groups, so that the protocol proxy chip in the other CPU group sends the data packet to the corresponding CPU.

[0011] Preferably, when the protocol proxy chip receives multiple data packets, the protocol proxy chip is further used to send each data packet in descending order of priority according to the priority of the data path corresponding to each data packet.

[0012] Preferably, the CPU group includes a plurality of connected protocol proxy chips, and each of the CPUs in the same CPU group is directly connected to at least one of the protocol proxy chips in the same CPU group.

[0013] Preferably, the number of ports on the protocol proxy chip is greater than 2 N +M, where M is the number of protocol proxy chips in the same CPU group.

[0014] Preferably, the protocol proxy chip is specifically used to determine the identification ID corresponding to the data packet based on the access address in the data packet, the mapping relationship between the access address and the identification ID in the mapping configuration information of the protocol proxy chip, and determine whether the data packet is sent to the target CPU in the same CPU group based on the identification ID.

[0015] Preferably, the protocol proxy chip is specifically used to identify an identification ID according to a command type in the data packet, and determine whether the data packet is sent to a target CPU in the same CPU group according to the identification ID.

[0016] A communication method for a multi-CPU system, applied to the multi-CPU system as described in any one of the above, comprising:

[0017] When a CPU in the same CPU group communicates with a directly connected CPU, a data packet is sent to the directly connected CPU according to the mapping configuration information in the CPU;

[0018] When a CPU in the same CPU group communicates with a non-directly connected CPU, a data packet is sent to the protocol proxy chip in the same CPU group;

[0019] The protocol proxy chip determines whether the data packet is sent to a target CPU in the same CPU group according to the identification IDs of the CPUs in the same CPU group contained in the data packet and its own mapping configuration information, and if so, sends the data packet to the target CPU.

[0020] Preferably, when the protocol proxy chip determines that the data packet is sent to other CPU groups, it also includes:

[0021] The protocol proxy chip sends the data packet to the protocol proxy chips in other CPU groups, so that the protocol proxy chips in other CPU groups send the data packet to the corresponding CPU.

[0022] Preferably, when the protocol proxy chip receives multiple data packets, it also includes:

[0023] The protocol proxy chip sends each data packet in descending order of priority according to the priority of the data path corresponding to each data packet.

[0024] The present application provides a multi-CPU system and a communication method thereof, wherein the multi-CPU system comprises: at least one group of CPU groups, wherein the CPU groups comprise a protocol proxy chip and 2 N A CPU is included in the CPU group, and each CPU in the CPU group is directly connected to the protocol proxy chip and some CPUs in the same CPU group according to its port number; N is the number of bits of the bit width of the CPU identification ID; the mapping configuration information of each CPU in the same CPU group includes the identification ID of the directly connected CPU and the identification ID of the protocol proxy chip, so as to send a data packet to the corresponding directly connected CPU or protocol proxy chip according to the identification ID; the mapping configuration information of the protocol proxy chip includes the identification ID of each CPU in the same CPU group, and the protocol proxy chip is used to send the data packet to the target CPU when receiving the data packet sent by the CPU in the same CPU group and determining that the data packet is sent to the target CPU in the same CPU group according to the data packet and the identification ID of each CPU.

[0025] The above technical solution disclosed in this application, each CPU group in the multi-CPU system includes a protocol proxy chip and 2 N A CPU is provided, and each CPU is directly connected to a protocol proxy chip and some CPUs according to the number of its ports. The mapping configuration information of each CPU in the same CPU group includes the identification ID of the CPU directly connected thereto and the identification ID of the protocol proxy chip, that is, the identification ID of the CPU that is not directly connected to the CPU in the same CPU group is configured to the protocol proxy chip, so that the CPU sends all data packets sent to the non-directly connected CPU to the protocol proxy chip for forwarding by the protocol proxy chip. The protocol proxy chip also includes the identification ID of each CPU in the same CPU group, so that the protocol proxy chip can identify each CPU in the same CPU group. When the protocol proxy chip receives a data packet sent by a CPU in the same group, it can identify the destination of the data packet according to the identification ID of each CPU contained in the data packet and the mapping configuration information, and when it is identified that the data packet is sent to a target CPU in the same CPU group, the data packet is sent to the target CPU in the same CPU group, thereby realizing the proxy of the CPU in the group. It can be seen that the present application configures the identification ID of the CPU that is not directly interconnected with the CPU in the same CPU group to the protocol proxy chip, and the protocol proxy chip can identify each CPU in the same CPU group and can proxy the CPU in the group so that the same CPU group can contain the maximum number of CPUs (i.e., 2 N )CPU, thereby increasing the number of CPUs in the group and the utilization rate of the identification ID, so that the system can include more CPUs to meet the performance requirements of the system. In addition, since the CPUs in this application are divided into direct connection and indirect connection, it can provide a basis for the integration of CPUs with different requirements on the system and for heterogeneous computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0027] Figure 1 A schematic diagram of intra-group connection in which the ID in the prior art is 2 bits wide and the CPU supports a maximum of three ports;

[0028] Figure 2 A schematic diagram of an intra-group connection in which the ID in the prior art is 2 bits wide and the CPU supports a maximum of two ports;

[0029] Figure 3 Another intra-group connection diagram in the prior art where the ID is 2 bits wide and the CPU supports a maximum of two ports;

[0030] Figure 4 A schematic diagram of the structure of a multi-CPU system provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of another multi-CPU system provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the interconnection structure within a CPU group with a 2-bit wide identification ID and three ports for each CPU provided in an embodiment of the present application;

[0033] Figure 7 A flow chart of a communication method for a multi-CPU system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] With the development of technologies such as big data and artificial intelligence, on the one hand, there are more and more targeted optimizations for different application scenarios, and on the other hand, the requirements for system power consumption and other aspects are becoming more and more stringent. As the process advances deeper (specifically, after 7nm), the material and physical limitations are increasing, and the performance improvement of a single CPU is also slowing down. In this case, faced with the requirements of performance and power consumption, more systems have chosen solutions different from the traditional ones. One is to improve the performance of a single CPU (by integrating more cores, etc.), and the other is to increase the number of CPUs or other chips in the system.

[0035] In the same system, the interconnection between multiple CPUs is limited by two conditions: the maximum number of transmission ports that can be used for interconnection on a single CPU and the design of the CPU in the data transmission protocol, which reserves how many bits of width for the CPU to identify and define the IDs of different CPUs in the same system. For example, if the width is 2 bits, then a single system supports up to 4 CPUs interconnected. Obviously, the above two conditions cannot be modified after the CPU is produced, and in the design stage before production, due to cost and reliability considerations, the CPU will not reserve too many transmission ports specifically for large-scale and ultra-large-scale systems. Similarly, too many ID bits will reduce the efficiency of data transmission, and generally no additional bits are reserved. In practice, mainstream CPU products generally integrate up to 3 ports for interconnecting CPUs and 2 to 3-bit identification IDs on the CPU.

[0036] At present, in order to increase the maximum number of CPUs that can be accommodated in a single system under the above two conditions, it is generally implemented through a protocol proxy chip, wherein the protocol proxy chip refers to a chip that integrates a CPU interconnection port, can be directly connected to the CPU, and implements the function of the proxy node in the CPU transmission protocol, that is, it can be recognized by the CPU at the protocol level, so that the CPU can communicate with a specific target through the forwarding of the protocol proxy chip. In simple terms, the CPUs are grouped, and each group contains a number of CPUs that can be distinguished by an identification ID and a corresponding protocol proxy chip. The data transmission between different groups needs to be forwarded through the protocol proxy chips of the two groups in turn, that is, the protocol proxy chip is responsible for the external agency, and the CPUs in the same group communicate through the port directly connected to the CPU. Obviously, the data transmission between different groups will have a much higher delay than the data transmission within the group. Therefore, the number of CPUs in the group will generally be increased as much as possible. For example, assuming that the identification ID is 2 bits wide, an identification ID must be assigned to the protocol proxy chip. Therefore, a maximum of 3 CPUs can be placed in a group. If each CPU supports a maximum of three ports, a fully interconnected topology can be directly achieved, as shown in the following example. Figure 1 As shown, it shows a schematic diagram of intra-group connection in the prior art where the ID is 2 bits wide and the CPU supports a maximum of three ports; if each CPU can only support a maximum of two ports, the connection diagram is as follows Figure 2 As shown, it shows a schematic diagram of a connection within a group in which the ID in the prior art is 2 bits wide and the CPU supports a maximum of two ports. However, in actual applications, for the sake of hardware symmetry (which can reduce the complexity of hardware design), it is generally preferred to put two CPUs in each group. For details, please refer to Figure 3 , which shows another intra-group connection schematic diagram in the prior art where the ID is 2 bits wide and the CPU supports a maximum of two ports.

[0037] From the above process, we can see that because a fixed ID is assigned to the protocol proxy chip, there will be only 2 n -1 CPU (n is the bit width of the identification ID), that is, 3, 7, 15..., which will reduce the number of CPUs in the same group, that is, the utilization rate of the identification ID cannot be maximized. At the same time, in order to design the circuit around the CPU symmetrically, it will tend to set 2, 4, 8 CPUs in each group, which will further reduce the number of CPUs in the same CPU group.

[0038] To this end, the present application provides a multi-CPU system and a communication method thereof, which is used to increase the number of CPUs in a group so that the system can include more CPUs.

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] See also Figure 4 and Figure 5 ,in, Figure 4 A schematic diagram of the structure of a multi-CPU system provided in an embodiment of the present application is shown. Figure 5 A schematic diagram of the structure of another multi-CPU system provided by an embodiment of the present application is shown. A multi-CPU system provided by an embodiment of the present application may include at least one group of CPU groups, wherein the CPU group may include a protocol proxy chip and 2 N Each CPU in a CPU group is directly connected to a protocol proxy chip and some CPUs in the same CPU group according to the number of its ports; N is the number of bits of the CPU identification ID;

[0041] The mapping configuration information of each CPU in the same CPU group may include the identification ID of the directly connected CPU and the identification ID of the protocol proxy chip, so as to send a data packet to the corresponding directly connected CPU or protocol proxy chip according to the identification ID;

[0042] The mapping configuration information of the protocol proxy chip may include the identification ID of each CPU in the same CPU group. The protocol proxy chip is used to send the data packet to the target CPU when it receives a data packet sent by the CPU in the same CPU group and determines that the data packet is sent to the target CPU in the same CPU group based on the data packet and the identification ID of each CPU.

[0043] In a multi-CPU system, there may be at least one group of CPU groups, each of which contains 2 N(N is the number of bits of the bit width of the CPU identification ID) CPUs and protocol proxy chips, and in each CPU group, the CPUs in the same CPU group are directly connected (i.e., directly connected) to the protocol proxy chips and some CPUs in the same CPU group according to the number of ports it contains. When the CPU is directly connected to the protocol proxy chips and some CPUs in the same CPU group, it is preferred to be directly connected to at least one protocol proxy chip in the same CPU group according to demand (as for how many protocol proxy chips the CPU is directly connected to in the same CPU group, it can depend on the connection requirements. Generally, the CPU also has ports reserved for direct connection with other CPUs in the same CPU group to ensure data transmission efficiency). After being directly connected to the protocol proxy chip in the same CPU group, the remaining ports are directly connected to the CPUs in the same CPU group. It should be noted that, in theory, there are two extreme cases: one is that the CPU has only one port, then this port is only directly connected to one protocol proxy chip in the same CPU group; the other is that after the CPU is connected to the protocol proxy chip, it can also be directly connected to each CPU in the group, that is, the number of ports of the CPU is greater than or equal to 2. N -1+M (where M is the number of protocol proxy chips in the same CPU group), where the first case can also be implemented using the technical solution of the present application, except that at this time, it can be considered that the part of the CPUs directly connected to some CPUs mentioned above is 0, and the second case generally does not occur in practice, because the actual CPU products generally do not design ports that are not used in most scenarios. Even if this situation occurs later, using one or more ports as redundant backups instead of direct connection to the CPU will not affect the implementation of the technical solution of the present application. In addition, different CPU groups are connected through protocol proxy chips between CPU groups.

[0044] It should be noted that Figure 4 and Figure 5 The CPU ID bit width is 2 as an example. Figure 4 Take the CPU with three ports as an example. Figure 5 Take the CPU with two ports as an example. From the above process, we can see that the number of nodes (including CPU and protocol proxy chip) directly connected to the CPU in the CPU group depends only on its port number. Figure 4 For example, that is, a 2-bit wide identification ID and three ports for each CPU. Although there are 4 CPUs and one protocol agent chip in the CPU group, each CPU is only connected to 3 nodes, and only 4 identification IDs are needed to distinguish the use of each port.

[0045] In the present application, the internal mapping of each CPU is independently configured (specifically, this can be accomplished by modifying registers in the firmware), and the identification ID of the CPU directly connected to the CPU itself is configured to the corresponding CPU respectively, so that when the CPU needs to communicate with the directly connected CPU, it can send data packets to the directly connected CPU according to the identification ID of the directly connected CPU to communicate with it, and when performing independent configuration, the identification ID of the CPU that was not directly connected to the CPU itself is configured to the protocol proxy chip (that is, the protocol proxy chip and the non-directly connected CPU share a CPU identification ID, and the CPU can only identify the protocol proxy chip when identifying according to the mapping configuration information, and cannot identify the non-directly connected CPU), that is, all data packets sent to the CPU that is not directly connected to itself are forwarded through the protocol proxy chip. Through the above configuration, the mapping configuration information of each CPU in the same CPU group includes the identification ID of the directly connected CPU and the identification ID of the protocol proxy chip, so that when the CPU needs to communicate with the directly connected CPU, it can send a data packet to the corresponding directly connected CPU according to the identification ID of the directly connected CPU; when it needs to communicate with a non-directly connected CPU in the same CPU group or a CPU outside the group, it can send a data packet to the protocol proxy chip according to the identification ID of the protocol proxy chip.

[0046] For the protocol proxy chip in the CPU group, compared with the existing protocol proxy chip, the protocol proxy chip provided by the present application, in addition to the original proxy function of the CPU outside the group, also assumes the proxy for the CPU in the CPU group, and for different CPUs, the protocol proxy chip proxy is the CPU that is not directly connected to the CPU. The mapping configuration information of the protocol proxy chip in the CPU group includes the identification ID of each CPU in the same CPU group, that is, the protocol proxy chip can identify each CPU in the same CPU group. In addition, the mapping configuration information of the protocol proxy chip also includes the identification ID of the protocol proxy chip contained in other CPU groups.

[0047] When the protocol proxy chip receives a data packet sent by a CPU in the same CPU group, it can parse the data packet and identify the data packet using the identification ID of each CPU in the same CPU group contained in its own mapping configuration information. If the identification ID corresponding to the data packet is the same as the identification ID of a CPU in the same CPU group (the CPU is determined as the target CPU in the same CPU group), the protocol proxy chip determines that the data packet is sent to the same CPU group. Then, the protocol proxy chip can send the data packet to the target CPU in the same CPU group. Specifically, the protocol proxy chip can send the data packet to the port corresponding to the target CPU in the same CPU group according to the mapping configuration information, and thus send it to the target CPU in the same CPU group, so as to use the protocol proxy chip to implement the forwarding of the data packet sent by the CPU to the non-directly connected CPU in the same CPU group, that is, to use the protocol proxy chip to implement the proxy for the CPUs in the group, so as to ensure that the two CPUs in the same CPU group N Through the above, the same CPU group can contain the maximum number of CPUs, and these CPUs can communicate normally, so that a multi-CPU system can have more CPUs, thereby meeting system requirements.

[0048] For details, please refer to Figure 6 , which shows a schematic diagram of the interconnection structure within a CPU group with a 2-bit wide identification ID provided by an embodiment of the present application, and each CPU has three ports, and Table 1 is a mapping configuration relationship table of data communication targets and ports corresponding to each CPU:

[0049]

[0050] 2'b00 indicates that the port is connected to CPU0, 2'b01 indicates that the port is connected to CPU1, 2'b10 indicates that the port is connected to CPU2, and 2'b11 indicates that the port is connected to CPU3. In Table 1, the second row and the fifth column represent that in the mapping configuration information of CPU0, the data actually to be sent to CPU3 will be sent to the node with the ID 2'b11, that is, the protocol proxy chip, and so on. The rest will not be repeated.

[0051] In addition, the existing multi-CPU system design implies the premise that each CPU is equal, including the equal status of each CPU in the same group, and the equality between each group. But in fact, the whole system must have a main CPU, and each group will also have a main CPU for system configuration, task allocation, etc. Secondly, the IO devices and corresponding task loads on each CPU will also be different. With the rise of heterogeneous computing, there will be a need to integrate different CPUs in the same system. The above concentration will cause different CPUs to have different requirements for connecting to other CPUs, but the existing design is difficult to meet the needs of CPUs connecting to different CPUs. In this application, since there are direct and indirect connections between CPUs in the CPU group, the status of each CPU is not equal, and this can provide a basis for CPUs in the same CPU group to connect to CPUs with different requirements and for CPUs with different requirements in a multi-CPU system, thereby facilitating the integration of different CPUs.

[0052] The above technical solution disclosed in this application, each CPU group in the multi-CPU system includes a protocol proxy chip and 2 N A CPU is provided, and each CPU is directly connected to a protocol proxy chip and some CPUs according to the number of its ports. The mapping configuration information of each CPU in the same CPU group includes the identification ID of the CPU directly connected thereto and the identification ID of the protocol proxy chip, that is, the identification ID of the CPU that is not directly connected to the CPU in the same CPU group is configured to the protocol proxy chip, so that the CPU sends all data packets sent to the non-directly connected CPU to the protocol proxy chip for forwarding by the protocol proxy chip. The protocol proxy chip also includes the identification ID of each CPU in the same CPU group, so that the protocol proxy chip can identify each CPU in the same CPU group. When the protocol proxy chip receives a data packet sent by a CPU in the same group, it can identify the destination of the data packet according to the identification ID of each CPU contained in the data packet and the mapping configuration information, and when it is identified that the data packet is sent to a target CPU in the same CPU group, the data packet is sent to the target CPU in the same CPU group, thereby realizing the proxy of the CPU in the group. It can be seen that the present application configures the identification ID of the CPU that is not directly interconnected with the CPU in the same CPU group to the protocol proxy chip, and the protocol proxy chip can identify each CPU in the same CPU group and can proxy the CPU in the group so that the same CPU group can contain the maximum number of CPUs (i.e., 2 N)CPU, thereby increasing the number of CPUs in the group and the utilization rate of the identification ID, so that the system can include more CPUs to meet the performance requirements of the system. In addition, since the CPUs in this application are divided into direct connection and indirect connection, it can provide a basis for the integration of CPUs with different requirements on the system and for heterogeneous computing.

[0053] In a multi-CPU system provided by an embodiment of the present application, a protocol proxy chip is used to send the data packet to the protocol proxy chip in the other CPU group when it is determined that the data packet is sent to other CPU groups, so that the protocol proxy chip in the other CPU group sends it to the corresponding CPU.

[0054] In the present application, when the protocol proxy chip parses the received data packet and determines that the identification ID corresponding to the data packet is not the identification ID of the CPU in the same CPU group as the protocol proxy chip based on the identification ID corresponding to the parsed data packet and the mapping configuration information of the protocol proxy chip itself, it is determined that the data packet is sent to other CPU groups, and the protocol proxy chip can determine which CPU group in the other CPU groups the data packet is specifically sent to based on the identification ID corresponding to the data packet. Then, the protocol proxy chip can send the data packet to the protocol proxy chip in the other CPU group corresponding to the data packet, so that the protocol proxy chip in the other CPU group corresponding to the data packet can parse and identify the data packet to determine the CPU corresponding to the data packet and send the data packet to the corresponding CPU.

[0055] Through the above process, it can be known that the protocol proxy chip can realize the proxy for CPUs outside the group, so that the CPUs in the CPU group can communicate with the CPUs in other CPU groups in the multi-CPU system, thereby ensuring that all CPUs in the multi-CPU system can communicate with each other.

[0056] A multi-CPU system provided by an embodiment of the present application, when a protocol proxy chip receives multiple data packets, the protocol proxy chip is also used to send each data packet in a descending order of priority according to the priority of the data path corresponding to each data packet.

[0057] In the present application, when the protocol proxy chip within the CPU group receives multiple data packets at the same time, it can obtain the priority of the data path corresponding to each data packet (specifically, the data packet from the sending end to the final receiving end can be considered as the data path corresponding to the data packet). Then, each data packet can be sent in order from high to low priority, thereby giving priority to the sending of data packets corresponding to data paths with high priorities, so as to improve the rationality and reliability of data packet sending.

[0058] It should be noted that the priority of the data path corresponding to each data packet can be pre-set by the relevant user, etc., and of course, it can also be automatically set according to the urgency of sending the data packet and / or the sending target, and this application does not impose any limitation on this.

[0059] An embodiment of the present application provides a multi-CPU system, in which a CPU group may include multiple connected protocol proxy chips, and each CPU in the same CPU group is directly connected to at least one protocol proxy chip in the same CPU group.

[0060] In the present application, each CPU group may include multiple protocol proxy chips, wherein multiple protocol proxy chips in the same CPU group may be interconnected in pairs so as to forward data packets to each other. Moreover, each CPU in the same CPU group may be directly connected to at least one protocol proxy chip in the same CPU group, so that the CPU may communicate with a non-directly connected CPU in the same CPU group or a CPU in another CPU group through the directly connected protocol proxy chip.

[0061] It should be noted that the bit width of the identification ID of the protocol proxy chip itself is not the same as the bit width of the identification ID of the CPU (i.e., N), and the identification ID of the protocol proxy chip itself can be set and adjusted in advance according to needs (when setting and adjusting, it is necessary to ensure that both the connected protocol proxy chip and CPU can be identified), so that the protocol proxy chip can identify the connected protocol proxy chip and CPU.

[0062] The embodiment of the present application provides a multi-CPU system, the number of ports on the protocol proxy chip is greater than 2 N +M, where M is the number of protocol proxy chips in the same CPU group.

[0063] In this application, in order to ensure that the protocol proxy chip can have enough ports to connect with the CPU, protocol proxy chip and protocol proxy chips of other CPU groups in the same group, the number of ports of the protocol proxy chip can be greater than 2. N +M, where M is the number of protocol proxy chips in the same CPU group.

[0064] In a multi-CPU system provided by an embodiment of the present application, a protocol proxy chip is specifically used to determine an identification ID corresponding to a data packet based on an access address in the data packet, a mapping relationship between the access address and the identification ID in mapping configuration information of the protocol proxy chip, and determine whether the data packet is sent to a target CPU in the same CPU group based on the identification ID.

[0065] In the present application, if the protocol proxy chip determines based on analysis that the data packet contains an access address, the protocol proxy chip can specifically determine the identification ID corresponding to the data packet based on the access address contained in the data packet and the mapping relationship between the access address and the identification ID contained in the mapping configuration information of the protocol proxy chip itself, and determine whether the data packet is sent to the target CPU in the same CPU group based on the identification ID corresponding to the data packet. This method of identification and judgment based on the access address is relatively accurate.

[0066] In a multi-CPU system provided by an embodiment of the present application, a protocol proxy chip is specifically used to identify an identification ID according to a command type in a data packet, and to determine whether the data packet is sent to a target CPU in the same CPU group according to the identification ID.

[0067] In the present application, if the protocol agent chip determines that the data packet contains a command type based on the analysis, it can identify the identification ID based on the command type contained in the data packet, and then determine whether the data packet is sent to the target CPU in the same CPU group based on the identified identification ID to ensure that the data packet can be normally identified.

[0068] It should be noted that if the protocol proxy chip determines that the data packet contains both the access address and the command type through parsing the data packet, it can determine the data packet sending object by any of the above two methods, or use one method to determine the data packet sending object and use another method to perform the corresponding verification of the data packet sending. If the two methods are consistent, the verification passes, and then the data packet is sent. If the two methods are not consistent, an error can be reported to the CPU that sends the data packet so that it can resend the data packet.

[0069] The present application also provides a communication method for a multi-CPU system, which is applicable to any of the above multi-CPU systems. Figure 7 , which shows a flow chart of a communication method for a multi-CPU system provided by an embodiment of the present application, which may include:

[0070] S71: When the CPUs in the same CPU group communicate with the directly connected CPU, a data packet is sent to the directly connected CPU according to the mapping configuration information in the CPU;

[0071] S72: When the CPUs in the same CPU group communicate with the non-directly connected CPUs, a data packet is sent to the protocol proxy chip in the same CPU group;

[0072] S73: The protocol proxy chip determines whether the data packet is sent to the target CPU in the same CPU group according to the identification IDs of each CPU in the same CPU group contained in the data packet and its own mapping configuration information. If so, the protocol proxy chip sends the data packet to the target CPU.

[0073] A communication method for a multi-CPU system provided in an embodiment of the present application may further include, when the protocol proxy chip determines that the data packet is sent to other CPU groups:

[0074] The protocol proxy chip sends the data packet to the protocol proxy chips in other CPU groups, so that the protocol proxy chips in other CPU groups send the data packet to the corresponding CPU.

[0075] A communication method for a multi-CPU system provided in an embodiment of the present application may further include, when a protocol proxy chip receives multiple data packets:

[0076] The protocol proxy chip sends each data packet in descending order of priority according to the priority of the data path corresponding to each data packet.

[0077] The description of the relevant parts of the communication method of a multi-CPU system provided in the present application can be found in the detailed description of the corresponding parts of a multi-CPU system provided in an embodiment of the present application, and will not be repeated here.

[0078] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment that includes a series of elements are inherent to the elements. In the absence of more restrictions, the elements limited by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or equipment that includes the elements. In addition, the above-mentioned technical solution provided in the embodiment of the present application is consistent with the corresponding technical solution in the prior art in principle, and the part is not described in detail, so as not to repeat too much.

[0079] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-CPU system, characterized in that: At least one CPU group is included, wherein the CPU group includes a protocol proxy chip and 2 N CPUs, each of the CPUs in the CPU group is directly connected to the protocol proxy chip and some CPUs in the same CPU group according to the number of its ports; N is the number of bits of the bit width of the identification ID of the CPU; The mapping configuration information of each of the CPUs in the same CPU group includes the identification ID of the directly connected CPU and the identification ID of the protocol proxy chip, so as to send a data packet to the corresponding directly connected CPU or protocol proxy chip according to the identification ID; The mapping configuration information of the protocol proxy chip includes the identification ID of each CPU in the same CPU group. The protocol proxy chip is used to send the data packet to the target CPU when it receives a data packet sent by a CPU in the same CPU group and determines that the data packet is sent to the target CPU in the same CPU group based on the data packet and the identification ID of each CPU.

2. The multi-CPU system according to claim 1, characterized in that: The protocol proxy chip is used to send the data packet to the protocol proxy chip in the other CPU group when it is determined that the data packet is sent to other CPU groups, so that the protocol proxy chip in the other CPU group sends the data packet to the corresponding CPU.

3. The multi-CPU system according to claim 1, characterized in that: When the protocol proxy chip receives multiple data packets, the protocol proxy chip is further configured to send each data packet in a descending order of priority according to the priority of the data path corresponding to each data packet.

4. The multi-CPU system according to claim 1, characterized in that: The CPU group includes a plurality of connected protocol agent chips, and each of the CPUs in the same CPU group is directly connected to at least one of the protocol agent chips in the same CPU group.

5. The multi-CPU system according to claim 4, characterized in that: The number of ports on the protocol proxy chip is greater than 2 N +M, where M is the number of protocol proxy chips in the same CPU group.

6. The multi-CPU system according to claim 1, characterized in that: The protocol proxy chip is specifically used to determine the identification ID corresponding to the data packet based on the access address in the data packet, the mapping relationship between the access address and the identification ID in the mapping configuration information of the protocol proxy chip, and determine whether the data packet is sent to the target CPU in the same CPU group based on the identification ID.

7. The multi-CPU system according to claim 1, characterized in that: The protocol proxy chip is specifically used to identify an identification ID according to a command type in the data packet, and determine whether the data packet is sent to a target CPU in the same CPU group according to the identification ID.

8. A communication method for a multi-CPU system, characterized in that: Applicable to a multi-CPU system as claimed in any one of claims 1 to 7, comprising: When a CPU in the same CPU group communicates with a directly connected CPU, a data packet is sent to the directly connected CPU according to the mapping configuration information in the CPU; When a CPU in the same CPU group communicates with a non-directly connected CPU, a data packet is sent to the protocol proxy chip in the same CPU group; The protocol proxy chip determines whether the data packet is sent to a target CPU in the same CPU group according to the identification IDs of the CPUs in the same CPU group contained in the data packet and its own mapping configuration information, and if so, sends the data packet to the target CPU.

9. The communication method of a multi-CPU system according to claim 8, characterized in that: When the protocol proxy chip determines that the data packet is sent to other CPU groups, it also includes: The protocol proxy chip sends the data packet to the protocol proxy chips in other CPU groups, so that the protocol proxy chips in other CPU groups send the data packet to the corresponding CPU.

10. The communication method of a multi-CPU system according to claim 8, characterized in that: When the protocol proxy chip receives multiple data packets, it also includes: The protocol proxy chip sends each data packet in descending order of priority according to the priority of the data path corresponding to each data packet.

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