A design method of a row decoding circuit and a related device

Abstract

The application discloses a design method of a row decoding circuit and a related device, relates to the technical field of integrated circuits, and can improve the problem that existing customized decoding circuits cannot be reused. The design method of the row decoding circuit comprises the following steps: in a circuit layout design environment, according to decoding capacity, a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module are called respectively; a first output end of a binary decoder in the first decoder structure package is electrically connected with a first splicing connection line of the splicing module, and a second input end of a logic gate level connection device in the second decoder structure package is electrically connected with a second splicing connection line of the splicing module; and the first splicing connection line and the second splicing connection line are electrically connected through punching.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a design method of a row decoding circuit and related equipment. BACKGROUND

[0002] Memory is an important part of large-scale integrated circuits, which can improve the efficiency of the system, reduce power consumption and reduce packaging costs. In the design phase, the required memory can be generated according to the generator of the Memory Compiler. The area, power consumption and speed of the generated memory are very important to the user. To realize the generation of a memory compiler with small area, low power consumption and high speed, the layout generation method of the SRAM (Static Random Access Memory) global decoding circuit is crucial. The SRAM structure mainly includes decoding circuit and storage array, etc. On the whole SRAM chip, the storage array occupies the most area, followed by the decoding circuit. The decoding circuit is an important structure for selecting a specific row and column storage unit.

[0003] However, the existing decoding circuit adopts a customized development method, and the decoding circuit layout cannot be reused, which is not suitable for implementing the Memory Compiler. SUMMARY

[0004] The embodiment of the present application provides a design method of a row decoding circuit and related equipment, which can improve the problem that the existing decoding circuit cannot be reused by customized development.

[0005] In a first aspect, the embodiment of the present application provides a design method of a row decoding circuit, comprising:

[0006] In the circuit layout design environment, according to the decoding capacity, a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module are called respectively, wherein the first decoder structure package includes circuit structures of a plurality of binary decoders, the second decoder structure package includes circuit structures of a plurality of logic gate level connection devices, and the splicing module includes a splicing connection line.

[0007] The first output end of the binary decoder in the called first decoder structure package is electrically connected with the first splicing connection line of the splicing module, and the second input end of the logic gate level connection device in the called second decoder structure package is electrically connected with the second splicing connection line of the splicing module.

[0008] The first splicing connection line and the second splicing connection line are electrically connected by punching.

[0009] In some embodiments, the logic gate cascade device comprises at least three second-level inputs, each of which is used to connect a corresponding first-level output of a different binary decoder, and the first splicing connection line and the second splicing connection line are electrically connected by punching, comprising:

[0010] The first splicing connection line and the second splicing connection line are electrically connected by punching, so that at least any two first-level outputs are connected to the same logic gate cascade device.

[0011] In some embodiments, the first-level row decoding module comprises a low bit decoder, a middle bit decoder, and a high bit decoder, the logic gate cascade device comprises three second-level inputs, and the three second-level inputs are respectively connected to any corresponding first-level output of the low bit decoder, the middle bit decoder, and the high bit decoder.

[0012] In some embodiments, two adjacent logic gate cascade devices form a decoder unit, and each decoder unit comprises a first unit input, a second unit input, a third unit input, and a fourth unit input.

[0013] The first splicing connection line and the second splicing connection line are electrically connected by punching, comprising:

[0014] The first splicing connection line and the second splicing connection line are electrically connected by punching, so that the first unit input is electrically connected to any corresponding first-level output of the low bit decoder, the second unit input is electrically connected to any corresponding first-level output of the middle bit decoder, the third unit input is electrically connected to any corresponding first-level output of the high bit decoder, the fourth unit input is electrically connected to any corresponding first-level output of the low bit decoder, and the fourth unit input and the first unit input are electrically connected to different first-level outputs.

[0015] In some embodiments, in the circuit layout design environment, according to the decoding capacity, a first-level decoder structure package required by a first-level row decoding module, a second-level decoder structure package required by a second-level row decoding module, and a splicing module are respectively called, comprising:

[0016] In the circuit layout design environment, when the decoding capacity is 32, a 3-to-8 decoder and a 2-to-4 decoder are respectively called, a first-level decoder structure package corresponding to the 3-to-8 decoder and the 2-to-4 decoder, a second-level decoder structure package corresponding to 32 logic gate cascade devices, and a splicing module corresponding to the number of lines.

[0017] In some embodiments, in the circuit layout design environment, according to the decoding capacity, the first-level decoder structure package required by the first-level row decoding module, the second-level decoder structure package required by the second-level row decoding module and the splicing module are respectively called, including:

[0018] In the circuit layout design environment, in the case that the decoding capacity is between 33 and 64, the first-level decoder structure package corresponding to two 3-to-8 decoders, the second-level decoder structure package corresponding to the same number of logic gate cascaded devices as the decoding capacity and the splicing module corresponding to the number of lines are respectively called; or,

[0019] In the circuit layout design environment, in the case that the decoding capacity is between 65 and 128, the first-level decoder structure package corresponding to two 3-to-8 decoders and one 1-to-2 decoder, the second-level decoder structure package corresponding to the same number of logic gate cascaded devices as the decoding capacity and the splicing module corresponding to the number of lines are respectively called; or,

[0020] In the circuit layout design environment, in the case that the decoding capacity is between 129 and 256, the first-level decoder structure package corresponding to two 3-to-8 decoders and one 2-to-4 decoder, the second-level decoder structure package corresponding to the same number of logic gate cascaded devices as the decoding capacity and the splicing module corresponding to the number of lines are respectively called; or,

[0021] In the circuit layout design environment, in the case that the decoding capacity is between 257 and 512, the first-level decoder structure package corresponding to three 3-to-8 decoders, the second-level decoder structure package corresponding to the same number of logic gate cascaded devices as the decoding capacity and the splicing module corresponding to the number of lines are respectively called.

[0022] In a second aspect of the embodiments of the application, a generating device of a decoding circuit is provided, including:

[0023] The calling module is configured to, in the circuit layout design environment, according to the decoding capacity, call the first-level decoder structure package required by the first-level row decoding module, the second-level decoder structure package required by the second-level row decoding module and the splicing module, wherein the first-level decoder structure package includes circuit structures of a plurality of binary decoders, the second-level decoder structure package includes circuit structures of a plurality of logic gate cascaded devices, and the splicing module includes a splicing connection line.

[0024] a connection module, configured to electrically connect a primary output end of the binary decoder in the called primary decoder structure package with a first splicing connection line of the splicing module, and electrically connect a secondary input end of the logic gate level interconnection device in the called secondary decoder structure package with a second splicing connection line of the splicing module;

[0025] a punching module, configured to electrically connect the first splicing connection line with the second splicing connection line through punching.

[0026] In a third aspect, an electronic device is provided, comprising:

[0027] a memory, in which a computer program is stored;

[0028] a processor, configured to implement the design method of the row decoding circuit according to the first aspect when the computer program is executed.

[0029] In a fourth aspect, a computer readable storage medium is provided, in which a computer program is stored, and the computer program is configured to implement the design method of the row decoding circuit according to the first aspect when executed by a processor.

[0030] In a fifth aspect, a row decoding circuit is provided, which is generated by the design method of the decoding circuit according to the first aspect, and the row decoding circuit comprises:

[0031] a primary row decoding module, comprising at least one binary decoder;

[0032] a secondary row decoding module, comprising at least one logic gate level interconnection device, and a primary output end of the binary decoder is electrically connected with a secondary input end of the logic gate level interconnection device.

[0033] The design method of the row decoding circuit and the related device provided by the embodiment of the application are customized and developed, and are not suitable for reuse, so that the row decoding circuit cannot be used in the Memory Compiler. In the circuit layout design environment, according to the decoding capacity, a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module are called respectively. The first output end of the binary decoder in the called first decoder structure package is electrically connected with the first splicing connection line of the splicing module, and the second input end of the logic gate cascade device in the called second decoder structure package is electrically connected with the second splicing connection line of the splicing module. The first splicing connection line and the second splicing connection line are electrically connected by punching. After the number and the corresponding type of the binary decoders required by the first row decoding module and the number of the logic gate cascade devices required by the second row decoding module are determined, the corresponding number and type of the decoder structure packages can be directly called, so that the generation efficiency of the decoding circuit can be improved. Different row decoding circuits with different decoding capacities can be generated according to the demand of the target storage capacity, so that the expansion of the row decoding circuit of the corresponding memory can be adapted. The position of the punching can be determined according to the connection mode of the first output end and the second input end, so that the splicing module can be applied to various changed connection schemes, and the splicing module can be called as a template and applied to generate row decoding circuits with different circuit structures. The automatic generation of the row decoding circuit can be realized, and the row decoding circuit can be automatically obtained by inputting the decoding capacity, so that the design technology of the decoding circuit is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A schematic flowchart of a design method of a row decoding circuit provided by the embodiment of the application is provided.

[0035] Figure 2 A schematic structural block diagram of a row decoding circuit provided by the embodiment of the application is provided.

[0036] Figure 3 A schematic structural block diagram of a logic gate cascade device provided by the embodiment of the application is provided.

[0037] Figure 4 A schematic structural block diagram of a decoder unit provided by the embodiment of the application is provided.

[0038] Figure 5 A splicing schematic diagram of a row decoding circuit provided by the embodiment of the application is provided.

[0039] Figure 6 A schematic structural block diagram of a design device of a row decoding circuit provided by the embodiment of the application is provided.

[0040] Figure 7A schematic structural block diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 1.

[0041] Figure 8 A schematic structural block diagram of a computer readable storage medium provided by an embodiment of the present application is shown in FIG. 2.

[0042] Figure 9 A schematic structural block diagram of a memory circuit provided by an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0043] In order to better understand the technical solutions provided by the embodiments of the present application, the technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0044] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The terms "two or more" and "two or more than two" include both two and more than two entities.

[0045] Memory is an important part of large-scale integrated circuits, which can improve the efficiency of the system, reduce power consumption and reduce packaging costs. In the design phase, the required memory can be generated according to the generator of the Memory Compiler. The area, power consumption and speed of the generated memory are very important to the user. To realize the generation of a memory compiler with small area, low power consumption and high speed, the layout generation method of SRAM global decoding is crucial. The SRAM structure mainly includes decoding circuit and storage array, etc. On the whole SRAM chip, the storage array occupies the most area, followed by the decoding circuit. The decoding circuit is an important structure for selecting a specific row and column storage unit. However, the existing decoding circuit adopts a customized development method, and the circuit structure cannot be reused, which is not suitable for Memory Compiler.

[0046] Therefore, the embodiment of the present application provides a design method of a row decoding circuit and related equipment, which can solve the problem that the existing decoding circuit module cannot be reused.

[0047] In a first aspect, the embodiment of the present application provides a design method of a row decoding circuit, Figure 1 The embodiment of the present application provides a design method of a row decoding circuit. As shown in the schematic flow chart of the design method of the row decoding circuit, Figure 1 The design method of the row decoding circuit provided by the embodiment of the present application comprises the following steps.

[0048] S100: In a circuit layout design environment, according to decoding capacity, a first-level decoder structure package required by a first-level row decoding module, a second-level decoder structure package required by a second-level row decoding module and a splicing module are respectively called, wherein the first-level decoder structure package includes circuit structures of multiple binary decoders, the second-level decoder structure package includes circuit structures of multiple logic gate cascade devices, and the splicing module includes splicing connection lines. In the circuit layout design environment, according to target storage capacity of a target memory, the number and corresponding types of binary decoders required by the first-level row decoding module can be determined, and the number of logic gate cascade devices required by the second-level row decoding module can be determined. Since the decoding circuit of direct decoding causes problems of large layout area requirement of the decoding circuit and slow decoding rate, it is difficult to meet the SRAM with large storage capacity. The decoding circuit designed in the design method of the row decoding circuit provided in the embodiments of the present application sets the first-level row decoding module and the second-level row decoding module, two-level decoding can be realized, the cascade of the first-level row decoding module and the second-level row decoding module can increase the number of decoding bits, increase the decoding capacity, improve the decoding rate, reduce the delay and power consumption, and in the case of the same decoding capacity, the row decoding circuit occupies smaller area. In the design stage of the row decoding circuit or in the design stage of the memory, the row decoding circuit can be designed in the circuit layout design environment, then the number of binary decoders required by the first-level row decoding module in the row decoding circuit can be determined according to the target storage capacity of the target memory, and the corresponding types of binary decoders required by the first-level row decoding module are determined. Usually, the types of binary decoders required by the first-level row decoding include 1-line-2-line decoder, 2-line-4-line decoder and 3-line-8-line decoder, the 1-line-2-line decoder represents a binary decoder with 1 input line and 2 output lines, the 2-line-4-line decoder represents a binary decoder with 2 input lines and 4 output lines, and the 3-line-8-line decoder represents a binary decoder with 3 input lines and 8 output lines, and the corresponding binary decoders can be 1-line-2-line decoder, 2-line-4-line decoder and 3-line-8-line decoder. The output lines of the binary decoders in the first-level row decoding module are connected to the input lines of the logic gate cascade devices in the second-level row decoding module. After the number and types are determined, the decoder structure package needs to be called further according to the number of binary decoders required by the first-level row decoding module and the corresponding types of binary decoders, and the number of logic decoders required by the second-level row decoding module. The first-level decoder structure package is called for the first-level row decoding module, the second-level decoder structure package is called for the second-level row decoding module, the first-level decoder structure package includes circuit structures of multiple binary decoders, the second-level decoder structure package includes circuit structures of multiple logic gate cascade devices, and the splicing module includes splicing connection lines.The decoder structure package can be a circuit structure of a ready decoder in a circuit layout design environment. After the number and type of binary decoders required by the first-level row decoding module and the number of logic decoders required by the second-level row decoding module are determined, the decoder structure package of the corresponding number and type can be directly called to improve the generation efficiency of the decoding circuit. Different capacity row decoding circuits can also be generated according to the demand of the target storage capacity, which can adapt to the expansion of the corresponding memory row decoding circuit. For example, each decoder structure package includes a circuit structure of a binary decoder or a circuit structure of a logic gate-level device, and the embodiments of the present application are not limited specifically. The number of splicing connection lines in the called splicing module corresponds to the output and input of the first-level decoder structure package and the second-level decoder structure package.

[0049] S200: The first-level output end of the binary decoder in the called first-level decoder structure package is electrically connected with the first splicing connection line of the splicing module, and the second-level input end of the logic gate-level device in the called second-level decoder structure package is electrically connected with the second splicing connection line of the splicing module. The splicing module includes the first splicing connection line and the second splicing connection line, the output end of the binary decoder is the first-level output end, the input end of the logic gate-level device is the second-level input end, the first-level output end is electrically connected with the first splicing connection line, and the second-level input end is electrically connected with the second splicing connection line. For example, if the first splicing connection line and the second splicing connection line in the splicing module are designed as the same connection line, the connection mode of the splicing module splicing the first-level decoder structure package and the second-level decoder structure package is fixed.

[0050] S300: The first splicing connection line and the second splicing connection line are electrically connected by punching. The first splicing connection line and the second splicing connection line in the splicing module are electrically connected by punching, so that the first-level output end in the first-level decoder structure package and the second-level input end in the second-level decoder structure package can be electrically connected. The first splicing connection line and the second splicing connection line are electrically connected by punching. The position of the punching can be determined according to the connection mode of the first-level output end and the second-level input end, so that the splicing module can be applied to various changed connection schemes. The splicing module can be called as a template and applied to generate row decoding circuits of different circuit structures.

[0051] The design method of the row decoding circuit provided by the embodiment of the present application is customized and developed for the existing decoding circuit, which is not suitable for reuse, so that it cannot be used in the Memory Compiler. By calling a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module according to the decoding capacity in the circuit layout design environment, the first output end of the binary decoder in the called first decoder structure package is electrically connected with the first splicing connection line of the splicing module, and the second input end of the logic gate cascade device in the called second decoder structure package is electrically connected with the second splicing connection line of the splicing module. The first splicing connection line and the second splicing connection line are electrically connected by punching. After the number and the corresponding type of the binary decoders required by the first row decoding module and the number of the logic gate cascade devices required by the second row decoding module are determined, the corresponding number and type of the decoder structure package can be directly called, so that the generation efficiency of the decoding circuit can be improved. Different decoding capacities of the row decoding circuit can be generated according to the demand of the target storage capacity, so that the expansion of the row decoding circuit of the corresponding memory can be adapted. The position of the punching can be determined according to the connection mode of the first output end and the second input end, so that the splicing module can be applied to various changed connection schemes, and the splicing module can be called as a template and applied to generate the row decoding circuit of different circuit structures. The automatic generation of the row decoding circuit can be realized, and the row decoding circuit can be automatically obtained by inputting the decoding capacity, so that the design technology of the decoding circuit is simplified.

[0052] In some embodiments, Figure 2 A schematic structural block diagram of a row decoding circuit is provided in the embodiment of the present application. As Figure 2 shown, the row decoder obtained by the design method of the row decoding circuit provided by the embodiment of the present application includes a first row decoding module 100, a second row decoding module 200 and a splicing module 300, and the first row decoding module 100 includes at least one binary decoder. The binary decoder can translate various states of the input binary code into corresponding output types according to the original meaning. Commonly used binary decoders include n-line-2 n line decoders, that is, the input line has n roots and the output line has 2 n roots, and the input and output line specifications are n-line-2 n line. Commonly used binary decoders include 1-line-2-line decoders, 2-line-4-line decoders and 3-line-8-line decoders. The second row decoding module 200 includes at least one logic gate cascade device, and the first output end of the binary decoder is electrically connected with the second input end of the logic gate cascade device. The number of the logic gate cascade device can be determined by the number of the output lines of all binary decoders, or the number of the logic gate cascade device is determined by the storage capacity of the memory accessed by the row decoding circuit, which is not limited in the embodiment of the present application.

[0053] In some embodiments, the row decoding circuit provided by the embodiments of the present application can further comprise other modules 400, which can comprise column decoding modules and / or column gating modules, and the other modules 400 can also be other types of modules, which are not specifically limited by the embodiments of the present application. The data flow of the decoded data can be: the decoded row address data is input into the first-level row decoding module 100, the data decoded by the first-level row decoding module 100 is input into the second-level row decoding module 200, the data processed by the second-level row decoding module 200 is transmitted to the storage unit array, and the row address decoding is completed. The decoded column address data is input into the column decoding module, and the result after column decoding is transmitted to the column gating module. For example, when the number of multiplexers in the memory is equal to 4, the number of multiplexers can represent the number of data multiplexing, and a 1-line-2-line decoder can be used as a high-bit decoder and a 1-line-2-line decoder can be used as a low-bit decoder in the column decoding module; when the number of data multiplexing in the memory is equal to 8, a 2-line-4-line decoder can be used as a high-bit decoder and a 1-line-2-line decoder can be used as a low-bit decoder in the column decoding module; when the number of data multiplexing in the memory is equal to 16, a 3-line-8-line decoder can be used as a high-bit decoder and a 1-line-2-line decoder can be used as a low-bit decoder in the column decoding module.

[0054] In some embodiments, the logic gate cascade device can comprise at least three second-level inputs, each of which is used to connect a first-level output of a different binary decoder, and the step S300 can comprise:

[0055] The first splicing connection line and the second splicing connection line are electrically connected by punching to connect at least any two first-level outputs to the same logic gate cascade device. One logic gate cascade device can operate the pre-decoding results output by two or more different first-level outputs, so that more decoding results can be obtained by the logic gate cascade device of the second-level row decoding module 200, the address decoding can be more detailed, the target address can be found, and the data read / write operation can be performed on the target address (the row where the target storage unit in the memory is located). For example, the first-level row decoding module 100 comprises a 3-line-8-line decoder and a 2-line-4-line decoder, and the logic gate cascade device connects any two different first-level outputs, for example, a logic gate cascade device connects a first-level output of the 3-line-8-line decoder and a first-level output of the 2-line-4-line decoder, operates the decoding results of the two first-level outputs, and obtains a result. The number of logic gate cascade devices can be 8x4, and the second-level row decoding module 200 can output 32 results.

[0056] The design method of the row decoding circuit provided by the embodiment of the application can obtain more decoding results by further operating the output results of the first-level row decoding module 100, thereby increasing the decoding bit number and the decoding capacity.

[0057] In some embodiments, the first-level row decoding module includes a low bit decoder, a middle bit decoder and a high bit decoder, and the logic gate cascade device includes three second-level input terminals, which are connected to any one first-level output terminal of the low bit decoder, the middle bit decoder and the high bit decoder respectively. The logic gate cascade device can operate the data output by the three first-level output terminals, can perform more combination operations, thereby obtaining more results, can obtain more decoding results by using fewer decoders, improves the decoding capacity, and does not increase the circuit area too much.

[0058] In some embodiments, two adjacent logic gate cascade devices are a decoder unit, and each decoder unit includes a first unit input terminal, a second unit input terminal, a third unit input terminal and a fourth unit input terminal.

[0059] The step S300 can include:

[0060] The first splicing connection line and the second splicing connection line are electrically connected by punching, so that the first unit input terminal is electrically connected to any one first-level output terminal of the low bit decoder, the second unit input terminal is electrically connected to any one first-level output terminal of the middle bit decoder, the third unit input terminal is electrically connected to any one first-level output terminal of the high bit decoder, the fourth unit input terminal is electrically connected to any one first-level output terminal of the low bit decoder, and the fourth unit input terminal and the first unit input terminal are electrically connected to different first-level output terminals.

[0061] It is easy to understand that the three second-level input terminals of each logic gate cascade device are connected to one first-level output terminal of the low bit decoder, one first-level output terminal of the middle bit decoder and one first-level output terminal of the high bit decoder respectively, which can meet the decoding capacity corresponding to various storage capacities of the existing memory.

[0062] An exemplary, Figure 3 An exemplary structure block diagram of a logic gate cascade device provided by the embodiment of the application is shown in FIG. 2. As shown in FIG. 2, the logic gate cascade device includes a first-level row decoding module 100, a low bit decoder, a middle bit decoder and a high bit decoder. Figure 3As shown, the logic gate cascade device includes three two-level inputs, which are a low two-level input G0, a middle two-level input G1 and a high two-level input G2. The low two-level input G0 can be connected to any one-level output of the low decoder in the one-level row decoding module 100, the middle two-level input G1 can be connected to any one-level output of the middle decoder in the one-level row decoding module 100, and the high two-level input G2 can be connected to any one-level output of the high decoder in the one-level row decoding module 100.

[0063] Exemplarily, Figure 3 The working principle of the logic gate cascade device shown can be as follows: at least one of the low two-level input G0, the middle two-level input G1 and the high two-level input G2 is a low level (specifically, 0), and the output result of the logic gate cascade device is 0; the pre-decoding results of the one-level row decoding input by the low two-level input G0, the middle two-level input G1 and the high two-level input G2 are all high levels (specifically, 1), and the output result of the logic gate cascade device is input to the corresponding storage array, for selecting the storage unit of the corresponding row to complete the row decoding, and the target data can be read and written in the selected storage unit.

[0064] Exemplarily, Figure 4 A schematic structural block diagram of a decoder unit provided by the embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, Figure 4As shown, two adjacent logic gate cascaded devices 210 can be used as a decoder unit 220, each decoder unit 220 includes a first unit input end, a second unit input end, a third unit input end and a fourth unit input end, the low bit two-level input end G0 of one logic gate cascaded device 210 in each decoder unit 220 is used as the first unit input end G01, the low bit two-level input end G0 of the other logic gate cascaded device 210 is used as the fourth unit input end G02, the middle bit two-level input ends G1 of the two logic gate cascaded devices 210 are connected in common and used as the second unit input end, and the high bit two-level input ends G2 of the two logic gate cascaded devices 210 are connected in common and used as the third unit input end, that is, the middle bit two-level input ends G1 of the two logic gate cascaded devices 210 are connected to the same primary output end, and the high bit two-level input ends G2 of the two logic gate cascaded devices 210 are connected to the same primary output end. The first unit input end G01 is used for connecting any primary output end corresponding to the low bit decoder, the second unit input end is used for connecting any primary output end corresponding to the middle bit decoder, the third unit input end is used for connecting any primary output end corresponding to the high bit decoder, and the fourth unit input end G02 is used for connecting any primary output end corresponding to the low bit decoder. The fourth unit input end and the first unit input end are connected to different primary output ends. Each logic gate cascaded device 210 corresponds to a two-level output end, and each decoder unit includes two two-level output ends, which are a first two-level output end GT1 and a second two-level output end GT2.

[0065] In some embodiments, step S100 can include:

[0066] In the circuit layout design environment, when the value of the decoding capacity is 32, a primary decoder structure package corresponding to a 3-line-8-line decoder and a 2-line-4-line decoder, a two-level decoder structure package corresponding to 32 logic gate cascaded devices, and a splicing module corresponding to the number of lines are called respectively.

[0067] In some embodiments, two primary decoder structure packages corresponding to a row decoding circuit with a decoding capacity of 32, the two primary decoder structure packages correspond to a circuit structure of a 3-line-8-line decoder and a circuit structure of a 2-line-4-line decoder respectively, the number of two-level decoder structure packages is 32, and the circuit structure of the logic gate cascaded device corresponding in the two-level decoder.

[0068] For example, decoding capacity can be understood as the number of decoding outputs, which can be determined based on the number of word lines in the memory. For instance, the ratio of the number of words (storage units) to the number of data multiplexed units can be considered as the number of word lines, in which case the number of word lines is the same as the decoding capacity. That is, WL = W / M, where WL is the number of word lines (also the decoding capacity), W is the number of storage units in the memory, and M is the number of channels in the memory's multiplexer, i.e., the number of data multiplexed units.

[0069] For example, when the decoding capacity is 32, the first-level row decoding module requires two binary decoders, namely a 3-line to 8-line decoder and a 2-line to 4-line decoder. Therefore, the second-level row decoding module requires 32 decoders. Figure 5 This is a schematic diagram of the splicing of a row decoding circuit provided in an embodiment of this application. Figure 5 As shown, the first-level row decoding module can include a low-order decoder and a middle-order decoder. The middle-order decoder can be a 2-to-4 line decoder, and the low-order decoder can be a 3-to-8 line decoder. No high-order decoder is required. The 3-to-8 line decoder, acting as the low-order decoder, has three first-level inputs (IN1) and eight first-level outputs (L1, L2, L3, L4, L5, L6, L7, and L8). The 2-to-4 line decoder, acting as the middle-order decoder, has two second-level outputs (IN2) and four first-level outputs (M1, M2, M3, and M4). There are 4×8 combinations of M1, M2, M3, and M4 with L1, L2, L3, L4, L5, L6, L7, and L8, resulting in 32 possible combinations. The second-level row decoding module can be configured with 32 cascaded logic gates, i.e., 16 decoder units. The first unit input G01 and the fourth unit input G02 of each decoder unit are connected to any two of L1, L2, L3, L4, L5, L6, L7, and L8, respectively. The middle second-level input G1 is connected to any one of M1, M2, M3, and M4. By punching holes in pairs between the first splicing connection line 310 and the second splicing connection line 320 within the splicing module 300... Figure 5The punch connection position shown is indicated by a black dot, to realize the connection of the first-level output end of the first-level row decoding module and the second-level input end of the second-level row decoding module. Since the row decoding circuit with a decoding capacity of 32 is not provided with a high-level decoder, the high-level second-level input end G2 of each decoder unit is connected to a high potential VDD, which can be a power supply voltage, and the embodiment of the present application is not limited in this regard. Each logic gate cascade device in the second-level row decoding module corresponds to the address of one storage unit or the address of one row of storage units, and one of the 32 output results is always a global pulse control signal. Therefore, the corresponding logic gate cascade device in the second-level row decoding module that outputs the global pulse control signal can correspond to the position of a certain storage unit in the memory, can complete row address decoding, and can store the data to be stored in a certain storage unit in the selected row. The output result of the second-level row decoding module is input to the corresponding storage array, to select the storage unit of the corresponding row, complete row decoding, and the target data can be stored in the selected storage unit of the row. Exemplarily, the global pulse control signal can be 0 or 1, and the embodiment of the present application is not limited in this regard.

[0070] In some embodiments, step S100 can include:

[0071] In the circuit layout design environment, when the decoding capacity is between 33 and 64, a first-level decoder structure package corresponding to two 3-line-8-line decoders, a second-level decoder structure package corresponding to the same number of logic gate cascade devices as the decoding capacity, and a splicing module corresponding to the number of lines are called.

[0072] Exemplarily, when 33≤WL≤64, both the low-level decoder and the middle-level decoder are 3-line-8-line decoders. Exemplarily, WL=48, and the first-level row decoding module composed of two 3-line-8-line decoders corresponds to 64 output results of the second-level row decoding module. However, since the number of target word lines is only 48, 16 output results do not have corresponding storage unit arrays and are useless, and therefore the number of decoders of the second-level row decoding module can be set to only 48. The low-level decoders are arranged from the beginning, and after the low-level decoders are arranged, the middle-level decoders are arranged, and the useless 16 positions can be the corresponding positions of the middle-level decoders.

[0073] In some embodiments, in the circuit layout design environment, when the decoding capacity is between 65 and 128, a first-level decoder structure package corresponding to two 3-line-8-line decoders and one 1-line-2-line decoder, a second-level decoder structure package corresponding to the same number of logic gate cascade devices as the decoding capacity, and a splicing module corresponding to the number of lines are called.

[0074] The row decoding circuit with the decoding capacity of 65-128 includes three binary decoders, two 3-line-8-line decoders and one 1-line-2-line decoder, and the number of logic gate cascade devices is equal to the decoding capacity.

[0075] In some embodiments, in the circuit layout design environment, when the decoding capacity is 129-256, a first decoder structure package corresponding to two 3-line-8-line decoders and one 2-line-4-line decoder is called, the second decoder structure package corresponding to the same number of logic gate cascade devices as the decoding capacity, and the splicing module corresponding to the number of lines.

[0076] The row decoding circuit with the decoding capacity of 129-256 includes three binary decoders, two 3-line-8-line decoders and one 2-line-4-line decoder, and the number of logic gate cascade devices is equal to the decoding capacity.

[0077] In some embodiments, in the circuit layout design environment, when the decoding capacity is 257-512, a first decoder structure package corresponding to three 3-line-8-line decoders is called, a second decoder structure package corresponding to the same number of logic gate cascade devices as the decoding capacity, and a splicing module corresponding to the number of lines.

[0078] When 257≤WL≤512, the low-bit decoder, the middle-bit decoder and the high-bit decoder are all 3-line-8-line decoders.

[0079] The design method of the row decoding circuit provided by the embodiments of the present application calculates the number of word lines of the memory according to the number of memory units of the memory and the number of paths of the multiplexer; based on the same number of word lines and decoding capacity, the number and corresponding types of binary decoders required in the first row decoding module are set, and the number of decoders required in the second row decoding module is set; when the decoding capacity is less than the maximum output combination number of the binary decoders in the first row decoding module, the decoding capacity can be used as the number of decoders required in the second row decoding module, which can save the area of the second row decoding module and the number of decoders in the second row decoding module, and avoid unnecessary waste of logic gate cascade devices. Based on the number of word lines, the number of decoders is determined, which can realize the automatic splicing and expansion of the decoding circuit layout corresponding to different capacity SRAMs for different numbers of memory units and different numbers of paths of the multiplexer.

[0080] In a second aspect, the embodiments of the present application provide a decoding circuit generation device, Figure 6 A schematic structural block diagram of a design device of a row decoding circuit is provided in the embodiments of the present application. As shown in Figure 6

[0081] ​The design device of the row decoding circuit comprises:

[0082] The calling module 500 is used for calling a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module according to decoding capacity in a circuit layout design environment, wherein the first decoder structure package comprises circuit structures of multiple binary decoders, the second decoder structure package comprises circuit structures of multiple logic gate cascade devices, and the splicing module comprises splicing connection lines.

[0083] The connecting module 600 is used for electrically connecting a first-level output end of the binary decoder in the called first decoder structure package and a first splicing connection line of the splicing module, and electrically connecting a second-level input end of the logic gate cascade device in the called second decoder structure package and a second splicing connection line of the splicing module.

[0084] The punching module 700 is used for electrically connecting the first splicing connection line and the second splicing connection line through punching.

[0085] The design device of the row decoding circuit provided by the embodiment of the present application is developed by customization for the existing decoding circuit, and is not suitable for reuse, so that it cannot be used in the Memory Compiler. By calling a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module according to decoding capacity in a circuit layout design environment. The first-level output end of the binary decoder in the called first decoder structure package is electrically connected with a first splicing connection line of the splicing module, and the second-level input end of the logic gate cascade device in the called second decoder structure package is electrically connected with a second splicing connection line of the splicing module. The first splicing connection line and the second splicing connection line are electrically connected through punching. After the number and corresponding types of binary decoders required by the first row decoding module and the number of logic gate cascade devices required by the second row decoding module are determined, the corresponding number and types of decoder structure packages can be directly called, so that the generation efficiency of the decoding circuit can be improved. Different decoding capacity of the row decoding circuit can be generated according to the demand of the target storage capacity, so that the expansion of the row decoding circuit of the corresponding memory can be adapted. The position of the punching can be determined according to the connection mode of the first-level output end and the second-level input end, so that the splicing module can be applied to multiple changed connection schemes. The splicing module can be called as a template and applied to generate row decoding circuits of different circuit structures. The automatic generation of the row decoding circuit can be realized, and the row decoding circuit can be automatically obtained by inputting the decoding capacity, so that the design technology of the decoding circuit is simplified.

[0086] In a third aspect, the embodiment of the present application provides an electronic device, Figure 7A schematic structural block diagram of an electronic device is provided in an embodiment of the present application. As shown in Figure 7 The electronic device comprises:

[0087] a memory 800, in which a computer program is stored;

[0088] a processor 900, which is configured to execute the computer program to implement the design method of the row decoding circuit according to the first aspect.

[0089] The design method of the row decoding circuit comprises the following steps:

[0090] In a circuit layout design environment, according to decoding capacity, a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module are respectively invoked, wherein the first decoder structure package comprises circuit structures of a plurality of binary decoders, the second decoder structure package comprises circuit structures of a plurality of logic gate cascade devices, and the splicing module comprises splicing connection lines;

[0091] A first output end of the binary decoder in the invoked first decoder structure package is electrically connected with a first splicing connection line of the splicing module, and a second input end of the logic gate cascade device in the invoked second decoder structure package is electrically connected with a second splicing connection line of the splicing module;

[0092] The first splicing connection line and the second splicing connection line are electrically connected by punching.

[0093] In a fourth aspect of the embodiment of the present application, a computer readable storage medium is provided, Figure 8 A schematic structural block diagram of a computer readable storage medium is provided in an embodiment of the present application. As shown in Figure 8 The computer readable storage medium 1000 stores a computer program 1100, and the computer program 1100 is executed by a processor to implement the design method of the row decoding circuit according to the first aspect.

[0094] The design method of the row decoding circuit comprises the following steps:

[0095] In a circuit layout design environment, according to decoding capacity, a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module are respectively invoked, wherein the first decoder structure package comprises circuit structures of a plurality of binary decoders, the second decoder structure package comprises circuit structures of a plurality of logic gate cascade devices, and the splicing module comprises splicing connection lines;

[0096] The first-level output end of the binary decoder in the called primary decoder structure package is electrically connected with the first splicing connection line of the splicing module, and the second-level input end of the logic gate cascade device in the called secondary decoder structure package is electrically connected with the second splicing connection line of the splicing module.

[0097] The first splicing connection line and the second splicing connection line are electrically connected through punching.

[0098] In a fifth aspect, the embodiment of the present application provides a row decoding circuit, which is generated by using the design method of the decoding circuit in the first aspect. Figure 2 The row decoding circuit comprises a primary row decoding module 100, the primary row decoding module 100 comprising at least one binary decoder; and a secondary row decoding module 200, the secondary row decoding module 200 comprising at least one logic gate cascade device, the first-level output end of the binary decoder being electrically connected with the second-level input end of the logic gate cascade device.

[0099] The existing decoding circuit is developed by customization and is not suitable for reuse, so that it cannot be used in the Memory Compiler. The row decoding circuit provided by the embodiment of the present application comprises a primary row decoding module 100 and a secondary row decoding module 200, the primary row decoding module 100 comprising at least one binary decoder, the binary decoder 110 being capable of providing address pre-decoding. The secondary row decoding module 200 comprises at least one logic gate cascade device, the first-level output end of the binary decoder being electrically connected with the second-level input end of the logic gate cascade device, the logic gate cascade device being capable of performing combination operation on the result output by the binary decoder to obtain more output results, the logic gate cascade device being capable of performing further address decoding, so that two-level decoding is realized. The cascaded primary row decoding module 100 and secondary row decoding module 200 are capable of increasing the number of decoding bits, increasing the decoding capacity and improving the decoding rate. In the case of the same decoding capacity, the decoding circuit occupies a smaller area.

[0100] The row decoding circuit provided by the embodiment of the present application comprises a primary row decoding module 100 and a secondary row decoding module 200, the primary row decoding module 100 comprising at least one binary decoder, the binary decoder being capable of providing address pre-decoding. The secondary row decoding module 200 comprises at least one logic gate cascade device, the logic gate cascade device being capable of performing combination operation on the result output by the binary decoder to obtain more output results, the logic gate cascade device being capable of performing further address decoding, so that two-level decoding is realized. The cascaded primary row decoding module and secondary row decoding module are capable of increasing the number of decoding bits, increasing the decoding capacity and improving the decoding rate. In the case of the same decoding capacity, the decoding circuit occupies a smaller area.

[0101] The embodiment of the present application can also provide a memory circuit, Figure 9 The embodiment of the present application provides a schematic structural block diagram of a memory circuit. As shown in the figure, Figure 9 The memory circuit provided by the embodiment of the present application comprises the row decoding circuit as described in the fifth aspect; and a storage unit array 2000, which is electrically connected with the row decoding circuit, and specifically, the storage unit array 2000 is electrically connected with the secondary row decoding module 200.

[0102] The memory circuit provided by the embodiment of the present application has the following advantages. The primary row decoding module and the secondary row decoding module are arranged in the row decoding circuit, at least one binary decoder is arranged in the primary row decoding module, and the binary decoder can perform address pre-decoding. At least one logic gate cascaded device is arranged in the secondary row decoding module, the logic gate cascaded device can perform combination operation on the result output by the binary decoder to obtain more output results, the logic gate cascaded device can perform further address decoding, two-stage decoding can be realized, the cascaded primary row decoding module and secondary row decoding module can increase the number of decoding bits, increase the decoding capacity, and improve the decoding rate. In the case of the same decoding capacity, the decoding circuit occupies a smaller area.

[0103] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0104] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer readable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer readable program code.

[0105] The present application is described with reference to flowcharts and / or block diagrams according to the method, device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce a machine that implements the function specified in the flowcharts and / or block diagrams. Figure 1 The device that implements the function specified in one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0106] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0108] The embodiments of the present application also provide a computer program product, which comprises computer software instructions, when the computer software instructions are executed on a processing device, the processing device executes the flow of the method of the row decoding circuit.

[0109] The computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of the present application is produced. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that the computer can store or the data storage device such as server, data center, etc. integrated with one or more available media. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, DVD), or semiconductor media (for example, solid state disk (SSD)) and the like.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0111] In several embodiments provided in the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other manners. For example, the embodiments of the apparatus described above are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0112] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0113] In addition, each functional unit in the embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0114] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or substantially, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

[0115] The above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0116] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the scope of the present description.

[0117] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A design method of a row decode circuit, characterized by, The application relates to a circuit layout design method. In a circuit layout design environment, according to decoding capacity, a first-level decoder structure package required by a first-level row decoding module, a second-level decoder structure package required by a second-level row decoding module and a splicing module are respectively called, wherein the first-level decoder structure package comprises circuit structures of various binary decoders, the second-level decoder structure package comprises circuit structures of various logic gate cascade devices, and the splicing module comprises splicing connection lines; A first-level output end of the binary decoder in the called first-level decoder structure package is electrically connected with a first splicing connection line of the splicing module, and a second-level input end of the logic gate cascade device in the called second-level decoder structure package is electrically connected with a second splicing connection line of the splicing module; The first splicing connection line and the second splicing connection line are electrically connected by punching; The logic gate cascade device comprises at least three second-level input ends, and each second-level input end is used for connecting a corresponding first-level output end of a different binary decoder. The first splicing connection line and the second splicing connection line are electrically connected by punching, so that at least any two first-level output ends are connected to a same logic gate cascade device.

2. The method of claim 1, wherein the row decode circuit is designed to: The first-level row decoding module comprises a low-bit decoder, a middle-bit decoder and a high-bit decoder, the logic gate cascade device comprises three second-level input ends, and the three second-level input ends are respectively connected to any corresponding first-level output end of the low-bit decoder, the middle-bit decoder and the high-bit decoder.

3. The method of claim 2, wherein the row decode circuit is designed to: Two adjacent logic gate cascade devices form a decoder unit, and each decoder unit comprises a first unit input end, a second unit input end, a third unit input end and a fourth unit input end. The first splicing connection line and the second splicing connection line are electrically connected by punching, so that the first unit input end is electrically connected to any corresponding first-level output end of the low-bit decoder, the second unit input end is electrically connected to any corresponding first-level output end of the middle-bit decoder, the third unit input end is electrically connected to any corresponding first-level output end of the high-bit decoder, the fourth unit input end is electrically connected to any corresponding first-level output end of the low-bit decoder, and the fourth unit input end and the first unit input end are electrically connected to different first-level output ends. The first-level row decoding module comprises a low-bit decoder, a middle-bit decoder and a high-bit decoder, the logic gate cascade device comprises three second-level input ends, and the three second-level input ends are respectively connected to any corresponding first-level output end of the low-bit decoder, the middle-bit decoder and the high-bit decoder.

4. The method of claim 1, wherein the row decode circuit is designed to: ​ In the circuit layout design environment, when the decoding capacity is 32, a 3-to-8 decoder and a 2-to-4 decoder are respectively called to correspond to the first decoder structure package, 32 logic gate cascade devices correspond to the second decoder structure package, and the splicing module corresponding to the number of lines.

5. The method of claim 1, wherein the row decode circuit is designed to: In the circuit layout design environment, according to the decoding capacity, a first row decoding module requires a first decoder structure package, a second row decoding module requires a second decoder structure package, and a splicing module is required, which comprises: In the circuit layout design environment, when the decoding capacity is between 33 and 64, two 3-to-8 decoders are respectively called to correspond to the first decoder structure package, the same number of logic gate cascade devices as the decoding capacity correspond to the second decoder structure package, and the splicing module corresponding to the number of lines; or, In the circuit layout design environment, when the decoding capacity is between 65 and 128, two 3-to-8 decoders and one 1-to-2 decoder are respectively called to correspond to the first decoder structure package, the same number of logic gate cascade devices as the decoding capacity correspond to the second decoder structure package, and the splicing module corresponding to the number of lines; or, In the circuit layout design environment, when the decoding capacity is between 129 and 256, two 3-to-8 decoders and one 2-to-4 decoder are respectively called to correspond to the first decoder structure package, the same number of logic gate cascade devices as the decoding capacity correspond to the second decoder structure package, and the splicing module corresponding to the number of lines; or, In the circuit layout design environment, when the decoding capacity is between 257 and 512, three 3-to-8 decoders are respectively called to correspond to the first decoder structure package, the same number of logic gate cascade devices as the decoding capacity correspond to the second decoder structure package, and the splicing module corresponding to the number of lines.

6. An apparatus for generating a decoding circuit, characterized by Comprise: The calling module is used for calling a first decoder structure package required by a first row decoding module, a second decoder structure package required by a second row decoding module and a splicing module in a circuit layout design environment according to decoding capacity, wherein the first decoder structure package comprises circuit structures of a plurality of binary decoders, the second decoder structure package comprises circuit structures of a plurality of logic gate cascade devices, and the splicing module comprises splicing connection lines; The connection module is used for electrically connecting a first output end of the binary decoder in the called first decoder structure package with a first splicing connection line of the splicing module, and electrically connecting a second input end of the logic gate cascade device in the called second decoder structure package with a second splicing connection line of the splicing module; The punching module is used for electrically connecting the first splicing connection line and the second splicing connection line by punching. The logic gate cascade device includes at least three secondary inputs, each of which is used to connect a corresponding primary output of a different binary decoder, and the first splicing connection line and the second splicing connection line are electrically connected by punching. The first splicing connection line and the second splicing connection line are electrically connected by punching, so that at least any two primary outputs are connected to the same logic gate cascade device.

7. An electronic device, comprising: It includes: A memory in which a computer program is stored; A processor configured to implement the design method of the row decoding circuit according to any one of claims 1-5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and the computer program is executed by the processor to implement the design method of the row decoding circuit according to any one of claims 1-5.

9. A row decode circuit, comprising: The design method of the decoding circuit according to any one of claims 1-5 is generated, and the row decoding circuit includes: A primary row decoding module including at least one binary decoder; A secondary row decoding module including at least one logic gate cascade device, and a primary output of the binary decoder is electrically connected to a secondary input of the logic gate cascade device.

Images