Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate, a fin structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin structure is disposed on and extends in a vertical direction from a top surface of the semiconductor substrate. The gate structure is disposed across a portion of the fin structure. At least a portion of the first doped region is disposed in the fin structure. The second doped region is disposed in the fin structure and disposed vertically above the first doped region. The intermediate region is disposed in the fin structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is vertically lower than or coplanar with a top surface of the first doped region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including fin structures. BACKGROUND

[0002] As the size of field effect transistors (FETs) continues to shrink, traditional planar field effect transistors are difficult to develop due to manufacturing limitations. Therefore, to overcome the manufacturing limitations, non-planar transistor technologies such as fin field effect transistor (FinFET) technology are developed to replace planar FETs, which is a development trend in the related industry. Due to the three-dimensional structure of FinFET, the overlapping area between the gate and the fin structure is increased, and the gate can more effectively control the channel region. In this way, the drain-induced barrier lowering (DIBL) effect and short channel effect (SCE) of small-size devices can be reduced. However, in order to further improve its electrical characteristics, there are still some problems to be solved in FinFET. SUMMARY

[0003] In the present disclosure, a semiconductor device and a manufacturing method thereof are provided. By separating a doped region, modifying an area of a fin structure covered by a gate structure across the fin structure, and / or enlarging a bottom portion of the gate structure, leakage current and / or capacitance between different doped regions within the fin structure can be reduced to improve the electrical characteristics of the semiconductor device.

[0004] According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a fin structure, a gate structure, a first doped region, a second doped region, and an intermediate region. The fin structure is disposed on a top surface of the semiconductor substrate and extends in a vertical direction from the top surface of the semiconductor substrate. The gate structure is disposed across a portion of the fin structure. At least a portion of the first doped region is disposed in the fin structure. The second doped region is disposed in the fin structure and disposed above the first doped region in the vertical direction. The intermediate region is disposed in the fin structure. The second doped region is separated from the first doped region by the intermediate region, and a bottom surface of the gate structure is lower than a top surface of the first doped region in the vertical direction or coplanar with the top surface of the first doped region.

[0005] According to an embodiment of the present disclosure, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A fin structure is formed on a semiconductor substrate, and the fin structure extends upward in a vertical direction from a top surface of the semiconductor substrate. At least a portion of a first doped region is located in the fin structure. A second doped region is formed in the fin structure. The second doped region is located above the first doped region in the vertical direction, and the second doped region is separated from the first doped region by an intermediate region located in the fin structure. A gate structure is formed to cross a portion of the fin structure. A bottom surface of the gate structure is lower than a top surface of the first doped region in the vertical direction or coplanar with the top surface of the first doped region.

[0006] According to an embodiment of the present application, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a fin structure, and a gate structure. The fin structure is disposed on a top surface of the semiconductor substrate and extends in a vertical direction from the top surface of the semiconductor substrate. The gate structure is disposed across a portion of the fin structure, and the gate structure includes a first portion and a second portion disposed on the first portion. A width of the first portion of the gate structure is greater than a width of the second portion of the gate structure.

[0007] According to an embodiment of the present application, a method of manufacturing a semiconductor device is provided. The method includes the following steps. A fin structure is formed on a semiconductor substrate, and the fin structure extends in a vertical direction upward from a top surface of the semiconductor substrate. A gate structure is formed to cross a portion of the fin structure, and the gate structure includes a first portion and a second portion disposed on the first portion. A width of the first portion is greater than a width of the second portion.

[0008] These and other objects of the present application will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various drawing and picture figures. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a perspective view showing a semiconductor device according to a first embodiment of the present application.

[0010] Figure 2 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present application.

[0011] Figure 3 is a cross-sectional view showing a source / drain structure in the semiconductor device according to the first embodiment of the present application.

[0012] Figure 4 is a cross-sectional view showing a gate structure in the semiconductor device according to the first embodiment of the present application.

[0013] Figures 5-9 is a perspective view showing a method of manufacturing a semiconductor device according to the first embodiment of the present application, wherein, Figure 6 is Figure 5 a subsequent step of Figure 7 is Figure 6 a subsequent step of Figure 8 is Figure 7 a subsequent step of Figure 9 is Figure 8 a subsequent step of

[0014] Figure 10 is a cross-sectional schematic view showing a source / drain structure in a semiconductor device according to a second embodiment of the present application.

[0015] Figure 11 is a cross-sectional schematic view showing a gate structure in a semiconductor device according to the second embodiment of the present application.

[0016] Figures 12-14 is a perspective schematic view showing a manufacturing method of a semiconductor device according to the second embodiment of the present application, wherein Figure 13 is Figure 12 a subsequent step of Figure 14 is Figure 13 a subsequent step of

[0017] Figure 15 is a cross-sectional schematic view showing a source / drain structure in a semiconductor device according to a third embodiment of the present application.

[0018] Figure 16 is a cross-sectional schematic view showing a gate structure in a semiconductor device according to the third embodiment of the present application.

[0019] Figures 17-19 is a perspective schematic view showing a manufacturing method of a semiconductor device according to the third embodiment of the present application, wherein Figure 18 is Figure 17 a subsequent step of Figure 19 is Figure 18 a subsequent step of

[0020] Figure 20 is a perspective schematic view showing a semiconductor device according to a fourth embodiment of the present application.

[0021] Figure 21 is a cross-sectional schematic view showing a semiconductor device according to the fourth embodiment of the present application.

[0022] Figure 22 is a cross-sectional schematic view showing a gate structure in a semiconductor device according to the fourth embodiment of the present application.

[0023] Figures 23-26 is a perspective schematic view showing a manufacturing method of a semiconductor device according to the fourth embodiment of the present application, wherein Figure 24 is Figure 23 a subsequent step of Figure 25 is Figure 24 a subsequent step of Figure 26 is Figure 25 a subsequent step of

[0024] Figure 20 is a cross-sectional schematic view showing a semiconductor device according to a fifth embodiment of the present application.

[0025] Figure 26 is a cross-sectional schematic view showing a semiconductor device according to a fifth embodiment of the present application. Figure 20-22 is Figure 25 a subsequent step of Figure 20-22 is Figure 25 a subsequent step of Figure 20-22 is Figure 25 a subsequent step of Figure 23 is Figure 23 a subsequent step of

[0026] Figure 24 is a cross-sectional schematic view showing a semiconductor device according to a sixth embodiment of the present application.

[0027] Figure 24 and Figure 25 is a cross-sectional schematic view showing a semiconductor device according to a sixth embodiment of the present application. Figure 25 is Figure 26 a subsequent step of

[0028] Figure 26 is a cross-sectional schematic view showing a semiconductor device according to a seventh embodiment of the present application.

[0029] Figure 20 and Figure 27 is a cross-sectional schematic view showing a semiconductor device according to a seventh embodiment of the present application. Figure 27 is Figures 28-32 a subsequent step of

[0030] Figure 29 is a cross-sectional schematic view showing a semiconductor device according to an eighth embodiment of the present application.

[0031] Figure 28 and Figure 30 is a cross-sectional schematic view showing a semiconductor device according to an eighth embodiment of the present application. Figure 29 is Figure 31 a subsequent step of

[0032] Figure 30 is a cross-sectional schematic view showing a semiconductor device according to a ninth embodiment of the present application.

[0033] Figure 32 and Figure 31is a schematic perspective view showing a manufacturing method of a semiconductor device according to a ninth embodiment of the present application, wherein Figure 27 is Figure 32 a subsequent step of

[0034] Figure 32 and Figure 27 is a schematic perspective view showing a manufacturing method of a semiconductor device according to a tenth embodiment of the present application, wherein Figure 32 is Figure 27 a subsequent step of

[0035] Figure 32 is a schematic perspective view showing a manufacturing method of a semiconductor device according to an eleventh embodiment of the present application. DETAILED DESCRIPTION

[0036] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be employed without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present application can also be employed in a variety of other applications.

[0037] It should be noted that references to “one embodiment,” “an embodiment,” “some embodiments,” etc. in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in this specification are not necessarily referring to the same embodiment.

[0038] It should be understood that although the terms “first,” “second,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and / or section from another region. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of this disclosure.

[0039] It should be understood that in this disclosure, “above,” “over,” or “on top” can be interpreted in the broadest way, such that “above” means not only “directly on” something, but also includes meaning “on top” of something in the presence of an intermediate feature or layer between them, and “over” or “on top” means not only “above” or “on top” of something, but also includes meaning “above” or “on top” of something in the absence of an intermediate feature or layer before it (i.e., directly on top of something).

[0040] The term "etching" is used herein to describe a process of patterning a material layer so as to retain at least a portion of the etched material layer. When a material layer is "etched," at least a portion of the material layer is retained after the process. In contrast, when a material layer is "removed," essentially all of the material layer is removed in the process. However, in some embodiments, "removal" is considered a broad term and may include etching.

[0041] The terms “forming” or “setting” are used below to describe the act of applying a material layer to a substrate. These terms are intended to describe any possible layer forming techniques, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0042] Figure 28 This is a perspective schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 28 This is a cross-sectional schematic diagram of the semiconductor device 101 in this embodiment. Figure 29 This is a schematic cross-sectional view of the source / drain structure 30 in the semiconductor device 101 according to this embodiment, and Figure 29 This is a schematic cross-sectional view of the gate structure GS in the semiconductor device 101 according to this embodiment. Figure 30 This can be considered as being along the elongation direction of the fin structure FS in the semiconductor device 101 (e.g., Figures 30-32 The cross-sectional view taken in the first direction D1 shown. Figure 32 and Figure 32 It can be viewed as a cross-sectional view taken along a direction perpendicular to the elongation direction of the fin structure FS (e.g., Figure 27 The second direction D2 is shown. Figure 27 As shown, the semiconductor device 101 includes a semiconductor substrate 10, a fin structure FS, a gate structure GS, a first doped region 14, a second doped region 24, and an intermediate region 16. The fin structure FS is disposed on the semiconductor substrate 10 and in the vertical direction (e.g., Figure 33The third direction D3) shown in the middle extends upward from the top surface 10TS of the semiconductor substrate 10. The gate structure GS is disposed to span a portion of the fin structure FS. At least a portion of the first doped region 14 is disposed in the fin structure FS. The second doped region 24 is disposed in the fin structure FS and above the first doped region 14 in the third direction D3. The intervening region 16 is disposed in the fin structure FS. The second doped region 24 is separated from the first doped region 14 by the intervening region 16, and a bottom surface BS of the gate structure GS is lower than or coplanar with a top surface 14TS of the first doped region 14 in the third direction D3.

[0043] In some embodiments, the fin structure FS can be formed by etching a portion of the semiconductor substrate 10, and a material composition of the fin structure FS and / or a material composition of a bottom portion of the fin structure FS can be the same as a material composition of the semiconductor substrate 10 and / or a material composition of a top portion of the semiconductor substrate 10 directly connected to the bottom portion of the fin structure FS. For example, when the semiconductor substrate 10 is a silicon semiconductor substrate, the fin structure FS can be a silicon semiconductor fin structure FS, but is not limited thereto. In other words, in the present disclosure, the fin structure FS is not a fin structure formed directly on an insulator layer of a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 10 can include a silicon semiconductor substrate, a silicon-germanium semiconductor substrate, a silicon carbide semiconductor substrate, or a substrate made of other suitable semiconductor materials. In a top view of the semiconductor device 101, the fin structure FS can be elongated in the first direction D1, the gate structure GS can be elongated in the second direction D2 to span a portion of the fin structure FS, and the second direction D2 can be substantially orthogonal to the first direction D1, but is not limited thereto. Thus, the gate structure GS can be partially disposed on two opposite sides of the fin structure FS in the second direction D2, and the fin structure FS can be partially disposed on two opposite sides of the gate structure GS in the first direction D1. It is worth noting that some components shown in the drawings of the present disclosure can further extend in the first direction D1 and / or the second direction D2, and are not limited to the shapes shown in the drawings. For example, the gate structure GS disposed on two opposite sides of the fin structure FS in the second direction D3 can further extend in the second direction D2 to span another fin structure, but is not limited thereto.

[0044] In some embodiments, the third direction D3 can be regarded as a thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 can have a top surface 10TS and a bottom surface opposite to the top surface 10TS in the third direction D3. In some embodiments, the first direction D1 and the second direction D2 can be regarded as horizontal directions in a horizontal plane orthogonal to a vertical direction (e.g., the third direction D3), and can be parallel to the top surface 10TS and / or the bottom surface of the semiconductor substrate 10, but are not limited thereto. Furthermore, in this specification, the distance between the bottom surface of the semiconductor substrate 10 and a relatively higher position and / or a relatively higher portion in the third direction D3 is greater than the distance between the bottom surface of the semiconductor substrate 10 and a relatively lower position and / or a relatively lower portion in the third direction D3. The bottom or lower portion of each component can be closer to the bottom surface of the semiconductor substrate 10 in the third direction D3 than the top or upper portion of the component. Another component provided above a certain component can be regarded as relatively more distanced from the bottom surface of the semiconductor substrate 10 in the third direction D3, and another component provided below the certain component can be regarded as relatively closer to the bottom surface of the semiconductor substrate 10 in the third direction D3. Furthermore, in this specification, the top surface of a certain component can include the uppermost surface of the component in the third direction D3, and the bottom surface of the certain component can include the lowermost surface of the component in the third direction D3.

[0045] In some embodiments, the second doped region 24 can have a different and complementary conductivity type than the first doped region 14. For example, the first doped region 14 can include a first conductive impurity, the second doped region 24 can include a second conductive impurity, and the first conductive impurity can have a different conductivity type than the second conductive impurity. In some embodiments, when the semiconductor device 101 is an n-type transistor, the first doped region 14 can be a p-type doped region including a p-type impurity, and the second doped region 24 can be an n-type doped region including an n-type impurity. When the semiconductor device 101 is a p-type transistor, the first doped region 14 can be an n-type doped region including an n-type impurity, and the second doped region 24 can be a p-type doped region including a p-type impurity. The above p-type impurity can include boron (B) or other suitable p-type conductive impurity, and the above n-type impurity can include phosphorus (P), arsenic (As), or other suitable n-type conductive impurity, but is not limited thereto. In addition, the intermediate region 16 can have the same conductivity type as the first doped region 14, and the impurity concentration in the first doped region 14 can be higher than the impurity concentration in the intermediate region 16. For example, the intermediate region 16 can include a third conductive impurity, the third conductive impurity can have the same conductivity type as the first conductive impurity, but the concentration of the third conductive impurity in the intermediate region 16 is lower than the concentration of the first conductive impurity in the first doped region 14. In some embodiments, the third conductive impurity can be the same as or different from the first conductive impurity, but the first conductive impurity and the third conductive impurity are both n-type conductive impurities or p-type conductive impurities.

[0046] In some embodiments, the semiconductor device 101 can further include a well region 12, an isolation structure 15, a channel region 18, a spacer structure 26, a source / drain region 28, a source / drain structure 30, and a dielectric layer 32. The well region 12 can be partially disposed in the semiconductor substrate 10 and partially disposed in the fin structure FS, and the first doped region 14 can be disposed above the well region 12. Accordingly, a bottom surface 14BS of the first doped region 14 can be higher than a top surface 10TS of the semiconductor substrate 10 in the third direction D3, but is not limited thereto. In some embodiments, the well region 12 can have the same conductivity type as the first doped region 14, and the impurity concentration in the first doped region 14 can be higher than the impurity concentration in the well region 12. For example, the well region 12 can include a fourth conductive impurity, the fourth conductive impurity can have the same conductivity type as the first conductive impurity, but the concentration of the fourth conductive impurity in the well region 12 is lower than the concentration of the first conductive impurity in the first doped region 14. In some embodiments, the fourth conductive impurity can be the same as or different from the first conductive impurity, but the first conductive impurity and the fourth conductive impurity are both n-type conductive impurities or p-type conductive impurities.

[0047] The channel region 18 can be disposed in the fin structure FS and above the middle region 16 in the third direction D3. In some embodiments, the channel region 18 can have the same conductivity type as the middle region 16, the channel region 18 can include the same conductive impurities as the third conductive impurities in the middle region 16, and the impurity concentration in the channel region 18 can be substantially equal to the impurity concentration in the middle region 16, but not limited thereto. In some embodiments, the channel region 18 can be directly connected with the middle region 16, and the gate structure GS can cover the channel region 18 in the second direction D2 and the third direction D3, and cover a portion of the middle region 16 in the second direction D2.

[0048] In some embodiments, the gate structure GS can include a gate dielectric and a gate material layer (not shown in the figures) disposed on the gate dielectric layer. The gate dielectric layer can include a high dielectric constant (high-k) dielectric material or other suitable dielectric material. The high-k dielectric material described above can include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k material. The gate material layer can include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by a work function layer and a low resistivity layer stacked with each other, but not limited thereto. The work function layer described above can include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium trialuminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function material. The low resistivity layer described above can include tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low resistivity material.

[0049] The isolation structure 15 can be disposed on the semiconductor substrate 10 and around a portion of the fin structure FS, such as a lower portion of the fin structure FS. The isolation structure 15 can include a single layer or multiple layers of insulating material, such as an oxide insulating material (e.g., silicon oxide), or other suitable insulating material. In some embodiments, a portion of the gate structure GS can be disposed on the isolation structure 15 in the third direction D3, and a top surface 15TS of the isolation structure 15 can be lower than or coplanar with a top surface 14TS of the first doped region 14 in the third direction D3. In some embodiments, a bottom surface BS of the gate structure GS can directly contact the top surface 15TS of the isolation structure 15, and the gate structure GS can cover a side surface 16SS of the middle region 16 in the second direction D2. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3 to ensure that the middle region 16 located between the channel region 18 and the first doped region 14 is covered by the gate structure GS in the second direction D2.

[0050] The spacer structure 26 can include a single layer or multiple layers of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. The spacer structure 26 can be partially disposed on the sidewall of the gate structure GS and partially disposed on the sidewall of the fin structure FS. For example, the spacer structure 26 can include a first portion 26A disposed on the sidewall of the gate structure GS and a second portion 26B disposed on the sidewall of the lower portion of the fin structure FS, but is not limited thereto. A portion of the first portion 26A can be directly connected with the second portion 26B, and a top surface of the second portion 26B can be lower than a top surface of the first portion 26A in the third direction D3. The source / drain region 28 is disposed in the fin structure FS and disposed above the second doped region 24 in the third direction D3. The source / drain region 28 can have the same conductivity type as the second doped region 24, and the impurity concentration in the source / drain region 28 can be higher than the impurity concentration in the second doped region 24. For example, the source / drain region 28 can include a fifth conductive impurity, and the fifth conductive impurity can have the same conductivity type as the second conductive impurity in the second doped region 24, but the concentration of the fifth conductive impurity in the source / drain region 28 is higher than the concentration of the second conductive impurity in the second doped region 24. Thus, the source / drain region 28 can be regarded as a heavily doped region, and the second doped region 24 can be regarded as a heavily doped region or a relatively lightly doped region (e.g., a lightly doped drain, LDD), but is not limited thereto. In some embodiments, the fifth conductive impurity can be the same as or different from the second conductive impurity, but both the second conductive impurity and the fifth conductive impurity are n-type conductive impurities or p-type conductive impurities. For example, for an n-type transistor, the second conductive impurity in the second doped region 24 can be arsenic, and the fifth conductive impurity in the source / drain region 28 can be phosphorus, because arsenic is less likely to diffuse than phosphorus, but is not limited thereto.

[0051] In some embodiments, the source / drain structure 30 can be disposed on and enclose the source / drain region 28, but not limited thereto. The source / drain structure 30 can comprise an epitaxial material, such as epitaxial silicon, epitaxial silicon germanium (SiGe), epitaxial silicon phosphide (SiP), or other suitable epitaxial material. In some embodiments, the source / drain structure 30 can contain a conductive impurity that is the same as or similar to the fifth conductive impurity in the source / drain region 28. The source / drain structure 30 can comprise two separate portions disposed on two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the source / drain structure 30 can be considered as a source electrode and a drain electrode of the semiconductor device, respectively. The source / drain region 28 can comprise two separate portions disposed on two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the source / drain region 28 can be considered as a source doped region and a drain doped region of the semiconductor device, respectively. The second doped region 24 can comprise two separate portions disposed on two opposite sides of the gate structure GS in the first direction D1, respectively, and the two portions of the second doped region 24 can be considered as an LDD region of the source electrode and an LDD region of the drain electrode in the semiconductor device, respectively, but not limited thereto. The dielectric layer 32 can comprise a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. The dielectric layer 32 can cover the source / drain structure 30 and the spacer structure 26, and a top surface 32TS of the dielectric layer 32 can be substantially coplanar with a top surface of the gate structure GS, but not limited thereto.

[0052] The first doped region 14 with a relatively high impurity concentration can be used to reduce the leakage current between the source electrode and the drain electrode (e.g., different portions of the source / drain structure 30 disposed on two opposite sides of the gate structure GS in the first direction D1, respectively) at the bottom of the fin structure FS, and the first doped region 14 can be considered as a channel cut-off region, but not limited thereto. The intermediate region 16 with a relatively low impurity concentration disposed between the first doped region 14 and the second doped region 24 can be used to reduce the leakage current between the first doped region 14 and the second doped region 24 and / or the capacitance between the first doped region 14 and the second doped region 24. Furthermore, the gate structure GS with the bottom surface BS lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3 can reduce the leakage current between different lightly doped regions (e.g., different portions of the second doped region 24 disposed on two opposite sides of the gate structure GS in the first direction D1, respectively) by covering the intermediate region 16 between the channel region 18 and the first doped region 14. Therefore, the electrical characteristics of the semiconductor device can be improved by the intermediate region 16 disposed between the first doped region 14 and the second doped region 24 and the gate structure GS with the bottom surface BS lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3.

[0053] Figure 33 This is a perspective schematic diagram illustrating a method for manufacturing a semiconductor device 101 according to a first embodiment of the present invention, wherein... Figures 20-22 yes Figure 34 A three-dimensional diagram for subsequent steps. Figure 35 yes Figure 35 A three-dimensional diagram for subsequent steps. Figure 34 yes Figure 33 A three-dimensional diagram for subsequent steps. Figure 35 yes Figure 34 The 3D diagram in the subsequent steps, and Figure 25 It can be regarded as Figures 23-25 A three-dimensional diagram for subsequent steps. For example... Figure 34 As shown, a method for manufacturing semiconductor device 101 may include the following steps. A fin structure FS is formed on a semiconductor substrate 10, and the fin structure FS extends upward from the top surface 10TS of the semiconductor substrate 10 in a vertical direction (e.g., third direction D3). At least a portion of a first doped region 14 is located in the fin structure FS. A second doped region 24 is formed in the fin structure FS. The second doped region 24 is located above the first doped region 14 in the third direction D3, and the second doped region 24 is separated from the first doped region 14 by an intermediate region 16 located in the fin structure FS. A gate structure GS is formed as a portion spanning the fin structure FS. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3.

[0054] Specifically, the manufacturing method of the semiconductor device 101 in this embodiment includes, but is not limited to, the following steps. First, as Figure 35 As shown, a semiconductor substrate 10 is provided, and a first doped region 14 can be formed in the semiconductor substrate 10 by a doping process 91. The doping process described in this specification may include ion implantation or other suitable impurity doping methods. The extent, depth, and impurity concentration of the first doped region 14 in the semiconductor substrate 10 can be controlled by modifying the process parameters of the doping process 91. Then, as... Figure 35 and Figure 33 As shown, the fin structure FS can be formed by patterning the semiconductor substrate 10, and the isolation structure 15 can be formed around the lower part of the fin structure FS. In some embodiments, a portion of the original surface 10S of the semiconductor substrate 10 can be recessed by patterning to become Figure 36 and Figure 36The top surface 10TS of the semiconductor substrate 10 shown, and another portion of the original surface 10S of the semiconductor substrate 10, can become the top surface of the fin structure FS, but are not limited thereto. In some embodiments, the top surface 15TS of the isolation structure 15 can be controlled by performing an etch-back process on the isolation structure 15, causing the isolation structure 15 to be recessed and exposing the upper portion of the fin structure FS and a portion of the sidewall SW1 of the fin structure FS. After the step of forming the isolation structure 15, the exposed portion of the fin structure FS can be doped with a third conductive impurity as described above, and the top surface 15TS of the isolation structure 15 can be controlled to be substantially coplanar with and / or aligned with the top surface of the first doped region 14 in the third direction D3. Therefore, the first doped region 14 can be formed before the step of forming the fin structure FS, but is not limited thereto. In some embodiments, depending on other design and / or process considerations, the first doped region 14 can be formed after the step of forming the fin structure FS.

[0055] like Figure 27 As shown, the dummy gate DG is formed across the fin structure FS. In some embodiments, the method of forming the dummy gate DG may include, but is not limited to, the following steps. Figure 37 and Figure 38 As shown, a material layer can be formed on an isolation structure and cover the fin structure FS. The material layer can be patterned using a mask layer 22 formed on the material layer as a mask to form a patterned material layer 20P on the semiconductor substrate after the step of forming the fin structure FS. A planarization process (e.g., chemical mechanical polishing (CMP)) of the material layer can be performed after the formation of the material layer and before the formation of the mask layer 22. The mask layer 22 can include an oxide insulating material (e.g., silicon oxide) or other suitable insulating material. In some embodiments, the patterned material layer 20P can include a first portion 20A and a second portion 20B connected to the first portion 20A. The first portion 20A can be configured to span a portion of the fin structure FS, and the second portion 20B can extend in a first direction D1 and cover a portion of the sidewall SW1 of the fin structure FS. For example, the second portion 20B of the patterned material layer 20P can cover the sidewall SW1 of the exposed lower portion of the fin structure FS. After the step of forming the patterned material layer 20P, the second doped region 24 can be formed in the fin structure FS by performing another doping process 92. In some embodiments, the patterned material layer 20P can be used as a mask in the doping process 92, the second doped region 24 can be formed in the exposed portion of the fin structure FS, and the portion of the fin structure FS covered by the patterned material layer 20P can be the aforementioned intermediate region 16 and channel region. Figure 38 and Figure 37As shown, after the step of forming the second doped region 24, the patterned material layer 20P can be etched, and the patterned material layer 20P can be etched into a dummy gate DG. In some embodiments, the second portion 20B of the patterned material layer 20P can be removed by the etching process, and the first portion 20A of the patterned material layer 20P can be considered as a dummy gate DG, but is not limited thereto. In some embodiments, the second doped region 24 can be formed after the step of forming the patterned material layer 20P and before the second portion 20B of the patterned material layer 20P is removed by the etching process, but is not limited thereto. Furthermore, the dummy gate DG can cover a portion of the side surface of the intermediate region 16 in the second direction D2, and the dummy gate DG can be replaced with a gate structure as described above in a subsequent process. In some embodiments, the dummy gate DG can be formed by the patterned material layer 20P, and the dummy gate DG and the patterned material layer 20P can include silicon-containing materials, such as polycrystalline silicon, amorphous silicon, or other suitable materials.

[0056] like Figure 36 As shown, the spacer structure 26 can be formed after the step of forming the second doped region 24. A first portion 26A of the spacer structure 26 can be formed on the sidewall of the dummy gate DG, and a second portion 26B of the spacer structure 26 can be formed on the sidewall of the fin structure FS. In some embodiments, a portion of the second portion 26B of the spacer structure 26 can be etched back to expose the upper part of the fin structure FS, and the source / drain structure 30 can be formed on the exposed fin structure FS by an epitaxial growth process or other suitable method. In some embodiments, a dielectric layer (e.g., Figure 38 The dielectric layer 19 shown can be formed on the fin structure FS before the steps of forming the material layer described above and forming the spacer structure 26. A portion of the dielectric layer must be removed before the step of forming the source / drain structure 30, and a portion of the dielectric layer can remain and be located between the spacer structure 26 and the fin structure FS, but is not limited thereto. In some embodiments, the source / drain structure 30 can be in-situ doped during the process of forming the source / drain structure 30, and the source / drain region 28 can be formed simultaneously by this process, but is not limited thereto. Instead of the above-described in-situ doping process, the source / drain structure 30 and the source / drain region 28 can be doped by an ion implantation process after the formation of the spacer structure 26. Subsequently, as Figure 37 and Figure 27As shown, the dielectric layer 32 can be formed, and the dummy gate DG can be replaced by the gate structure GS by a replacement metal gate (RMG) process, but not limited thereto. In some embodiments, the dummy gate DG and the mask layer 22 can be replaced by the gate structure GS. In some embodiments, the mask layer 22 can be removed by a planarization process performed on the dielectric layer 32, the spacer structure 26, and the mask layer 22, and the dummy gate DG can be replaced by the gate structure GS after the planarization process. The planarization process can include a CMP process, an etch-back process, or other suitable planarization methods.

[0057] It is noted that the method of manufacturing the semiconductor device is not limited to the above-described method, and the method of manufacturing the semiconductor device of the present application can employ other suitable methods. In addition, at least some of the steps in the above-described manufacturing method can be applied to other embodiments of the present application.

[0058] The following description will detail different embodiments of the present application. For simplicity of explanation, the same elements in the following embodiments are denoted by the same reference numerals. For ease of understanding the differences between the embodiments, the following description will detail the differences between the different embodiments, and the same features will not be described again.

[0059] Figures 28-32 is a cross-sectional schematic view showing a source / drain structure 30 in a semiconductor device 102 according to a second embodiment of the present application, Figure 37 is a cross-sectional schematic view showing a gate structure GS in the semiconductor device 102 according to the embodiment. Figure 38 and Figure 38 may be considered as cross-sectional views at different portions of the semiconductor device 102. As shown in FIG. 2A, Figure 36 and Figure 33As shown, in the semiconductor device 102, the fin structure FS can include a first portion P1, a second portion P2, and a third portion P3. The second portion P2 is disposed on the first portion P1 in the third direction D3, and the third portion P3 is disposed between the first portion P1 and the second portion P2 in the third direction D3. The width W1 of the first portion P1 can be greater than the width W2 of the second portion P2, and the sidewall SW2 of the third portion P3 can be tapered to increase the area of the fin structure FS covered by the gate structure GS. In some embodiments, the width W1 of the first portion P1 can be considered as the length of the first portion P1 in the second direction D2, and the width W2 of the second portion P2 can be considered as the length of the second portion P2 in the second direction D2. In addition, at least a portion of the intermediate region 16 can be disposed in the third portion P3, at least a portion of the first doped region 14 can be disposed in the first portion P1, and the second doped region 24 and the source / drain region 28 can be disposed in the second portion P2, but not limited thereto. In some embodiments, the interface between the first portion P1 and the third portion P3 in the third direction D3 can be substantially coplanar with the top surface 15TS of the isolation structure 15 and / or the bottom surface BS of the gate structure GS, but not limited thereto. In addition, the length of the second portion P2 in the third direction D3 can be greater than the length of the third portion P3 in the third direction D3, the slope of the sidewall of the second portion P2 can be greater than the slope of the sidewall SW2 of the third portion P3, and the third portion P3 can be considered as an enlarged portion for increasing the surface area of the fin structure FS covered by the gate structure GS, but not limited thereto.

[0060] Figure 10 is a schematic perspective view showing a manufacturing method of the semiconductor device 102 according to the second embodiment of the present application, wherein Figure 11 is Figure 33 a subsequent step of Figure 10 is Figure 11 a subsequent step of Figure 33 and Figure 36 can be considered as Figure 10 a subsequent step of Figure 11 As shown, the above-mentioned fin structure FS including the first portion P1, the second portion P2, and the third portion P3 can be formed by modifying the above-mentioned patterning process of the semiconductor substrate 10. As shown in Figure 36 , 11 and 13, in some embodiments, during the doping process 92 for forming the second doped region 24, the second portion 20B of the patterned material layer 20P can cover the third portion P3 and a portion of the second portion P2 of the fin structure FS in the second direction D2. As shown in Figure 10 , 11As shown in FIGS. 13 and 14, the second portion 20B of the patterned material layer 20P can be removed to form the dummy gate DG, which can cover a portion of the sidewall SW2 of the third portion P3, and the intermediate region 16 can be formed partially in the third portion P3 and partially in the second portion P2, but not limited thereto. Subsequently, the dummy gate DG can be replaced with the gate structure GS to form the semiconductor device 102.

[0061] It is noted that the manufacturing method of the semiconductor device 102 is not limited to the above method, and the manufacturing method of the semiconductor device 102 can also employ other suitable methods. In addition, in this embodiment, the fin structure FS including the first portion P1, the second portion P2 and the third portion P3 can also be applied to other embodiments of the present application.

[0062] Figure 11 is a cross-sectional schematic view showing a source / drain structure 30 in a semiconductor device 103 according to a third embodiment of the present application, Figure 36 is a cross-sectional schematic view showing a gate structure GS in the semiconductor device 103 according to this embodiment. Figure 39 and Figure 39 may be regarded as cross-sectional views at different portions of the semiconductor device 103. As shown in FIG. 15, Figure 40 and Figure 41 in the semiconductor device 103, the top surface 15TS of the isolation structure 15 and the bottom surface BS of the gate structure GS can be lower than the top surface 14TS of the first doped region 14 in the third direction D3 and higher than the bottom surface 14BS of the first doped region 14 in the third direction D3. Therefore, the gate structure GS can further cover a portion of the side surface 14SS of the first doped region 14 in the second direction D2 to ensure that the intermediate region 16 located between the channel region 18 and the first doped region 14 is covered by the gate structure GS in the second direction D2.

[0063] Figure 41 is a perspective schematic view showing a manufacturing method of the semiconductor device 103 according to the third embodiment of the present application, wherein Figure 40 is Figure 39 a subsequent step of Figure 41 is Figure 40 a subsequent step of Figure 34 and Figure 40 may be regarded as Figure 41 subsequent steps of Figure 41As shown, after the step of forming the isolation structure 15, the top surface 15TS of the isolation structure 15 can be lower than the top surface 14TS of the first doped region 14 in the fin-shaped structure FS. In some embodiments, the top surface 15TS of the isolation structure 15 can be controlled by performing a back-etching process on the isolation structure 15 to recess the isolation structure 15 and expose an upper portion of the fin-shaped structure FS and a portion of the first doped region 14. As Figure 39 As shown, in some embodiments, during the doping process 92 for forming the second doped region 24, the second portion 20B of the patterned material layer 20P can cover a portion of the side surface of the first doped region 14 and the side surface of the intermediate region 16 in the second direction D2. As Figure 42 and Figure 42 As shown, the second portion 20B of the patterned material layer 20P can be removed to form a dummy gate DG, which can cover a portion of the side surface 16SS of the intermediate region 16 and a portion of the side surface 14SS of the first doped region 14 in the second direction D2, and a bottom surface of the dummy gate DG can be lower than the top surface 14TS of the first doped region in the third direction D3. Subsequently, as Figure 43 , 15 and 16, the dummy gate DG can be replaced with a gate structure GS to form the semiconductor device 103.

[0064] It is noted that the manufacturing method of the semiconductor device 103 is not limited to the above method, and other suitable methods can also be employed for the manufacturing method of the semiconductor device 103. In addition, in this embodiment, the gate structure GS covering a portion of the side surface 16SS of the intermediate region 16 and a portion of the side surface 14SS of the first doped region 14 can also be applied to other embodiments of the present application.

[0065] Figure 44 is a perspective view showing a semiconductor device 104 according to a fourth embodiment of the present application, Figure 44 is a cross-sectional view showing the semiconductor device 104 in this embodiment, and Figure 43 is a cross-sectional view showing a gate structure GS in the semiconductor device 104 according to this embodiment. Figure 42 may be considered as a cross-sectional view taken along an elongation direction of a fin-shaped structure FS in the semiconductor device 104, and Figure 44 may be considered as a cross-sectional view taken along a direction perpendicular to the elongation direction of the fin-shaped structure FS. As Figure 43As shown, the semiconductor device 104 includes a semiconductor substrate 10, a fin structure FS, and a gate structure GS. The fin structure FS is disposed on a top surface 10TS of the semiconductor substrate 10 and extends upward therefrom in a vertical direction (e.g., the third direction D3). The gate structure GS is disposed across a portion of the fin structure FS, and the gate structure GS includes a first portion GS1 and a second portion GS2, the second portion GS2 being disposed on and directly connected to the first portion GS1 in the third direction D3. A width W3 of the first portion GS1 of the gate structure GS is greater than a width W4 of the second portion GS2 of the gate structure GS. The width W4 of the second portion GS2 can be considered a length of the second portion GS2 in the first direction D1, and the width W3 of the first portion GS1 can be considered a length of the first portion GS1 in the first direction D1, such as a maximum length of the first portion GS1 in the first direction D1, but is not limited thereto.

[0066] In some embodiments, the first portion GS1 of the gate structure GS can include a lower portion GS11 and an upper portion GS12 directly connected to the lower portion GS11, the slope of the sidewall SW3 of the lower portion GS11 can be different from the slope of the sidewall SW4 of the upper portion GS12, and the width of the first portion GS1 of the gate structure GS can gradually change in the first direction D3, but not limited thereto. For example, the slope of the sidewall SW3 of the lower portion GS11 can be greater than the slope of the sidewall SW4 of the upper portion GS12, and the width of the first portion GS1 of the gate structure GS can gradually decrease from the bottom surface BS of the gate structure GS to the interface between the first portion GS1 and the second portion GS2. In some embodiments, the angle between the sidewall SW3 of the lower portion GS11 and the bottom surface BS of the gate structure GS can be greater than the angle AG between the sidewall SW4 of the upper portion GS12 and a horizontal plane HP parallel to the top surface 10TS of the semiconductor substrate 10 to increase the area of the fin structure FS covered by the first portion GS1 of the gate structure GS. For example, the angle AG between the sidewall SW4 of the upper portion GS12 and the horizontal plane HP can be less than 45 degrees, and the angle between the sidewall SW3 of the lower portion GS11 and the bottom surface BS of the gate structure GS can be greater than 45 degrees and less than 90 degrees, but not limited thereto. In some embodiments, the sidewall of the first portion GS1 can have a curved surface, and the width thereof gradually decreases from the bottom surface BS of the gate structure GS to the interface between the first portion GS1 and the second portion GS2. In addition, the length of the second portion GS2 in the third direction D3 can be greater than the length of the first portion GS1 in the third direction D3, and the slope of the sidewall of the second portion GS2 can be greater than the slope of the sidewall SW3 of the lower portion GS11. Therefore, in the third direction D3, the rate of change of the width of the second portion GS2 can be less than the first portion GS1. In addition, the first portion GS1 of the gate structure GS can include two separate portions respectively disposed on two opposite sides of the fin structure FS in the second direction D2, and each of the two separate portions includes the lower portion GS11 and the upper portion GS12 described above.

[0067] Similarly, the semiconductor device 104 can also include the well region 12, the first doped region 14, the isolation structure 15, the channel region 18, the spacer structure 26, the source / drain region 28, the source / drain structure 30, and the dielectric layer 32 as described above. At least a portion of the first doped region 14 can be disposed in the fin structure FS. The second doped region 24 can be disposed in the fin structure FS and above the first doped region 14 in the third direction D3, and the second doped region 24 can have a different and complementary conductivity type from the first doped region 14. The bottom surface BS of the gate structure GS can be lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3. In some embodiments, the second doped region 24 can be directly connected with the first doped region 14, and the first portion GS1 of the gate structure GS can be considered as an enlarged bottom portion of the gate structure GS to reduce the leakage current between the first doped region 14 and the second doped region 24 and the capacitance between the first doped region 14 and the second doped region 24, as the area of the interface between the second doped region 24 and the first doped region 14 is relatively reduced, the second doped region 24 is separated from the first doped region 14 in the third direction D3 by a portion of the channel region 18 covered by the first portion GS1 of the gate structure GS, and / or the impurity concentration in the first doped region 14 can be relatively reduced. In other words, the electrical characteristics of the semiconductor device 104 can be improved by the gate structure GS including the above-mentioned first portion GS1 without forming an intermediate region separating the first doped region 14 and the second doped region 24.

[0068] Figure 37 is a perspective schematic view showing a manufacturing method of the semiconductor device 104 according to the fifth embodiment of the present application, wherein Figure 43 is Figure 44 a subsequent step of Figure 44 is Figure 42 a subsequent step of Figure 45 is Figure 46 a subsequent step of Figure 46 can be considered as Figure 45 a subsequent step of Figure 45 As shown in FIG. 30A, the manufacturing method of the semiconductor device 104 can include the following steps. The fin structure FS is formed on the semiconductor substrate 10, and the fin structure FS extends upward from the top surface 10TS of the semiconductor substrate 10 in a vertical direction (e.g., the third direction D3). The gate structure GS is formed across a portion of the fin structure FS, and the gate structure GS includes the first portion GS1 and the second portion GS2 disposed on the first portion GS1. The width W3 of the first portion GS1 is greater than the width W4 of the second portion GS2.

[0069] Specifically, the method of manufacturing the semiconductor device 104 in this embodiment includes, but is not limited to, the following steps. As shown in Figure 8 The dummy gate DG is formed to span a portion of the fin structure FS. In this embodiment, the dummy gate DG can include a first portion DG1 and a second portion DG2 disposed on the first portion DG1, and a width of the first portion DG1 of the dummy gate DG can be greater than a width of the second portion DG2 of the dummy gate DG. Further, the first portion DG1 of the dummy gate DG can include a lower portion DG11 and an upper portion DG12, and a slope of a sidewall SW5 of the lower portion DG11 can be different from a slope of a sidewall SW6 of the upper portion DG12. In some embodiments, a shape of the dummy gate DG can be substantially the same as a shape of the gate structure described above (e.g., a shape of the gate structure GS shown in Figure 8 In other words, as shown in Figure 45 and Figure 45 A shape and a size of the first portion DG1 of the dummy gate DG can be the same as or similar to a shape and a size of the first portion GS1 of the gate structure GS, and a shape and a size of the second portion DG2 of the dummy gate DG can be the same as or similar to a shape and a size of the second portion GS2 of the gate structure GS. As shown in Figure 46 At least a portion of the first doped region 14 can be located in the fin structure FS, and the second doped region 24 can be formed in the fin structure FS by a doping process 92 after the step of forming the dummy gate DG. The second doped region 24 can be located above the first doped region 14 in the third direction D3, and a conductivity type of the second doped region 24 can be different from and complementary to a conductivity type of the first doped region 14.

[0070] In some embodiments, the method of forming the dummy gate DG including the first portion DG1 and the second portion DG2 described above can include, but is not limited to, the following steps. As shown in Figure 46As shown, a patterned material layer 20P can be formed on a semiconductor substrate after the step of forming the fin structure FS. In some embodiments, the patterned material layer 20P may include a first portion 20A configured to span the fin structure FS and a third portion 20C disposed on the first portion 20A, and a mask layer 22 may be disposed on the third portion 20C of the patterned material layer 20P. Furthermore, dummy spacers DS may be formed on the sidewalls of the third portion 20C and the sidewalls of the mask layer 22, and a patterned mask layer 23 may be formed to cover a portion of the first portion 20A, a portion of the dummy spacers DS, and a portion of the mask layer 22. In some embodiments, the dummy spacers DS may include an insulating material, such as silicon nitride, or other suitable insulating material, and the patterned mask layer 23 may include a photoresist or other suitable mask material. In some embodiments, the material composition of the dummy spacers DS may be the same as or similar to the material composition of the patterned material layer 20P etched in a subsequent etching process, but is not limited thereto. Subsequently, as Figure 46 and Figure 47 As shown, using a patterned mask layer 23 as an etching mask, an etching process can be performed on the patterned material layer 20P, the dummy spacer DS, and the mask layer 22 to remove the exposed portions of the dummy spacer DS, the exposed portions of the mask layer 22, the third portion 20C of the patterned material layer 20P, and a portion of the exposed portion of the first portion 20A of the patterned material layer 20P, and to form a fourth portion 20D in the patterned material layer 20P. The patterned mask layer 23 can be removed after the above etching process. The shape of the fourth portion 20D can be similar to the shape of the exposed portions of the dummy spacer DS and the exposed portions of the mask layer 22 before the etching process, and the etching process can be considered as a process of transferring the shapes of the exposed portions of the dummy spacer DS and the exposed portions of the mask layer 22 into the patterned material layer 20P, but is not limited thereto.

[0071] Subsequently, as Figure 47 and Figure 47 As shown, mask layer 22 can be used as an etching mask to perform another etching process on the patterned material layer 20P, which includes the first portion 20A, the third portion 20C, and the fourth portion 20D. The patterned material layer 20P can be etched into a dummy gate DG including the aforementioned first portion DG1 and second portion DG2. After forming the dummy gate DG, a second doped region 24 can be formed in the fin structure FS, and a portion of the fin structure FS covered by the dummy gate DG can be the aforementioned channel region. ​ and ​As shown, the spacer structure 26 can be formed after the step of forming the second doped region 24, a portion of the second portion 26B of the spacer structure 26 can be etched back to expose the upper portion of the fin structure FS, and the source / drain structure 30 can be formed on the exposed fin structure FS by an epitaxial growth process or other suitable method. In some embodiments, the source / drain structure 30 can be in-situ doped during the process of forming the source / drain structure 30, and the source / drain region 28 can be simultaneously formed by the process, but not limited thereto. Instead of the above in-situ doping process, the source / drain structure 30 and the source / drain region 28 can be doped by an ion implantation process after the formation of the source / drain structure 30. Subsequently, as shown in ​ and ​ the dielectric layer 32 can be formed, and the dummy gate DG can be replaced by the gate structure GS by the RMG process, but not limited thereto.

[0072] It is worth noting that the manufacturing method of the semiconductor device 104 is not limited to the above method, and the manufacturing method of the semiconductor device 104 of the present application can also employ other suitable methods. In addition, in this embodiment, the gate structure GS including the first portion GS1 and the second portion GS2 can also be applied to other embodiments of the present application.

[0073] ​ is a perspective view showing a semiconductor device 105 according to a fifth embodiment of the present application. As shown in ​ In the semiconductor device 105, the gate structure GS includes the first portion GS1 and the second portion GS2, and the second portion GS2 is disposed on and directly connected to the first portion GS1 in the third direction D3. The width W3 of the first portion GS1 of the gate structure GS is greater than the width W4 of the second portion GS2 of the gate structure GS. In some embodiments, the included angle between the sidewall of the first portion GS1 and the bottom surface BS of the gate structure GS can be about 90 degrees, and the gate width can sharply increase from the interface between the second portion GS2 and the first portion GS1 to the first portion GS1. In other words, in the third direction D3, the rate of change of the gate width from the first portion GS1 to the interface between the second portion GS2 and the first portion GS1 can be greater than the second portion GS2. The first portion GS1 of the gate structure GS can be regarded as an enlarged bottom portion of the gate structure GS to reduce the leakage current between the first doped region 14 and the second doped region 24, and the capacitance between the first doped region 14 and the second doped region 24, because the area of the interface between the second doped region 24 and the first doped region 14 is relatively reduced and / or the impurity concentration in the first doped region 14 can be relatively reduced.

[0074] ​is a perspective view showing a manufacturing method of the semiconductor device 105 according to the fifth embodiment of the present application, wherein ​ is ​ a perspective view in a subsequent step of ​ is ​ a perspective view in a subsequent step of ​ is ​ a perspective view in a subsequent step of ​ is ​ a perspective view in a subsequent step of, and ​ may be considered as ​ a cross-sectional view in a subsequent step of. As shown in ​ , the dummy gate DG is formed to span a portion of the fin structure FS. In this embodiment, the dummy gate DG can include a first portion DG1 and a second portion DG2 disposed on the first portion DG1, and a width of the first portion DG1 of the dummy gate DG can be greater than a width of the second portion DG2 of the dummy gate DG. In some embodiments, a shape of the dummy gate DG can be substantially the same as a shape of the above-mentioned gate structure (e.g., a shape of the gate structure GS shown in ​ ). In other words, as shown in ​ and ​ , a shape and a size of the first portion DG1 of the dummy gate DG can be the same or similar to those of the first portion GS1 of the gate structure GS, and a shape and a size of the second portion DG2 of the dummy gate DG can be the same or similar to those of the second portion GS2 of the gate structure GS. As shown in ​ , at least a portion of the first doped region 14 can be located in the fin structure FS, the second doped region 24 can be formed in the fin structure FS by a doping process 92 after the step of forming the dummy gate DG, and a portion of the fin structure FS covered by the dummy gate DG can be the above-mentioned channel region.

[0075] In some embodiments, a method of forming the dummy gate DG including the above-mentioned first portion DG1 and the second portion DG2 can include, but is not limited to, the following steps. As shown in ​As shown, after the step of forming the fin structure FS, a material layer 20 can be formed on the semiconductor substrate and covering the fin structure FS. The material layer 20 can include a silicon-containing material, such as polysilicon, amorphous silicon, or other suitable material. Subsequently, a mask layer 22 can be formed on the material layer 20, and a dummy spacer DS can be formed on the sidewalls of the material layer 20 and the mask layer 22. In some embodiments, the material composition of the dummy spacer DS can be different from the material composition of the mask layer 22 and the material composition of the material layer 20 for etch selectivity involved in subsequent etching steps. For example, in some embodiments, the material of the dummy spacer DS can be silicon nitride, the material of the mask layer 22 can be silicon oxide, and the material layer 20 can be a polysilicon layer, but not limited thereto. In some embodiments, as shown in ​ and ​ the dummy spacer DS and the mask layer 22 can be subjected to an etching process to remove a portion of the dummy spacer DS and a portion of the mask layer 22, and adjust the length of the dummy spacer DS and the mask layer 22 in the second direction D2 and / or the area of the portion of the material layer 20 overlapped by the dummy spacer DS and the mask layer 22 in the third direction D3.

[0076] Subsequently, as shown in ​ and ​ another etching process can be performed on the material layer 20 using the mask layer 22 and the dummy spacer DS as etching masks to form a patterned material layer 20P including a first portion 20A and a third portion 20C. In other words, the material layer 20 can be patterned into the patterned material layer 20P by an etching process using the mask layer 22 and the dummy spacer DS as etching masks. As shown in ​ the dummy spacer DS can be removed after the step of forming the patterned material layer 20P, and an etching process can be performed on the patterned material layer 20P including the first portion 20A and the third portion 20C using the mask layer 22 as an etching mask for forming ​ a dummy gate DG including a first portion DG1 and a second portion DG2 as shown. In some embodiments, the etching process can be regarded as a process of transferring the shape of the third portion 20C to the first portion DG1 of the dummy gate DG, but not limited thereto. After the step of forming the dummy gate DG, a second doped region 24 can be formed in the fin structure FS by performing a doping process 92. As shown in ​ and ​ the spacer structure 26, the source / drain structure 30, the source / drain region 28, and the dielectric layer 32 can be formed after the step of forming the second doped region 24, and the dummy gate DG can be replaced by the gate structure GS by an RMG process to form ​ the semiconductor device 105 as shown.

[0077] Note that the manufacturing method of the semiconductor device 105 is not limited to the above-described method, and the manufacturing method of the semiconductor device 105 of the present application can employ other suitable methods. Further, in this embodiment, the gate structure GS including the first portion GS1 and the second portion GS2 can also be applied to other embodiments of the present application.

[0078] ​ is a cross-sectional schematic view illustrating a semiconductor device 106 according to a sixth embodiment of the present application. As shown in ​ , in the semiconductor device 106, the gate structure GS can include the first portion GS1 and the second portion GS2, and the first portion GS1 can include the lower portion GS11 and the upper portion GS12 described above. In other words, in this embodiment, the gate structure GS can be the same as or at least similar to the gate structure GS shown in ​ . Further, the semiconductor device 106 can also include an intermediate region 16 disposed in the fin structure FS, and the second doped region 24 can be separated from the first doped region 14 by the intermediate region 16. The intermediate region 16 can have the same conductivity type as the first doped region 14, and the impurity concentration in the first doped region 14 can be higher than the impurity concentration in the intermediate region 16. The bottom surface BS of the gate structure GS can be lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3, and a portion of the intermediate region 16 located in the channel region 18 and a portion of the intermediate region 16 located between the second doped region 24 and the first doped region 14 can be covered by the gate structure GS in the second direction D2. In some embodiments, the shape of the intermediate region 16 is affected by the process of forming the gate structure GS, and the shape of the upper portion of the intermediate region 16 can be similar to the shape of the first portion GS1 of the gate structure GS, but is not limited thereto. Thus, the top surface 16TS of the intermediate region 16 (e.g., the topmost surface of the intermediate region 16) can be higher than the bottom surface 24BS of the second doped region 24 (e.g., the bottommost surface of the second doped region 24) in the third direction D3.

[0079] In this embodiment, the intermediate region 16 having a relatively low impurity concentration disposed between the first doped region 14 and the second doped region 24 can be used to reduce the leakage current between the first doped region 14 and the second doped region 24 and / or the capacitance between the first doped region 14 and the second doped region 24. In addition, the first portion GS1 of the gate structure GS can be regarded as an enlarged bottom portion of the gate structure GS to reduce the leakage current between the first doped region 14 and the second doped region 24 and the capacitance between the first doped region 14 and the second doped region 24, as the distance of a portion of the second doped region 24 from the first doped region 14 in the third direction D3 is increased by the upper portion of the intermediate region 16, a portion of the intermediate region 16 located between the channel region 18 and the first doped region 14 and a portion of the intermediate region 16 located between the second doped region 24 and the first doped region 14 are covered by the gate structure GS in the second direction D2, and / or the impurity concentration in the first doped region 14 can be relatively reduced. In other words, the electrical characteristics of the semiconductor device 106 can be improved by the above-mentioned gate structure GS including the first portion GS1 and the second portion GS2 and the intermediate region 16 separating the first doped region 14 and the second doped region 24.

[0080] ​ and ​ is a perspective view showing a manufacturing method of the semiconductor device 105 according to the sixth embodiment of the present application, wherein ​ is ​ is a perspective view in a subsequent step of ​ may be regarded as ​ is a cross-sectional view in a subsequent step of ​ As shown in FIG. 20B, the patterned material layer 20P can include a first portion 20A, a second portion 20B, and a fifth portion 20E located between the first portion 20A and the second portion 20B in the third direction D3. The first portion 20A can be disposed to span the fin structure FS, and the second portion 20B can cover a portion of the sidewall SW1 of the fin structure FS. In some embodiments, the shape of the fifth portion 20E can be similar to the shape of the first portion DG1 shown in FIG. 19B, and the method of forming the patterned material layer 20P including the first portion 20A, the second portion 20B, and the fifth portion 20E can be similar to the method shown in FIG. 19C, but is not limited thereto. Subsequently, the second doped region 24 can be formed in the fin structure FS, and the intermediate region 16 in the fin structure FS can be covered by the patterned material layer 20P in the second direction D2. As shown in FIG. 20C, the semiconductor device 105 according to the sixth embodiment of the present application can include the first doped region 14, the second doped region 24, the channel region 18, and the gate structure GS. ​ ​ ​ and ​ ​​As shown, after the step of forming the second doped region 24, an etching process can be performed on the patterned material layer 20P, the patterned material layer 20P can be etched into a dummy gate DG including a first portion DG1 and a second portion DG2 by the etching process, and at least a portion of the second portion 20B of the patterned material layer 20P can be removed by the etching process. The dummy gate DG can cover a portion of the side surface of the first doped region 14 in the second direction D2, the dummy gate DG can include the first portion DG1 and the second portion DG2 disposed on the first portion DG1, and a width of the first portion DG1 of the dummy gate DG can be greater than a width of the second portion DG2 of the dummy gate DG. In addition, the first portion DG1 of the dummy gate DG can include a lower portion DG11 and an upper portion DG12, and a slope of the sidewall SW5 of the lower portion DG11 can be different from a slope of the sidewall SW6 of the upper portion DG12. In some embodiments, in this embodiment, the second doped region 24 can be formed after the step of forming the patterned material layer 20P, and before the step of forming the dummy gate DG and the step of removing at least a portion of the second portion 20B of the patterned material layer 20P. As ​ and ​ As shown, the spacer structure 26, the source / drain structure 30, the source / drain region 28 and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced with the gate structure GS by the RMG process to form the semiconductor device 106.

[0081] It is worth noting that the manufacturing method of the semiconductor device 106 is not limited to the above method, and the manufacturing method of the semiconductor device 106 of the present application can also employ other suitable methods.

[0082] ​ is a cross-sectional schematic view showing a semiconductor device 107 according to a seventh embodiment of the present application. As shown, ​ In the semiconductor device 107, the gate structure GS can include a first portion GS1 and a second portion GS2, and in this embodiment, the gate structure GS can be similar to the above-described ​The gate structure GS shown is the same as or at least similar to the gate structure GS. Furthermore, the semiconductor device 107 may also include an intermediate region 16 disposed in the fin structure FS, and the second doped region 24 may be separated from the first doped region 14 by the intermediate region 16. The conductivity type of the intermediate region 16 may be the same as that of the first doped region 14, and the impurity concentration in the first doped region 14 may be higher than the impurity concentration in the intermediate region 16. The bottom surface BS of the gate structure GS is lower than or coplanar with the top surface 14TS of the first doped region 14 in the third direction D3, and a portion of the intermediate region 16 located between the channel region 18 and the first doped region 14, and a portion of the intermediate region 16 located between the second doped region 24 and the first doped region 14, may be covered by the gate structure GS in the second direction D2. In some embodiments, the shape of the intermediate region 16 is influenced by the process of forming the gate structure GS, and the shape of the upper part of the intermediate region 16 may be similar to, but not limited to, the shape of the first portion GS1 of the gate structure GS. Therefore, the top surface 16TS of the intermediate region 16 (e.g., the topmost surface of the intermediate region 16) can be higher than the bottom surface 24BS of the second doped region 24 (e.g., the bottommost surface of the second doped region 24) in the third direction D3. The width W3 of the first portion GS1 of the gate structure GS is greater than the width W4 of the second portion GS2 of the gate structure GS, and the gate width can increase sharply from the interface between the second portion GS2 and the first portion GS1 to the first portion GS1. The electrical characteristics of the semiconductor device 107 can be improved by the gate structure GS including the first portion GS1 and the second portion GS2, and the intermediate region 16 separating the first doped region 14 and the second doped region 24 as described above.

[0083] ​ and ​ This is a perspective schematic diagram illustrating a method for manufacturing a semiconductor device 107 according to a seventh embodiment of the present invention, wherein... ​ yes ​ The three-dimensional diagram in the subsequent steps, and ​ It can be regarded as ​ A cross-sectional diagram in subsequent steps. For example... ​ As shown, the patterned material layer 20P may include a first portion 20A, a second portion 20B, and a fifth portion 20E located on a third direction D3 between the first portion 20A and the second portion 20B. In some embodiments, the shape of the fifth portion 20E may be similar to that described above. ​ The shape of the first portion DG1 of the dummy gate DG shown, and the method for forming the patterned material layer 20P including the first portion 20A, the second portion 20B, and the fifth portion 20E, can be similar to that described above. ​The method shown in FIG. 6 is not limited thereto. Subsequently, the second doped region 24 can be formed in the fin structure FS, and the middle region 16 in the fin structure FS can be covered by the patterned material layer 20P in the second direction D2. As shown in FIG. 7, the patterned material layer 20P can be etched by an etching process after the step of forming the second doped region 24, and the patterned material layer 20P can be etched to a dummy gate DG including a first portion DG1 and a second portion DG2 by the etching process. Thus, in this embodiment, the second doped region 24 can be formed after the step of forming the patterned material layer 20P and before the step of forming the dummy gate DG. As shown in FIG. 8, the spacer structure 26, the source / drain structure 30, the source / drain region 28 and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced by a gate structure GS by an RMG process to form the semiconductor device 107. ​ and ​ As shown in FIG. 7, the patterned material layer 20P can be etched by an etching process after the step of forming the second doped region 24, and the patterned material layer 20P can be etched to a dummy gate DG including a first portion DG1 and a second portion DG2 by the etching process. Thus, in this embodiment, the second doped region 24 can be formed after the step of forming the patterned material layer 20P and before the step of forming the dummy gate DG. As shown in FIG. 8, the spacer structure 26, the source / drain structure 30, the source / drain region 28 and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced by a gate structure GS by an RMG process to form the semiconductor device 107. ​ and ​ As shown in FIG. 8, the spacer structure 26, the source / drain structure 30, the source / drain region 28 and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced by a gate structure GS by an RMG process to form the semiconductor device 107.

[0084] It is noted that the method of manufacturing the semiconductor device 107 is not limited to the above method, and other suitable methods can also be employed for the method of manufacturing the semiconductor device 107 according to the present application.

[0085] In addition, ​ may be considered as showing a cross-sectional schematic view of a semiconductor device according to another embodiment of the present application, ​ may be considered as showing a cross-sectional schematic view of the source / drain structure 30 in this embodiment, and ​ may be considered as showing a cross-sectional schematic view of the gate structure GS in this semiconductor device. As shown in FIG. 6, ​ , ​ and ​ As shown in FIG. 6, the fin structure FS can include the first portion P1, the second portion P2 and the third portion P3 as described above. The width W1 of the first portion P1 can be greater than the width W2 of the second portion P2, and the sidewall SW2 of the third portion P3 can be tapered to increase the area of the fin structure FS covered by the gate structure GS including the first portion GS1 and the second portion GS2 as shown in FIG. 7. ​ As shown in FIG. 6, the fin structure FS can include the first portion P1, the second portion P2 and the third portion P3 as described above. The width W1 of the first portion P1 can be greater than the width W2 of the second portion P2, and the sidewall SW2 of the third portion P3 can be tapered to increase the area of the fin structure FS covered by the gate structure GS including the first portion GS1 and the second portion GS2 as shown in FIG. 7.

[0086] In addition, ​ may be considered as showing a cross-sectional schematic view of a semiconductor device according to another embodiment of the present application, ​ may be considered as showing a cross-sectional schematic view of the source / drain structure 30 in this embodiment, and ​ may be considered as showing a cross-sectional schematic view of the gate structure GS in this semiconductor device. As shown in FIG. 6, ​ , ​ and ​As shown, the fin-shaped structure FS can include the first portion PI, the second portion P2, and the third portion P3 described above. The width Wl of the first portion PI can be greater than the width W2 of the second portion P2, and the sidewall SW2 of the third portion P3 can be tapered to increase the area of the fin-shaped structure FS covered by the gate structure GS including the first portion GS1 and the second portion GS2 shown in ​ .

[0087] ​ is a cross-sectional schematic view showing a semiconductor device 108 according to an eighth embodiment of the present application. As shown in ​ , in the semiconductor device 108, the bottom surface BS of the gate structure GS can be lower than the top surface 14TS of the first doped region 14 in the third direction D3, and the gate structure GS can cover a portion of the side surface of the intermediate region 16 and a portion of the side surface of the first doped region 14 in the second direction D2 to ensure that the intermediate region 16 between the channel region 18 and the first doped region 14 in the third direction D3 is covered by the gate structure GS in the second direction D2. In some embodiments, a portion of the side surface of the first doped region 14 can be covered by the first portion GS1 of the gate structure GS in the second direction D2, and a portion of the side surface of the intermediate region 16 can be covered by the second portion GS2 of the gate structure GS in the second direction D2, but not limited thereto. The electrical characteristics of the semiconductor device 108 can be improved by the gate structure GS including the first portion GS1 and the second portion GS2 described above and the intermediate region 16 separating the first doped region 14 and the second doped region 24.

[0088] ​ and ​ is a perspective schematic view showing a method of manufacturing the semiconductor device 108 according to the eighth embodiment of the present application, in which ​ is ​ a subsequent step of ​ may be considered as ​ a cross-sectional schematic view in a subsequent step of ​ , after the step of forming the isolation structure 15, the top surface 15TS of the isolation structure 15 can be lower than the top surface of the first doped region 14 in the fin-shaped structure FS. In this embodiment, the shape of the patterned material layer 20P including the first portion 20A, the second portion 20B, and the fifth portion 20E can be similar to the patterned material layer 20P shown in ​ described above, but in this embodiment, the second portion 20B can be relatively thick to cover a portion of the side surface of the first doped region 14 and the side surface of the intermediate region 16 in the second direction D2 during the doping process 92 of forming the second doped region 24. As ​ and ​As shown, after the step of forming the second doped region 24, an etching process can be performed on the patterned material layer 20P, and the patterned material layer 20P can be etched into a dummy gate DG including a first portion DG1 and a second portion DG2 by the etching process. As ​ and ​ As shown, the spacer structure 26, the source / drain structure 30, the source / drain region 28, and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced with the gate structure GS by the RMG process to form the semiconductor device 108.

[0089] It is worth noting that the manufacturing method of the semiconductor device 108 is not limited to the above method, and other suitable methods can also be used for the manufacturing method of the semiconductor device 108 of the present application.

[0090] ​ is a cross-sectional schematic view showing a semiconductor device 109 according to a ninth embodiment of the present application. As shown, ​ In the semiconductor device 109, the bottom surface BS of the gate structure GS can be lower than the top surface 14TS of the first doped region 14 in the third direction D3, and the gate structure GS can cover a portion of the side surface of the intermediate region 16 and a portion of the side surface of the first doped region 14 in the second direction D2 to ensure that the intermediate region 16 between the channel region 18 and the first doped region 14 in the third direction D3 is covered by the gate structure GS in the second direction D2. In some embodiments, a portion of the side surface of the first doped region 14 can be covered by the first portion GS1 of the gate structure GS in the second direction D2, and a portion of the side surface of the intermediate region 16 can be covered by the second portion GS2 of the gate structure GS in the second direction D2, but not limited thereto. The width W3 of the first portion GS1 of the gate structure GS is greater than the width W4 of the second portion GS2 of the gate structure GS, and the gate width can increase sharply from the interface between the second portion GS2 and the first portion GS1 to the first portion GS1. The electrical properties of the semiconductor device 109 can be improved by the above-mentioned gate structure GS including the first portion GS1 and the second portion GS2 and the intermediate region 16 separating the first doped region 14 and the second doped region 24.

[0091] ​ and ​ is a perspective schematic view showing a manufacturing method of the semiconductor device 109 according to the ninth embodiment of the present application, wherein ​ is ​ a subsequent step of ​ may be regarded as ​ a cross-sectional schematic view in a subsequent step of ​As shown, after the step of forming the isolation structure 15, the top surface 15TS of the isolation structure 15 can be lower than the top surface of the first doped region 14 in the fin structure FS. In this embodiment, the shape of the patterned material layer 20P, including the first portion 20A, the second portion 20B, and the fifth portion 20E, can be similar to that described above. ​ The patterned material layer 20P shown is illustrated, but in this embodiment, the second portion 20B can be relatively thick to cover a portion of the side surface of the intermediate region 16 and the side surface of the first doped region 14 in the second direction D2 during the doping process 92 that forms the second doped region 24. ​ and ​ As shown, after the step of forming the second doped region 24, the patterned material layer 20P can be etched, and the patterned material layer 20P can be etched into a dummy gate DG including a first portion DG1 and a second portion DG2. ​ and ​ As shown, the spacer structure 26, the source / drain structure 30, the source / drain region 28, and the dielectric layer 32 can be formed after the step of forming the dummy gate DG, and the dummy gate DG can then be replaced by the gate structure GS through the RMG process to form the semiconductor device 109.

[0092] It is worth noting that the manufacturing method of the semiconductor device 109 is not limited to the above method, and other suitable methods may also be used in the manufacturing method of the semiconductor device 109 of the present invention.

[0093] ​ and ​ This is a perspective schematic diagram illustrating a method for manufacturing a semiconductor device according to a tenth embodiment of the present invention, wherein... ​ yes ​ The three-dimensional diagram in the subsequent steps, and ​ It can be regarded as ​ A three-dimensional diagram for subsequent steps. For example... ​ and ​ As shown, in some embodiments, after the step of etching back the second portion 26B of the spacer structure 26 and exposing the upper portion of the fin structure FS, the exposed portion of the fin structure FS (e.g., the upper portion of the second doped region 24) can be removed by etching process 93. Subsequently, as ​ and ​ As shown, the source / drain structure 30 can be formed on the fin structure FS by epitaxial growth or other suitable methods. It is worth noting that the method of removing a portion of the fin structure FS before forming the source / drain structure 30 can also be applied to other embodiments of the invention (e.g., the embodiments described above). The etching process 93 can include a dry etching process or a wet etching process. ​In the illustrated structure, the source / drain structure 30 can laterally push or pull the channel region 18. Therefore, removing a portion of the fin structure FS before the step of forming the source / drain structure 30 can increase the source / drain current of a fin field effect transistor (fin-FET) because the lateral stress of the channel region 18 can be increased. In addition, in ​ In the illustrated structure, the source / drain structure 30 having a heavy impurity concentration is disposed closer to the bottom surface of the second doped region 24 than in other embodiments. Therefore, the impurities of the source / drain structure 30 can diffuse downward beyond the bottom surface of the second doped region 24 in the third direction D3. Even in this case, the advantages of other embodiments of the present application are still valid if the portion of the second doped region 24 covered by the first portion 26A of the spacer structure 26 is separated from the first doped region 14.

[0094] ​ is a perspective view illustrating a manufacturing method of a semiconductor device according to an eleventh embodiment of the present application. As illustrated in ​ As illustrated, the fin structure FS can include a plurality of first layers 11A and a plurality of second layers 11B alternately stacked in the third direction D3. The material composition of each first layer 11A can be different from that of each second layer 11B. For example, the first layers 11A can be silicon layers, and the second layers 11B can be silicon germanium layers, but are not limited thereto. In some embodiments, a dummy gate DG can be formed across the fin structure FS including the alternately stacked first layers 11A and second layers 11B, and the above-mentioned second doped region and / or source / drain region can be formed in the first layers 11A and / or second layers 11B of the fin structure FS, but are not limited thereto. In some embodiments, the portion of the second layers 11B covered by the dummy gate DG can be removed after the above-mentioned step of forming the dummy gate DG and before the step of forming the gate structure, and the gate structure can surround a portion of each first layer 11A to form a gate-all-around (GAA) transistor, but are not limited thereto. Notably, the fin structure FS including the alternately stacked first layers 11A and second layers 11B can also be applied in other embodiments of the present application (e.g., the above-mentioned embodiments). In the gate-all-around transistor (GAA), the short channel effect (SCE) can be suppressed because the channel composed of the first layers 11A is surrounded by the gate structure. In addition, the gate-all-around transistor (GAA) can have a higher current density than the planar transistor because the channel is surrounded by the gate structure. ​ In the illustrated structure, the top surface 14TS of the first doped region 14 is disposed higher than or coplanar with the top surface 15TS of the isolation structure 15. Therefore, if the structure explained in the embodiments of the present application is not applied, the second doped region 24 would be formed in the top portion of the first doped region 14 and would increase the leakage current and / or the capacitance. Therefore, the advantages of other embodiments of the present application are still valid even in the case of the gate-all-around transistor (GAA).

[0095] In view of the above, according to the semiconductor device and the manufacturing method thereof of the present application, the leakage current and / or the capacitance between the first doped region and the second doped region within the fin structure can be reduced by separating the first doped region from the second doped region, modifying the area of the fin structure covered by the gate structure across the fin structure, and / or enlarging the bottom portion of the gate structure to improve the electrical characteristics of the semiconductor device.

[0096] Those skilled in the art will readily observe that numerous modifications and changes can be made to the embodiments of the present application without departing from the scope and spirit of the application. Accordingly, the disclosures and descriptions herein are intended to be illustrative only and are not in limitation of the scope of the application as defined by the following claims.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A fin-like structure is disposed on the top surface of the semiconductor substrate and extends vertically upward from the top surface of the semiconductor substrate; A gate structure is configured to span a portion of the fin structure; Source / drain regions and channel regions are disposed in the fin structure, wherein the gate structure covers the channel region; A first doped region, wherein at least a portion of the first doped region is disposed in the fin structure; A second doped region is disposed in the fin structure and positioned above the first doped region in the vertical direction; as well as An intermediate region is disposed in the fin structure, wherein the second doped region is separated from the first doped region through the intermediate region, and the bottom surface of the gate structure is lower than or coplanar with the top surface of the first doped region in the vertical direction. The second doped region and the source / drain region are located on the same side of the channel region. A first portion of the second doped region is located directly below the source / drain region in the vertical direction, and a second portion of the second doped region is located between the source / drain region and the channel region.

2. The semiconductor device of claim 1, wherein, The conductivity type of the second doped region is complementary to that of the first doped region.

3. The semiconductor device as claimed in claim 2, wherein, The conductivity type of the intermediate region is the same as that of the first doped region, and the impurity concentration in the first doped region is higher than that in the intermediate region.

4. The semiconductor device of claim 1, wherein, The gate structure covers a portion of the side surface of the intermediate region in the horizontal direction.

5. The semiconductor device of claim 4, wherein, The gate structure also covers a portion of the side surface of the first doped region in the horizontal direction.

6. The semiconductor device of claim 1, further comprising: An isolation structure is disposed on the semiconductor substrate and surrounding the fin structure, wherein a portion of the gate structure is disposed on the isolation structure, and the top surface of the isolation structure is lower than or coplanar with the top surface of the first doped region in the vertical direction.

7. The semiconductor device of claim 1, wherein the fin structure comprises: Part One; The second part is disposed on the first part in the vertical direction, wherein the width of the first part is greater than the width of the second part; as well as The third part is disposed between the first part and the second part in the vertical direction, wherein the sidewalls of the third part are tapered, and at least a portion of the intermediate region is disposed in the third part.

8. The semiconductor device of claim 1, wherein the gate structure comprises: Part One; as well as The second part is disposed on the first part, wherein the width of the first part of the gate structure is greater than the width of the second part of the gate structure.

9. The semiconductor device of claim 8, wherein the first portion of the gate structure comprises: lower part; as well as The upper part, wherein the slope of the sidewall of the lower part is different from the slope of the sidewall of the upper part.

10. The semiconductor device of claim 9, wherein, The angle between the upper sidewall and the horizontal plane parallel to the top surface of the semiconductor substrate is less than 45 degrees.

11. The semiconductor device of claim 8, wherein, The width of the first portion of the gate structure gradually changes in the vertical direction.

12. A semiconductor device, comprising: Semiconductor substrate; A fin-like structure is disposed on the top surface of the semiconductor substrate and extends vertically upward from the top surface of the semiconductor substrate; A gate structure, configured to span a portion of the fin structure, wherein the gate structure comprises: Part One; and The second part is disposed on the first part, wherein the width of the first part of the gate structure is greater than the width of the second part of the gate structure; Source / drain regions and channel regions are disposed in the fin structure, wherein the gate structure covers the channel region; A first doped region, wherein at least a portion of the first doped region is disposed within the fin structure; and A second doped region is disposed in the fin structure and positioned above the first doped region in the vertical direction, wherein the second doped region and the source / drain region are located on the same side of the channel region, a first portion of the second doped region is located directly below the source / drain region in the vertical direction, and a second portion of the second doped region is located between the source / drain region and the channel region.

13. The semiconductor device of claim 12, wherein the first portion of the gate structure comprises: lower part; as well as The slope of the lower sidewall of the upper part is different from that of the upper sidewall.

14. The semiconductor device of claim 13, wherein, The angle between the upper sidewall and the horizontal plane parallel to the top surface of the semiconductor substrate is less than 45 degrees.

15. The semiconductor device of claim 12, wherein, The width of the first portion of the gate structure gradually changes in the vertical direction.

16. The semiconductor device of claim 12, wherein the conductivity type of the second doped region is complementary to the conductivity type of the first doped region.

17. The semiconductor device of claim 16, wherein, The bottom surface of the gate structure is lower than or coplanar with the top surface of the first doped region in the vertical direction.

18. The semiconductor device of claim 16, further comprising: An intermediate region is disposed in the fin structure, wherein the second doped region is separated from the first doped region through the intermediate region, the conductivity type of the intermediate region is the same as that of the first doped region, and the impurity concentration in the first doped region is higher than that in the intermediate region.

19. The semiconductor device of claim 18, wherein, The gate structure covers a portion of the side surface of the intermediate region and a portion of the side surface of the first doped region in the horizontal direction.

20. The semiconductor device of claim 18, wherein, The top surface of the intermediate region is higher than the bottom surface of the second doped region in the vertical direction.

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