Lateral Schottky Barrier Diode with a Hybrid P-Type Material Ohmic Cathode

Abstract

The present invention discloses a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode, comprising: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer stacked in sequence from bottom to top; wherein, a P-type cathode island structure is provided at the upper right of the cap layer; a cathode groove and an anode groove are respectively provided on the right side of the P-type cathode island structure and the left side of the device; a cathode electrode is provided on the channel layer in the cathode groove, and a cathode plate is provided on the upper surface of the P-type cathode island structure, and the cathode plate is connected to the cathode electrode to form a hybrid P-type material ohmic cathode; an anode electrode is provided on the channel layer in the anode groove; on the upper surface of the cap layer, an anode field plate connected to the anode electrode is provided within a certain length range near the groove anode; a passivation layer is covered on the cap layer between the anode field plate and the P-type cathode island. The diode provided by the present invention has a significant effect on suppressing current collapse and improves the dynamic on-resistance degradation phenomenon of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode. Background Art

[0002] With the development of semiconductor technology, gallium nitride (GaN), as a typical representative of the third-generation wide-bandgap semiconductor material, has a bandgap width of 3.4 eV and a breakdown field strength of 3.3 MV / cm. In the heterojunction structure formed by it and AlGaN, the mobility of two-dimensional electron gas (2DEG) is greater than 2000 cm 2 / V·s, and the carrier surface density can reach 10 13 order of magnitude. Therefore, it is particularly suitable for applications in high-frequency, high-voltage, high-power, and high-temperature environments, and is increasingly valued in application fields such as military, radio, radar, satellite, and power line transmission.

[0003] Schottky barrier diodes (SBDs) have attracted great attention and are widely used due to their low conduction voltage drop and extremely short reverse recovery time, which improve the efficiency of circuit systems. At present, GaN-based Schottky diodes are key unit devices in microwave rectifier circuits, determining the conversion efficiency between RF-DC signals. Because of their excellent channel conduction characteristics, they have the characteristics of low on-resistance and low junction capacitance, meeting the requirements for devices to operate at high frequencies.

[0004] However, in traditional AlGaN / GaN lateral Schottky diodes, since the conduction path is close to the device surface, under high-voltage conditions, the surface states have a non-negligible impact on the device. Before reaching the critical breakdown electric field of the GaN material, the high-field effect will cause electrons near the electrode to tunnel into the surface passivation layer by field emission. These tunneling electrons will neutralize the surface polarization positive charges in the AlGaN layer, and these surface polarization positive charges are directly related to the concentration of 2DEG at the heterojunction interface. The partial neutralization of surface positive charges will reduce the high-density 2DEG concentration, thereby significantly reducing the output current of the lateral AlGaN / GaN Schottky diode. This is the current collapse effect. These defects seriously affect the working performance and reliability of the device, especially when the device is in a high-temperature and high-voltage working state for a long time. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] On the one hand, the present invention provides a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode, comprising: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer, which are sequentially stacked from bottom to top; wherein,

[0007] A P-type cathode island structure is provided above the right upper part of the cap layer;

[0008] A cathode groove and an anode groove are respectively provided on the right side of the P-type cathode island structure and the left side of the device. Both the cathode groove and the anode groove start from the upper surface of the cap layer and extend downward into the channel layer;

[0009] A cathode electrode is provided on the channel layer in the cathode groove, and a cathode plate is provided on the upper surface of the P-type cathode island structure. The cathode plate is connected to the cathode electrode to form a hybrid P-type material ohmic cathode;

[0010] An anode electrode is provided on the channel layer in the anode groove; on the upper surface of the cap layer, an anode field plate connected to the anode electrode is provided within a certain length range near the anode groove;

[0011] A passivation layer is covered on the cap layer between the anode field plate and the P-type cathode island.

[0012] In an embodiment of the present invention, an insertion layer is further provided between the channel layer and the barrier layer.

[0013] In an embodiment of the present invention, the material of the insertion layer is AlN, and the thickness is 0.5 - 2 nm.

[0014] In an embodiment of the present invention, the material of the P-type cathode island structure is Mg-doped GaN or P-type NiO, SnO material, and its thickness is greater than or equal to 10 nm.

[0015] In an embodiment of the present invention, the length of the P-type cathode island structure is 2 μm - 4 μm.

[0016] In an embodiment of the present invention, the channel layer and the cathode electrode are in ohmic contact, and the contact surfaces between the channel layer and the anode electrode are all Schottky contacts.

[0017] In an embodiment of the present invention, the distance from the bottom of the cathode groove to the upper surface of the channel layer is 10 - 40 nm.

[0018] On the other hand, the present invention also provides a preparation method for a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode, comprising:

[0019] Based on the substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a cap layer, and a P-type layer are sequentially deposited and stacked from bottom to top;

[0020] The P-type layer is etched completely to form an independent P-type material block, referred to as a P-type cathode island structure;

[0021] The cap layer, the barrier layer, and the channel layer are etched in sequence to form a cathode groove;

[0022] Cathode metal is deposited in the cathode groove and on the upper surface of the P-type cathode island respectively to form a mutually connected cathode electrode and a cathode plate, thereby forming a hybrid P-type material ohmic cathode;

[0023] The epitaxial wafer is etched to form an anode groove, and anode metal is deposited in the anode groove and on a part of the upper surface of the cap layer to form a mutually connected anode electrode and an anode field plate;

[0024] A passivation layer is deposited on the entire device surface, and photolithography and etching are performed on the passivation layer on the cathode electrode and the cathode plate to form a cathode contact hole, and photolithography and etching are performed on the passivation layer on the anode electrode and the anode field plate to form an anode contact hole, so as to complete the preparation of the device.

[0025] In an embodiment of the present invention, after depositing the channel layer and before depositing the barrier layer, it further includes:

[0026] An insertion layer is deposited on the channel layer.

[0027] In an embodiment of the present invention, cathode metal is deposited in the cathode groove and on the upper surface of the P-type cathode island respectively to form a mutually connected cathode electrode and a cathode plate, including:

[0028] A mask is fabricated on the cathode groove and the P-type cathode island structure;

[0029] The epitaxial wafer with the mask fabricated is placed in a magnetron sputtering reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 - 2 Pa;

[0030] Ti / Al, Ti / Al / Ni / Au or Ti / Al / Mo / Au metal is deposited in the mask and annealed at a high temperature of 870 °C in a nitrogen atmosphere to form a mutually connected cathode electrode and a cathode plate.

[0031] Advantages of the present invention:

[0032] 1. The lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by the present invention uses a hybrid P-type material ohmic cathode. Through the hole injection phenomenon in the P-type material under high voltage, the trapped electrons at the cathode edge are neutralized, which has a significant effect on suppressing current collapse. The dynamic on-resistance degradation phenomenon of the device has been significantly improved compared with the traditional lateral AlGaN / GaN Schottky diode, thereby improving the performance and reliability of the device;

[0033] 2. The present invention also increases the conduction band discontinuity at the heterojunction interface by using an AlN insertion layer, improves the confinement of 2DEG in the potential well, enhances the polarization effect, and increases the 2DEG surface density; and effectively separates the 2DEG wave function and the barrier layer in space, inhibits the penetration of the 2DEG wave function into the barrier layer, thereby reducing alloy disorder scattering and enhancing electron lateral transport; at the same time, a flat and smooth interface is formed to reduce interface roughness scattering, further improving the performance of the device.

[0034] The present invention will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a cross-sectional structure diagram of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention;

[0036] Figure 2 is a flowchart of a preparation method of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention;

[0037] Figures 3a to 3o is a schematic diagram of the preparation process of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0039] It should be noted that the "upper", "lower", "left", and "right" mentioned in this embodiment are the positional relationships of the Schottky diode structure in the illustrated state, the "length" is the lateral dimension of the Schottky diode in the illustrated state, and the "depth" is the longitudinal dimension of the Schottky diode in the illustrated state.

[0040] Embodiment 1

[0041] Please refer to Figure 1 , Figure 1It is a cross-sectional structure diagram of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention, which includes: a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 6, and a cap layer 7 stacked in sequence from bottom to top; wherein,

[0042] A P-type cathode island structure 8 is provided in the upper right of the cap layer 7;

[0043] A cathode groove and an anode groove are respectively provided on the right side of the P-type cathode island structure 8 and the left side of the device. The cathode groove and the anode groove both start from the upper surface of the cap layer 7 and extend downward into the channel layer 4;

[0044] A cathode electrode 9 is provided on the channel layer 4 in the cathode groove, and a cathode plate 10 is provided on the upper surface of the P-type cathode island structure 8. The cathode plate 10 is connected to the cathode electrode 9 to form a hybrid P-type material ohmic cathode;

[0045] An anode electrode 11 is provided on the channel layer 4 in the anode groove; on the upper surface of the cap layer 7, an anode field plate 12 connected to the anode electrode 11 is provided within a certain length range near the anode groove 11;

[0046] A passivation layer 13 is covered on the cap layer 7 between the anode field plate 12 and the P-type cathode island 8.

[0047] In this embodiment, the material of the substrate 1 can be sapphire, Si, SiC or GaN; the material of the nucleation layer 2 is AlN or GaN, and its thickness is 30 - 90 nm; the material of the buffer layer 3 is GaN, and its thickness is 0.5 - 5 μm; the material of the channel layer 4 is GaN, and its thickness is 100 - 300 nm; the material of the barrier layer 6 is AlGaN, and its thickness is 10 - 30 nm, wherein the Al component is 0.15 - 0.3; the material of the cap layer 7 is GaN, and its thickness is 1 - 5 nm; the material of the passivation layer 13 is SiO2, Al2O3 or HfO2, and its thickness is preferably 20 nm.

[0048] In another embodiment of the present invention, an insertion layer 5 is further provided between the channel layer 4 and the barrier layer 6, as Figure 1 shown. Among them, the material of the insertion layer 5 is AlN, and its thickness is 0.5 - 2 nm.

[0049] In this embodiment, the adoption of the AlN insertion layer can increase the conduction band discontinuity at the heterojunction interface, improve the confinement of 2DEG in the potential well, enhance the polarization effect, and increase the 2DEG surface density; and effectively separate the 2DEG wave function and the barrier layer in space, inhibit the penetration of the 2DEG wave function into the barrier layer, thereby reducing alloy disorder scattering and enhancing electron lateral transport; at the same time, form a flat and smooth interface, reduce interface roughness scattering, and thus improve the performance of the device.

[0050] Furthermore, the material of the P-type cathode island structure 8 is Mg-doped GaN or P-type NiO, SnO material, and its thickness is greater than or equal to 10 nm, and its length is 2 μm to 4 μm.

[0051] In this embodiment, the depth from the bottom of the anode groove to the upper surface of the channel layer 4 is 10 to 40 nm; the length of the anode field plate 12 on the upper surface of the cap layer 7 is 1 μm to 4 μm; the materials of the anode electrode 11 and the anode field plate 12 are Ni / Au / Ni, Ni / Au, W / Au or Mo / Au, and the thicknesses of the anode electrode 11 and the anode field plate 12 are related to the materials used. Correspondingly, the depth from the bottom of the cathode groove to the upper surface of the channel layer 4 is 10 to 40 nm; the length of the cathode plate 10 on the upper surface of the P-type cathode island structure 8 is equal to the length of the P-type cathode island structure 8 and is connected to the cathode electrode 9, and the materials of the cathode electrode 9 and the cathode plate 10 are Ti / Al, Ti / Al / Ni / Au or Ti / Al / Mo / Au. It should be noted that the thicknesses of the cathode electrode 9 and the cathode plate 10 are related to the materials used.

[0052] Furthermore, the channel layer 4 and the cathode electrode 9 are in ohmic contact, and the contact surfaces between the channel layer 4 and the anode electrode 11 are all Schottky contacts. When the device is in the on state: a positive bias is applied to the Schottky anode, the cathode is grounded, and the depletion region formed by the P-type island in the barrier layer will not affect the concentration of the 2DEG below it, so it will not affect the forward conduction characteristics of the device. When the device is in the off state: a negative voltage is applied to the Schottky anode, the cathode is grounded, and the cathode end is at a relatively high potential, causing the P-Cathode to emit holes, suppressing the traps in the buffer layer or the channel on the cathode side, and suppressing current collapse.

[0053] It should be noted that the anode groove and the cathode groove in this embodiment can be located at both ends of the device, as Figure 1 shown, or can have a certain distance from both ends of the device. In this regard, this embodiment does not make specific limitations.

[0054] In this embodiment, by adopting a hybrid P-type material ohmic cathode, through the hole injection phenomenon in the P-type material under high voltage, the trap electrons at the cathode edge are neutralized, which has a significant effect on suppressing current collapse. The dynamic on-resistance degradation phenomenon of the device has been significantly improved compared with the traditional lateral AlGaN / GaN Schottky diode, thereby improving the performance and reliability of the device.

[0055] Embodiment 2

[0056] On the basis of the above Embodiment 1, this embodiment provides a preparation method of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode. Please refer to Figure 2 , Figure 2It is a flow chart of a preparation method of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention, specifically including the following steps:

[0057] S1: Based on the substrate, deposit a nucleation layer, a buffer layer, a channel layer, a barrier layer, a cap layer, and a P-type layer in sequence from bottom to top.

[0058] First, select any one of sapphire, Si, SiC, or GaN as the substrate, and perform a pretreatment to eliminate dangling bonds on its surface.

[0059] A dangling bond refers to a situation where the crystal lattice suddenly terminates at the surface. Each atom in the outermost layer of the outer surface will have an unpaired electron, that is, an unsaturated bond; dangling bonds will affect the bonding between atoms and are prone to form dislocations.

[0060] Then, clean the substrate. Specifically, immerse the substrate material in an HF acid solution for 30 s, and ultrasonically clean it in acetone solution, absolute ethanol solution, and deionized water for 2 min each in sequence. Dry the cleaned substrate 1 with nitrogen.

[0061] Next, use the MOCVD (Metal-organic Chemical Vapor Deposition) process to deposit a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer on the substrate in sequence. Among them, the material of the nucleation layer can be AlN or GaN, the material of the buffer layer can be GaN, the material of the channel layer can be GaN, the material of the barrier layer can be AlGaN, where the Al component is 0.15 - 0.3; the material of the cap layer can be GaN.

[0062] MOCVD is a new type of gas-phase epitaxial growth technology developed on the basis of gas-phase epitaxial growth. When growing GaN or AlN materials by MOCVD, ammonia, trimethylgallium, or trimethylaluminum needs to be introduced into the reaction chamber at high temperature with hydrogen or nitrogen as the carrier gas. After the ammonia and the metal source are fully mixed in the chamber, they are transported downward to the surface of the substrate. Since the substrate generally has a relatively high temperature, the decomposition products of the metal source under the action of high temperature react with ammonia to form GaN molecules or AlN molecules and precipitate on the surface of the substrate 1. By adjusting the ratio and composition of the metal source, epitaxial growth of materials such as AlGaN and InAlN can also be carried out. For the specific parameters of the MOCVD process in this embodiment, they can be set according to the materials and specific requirements.

[0063] Finally, a P-type layer with a thickness greater than or equal to 10 nm can be formed by epitaxially growing Mg-doped GaN on the upper surface of the cap layer, or by depositing P-type materials such as NiO and SnO through oxidation.

[0064] In another embodiment of the present invention, after depositing the channel layer and before depositing the barrier layer, it further includes: depositing an insertion layer on the channel layer. Specifically, the insertion layer can still be formed by MOCVD process, and its material is AlN.

[0065] S2: Completely etch the P-type layer to form an independent P-type material block, which is called the P-type cathode island structure.

[0066] Specifically, use the processes of coating photoresist, baking photoresist, exposure, development, and post-baking to lithographically pattern an independent p-type semiconductor region on the upper surface of the P-type layer, and use ICP (inductively coupled plasma etching) process to completely etch it to obtain the P-type cathode island structure. Among them, the thickness of the P-type cathode island structure is greater than or equal to 10 nm, and the length is 2 μm to 4 μm.

[0067] S3: Etch the cap layer, barrier layer, and channel layer in sequence to form a cathode groove.

[0068] First, use the processes of coating photoresist, baking photoresist, exposure, and development to lithographically pattern the cathode region on the upper surface of the cap layer 7, and rinse the sample with deionized water and dry it with nitrogen.

[0069] Then, use ICP (inductively coupled plasma etching) process to etch the cap layer, barrier layer, and a small amount of channel layer respectively to obtain the cathode groove region.

[0070] It should be noted that if the device includes an insertion layer, the insertion layer also needs to be etched. Among them, the etching depth is greater than the sum of the thicknesses of the cap layer, barrier layer, and insertion layer, and less than the sum of the thicknesses of the cap layer 7, barrier layer 6, insertion layer 5, and channel layer 4, so that the etched groove contacts the two-dimensional electron gas (2DEG) at the interface with the channel layer 4.

[0071] S4: Deposit cathode metal in the cathode groove and on the upper surface of the P-type cathode island respectively to form a mutually connected cathode electrode and cathode plate, thereby forming a hybrid P-type material ohmic cathode.

[0072] First, make a mask on the cathode groove and the P-type cathode island structure;

[0073] Then, place the epitaxial wafer with the mask made in the magnetron sputtering reaction chamber, and keep the pressure in the reaction chamber at 8.8×10 -2 Pa.

[0074] Finally, use electron beam evaporation or magnetron sputtering process to deposit Ti / Al, Ti / Al / Ni / Au, or Ti / Al / Mo / Au metal in the mask, and perform annealing at 870 °C for 35 s in a nitrogen atmosphere to form the cathode electrode and cathode plate. Among them, the contact surface between the channel layer and the cathode electrode is an ohmic contact.

[0075] The electron beam evaporation process is a type of vacuum evaporation coating. It directly heats and evaporates materials using an electron beam under vacuum conditions, vaporizes the evaporation materials and transports them to the substrate, and condenses on the substrate to form a thin film. In the electron beam heating device, the material to be heated is placed in a water-cooled crucible to avoid the reaction between the evaporation material and the crucible wall from affecting the quality of the thin film. Therefore, the electron beam evaporation deposition method can prepare high-purity thin films. At the same time, multiple crucibles can be placed in the same evaporation deposition device to achieve simultaneous or separate evaporation and deposition of multiple different substances.

[0076] The magnetron sputtering process is a type of physical vapor deposition. By introducing a magnetic field on the surface of the target cathode, the magnetic field is used to constrain charged particles to increase the plasma density and thus increase the sputtering rate, that is, high-speed sputtering is carried out under low pressure. It is mostly used for preparing metals, semiconductors, insulators, etc., and has the advantages of simple equipment, easy control, large coating area, and strong adhesion.

[0077] S5: Etch the epitaxial wafer to form an anode groove, and deposit anode metal in the anode groove and on a part of the upper surface of the cap layer to form interconnected anodes and anode field plates.

[0078] First, use the processes of spin coating, baking, exposure, and development to lithograph the anode area on the upper surface of the cap layer 7 away from the cathode end. Rinse the sample with deionized water and dry it with nitrogen.

[0079] Then, use the ICP (inductively coupled plasma etching) process to etch the cap layer, AlGaN barrier layer, and a small amount of GaN channel layer respectively to obtain the anode groove area, and the etching depth is the same as that of the cathode groove.

[0080] Finally, use the electron beam evaporation or magnetron sputtering process to deposit metals such as Ni / Au / Ni, Ni / Au, W / Au, or Mo / Au in the mask, and then anneal at 450 °C for 5 min in a nitrogen atmosphere to form the cathode and anode electrodes and the anode field plate. Among them, the contact surface between the channel layer and the anode electrode is a Schottky contact.

[0081] S6: Deposit a passivation layer on the entire device surface, perform photolithography and etching on the passivation layer on the cathode electrode and the cathode plate to form a cathode contact hole, and perform photolithography and etching on the passivation layer on the anode electrode and the anode field plate to form an anode contact hole to complete the preparation of the device.

[0082] Specifically, after cleaning and drying the epitaxial wafer obtained in step S5, place it in a plasma chemical vapor deposition reaction chamber, and deposit a passivation layer with a thickness of 20 nm at a high temperature of 400 °C. The material can be Al2O3, HfO2, or SiO2.

[0083] Then, photolithography and etching are performed on the passivation layer on the cathode plate to form cathode contact holes, and photolithography and etching are performed on the passivation layer on the anode field plate to form anode contact holes.

[0084] Thus, the preparation of the lateral Schottky barrier diode with a hybrid P-type material ohmic cathode is completed.

[0085] Embodiment 3

[0086] Next, taking a diode with a sapphire material for the substrate 1, an AlN material for the nucleation layer 2, an AlN material for the insertion layer 5, an Al2O3 material for the passivation layer 8, and a Mg-doped GaN material for the P-type cathode island structure 8 as an example, the preparation process of the present invention will be described in detail.

[0087] Please refer to Figures 3a to 3o , Figures 3a to 3o which is a schematic diagram of the preparation process of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode provided by an embodiment of the present invention. Specifically as follows:

[0088] Step 1: Select the substrate 1.

[0089] Select the substrate 1 made of sapphire material, and perform pretreatment for eliminating dangling bonds and cleaning treatment on its surface, as Figure 3a shown.

[0090] Step 2: Based on the substrate 1, deposit and stack the nucleation layer 2, buffer layer 3, channel layer 4, insertion layer 5, barrier layer 6, cap layer 7, and P-type layer from bottom to top in sequence.

[0091] 21) Grow the nucleation layer 2 on the upper surface of the substrate 1.

[0092] Specifically, based on the MOCVD process, put the pretreated substrate 1 into a metalorganic chemical vapor deposition (MOCVD) system. Under the conditions that the pressure in the system chamber is 40 Torr and the temperature is 900 °C, simultaneously introduce an Al source with a flow rate of 40 μmol / min, hydrogen with a flow rate of 1000 sccm, and ammonia with a flow rate of 1500 sccm into the reaction chamber of the system to form an AlN nucleation layer 2 with a thickness of 45 nm, as Figure 3b shown.

[0093] 22) Grow the buffer layer 3 on the surface of the nucleation layer 2.

[0094] Specifically, based on the MOCVD process, control the temperature to be 1000 °C and the pressure in the system chamber to be 10 Torr. Simultaneously introduce trimethylgallium with a flow rate of 100 sccm, hydrogen with a flow rate of 800 sccm, and ammonia with a flow rate of 1000 sccm into the reaction chamber of the MOCVD system to form a GaN buffer layer 3 with a thickness of 2.4 μm, as Figure 3cas shown

[0095] 23) Grow the channel layer 4 on the surface of the buffer layer 3.

[0096] Specifically, based on the MOCVD process, maintain the temperature at 1000 °C and the pressure of the system chamber at 10 Torr. In the reaction chamber of the MOCVD system, trimethylgallium with a flow rate of 10 sccm, hydrogen with a flow rate of 80 sccm, and ammonia with a flow rate of 100 sccm are simultaneously introduced to form a GaN channel layer 4 with a thickness of 200 nm, as Figure 3d shown

[0097] 24) Grow the insertion layer 5 on the surface of the channel layer 4.

[0098] Specifically, based on the MOCVD process, in the reaction chamber of the MOCVD system, an Al source with a flow rate of 40 μmol / min, hydrogen with a flow rate of 1000 sccm, and ammonia with a flow rate of 1500 sccm are simultaneously introduced to form an insertion layer 5 of AlN material with a thickness of 1 nm, as Figure 3e shown

[0099] 25) Grow the barrier layer 6 on the surface of the insertion layer 5.

[0100] Specifically, based on the MOCVD process, control the temperature to be maintained at 950 °C and the pressure of the system chamber at 40 Torr. Using hydrogen as a carrier, trimethylaluminum is introduced as an aluminum source, and using nitrogen as a carrier, triethylgallium is introduced as a gallium source. Ammonia is simultaneously introduced as a nitrogen source. Therefore, in the reaction chamber of the MOCVD system, trimethylaluminum with a molar flow rate of 27.4 μmol / min and triethylgallium with a molar flow rate of 8.6 μmol / min, hydrogen with a flow rate of 800 sccm, and ammonia with a flow rate of 1000 sccm are introduced to grow the barrier layer 6 of AlGaN material. As Figure 3f shown. Among them, the thickness of the barrier layer 6 is 25 nm, and the Al component is 0.3.

[0101] 26) Grow the cap layer 7 on the surface of the barrier layer 6.

[0102] Specifically, based on the MOCVD process, control the temperature at 1000 °C and the pressure of the system chamber at 10 Torr. In the reaction chamber of the MOCVD system, trimethylgallium with a flow rate of 10 sccm, hydrogen with a flow rate of 80 sccm, and ammonia with a flow rate of 100 sccm are simultaneously introduced to form a GaN cap layer 7 with a thickness of 2 nm, as Figure 3g shown

[0103] 27) Grow the P-type layer on the surface of the cap layer 7.

[0104] Specifically, based on the MOCVD process, the temperature is controlled at 1000 °C, the pressure of the system chamber is 10 Torr. Trimethylgallium with a flow rate of 10 sccm, hydrogen with a flow rate of 80 sccm, ammonia with a flow rate of 100 sccm, and magnesium cyclopentadienyl with a flow rate of 40 nmol / min are simultaneously introduced into the reaction chamber of the MOCVD system as the Mg source. Finally, a p-type doped GaN material is grown as the P-type layer. Among them, the p-type doping concentration of the P-type layer is 5.0×10 18 cm -3 , and the thickness is 50 nm, as Figure 3h shown.

[0105] Step 3: Etch the P-type layer to form a P-type cathode island structure.

[0106] Please refer to Figure 3i . Using the processes of spin coating, soft baking, exposure, development, and post-baking, lithograph independent p-type semiconductor regions on the upper surface of the P-type layer, and use the ICP process to completely etch to obtain the P-type cathode island structure 8, with an etching depth of approximately 50 nm.

[0107] Step 4: Etch the cap layer 7, barrier layer 6, insertion layer 5, and channel layer 4 in sequence to form a cathode groove.

[0108] Please refer to Figure 3j . Using the processes of spin coating, soft baking, exposure, and development, lithograph the cathode region on the upper surface of the cap layer 7. Rinse the sample with deionized water and dry it with nitrogen. Use the ICP process to etch the cap layer 7, AlGaN barrier layer 6, AlN insertion layer 5, and a small amount of GaN channel layer 4 respectively to obtain the cathode groove region, with an etching depth of approximately 48 nm.

[0109] Step 5: Deposit cathode metal in the cathode groove and above the cathode island simultaneously to form the cathode electrode 9 and the connected cathode plate 10.

[0110] Please refer to Figure 3k . First, fabricate a mask, then place the diode epitaxial wafer with the fabricated mask in the magnetron sputtering reaction chamber, keep the pressure of the reaction chamber at 8.8×10 -2 Pa. Using gold, nickel, aluminum, and titanium target materials with a purity of 99.999% respectively, deposit metals Ti / Al / Ni / Au with thicknesses of 20 nm / 140 nm / 50 nm / 40 nm respectively in this mask to form the cathode electrode. Then, perform annealing at 870 °C for 35 s in a nitrogen atmosphere. The contact surface between the channel layer 4 and the cathode electrode 9 is an ohmic contact.

[0111] Step 6: Fabricate a mask on the upper surface of the cap layer 7 at the end far from the cathode 9, and etch the cap layer 7, barrier layer 6, insertion layer 5, and channel layer 4 in sequence to form an anode groove.

[0112] Please refer to Figure 3l , using the processes of glue coating, glue baking, exposure, and development, lithographically pattern the anode region on the upper surface of the cap layer 7. Rinse the sample with deionized water and blow it dry with nitrogen. Use the ICP process to etch the cap layer 7, the AlGaN barrier layer 6, the AlN insertion layer 5, and a small amount of the GaN channel layer 4 respectively to obtain the anode groove region, and the etching depth is about 48 nm.

[0113] Step 7: Deposit anode metal to form the anode electrode 11 and the anode field plate 12.

[0114] Please refer to Figure 3m , first fabricate a mask on the upper surface of the channel layer 4 at the end far from the cathode electrode 9. Then, place the diode epitaxial wafer with the fabricated mask in the magnetron sputtering reaction chamber using the magnetron sputtering process. Keep the pressure in the reaction chamber at 8.8×10 -2 Pa. Using tungsten and gold target materials with a purity of 99.999% each, deposit metals W / Au with thicknesses of 30 nm / 150 nm respectively to form the anode electrode. Then, perform annealing for 5 minutes at a high temperature of 450 °C in a nitrogen atmosphere. The contact surface between the channel layer 4 and the anode electrode 9 is a Schottky contact.

[0115] Step 8: Deposit a passivation layer 13 on the upper surfaces of the anode field plate 12, the cap layer 7, and the cathode plate 10.

[0116] Please refer to Figure 3n , after cleaning and drying the now fabricated diode epitaxial wafer, place it in the plasma enhanced chemical vapor deposition reaction chamber. At a high temperature of 400 °C, deposit an Al2O3 passivation layer 13 with a thickness of 20 nm.

[0117] Step 9: Perform lithography and etching on the passivation layer 13 on the cathode plate 10 to form a cathode contact hole, and perform lithography and etching on the passivation layer 13 on the anode field plate 12 to form an anode contact hole.

[0118] Please refer to again Figure 3o , perform lithography and etching on the passivation layer 13 on the cathode plate 10 and the anode field plate 12 respectively to form a cathode contact hole and an anode contact hole.

[0119] Thus, the fabrication of the device is completed.

[0120] Example 4

[0121] Next, taking a diode with the material of the substrate 1 being silicon carbide, the material of the insertion layer 5 being AlN, the material of the passivation layer 8 being HfO2, and the material of the P-type cathode island structure 8 being Mg-doped GaN as an example, the fabrication process of the present invention will be described in detail.

[0122] Step 1: Select the substrate 1.

[0123] Select a silicon carbide material as the substrate 1, and perform pretreatment and cleaning on its surface to eliminate dangling bonds.

[0124] Step 2: Based on the substrate 1, sequentially stack and deposit a nucleation layer 2, a buffer layer 3, a channel layer 4, an insertion layer 5, a barrier layer 6, a cap layer 7, and a P-type layer from bottom to top.

[0125] Specifically, in this embodiment, for the detailed processes of depositing the nucleation layer 2, the buffer layer 3, the channel layer 4, the insertion layer 5, the barrier layer 6, and the cap layer 7, refer to steps 21)-27) in Embodiment 3 above and the attached Figures 3b - 3g ; among them, the Al component of the AlGaN barrier layer 6 is 0.3.

[0126] The process of growing the P-type layer on the surface of the cap layer 7 is as follows:

[0127] Based on the MOCVD process, control the temperature to 1000 °C and the pressure of the system chamber to 10 Torr. In the reaction chamber of the MOCVD system, simultaneously introduce trimethylgallium with a flow rate of 10 sccm, hydrogen with a flow rate of 80 sccm, ammonia with a flow rate of 100 sccm, and magnesium bis(cyclopentadienyl) with a flow rate of 40 nmol / min as the Mg source to form a P-type layer of p-type doped GaN material. Among them, the doping concentration of the P-type layer is 1.0×10 20 cm -3 , and the thickness is 100 nm.

[0128] Step 3: Etch the P-type layer to form a P-type cathode island structure 8.

[0129] Use the processes of coating, baking, exposure, development, and post-baking to lithographically pattern an independent p-type semiconductor region on the upper surface of the P-type layer, and use the ICP process to completely etch it to obtain the cathode island region. The etching depth is about 100 nm, as Figure 3i shown.

[0130] Step 4: Sequentially etch the cap layer 7, the barrier layer 6, the insertion layer 5, and the channel layer 4 to form a cathode groove.

[0131] Step 5: Simultaneously deposit cathode metal in the cathode groove and above the cathode island to form a cathode electrode 9 and a connected cathode plate 10.

[0132] Step 6: Fabricate a mask on the upper surface of the cap layer 7 at the end far from the cathode 9, and sequentially etch the cap layer 7, the barrier layer 6, the insertion layer 5, and the channel layer 4 to form an anode groove.

[0133] In this embodiment, for the specific processes of Step 4 to Step 6, refer to steps 4-6 in Embodiment 3.

[0134] Step 7: Deposit anode metal to form an anode electrode 11 and an anode field plate 12.

[0135] First, a mask is fabricated on the upper surface of the end of the channel layer 4 away from the cathode 9. Then, the diode epitaxial wafer with the fabricated mask is placed in a magnetron sputtering reaction chamber using the magnetron sputtering process, and the pressure in the reaction chamber is maintained at 8.8×10 -2 Pa. Using tungsten and gold target materials with a purity of 99.999% each, a metal Ni / Au with a deposition thickness of 50 nm / 150 nm is deposited to form the anode, and then annealing is performed at a high temperature of 450 °C for 5 min in a nitrogen atmosphere. The contact surface between the channel layer 4 and the anode 9 is a Schottky contact.

[0136] Step eight: Deposit a passivation layer 13 on the upper surfaces of the anode field plate 12, the cap layer 7, and the cathode plate 10.

[0137] Please refer again to Figure 3n , after cleaning and drying the now fabricated diode epitaxial wafer, it is placed in a plasma enhanced chemical vapor deposition reaction chamber, and at a high temperature of 400 °C, a HfO2 passivation layer 13 with a deposition thickness of 20 nm is deposited.

[0138] Step nine: Perform photolithography and etching on the passivation layer 13 on the cathode plate 10 to form a cathode contact hole, and perform photolithography and etching on the passivation layer 13 on the anode field plate 12 to form an anode contact hole.

[0139] Thus, the device fabrication is completed.

[0140] Example five

[0141] Next, taking the material of the substrate 1 as gallium nitride, the material of the insertion layer 5 as AlN, the material of the passivation layer 8 as SiO2, and the material of the P-type cathode island structure 8 as NiO diode as an example, the fabrication process of the present invention will be described in detail.

[0142] Step A: Select the substrate 1.

[0143] Select gallium nitride material as the substrate 1, and perform pretreatment and cleaning on its surface to eliminate dangling bonds.

[0144] Step B: Based on the substrate 1, deposit and stack a nucleation layer 2, a buffer layer 3, a channel layer 4, an insertion layer 5, a barrier layer 6, a cap layer 7, and a P-type layer from bottom to top in sequence.

[0145] Specifically, in this embodiment, for the detailed process of depositing the nucleation layer 2, the buffer layer 3, the channel layer 4, the insertion layer 5, the barrier layer 6, and the cap layer 7, refer to steps 21)-27) in the above Example three and the attached Figures 3b - 3g .

[0146] The process of growing the P-type layer on the surface of the cap layer 7 is as follows:

[0147] Based on the PEALD (Plasma Enhanced Atomic Layer Deposition) process, argon with a flow rate of 250 sccm is introduced into the system reaction chamber as the carrier gas, and oxygen with a flow rate of 150 sccm is used as the oxygen plasma system. At the same time, ethylnickelocene is used as the Ni source, and the reaction chamber temperature is controlled to form a NiO P-type layer with a thickness of 20 nm.

[0148] Step C: Etch the P-type layer to form a cathode island structure.

[0149] Use the processes of spin coating, soft baking, exposure, development, and post-baking to lithographically pattern independent p-type semiconductor regions on the upper surface of the P-type layer, and use the ICP process to completely etch to obtain the P-type cathode island structure 8 with an etching depth of about 20 nm.

[0150] Step D: Etch the cap layer 7, barrier layer 6, insertion layer 5, and channel layer 4 in sequence to form a cathode groove. For the specific etching process, refer to step 4 in Example 3.

[0151] Step E: Deposit cathode metal in the cathode groove and above the cathode island simultaneously to form the cathode electrode 9 and the connected cathode plate 10.

[0152] First, make a mask. Then, place the diode epitaxial wafer with the mask made on it in the magnetron sputtering reaction chamber, keep the reaction chamber pressure at 8.8×10-2 Pa, use gold and titanium target materials with a purity of 99.999% each, deposit metals Ti / Au with thicknesses of 50 nm / 150 nm respectively in this mask to form the cathode electrode, and then perform annealing at 870 °C for 35 s in a nitrogen atmosphere. The contact surface between the channel layer 4 and the cathode electrode 9 is an ohmic contact.

[0153] Step F: Make a mask on the upper surface of the cap layer 7 at the end far from the cathode 9, and etch the cap layer 7, barrier layer 6, insertion layer 5, and channel layer 4 in sequence to form an anode groove. For the specific process, refer to step 6 in Example 3.

[0154] Step G: Deposit anode metal to form the anode electrode 11 and the anode field plate 12. For the specific process, refer to step seven in Example 4.

[0155] Step H: Deposit a passivation layer 13 on the upper surfaces of the anode field plate 12, cap layer 7, and cathode plate 10.

[0156] Please refer to Figure 3n , after cleaning and drying the now fabricated diode epitaxial wafer, place it in the plasma chemical vapor deposition reaction chamber, and deposit a SiO2 passivation layer 13 with a thickness of 20 nm at a high temperature of 400 °C.

[0157] Step I: Lithograph and etch the passivation layer 13 on the cathode plate 10 to form a cathode contact hole, and lithograph and etch the passivation layer 13 on the anode field plate 12 to form an anode contact hole.

[0158] So far, the device fabrication is completed.

[0159] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A lateral Schottky barrier diode with a hybrid P-type material ohmic cathode, characterized in that, Comprising: A substrate (1), a nucleation layer (2), a buffer layer (3), a channel layer (4), a barrier layer (6), and a cap layer (7) which are stacked in sequence from bottom to top; wherein, There is a P-type cathode island structure (8) provided at the upper right of the cap layer (7); A cathode groove and an anode groove are respectively provided corresponding to the right side of the P-type cathode island structure (8) and the left side of the device. Both the cathode groove and the anode groove start from the upper surface of the cap layer (7) and extend downward into the channel layer (4); A cathode electrode (9) is provided on the channel layer (4) within the cathode groove. A cathode plate (10) is provided on the upper surface of the P-type cathode island structure (8). The cathode plate (10) is connected to the cathode electrode (9) to form a hybrid P-type material ohmic cathode; An anode electrode (11) is provided on the channel layer (4) within the anode groove. On the upper surface of the cap layer (7), an anode field plate (12) connected to the anode electrode (11) is provided within a certain length range near the anode electrode (11); A passivation layer (13) is covered on the cap layer (7) between the anode field plate (12) and the P-type cathode island structure (8).

2. The lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 1, characterized in that, An insertion layer (5) is further provided between the channel layer (4) and the barrier layer (6).

3. The lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 2, characterized in that, The material of the insertion layer (5) is AlN, and the thickness is 0.5 - 2 nm.

4. The lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 1 or 2, characterized in that, The material of the P-type cathode island structure (8) is Mg-doped GaN or P-type NiO, SnO material, and its thickness is greater than or equal to 10 nm.

5. The lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 1 or 2, characterized in that, The length of the P-type cathode island structure (8) is 2 μm - 4 μm.

6. The lateral Schottky barrier diode having a hybrid P-type material ohmic cathode according to claim 1 or 2, characterized in that, The channel layer (4) and the cathode electrode (9) are in ohmic contact, and the contact surfaces between the channel layer (4) and the anode electrode (11) are all Schottky contacts.

7. The lateral Schottky barrier diode having a hybrid P-type material ohmic cathode according to claim 1 or 2, characterized in that, The distance from the bottommost part of the cathode groove to the upper surface of the channel layer (4) is 10 - 40 nm.

8. A method for fabricating a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode, characterized in that, Comprising: Based on the substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a cap layer, and a P-type layer are stacked and deposited in sequence from bottom to top; The P-type layer is completely etched to form an independent P-type material block, which is called a P-type cathode island structure; The cap layer, the barrier layer, and the channel layer are etched in sequence to form a cathode groove; Cathode metals are respectively deposited within the cathode groove and on the upper surface of the P-type cathode island to form a mutually connected cathode electrode and cathode plate, thereby forming a hybrid P-type material ohmic cathode; The epitaxial wafer is etched to form an anode groove, and anode metals are deposited within the anode groove and on a partial upper surface of the cap layer to form a mutually connected anode electrode and anode field plate; A passivation layer is deposited on the entire device surface, and the passivation layer on the cathode electrode and the cathode plate is lithographed and etched to form a cathode contact hole, and the passivation layer on the anode electrode and the anode field plate is lithographed and etched to form an anode contact hole to complete the preparation of the device.

9. The manufacturing method of a lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 8, characterized in that, After depositing the channel layer and before depositing the barrier layer, it further includes: Depositing an insertion layer on the channel layer.

10. The manufacturing method of the lateral Schottky barrier diode with a hybrid P-type material ohmic cathode according to claim 8, characterized in that, Cathode metals are respectively deposited within the cathode groove and on the upper surface of the P-type cathode island to form a mutually connected cathode electrode and cathode plate, including: Fabricate a mask on the cathode groove and the P-type cathode island structure; Place the epitaxial wafer with the mask fabricated thereon in a magnetron sputtering reaction chamber, and maintain the pressure in the reaction chamber at 8.8×10 -2 Pa; Deposit metals such as Ti / Al, Ti / Al / Ni / Au or Ti / Al / Mo / Au in the mask and anneal at a high temperature of 870 °C in a nitrogen atmosphere to form interconnected cathode electrodes and cathode plates.

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