A power tube gate end driving circuit

Abstract

The application discloses a power tube gate end driving circuit, which comprises a driving circuit and a logic control circuit; the driving circuit comprises PMOS tubes (P1, P2, P3, P4, P5, P6, P7, P8, P9), NMOS tubes (N1, N2, N3, N4, N5, N6, N7, N8), resistors (R1, R2, R3), Zener diodes (D1, D2) and a current source Ibias; the logic control circuit comprises inverters (INV1, INV2, INV3, INV4, INV5, INV6); the technical scheme is ingeniously designed to reduce the limitation of process requirements of the driving circuit; and the controllable driving current and driving voltage are beneficial to the application of a switching power supply module.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a power transistor gate drive circuit. Background Technology

[0002] With the development of integrated circuit technology, MOSFETs have been widely used in various switching power supply management circuits due to their high cost-effectiveness and high reliability. To control the turn-on and turn-off of MOSFETs, a dedicated drive circuit is usually designed in the control IC, which controls the gate voltage of the MOSFET to achieve turn-on and turn-off. To reduce the conduction losses of MOSFETs, their area is usually large, and their parasitic input capacitance is also large; therefore, a certain driving capability is required.

[0003] Currently commonly used drive circuits include Figure 1 As shown, all digital gates are powered by VCC (typically 10~30V). INV1~INV7 are inverters; NOR1 is a NOR gate; NAND1 is a NAND gate; P0 and N0 are two driver transistors, which usually have strong driving capabilities; DRV is the internal drive signal, which has weak driving capabilities; GATE is the output signal, directly connected to the GATE terminal of the external MOS power transistor. INV2~INV7, NOR1, and NAND1 are designed for dead time. To prevent P0 and N0 from passing through, if DRV goes high, the gate terminal of N0 is first pulled low, turning off N0. After a certain delay, the gate terminal of P0 is pulled low, turning on P0 and pulling the output GATE high. If DRV goes low, the gate terminal of P0 is first quickly pulled high, turning off P0. After a certain delay, the gate terminal of N0 is pulled high, turning on N0 and pulling the output GATE low.

[0004] However, in existing driving technologies, the high-level voltage of the driver output GATE is the control chip's power supply VCC. Therefore, the control chip's power supply voltage VCC should not be too high to prevent gate oxide breakdown of the external power transistors. The current of the driver transistors P0 and N0 is controlled by the gate oxide voltage VGS (i.e., VCC), and the driving capability varies greatly under different power supply voltages. Furthermore, with the development of semiconductor manufacturing technology, in more advanced processes of 0.18µm and below, the gate oxide thickness is usually thinner, and the gate oxide operating voltage of medium-voltage transistors is usually not allowed to exceed 5V. Existing driving technologies are clearly unsuitable for use in advanced processes.

[0005] In view of the above-mentioned defects in the existing technology, the present invention proposes a novel power transistor gate drive circuit, which can not only solve the driving application problem under thin gate oxide process, but also effectively control the driving voltage and driving current. Summary of the Invention

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: a power transistor gate terminal driving circuit, the circuit comprising:

[0007] The driving circuit includes PMOS transistors (P1, P2, P3, P4, P5, P6, P7, P8, P9), NMOS transistors (N1, N2, N3, N4, N5, N6, N7, N8), resistors (R1, R2, R3), Zener diodes (D1, D2), and a current source Ibias.

[0008] The logic control circuit includes inverters (INV1, INV2, INV3, INV4, INV5, INV6).

[0009] As an improvement of the present invention, in the driving circuit, the gate terminal of PMOS transistor P1 is connected to the gate terminal of PMOS transistor P2, the source terminals of PMOS transistor P1 and PMOS transistor P2 are connected to VDD, the drain terminal of PMOS transistor P1 is connected to the input terminal of current source Ibias, the gate terminal and drain terminal of PMOS transistor P1 are connected, the drain terminal of PMOS transistor P2 is connected to the source terminal of PMOS transistor P3, the drain terminal of PMOS transistor P3 is connected to the source terminal of PMOS transistor P4, and the drain terminal of PMOS transistor P4 is connected to the drain terminal of NMOS transistor N1.

[0010] Based on the above technical solution, PMOS transistors P1 and P2 form a current mirror.

[0011] As an improvement of the present invention, in the driving circuit, the source terminal of NMOS transistor N1 is grounded, the gate terminal of NMOS transistor N1 is connected to the gate terminal of NMOS transistor N2, the gate terminal of NMOS transistor N1 is connected to the drain terminal, the source terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, and the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N3.

[0012] Based on the above technical solution, NMOS transistors N1 and NMOS transistors N2 constitute a current mirror.

[0013] As an improvement of the present invention, in the driving circuit, the drain terminal of NMOS transistor N3 is connected to the drain terminal of PMOS transistor P5, the drain terminal and gate terminal of PMOS transistor P5 are connected, the source terminal of PMOS transistor P5 is connected to VCC, and the gate terminal of PMOS transistor P5 is connected to the gate terminal of PMOS transistor P6.

[0014] Based on the above technical solution, PMOS transistors P5 and P6 form a current mirror with a ratio of 1:n, and PMOS transistor P6 is a pull-up drive transistor.

[0015] As an improvement of the present invention, in the driving circuit, the drain of NMOS transistor N4 is connected to the source of NMOS transistor N6, the source of NMOS transistor N4 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N6 is connected to the gate of PMOS transistor P8, the drain of PMOS transistor P7 and the anode of Zener diode D1, the cathode of Zener diode D1 is connected to the source of PMOS transistor P5, the source of PMOS transistor P7 is connected to the cathode of Zener diode D1, the source of NMOS transistor N5 is connected to the source of NMOS transistor N4, the source of NMOS transistor N4 is connected to the source of NMOS transistor N7, the drain of NMOS transistor N7 is connected to the gate of PMOS transistor P7, the gate of PMOS transistor P9, the anode of Zener diode D2 and the drain of PMOS transistor P8, and the source of PMOS transistor P8 is connected to the source of PMOS transistor P7.

[0016] Based on the above technical solution, PMOS transistors P7, PMOS transistor P8, NMOS transistors N6, NMOS transistor N7, NMOS transistor N4, and NMOS transistor N5 constitute a level shifting circuit. The gate terminal of PMOS transistor P9 is connected to the output of the level shifting circuit, and the drain terminal is connected to the gate terminal of PMOS transistor P6. Resistor R1 is connected between the gate terminal of PMOS transistor P9 and ground, which serves as an initialization function. In the initial stage of power-on, P9 is first turned on, thereby turning off the pull-up drive transistor P6.

[0017] As an improvement of the present invention, the source terminal of PMOS transistor P6 is connected to the source terminal of PMOS transistor P9, the drain terminal of PMOS transistor P6 is connected to the drain terminal of NMOS transistor N8, the source terminal of NMOS transistor N8 is connected to the source terminal of NMOS transistor N5, resistor R1 is connected between the source terminal of NMOS transistor N8 and the gate terminal of PMOS transistor P9, the connection point of PMOS transistor P6 and NMOS transistor N8 is connected to the GATE terminal and one end of voltage divider resistor R2, the other end of voltage divider resistor R2 is connected to voltage divider resistor R3, the other end of voltage divider resistor R3 is connected to the source terminal of NMOS transistor N8, and the connection point of voltage divider resistor R2 and voltage divider resistor R3 is connected to the gate terminal of PMOS transistor.

[0018] Based on the above technical solution, N8 is a pull-down driver transistor, and the Gate terminal is the control signal S2; the driver output GATE has a resistor divider network of R2 / R3 to ground.

[0019] As an improvement of the present invention, in the logic control circuit, the input terminal of inverter INV1 is connected to the DRV signal, the output terminal of inverter INV1 is connected to the input terminals of inverter INV2 and inverter INV4, the output terminal of inverter INV2 outputs the S1 signal, the output terminal of inverter INV2 is connected to the input terminal of inverter INV3, the output terminal of inverter INV3 outputs the S2 signal, the output terminal of inverter INV4 is connected to the input terminal of inverter INV5, the output terminal of inverter INV5 outputs the S3 signal, the output terminal of inverter INV5 is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 outputs the S4 signal.

[0020] As an improvement of the present invention, the gate terminal of PMOS transistor P4 is connected to signal S3, the gate terminal of NMOS transistor N3 is connected to signal S4, the gate terminal of NMOS transistor N4 is connected to signal S1, the gate terminal of NMOS transistor N5 is connected to signal S5, and the gate terminal of NMOS transistor N8 is connected to signal S2.

[0021] Compared with the prior art, the beneficial effects of the present invention are: the present invention can not only solve the driving problem in the design of thin gate oxide process, but also effectively control the driving voltage and driving current, which is conducive to the debugging of system-level solutions. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a driving circuit in the prior art.

[0023] Figure 2 This is a schematic diagram of the power transistor gate drive circuit in this invention.

[0024] Figure 3 This is a schematic diagram of the power transistor gate logic control circuit in this invention. Detailed Implementation

[0025] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0026] Example: See Figure 2 and Figure 3 A power transistor gate drive circuit, the circuit comprising:

[0027] The driving circuit includes PMOS transistors (P1, P2, P3, P4, P5, P6, P7, P8, P9), NMOS transistors (N1, N2, N3, N4, N5, N6, N7, N8), resistors (R1, R2, R3), Zener diodes (D1, D2), and a current source Ibias.

[0028] The logic control circuit includes inverters (INV1, INV2, INV3, INV4, INV5, INV6).

[0029] In the driving circuit, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2. The sources of PMOS transistors P1 and P2 are connected to VDD. The drain of PMOS transistor P1 is connected to the input of the current source Ibias. The gate and drain of PMOS transistor P1 are connected. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P3. The drain of PMOS transistor P3 is connected to the source of PMOS transistor P4. The drain of PMOS transistor P4 is connected to the drain of NMOS transistor N1. PMOS transistors P1 and P2 form a current mirror.

[0030] Furthermore, in the driving circuit, the source terminal of NMOS transistor N1 is grounded, the gate terminal of NMOS transistor N1 is connected to the gate terminal of NMOS transistor N2, the gate terminal and drain terminal of NMOS transistor N1 are connected, the source terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, and the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N3. NMOS transistors N1 and NMOS transistor N2 form a current mirror.

[0031] Furthermore, in the driving circuit, the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P5, the drain and gate of PMOS transistor P5 are connected, the source of PMOS transistor P5 is connected to VCC, and the gate of PMOS transistor P5 is connected to the gate of PMOS transistor P6. PMOS transistors P5 and P6 form a current mirror with a ratio of 1:n, and PMOS transistor P6 is a pull-up driving transistor.

[0032] Furthermore, in the driving circuit, the drain of NMOS transistor N4 is connected to the source of NMOS transistor N6, the source of NMOS transistor N4 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N6 is connected to the gate of PMOS transistor P8, the drain of PMOS transistor P7, and the anode of Zener diode D1, the cathode of Zener diode D1 is connected to the source of PMOS transistor P5, the source of PMOS transistor P7 is connected to the cathode of Zener diode D1, the source of NMOS transistor N5 is connected to the source of NMOS transistor N4, the source of NMOS transistor N4 is connected to the source of NMOS transistor N7, the drain of NMOS transistor N7 is connected to the gate of PMOS transistor P7, the gate of PMOS transistor P9, the anode of Zener diode D2, and the drain of PMOS transistor P8, and the source of PMOS transistor P8 is connected to the source of PMOS transistor P7. PMOS transistors P7, PMOS transistor P8, NMOS transistors N6, NMOS transistor N7, NMOS transistor N4, and NMOS transistor N5 constitute a level shifting circuit. The gate of PMOS transistor P9 is connected to the output of the level shifting circuit, and its drain is connected to the gate of PMOS transistor P6. Resistor R1 is connected between the gate of PMOS transistor P9 and ground, which serves as an initialization function. In the initial stage of power-on, P9 is turned on first, thereby turning off the pull-up drive transistor P6.

[0033] Furthermore, the source of PMOS transistor P6 is connected to the source of PMOS transistor P9, the drain of PMOS transistor P6 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N8 is connected to the source of NMOS transistor N5. Resistor R1 is connected between the source of NMOS transistor N8 and the gate of PMOS transistor P9. The connection point between PMOS transistor P6 and NMOS transistor N8 is connected to the GATE terminal and one end of resistor R2. The other end of resistor R2 is connected to resistor R3, and the other end of resistor R3 is connected to the source of NMOS transistor N8. The connection point of resistors R2 and R3 is connected to the gate of the PMOS transistor. N8 is a pull-down driver transistor, and the Gate terminal is the control signal S2. The driver output GATE is connected to ground via a resistor divider network of R2 / R3.

[0034] Furthermore, in the logic control circuit, the input terminal of inverter INV1 is connected to the DRV signal, the output terminal of inverter INV1 is connected to the input terminals of inverter INV2 and inverter INV4, the output terminal of inverter INV2 outputs the S1 signal, the output terminal of inverter INV2 is connected to the input terminal of inverter INV3, the output terminal of inverter INV3 outputs the S2 signal, the output terminal of inverter INV4 is connected to the input terminal of inverter INV5, the output terminal of inverter INV5 outputs the S3 signal, the output terminal of inverter INV5 is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 outputs the S4 signal.

[0035] Furthermore, the gate of the PMOS transistor P4 is connected to the S3 signal, the gate of the NMOS transistor N3 is connected to the S4 signal, the gate of the NMOS transistor N4 is connected to the S1 signal, the gate of the NMOS transistor N5 is connected to the S5 signal, and the gate of the NMOS transistor N8 is connected to the S2 signal.

[0036] Working principle: When the input signal DRV of the drive circuit changes from low to high, signal S1 becomes high, signal S2 becomes low, the lower drive transistor N8 is turned off, the level shift circuit outputs a high level VCC, P9 is turned off, and the current mirrors P5 and P6 can work; at the same time, signal S3 becomes low, signal S4 becomes high, P4 and N3 are both turned on, and the current source Ibias can be converted through several stages of current mirrors to generate a drive current at the pull-up drive transistor P6, and this current is determined by the ratio of the current mirrors. For example, if P1 / P2 and N1 / N2 are both 1:1 current mirrors, and P5 / P6 is a 1:n current mirror, then the drive current generated by P6 is n*Ibias. Afterwards, the gate voltage gradually rises. Following the voltage division by R2 and R3, the voltage at the dividing node of R2 and R3 slowly increases. Once it reaches a certain level, P3 turns off, eventually cutting off the current to P6. The output gate voltage then drops. As the voltage at the dividing node of R2 and R3 decreases, P3 turns on, controlling the output gate voltage to rise again until a steady state is reached. The final output gate voltage will stabilize at a certain value, determined by the voltage division ratio of R2 and R3. If the low-voltage power supply VDD is 5V, then the turn-off voltage of P3 is approximately 4V, and the output gate voltage is (R2+R3)*4 / R3, but it cannot exceed VCC.

[0037] When the input signal DRV of the drive circuit changes from high to low, signal S3 goes high, signal S4 goes low, P4 and N3 are turned off, P5 has no current, and therefore the pull-up drive transistor P6 has no current. Simultaneously, signal S1 goes low, signal S2 goes high, and the output voltage of the level shifting circuit is VCC - Vdz, where Vdz is the breakdown voltage of Zener transistors D1 and D2. P9 conducts, pulling the gate terminal of P6 high, completely eliminating current to P6. Since signal S2 goes high, the pull-down drive transistor N8 conducts, and the output gate goes low. The drive current of N8 is entirely determined by the low-voltage power supply VDD, which is a fixed voltage; therefore, this current value is controllable.

[0038] In the driving circuit provided by this invention, the logic control circuit in the lower half only schematically illustrates the logical relationship. Through specific design, such as adjusting the size of the transistors in each logic gate and changing the order of control signals S1~S4, a dead time can be designed between the pull-up driving transistor P6 and the pull-down driving transistor N8. For example, when the input signal DRV goes high, after a delay through logic gates INV8~INV13, signal S1 goes high first, signal S2 goes low, then signal S3 goes low, and signal S4 goes high. For the two driving transistors P6 and N8, N8 is turned off first, and P6 is turned on later, directly generating a dead time between the two driving transistors. When the input signal DRV goes low, after a delay through logic gates INV8~INV13, signal S3 goes high first, signal S4 goes low, then signal S1 goes low, and signal S2 goes high. For the two driving transistors P6 and N8, P6 is turned off first, and N8 is turned on later, similarly introducing a dead time.

[0039] In the driving circuit, the gate oxide voltage of all PMOS and NMOS will not exceed 5V~5.5V. This structure can be applied to more advanced thin gate processes of 0.18um and below. The driving current of this driving circuit is determined by the specific current mirror ratio, and the driving current is controllable. The output voltage of this driving circuit can be set through the output resistor network. The output GATE voltage value is constant and will not change with the power supply of the control chip.

[0040] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A power transistor gate terminal driving circuit, characterized in that, The circuit includes: The driving circuit includes PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, and P9; NMOS transistors N1, N2, N3, N4, N5, N6, N7, and N8; resistors R1, R2, and R3; Zener diodes D1 and D2; and a current source Ibias. The logic control circuit includes inverters INV1, INV2, INV3, INV4, INV5, and INV6. In the driving circuit, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P2; the sources of PMOS transistors P1 and P2 are connected to VDD; the drain of PMOS transistor P1 is connected to the input of the current source Ibias; the gate and drain of PMOS transistor P1 are connected; the drain of PMOS transistor P2 is connected to the source of PMOS transistor P3; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4; and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N1. In the driving circuit, the source terminal of NMOS transistor N1 is grounded, the gate terminal of NMOS transistor N1 is connected to the gate terminal of NMOS transistor N2, the gate terminal and drain terminal of NMOS transistor N1 are connected, the source terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, and the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N3. In the driving circuit, the drain of NMOS transistor N3 is connected to the drain of PMOS transistor P5, the drain and gate of PMOS transistor P5 are connected, the source of PMOS transistor P5 is connected to VCC, and the gate of PMOS transistor P5 is connected to the gate of PMOS transistor P6. In the driving circuit, the drain of NMOS transistor N4 is connected to the source of NMOS transistor N6, the source of NMOS transistor N4 is connected to the source of NMOS transistor N2, the drain of NMOS transistor N6 is connected to the gate of PMOS transistor P8, the drain of PMOS transistor P7, and the anode of Zener diode D1, the cathode of Zener diode D1 is connected to the source of PMOS transistor P5, the source of PMOS transistor P7 is connected to the cathode of Zener diode D1, the source of NMOS transistor N5 is connected to the source of NMOS transistor N4, the source of NMOS transistor N4 is connected to the source of NMOS transistor N7, the drain of NMOS transistor N7 is connected to the gate of PMOS transistor P7, the gate of PMOS transistor P9, the anode of Zener diode D2, and the drain of PMOS transistor P8, and the source of PMOS transistor P8 is connected to the source of PMOS transistor P7. The source of PMOS transistor P6 is connected to the source of PMOS transistor P9, and the drain of PMOS transistor P6 is connected to the drain of NMOS transistor N8. The source of NMOS transistor N8 is connected to the source of NMOS transistor N5. Resistor R1 is connected between the source of NMOS transistor N8 and the gate of PMOS transistor P9. The junction of PMOS transistor P6 and NMOS transistor N8 is connected to the GATE terminal and one end of resistor R2. The other end of resistor R2 is connected to resistor R3, and the other end of resistor R3 is connected to the source of NMOS transistor N8. The junction of resistors R2 and R3 is connected to the gate of the PMOS transistor. In the logic control circuit, the input of inverter INV1 is connected to the DRV signal; the output of inverter INV1 is connected to the inputs of inverters INV2 and INV4; the output of inverter INV2 outputs the S1 signal; the output of inverter INV2 is connected to the input of inverter INV3; the output of inverter INV3 outputs the S2 signal; the output of inverter INV4 is connected to the input of inverter INV5; the output of inverter INV5 outputs the S3 signal; the output of inverter INV5 is connected to the input of inverter INV6; the output of inverter INV6 outputs the S4 signal. The gate of PMOS transistor P4 is connected to signal S3, the gate of NMOS transistor N3 is connected to signal S4, the gate of NMOS transistor N4 is connected to signal S1, the gate of NMOS transistor N5 is connected to signal S5, and the gate of NMOS transistor N8 is connected to signal S2. By changing the order of control signals S1~S4, a dead time is set between the pull-up drive transistor P6 and the pull-down drive transistor N8. When the input signal DRV goes high, after being delayed by logic gates INV8~INV13, signal S1 goes high first and signal S2 goes low, then signal S3 goes low and signal S4 goes high. For the two driver transistors P6 and N8, N8 is turned off first, and P6 is turned on later, which creates a dead time between the two driver transistors. When the input signal DRV goes low, after being delayed by the logic gates INV8~INV13, signal S3 goes high first and signal S4 goes low, then signal S1 goes low and signal S2 goes high. For the two driver transistors P6 and N8, P6 is turned off first and N8 is turned on later, which also introduces a dead time.

Images