Gate voltage regulating circuit for isolated power supply and isolated power supply

Abstract

The application relates to a gate voltage regulating circuit for an isolated power supply and the isolated power supply, and belongs to the field of integrated circuit design. The gate voltage regulating circuit detects a direct current input voltage and adjusts the gate voltage of an NMOS tube according to the input direct current voltage. The circuit is simple in realization and low in cost. The switch control circuit is used to control the closing and opening of the switch array, the connection relationship between the capacitor array and the NMOS tube is adjusted, the gate voltage regulation is realized, the capacitance value of the capacitor connected with the NMOS tube can be adjusted according to the change of the input direct current voltage, the primary side driving capability of the isolated power supply and the direct current voltage input width are ensured, and the influence on the load capacity of the isolated power supply is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to a gate voltage regulation circuit for an isolated power supply and an isolated power supply. Background Technology

[0002] like Figure 1 The diagram shows the primary-side LC resonant circuit of an isolated power supply, including two NMOS transistors (MN1, MN2), two oscillating capacitors (C1, C2), the primary side of a transformer (Lp1, Lp2), and the equivalent parasitic capacitances (Cg11 and Cg21) from the gate junctions of MN1 and MN2 to ground. The gate voltages (VG1, VG2) of MN1 and MN2 are shown in Equations 1 and 2, respectively.

[0003]

[0004]

[0005] In related technologies, to avoid the high input DC voltage VDD causing MN1 and MN2 to break down due to high gate voltage amplitude, the gate voltage is adjusted by detecting the peak voltages of Vp and Vn to regulate the gate voltage scaling factors (Cg11, Cg21, C1 and C2) of MN1 and MN2, thereby ensuring the DC voltage input width of the isolation power supply.

[0006] However, since Vp and Vn are AC voltages, it is difficult to implement circuits to detect their peak values, resulting in high costs for circuit implementation. If the gate voltage scaling factor of MN1 and MN2 is set to a specific value to ensure the DC voltage input width, since the current flowing through MN1 and MN2 is positively correlated with the gate voltage of MN1 and MN2, there is a situation where the primary-side driving capability of the isolation power supply is weak when the input DC voltage VDD is low, thus reducing the load-carrying capacity of the isolation power supply. Summary of the Invention

[0007] To address the shortcomings of existing gate voltage regulation methods, such as high circuit implementation costs or impact on the load-carrying capacity of isolated power supplies, this invention provides a gate voltage regulation circuit for isolated power supplies and an isolated power supply itself.

[0008] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0009] In a first aspect, the present invention provides a gate voltage regulation circuit for an isolated power supply, comprising a switch control circuit and a switched capacitor array for an external NMOS cross-coupled oscillator circuit, wherein the NMOS cross-coupled oscillator circuit includes an NMOS transistor, wherein:

[0010] The switched capacitor array includes a switch array and a first capacitor array. The first capacitor array is connected to an NMOS transistor through the switch array, and the switch array is connected to a switch control circuit.

[0011] A switch control circuit is used to adjust the gate voltage of an NMOS transistor by controlling the closing or opening of a switch array based on the input DC voltage.

[0012] The beneficial effects of this invention are: the switch control circuit adjusts the gate voltage of the NMOS transistor according to the input DC voltage, the circuit is simple to implement and low in cost, and the gate voltage is adjusted by controlling the switch array to close or open, thereby adjusting the connection relationship between the capacitor array and the NMOS transistor. This allows the capacitance value of the capacitor connected to the NMOS transistor to be adjusted according to the change of the input DC voltage, thereby ensuring the primary-side driving capability and DC voltage input width of the isolated power supply, and effectively avoiding the impact on the load-carrying capacity of the isolated power supply.

[0013] Based on the above technical solution, the present invention can be further improved as follows.

[0014] Furthermore, the switch array includes a first switch and a second switch, the first capacitor array includes a first capacitor and a second capacitor, and the NMOS transistor includes a first NMOS transistor and a second NMOS transistor, wherein:

[0015] One end of the first capacitor is connected to the drain of the second NMOS transistor, and the other end of the first capacitor is connected to the gate of the first NMOS transistor through the first switch.

[0016] One end of the second capacitor is connected to the drain of the first NMOS transistor, and the other end of the second capacitor is connected to the gate of the second NMOS transistor through the second switch.

[0017] The first switch and the second switch are respectively connected to the switch control circuit.

[0018] The beneficial effects of adopting the above-mentioned improvement scheme are: the switch control circuit uses the first switch and the second switch to adjust the connection state of the first capacitor, the second capacitor and the NMOS transistor respectively, so as to realize the gate voltage regulation of the first NMOS transistor and the second NMOS transistor, which can avoid the influence on the load-carrying capacity of the isolation power supply and effectively prevent the circuit from being damaged by the high input DC voltage.

[0019] Furthermore, the switch array includes a third switch and a fourth switch, the first capacitor array includes a third capacitor and a fourth capacitor, and the NMOS transistors include a first NMOS transistor and a second NMOS transistor, wherein:

[0020] One end of the third capacitor is connected to the gate of the first NMOS transistor, and the other end of the third capacitor is grounded through the third switch;

[0021] One end of the fourth capacitor is connected to the gate of the second NMOS transistor, and the other end of the fourth capacitor is grounded through the fourth switch;

[0022] The third and fourth switches are respectively connected to the switch control circuit.

[0023] The beneficial effects of adopting the above-mentioned improvement scheme are: the switch control circuit uses the third switch and the fourth switch to adjust the connection state of the third capacitor, the fourth capacitor and the NMOS transistor respectively, so as to realize the gate voltage regulation of the first NMOS transistor and the second NMOS transistor, which can avoid the influence on the load-carrying capacity of the isolation power supply and effectively prevent the circuit from being damaged by the high input DC voltage.

[0024] Furthermore, the switched capacitor array also includes a second capacitor array, which comprises a first oscillating capacitor, a second oscillating capacitor, a third oscillating capacitor, and a fourth oscillating capacitor, wherein:

[0025] The drain of the first NMOS transistor is connected to the gate of the second NMOS transistor through the second oscillation capacitor, and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor through the first oscillation capacitor.

[0026] The source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is grounded through the third oscillation capacitor;

[0027] The source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is grounded through the fourth oscillation capacitor.

[0028] The beneficial effect of adopting the above-mentioned improvement scheme is that by setting a second capacitor array directly connected to the NMOS transistor in the gate voltage regulation circuit, the gate voltage regulation function based on the connection relationship of the first capacitor array circuit can be further guaranteed.

[0029] Furthermore, the switching control circuit includes a proportional voltage divider circuit, a comparison adjustment circuit, and a reference circuit, wherein:

[0030] The proportional voltage divider circuit and the reference circuit are respectively connected to the comparison adjustment circuit, which is also connected to the switch array.

[0031] A proportional voltage divider circuit is used to divide the input DC voltage to obtain a divided voltage.

[0032] The comparison adjustment circuit is used to control the switch array to close or open based on the voltage divided by the proportional voltage divider circuit and the reference voltage output by the reference circuit.

[0033] The beneficial effects of adopting the above-mentioned improved scheme are: the comparison and adjustment circuit realizes reasonable control of the switching array based on the divided DC voltage and the reference voltage, thereby realizing the automatic gate voltage adjustment function based on the input DC voltage.

[0034] Further, the comparison and regulation circuit includes a plurality of voltage comparators, and the number of voltage comparators is the same as the number of switches in the switch array, where:

[0035] The output terminal of each voltage comparator is respectively connected to each switch in the switch array, and the proportional voltage division circuit and the reference circuit are respectively connected to the input terminal of each voltage comparator.

[0036] The beneficial effect of adopting the above improvement scheme is that the voltage comparator is used to precisely control each switch, which can further improve the reliability of the gate voltage regulation function.

[0037] Further, the proportional voltage division circuit includes at least two resistors connected in series, and a common connection point is formed when every two resistors connected in series are connected. The common connection point is used as the output terminal of the proportional voltage division circuit;

[0038] The input terminal of each voltage comparator is respectively connected to the output terminal of the proportional voltage division circuit.

[0039] The beneficial effect of adopting the above improvement scheme is that the proportional voltage division circuit is formed based on the resistor voltage division network, and the structure is simple and easy to implement.

[0040] Further, according to the input DC voltage, by controlling the switch array to be closed or opened, the gate voltage of the NMOS transistor is regulated, including:

[0041] In response to VDD*π < Vwork, controlling each switch in the switch array to be closed or opened to increase the gate voltage of the NMOS transistor;

[0042] In response to VDD*π > Vwork, controlling each switch in the switch array to be closed or opened to decrease the gate voltage of the NMOS transistor;

[0043] Where, VDD represents the DC voltage, Vwork represents the gate operating voltage of the NMOS transistor, and π represents the pi.

[0044] The beneficial effect of adopting the above improvement scheme is that the gate operating voltage of the NMOS transistor is used to measure the level of the input DC voltage, so as to reasonably control the switches of the switched-capacitor array, thereby improving the reliability of the gate voltage regulation method based on the DC voltage.

[0045] In a second aspect, the present invention provides an isolated power supply, including an NMOS cross-coupled oscillation circuit, an isolation transfer transformer, and a gate voltage regulation circuit for the isolated power supply as described in the first aspect. The NMOS cross-coupled oscillation circuit is respectively connected to the gate voltage regulation circuit and the isolation transfer transformer.

[0046] Furthermore, it also includes a rectifier filter circuit, a logic drive circuit, and a feedback control circuit, wherein:

[0047] The primary winding of the isolation transmission transformer is connected to an external DC voltage source. The primary winding is also connected to the drain of the NMOS transistor in the NMOS cross-coupled oscillator circuit. The external DC voltage source is used to input DC voltage to the isolation power supply.

[0048] The secondary coil of the isolation transmission transformer is connected to the rectifier and filter circuit;

[0049] The rectifier and filter circuit is connected to the logic drive circuit through the feedback control circuit, and the logic drive circuit is connected to the gate of the NMOS transistor.

[0050] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the primary-side LC resonant circuit of an existing isolated power supply.

[0053] Figure 2 This is a schematic diagram of a gate voltage regulation circuit for an isolated power supply provided in one embodiment of the present invention;

[0054] Figure 3 A schematic diagram of a primary-side LC resonant circuit with a gate voltage regulation control circuit provided in an embodiment of the present invention;

[0055] Figure 4 A schematic diagram of a primary-side LC resonant circuit with a gate voltage regulation control circuit is provided for another embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of the structure of an isolated power supply provided in one embodiment of the present invention;

[0057] Figure 6 A schematic diagram of the structure of an isolated power supply provided in another embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of a proportional voltage divider circuit provided in one embodiment of the present invention;

[0059] Figure 8 This is a schematic diagram of the structure of a comparison adjustment circuit provided in one embodiment of the present invention;

[0060] Figure 9 This is a schematic diagram of a proportional voltage divider circuit provided in another embodiment of the present invention;

[0061] Figure 10 This is a schematic diagram of the comparison adjustment circuit provided in another embodiment of the present invention.

[0062] The attached diagram lists the components represented by each number as follows:

[0063] 10. Switch control circuit; 20. Switched capacitor array; 101. Proportional voltage divider circuit; 102. Comparison and adjustment circuit; 103. Reference circuit; 200. Switch array; 201. First capacitor array. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] Reference Figure 2 As shown, Figure 2 This embodiment provides a gate voltage regulation circuit for an isolated power supply, including a switch control circuit 10 and a switched capacitor array 20 for connecting an external NMOS cross-coupled oscillation circuit. The NMOS cross-coupled oscillation circuit includes an NMOS transistor, wherein:

[0066] The switched capacitor array 20 includes a switch array 200 and a first capacitor array 201. The first capacitor array 201 is connected to an NMOS transistor through the switch array 200, and the switch array 200 is connected to the switch control circuit 10.

[0067] The switch control circuit 10 is used to adjust the gate voltage of the NMOS transistor by controlling the closing or opening of the switch array 200 according to the input DC voltage.

[0068] It should be noted that the isolated power supply includes a primary-side LC resonant circuit, an isolation transmission transformer, and a secondary-side receiving circuit. The primary-side LC resonant circuit is used to convert the DC power input into AC power, and the isolation transmission transformer transmits the converted AC power to the secondary-side receiving circuit, thereby achieving isolated output.

[0069] Among them, the primary LC resonance circuit in this embodiment is a NMOS cross-coupled oscillation circuit, which includes two cross-connected NMOS transistors, as well as an oscillation inductor and an oscillation capacitor connected to the two NMOS transistors. The oscillation inductor uses the primary coil of an isolation transformer.

[0070] In this embodiment, the switch control circuit 10 controls the switch array 200 to be closed or opened according to the input DC voltage, so as to adjust the connection relationship between the first capacitor array 201 and the NMOS transistor, so that the capacitance value of the capacitor connected to the NMOS transistor can be adjusted according to the change of the input DC voltage, thereby adjusting the gate voltage of the NMOS transistor. Its circuit implementation is simple and low-cost, can effectively avoid circuit damage such as NMOS transistor breakdown, and ensure the load-carrying capacity of the isolated power supply.

[0071] As a possible implementation, the above-mentioned adjusting the gate voltage of the NMOS transistor by controlling the closing or opening of the switch array 200 according to the input DC voltage includes:

[0072] In response to VDD*π<Vwork, control each switch in the switch array 200 to be closed or opened to increase the gate voltage of the NMOS transistor;

[0073] In response to VDD*π>Vwork, control each switch in the switch array 200 to be closed or opened to decrease the gate voltage of the NMOS transistor;

[0074] Among them, VDD represents the DC voltage, Vwork represents the gate operating voltage of the NMOS transistor, and π represents the pi.

[0075] In this embodiment, first detect the DC voltage VDD, and calculate the product of the DC voltage VDD and the pi π, and compare this product with the gate operating voltage Vwork of the NMOS transistor to measure the magnitude of the input DC voltage VDD. When VDD*π<Vwork, it means that the input DC voltage VDD is small. At this time, the switch array 200 should be controlled to increase the gate voltage of the NMOS transistor, so that the gate voltage of the NMOS transistor is close to the gate operating voltage Vwork to improve the load-carrying capacity of the isolated power supply; when VDD*π>Vwork, it means that the input DC voltage VDD is large. At this time, the switch array 200 should be controlled to decrease the gate voltage of the NMOS transistor to avoid the gate voltage of the NMOS transistor being too high, resulting in circuit damage such as NMOS breakdown.

[0076] It can be understood that, as Figure 1As shown, when the primary-side LC resonant circuit is in resonance, the waveform of Vp or Vn in the circuit is a sinusoidal signal. Therefore, by calculating the product of the DC voltage VDD and π, the peak voltages of Vp and Vn can be reasonably estimated. Based on this estimated peak voltage, it is compared with the set gate operating voltage Vwork. The gate operating voltage Vwork can also be replaced with other set values ​​as needed. By comparing VDD with the set value, the level of the input DC voltage VDD can be reasonably measured, thereby further improving the reliability of the gate voltage regulation method based on DC voltage.

[0077] As one possible implementation, the operator can manually control the switch array based on the observed DC voltage VDD to bring the gate voltage of the NMOS transistor close to the gate operating voltage Vwork.

[0078] Optionally, in one embodiment, such as Figure 3 As shown, the switch array 200 includes a first switch S1 and a second switch S2, the first capacitor array 201 includes a first capacitor C12 and a second capacitor C22, and the NMOS transistors include a first NMOS transistor MN1 and a second NMOS transistor MN2, wherein:

[0079] One end of the first capacitor C12 is connected to the drain of the second NMOS transistor MN2, and the other end of the first capacitor C12 is connected to the gate of the first NMOS transistor MN1 through the first switch S1.

[0080] One end of the second capacitor C22 is connected to the drain of the first NMOS transistor MN1, and the other end of the second capacitor C22 is connected to the gate of the second NMOS transistor MN2 through the second switch S2.

[0081] The first switch S1 and the second switch S2 are respectively connected to the switch control circuit 10.

[0082] In this embodiment, when the input DC voltage VDD is lower than the set value, switches S1 and S2 are closed, the first capacitor C12 is connected to the gate of the first NMOS transistor MN1 to increase the gate voltage of the first NMOS transistor MN1, and the second capacitor C22 is connected to the gate of the second NMOS transistor MN2 to increase the gate voltage of the second NMOS transistor MN1, thereby improving the load-carrying capacity of the isolated power supply. When the input DC voltage VDD is higher than the set value, switches S1 and S2 are opened, the connection between the first capacitor C12 and the gate of the first NMOS transistor MN1 is broken to decrease the gate voltage of the first NMOS transistor MN1, and the connection between the second capacitor C22 and the gate of the second NMOS transistor MN2 is broken to decrease the gate voltage of the second NMOS transistor MN1, thereby preventing the first NMOS transistor MN1 and the second NMOS transistor MN2 from being broken down.

[0083] Understandably, according to formulas 1 and 2, to ensure the gate voltage regulation function of the switch and capacitor connected in series between the gate of one NMOS transistor and the drain of another, at least one oscillating capacitor (such as Cg1 or Cg2) can be set between the gate node and ground of each NMOS transistor. This oscillating capacitor can be freely set according to actual needs. For example, a variable capacitor or a capacitor connected in series with the switch can be used as the oscillating capacitor. Thus, by adjusting the capacitance value or circuit connection state of the oscillating capacitor, and by adjusting the circuit connection state of the first capacitor C12 and the second capacitor C22, the gate voltage of each NMOS transistor can be regulated together.

[0084] Considering that there is always mutual capacitance between the wiring in the existing circuit, that is, each NMOS transistor (MN1, MN2) actually has an equivalent parasitic capacitance from the gate node to ground. This equivalent parasitic capacitance can also ensure the gate voltage regulation function of the switch array 200 and the first capacitor array 201. Therefore, in actual use, it is not necessary to set an additional oscillation capacitor between the gate node and ground of the NMOS transistor, thereby simplifying the circuit structure.

[0085] In one possible implementation, the switch array 200 and the first capacitor array 201 may include multiple switches and capacitors. Multiple series-connected switches and capacitors are connected in parallel with the series-connected first capacitor C12 and first switch S1 or the series-connected second capacitor C22 and second switch S2, respectively. By controlling the closing or opening of at least one switch (such as switch S1) corresponding to the first NMOS transistor MN1 and at least one switch (such as switch S2) corresponding to the second NMOS transistor MN2 in the switch array 200, the gate voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 can be adjusted. Thus, by adjusting the number of switches in the switch array that are in the closed or open state, the gate voltage of the NMOS transistor can be precisely adjusted.

[0086] The first capacitor C12 and the second capacitor C22 can be variable capacitors. By adjusting the capacitance values ​​of the first capacitor C12 and the second capacitor C22 connected to the gate of the NMOS transistor, the gate voltage regulation accuracy of the NMOS transistor can be further improved.

[0087] Optionally, in one embodiment, such as Figure 4 As shown, the switch array 200 includes a third switch S3 and a fourth switch S4, the first capacitor array 201 includes a third capacitor C3 and a fourth capacitor C4, and the NMOS transistors include a first NMOS transistor MN1 and a second NMOS transistor MN2, wherein:

[0088] One end of the third capacitor C3 is connected to the gate of the first NMOS transistor MN1, and the other end of the third capacitor C3 is grounded through the third switch S3.

[0089] One end of the fourth capacitor C4 is connected to the gate of the second NMOS transistor MN2, and the other end of the fourth capacitor C4 is grounded through the fourth switch S4;

[0090] The third switch C3 and the fourth switch S4 are respectively connected to the switch control circuit 10.

[0091] In this embodiment, when the input DC voltage VDD is lower than the set value, switches S3 and S4 are opened, the third capacitor C3 is disconnected from the gate of the first NMOS transistor MN1, thereby increasing the gate voltage of the first NMOS transistor MN1, and the fourth capacitor C4 is disconnected from the gate of the second NMOS transistor MN2, thereby increasing the gate voltage of the second NMOS transistor MN2, thus improving the load-carrying capacity of the isolated power supply. When the input DC voltage VDD is higher than the set value, switches S3 and S4 are closed, the third capacitor C3 is connected to the gate of the first NMOS transistor MN1, thereby decreasing the gate voltage of the first NMOS transistor MN1, and the fourth capacitor C4 is connected to the gate of the second NMOS transistor MN2, thereby decreasing the gate voltage of the second NMOS transistor MN1, thus preventing the first NMOS transistor MN1 and the second NMOS transistor MN2 from being broken down.

[0092] Understandably, according to formulas 1 and 2, to ensure the gate voltage regulation function of the switch and capacitor connected in series between the gate and ground of the NMOS transistor, at least one oscillating capacitor (such as C1 or C2) can be connected to the gate of each NMOS transistor. The two ends of this oscillating capacitor are connected to the gate of one NMOS transistor and the drain of another, respectively. This oscillating capacitor can be freely set according to actual needs. For example, a variable capacitor or a capacitor connected in series with the switch can be used as the oscillating capacitor. Thus, by adjusting the capacitance value or circuit connection state of the oscillating capacitor, and by adjusting the circuit connection state of the third capacitor C3 and the fourth capacitor C4, the gate voltage of each NMOS transistor can be regulated together.

[0093] In one possible implementation, the switch array 200 and the first capacitor array 201 may include multiple switches and capacitors. Multiple series-connected switches and capacitors are connected in parallel with a series-connected third capacitor C3 and third switch S3 or a series-connected fourth capacitor C4 and fourth switch S4, respectively. By controlling the closing or opening of at least one switch (such as switch S3) corresponding to a first NMOS transistor MN1 and at least one switch (such as switch S4) corresponding to a second NMOS transistor MN2 in the switch array 200, the gate voltages of the first NMOS transistor MN1 and the second NMOS transistor can be adjusted. Thus, by adjusting the number of switches in the switch array that are in the closed or open state, the gate voltage of the NMOS transistor can be precisely adjusted.

[0094] Among them, the third capacitor C3 and the fourth capacitor C4 can be variable capacitors. By adjusting the capacitance values of the third capacitor C3 and the fourth capacitor C4 connected to the gate of the NMOS transistor, the regulation accuracy of the gate voltage of the NMOS transistor can be further improved.

[0095] Optionally, as Figure 3 or Figure 4 shown, the switched capacitor array 20 further includes a second capacitor array. The second capacitor array includes a first oscillating capacitor C11, a second oscillating capacitor C21, a third oscillating capacitor Cg1, and a fourth oscillating capacitor Cg2, where:

[0096] The drain of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2 through the second oscillating capacitor C21, and the drain of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1 through the first oscillating capacitor C11;

[0097] The source of the first NMOS transistor MN1 is grounded, and the gate of the first NMOS transistor MN1 is grounded through the third oscillating capacitor Cg1;

[0098] The source of the second NMOS transistor MN2 is grounded, and the gate of the second NMOS transistor MN2 is grounded through the fourth oscillating capacitor Cg2.

[0099] As a possible implementation manner, as Figure 3 shown, at this time, the gate voltages VG3 and VG4 of MN1 and MN2 are respectively as shown in Formulas 3 and 4:

[0100]

[0101]

[0102] When the input DC voltage VDD is small, for example, when VDD*π < Vwork is satisfied, the switch control circuit outputs a signal to control S1 and S2 to be all closed. According to Formulas 3 and 4, by connecting C12 and C22 to the gate of the NMOS transistor, the gate voltages of MN1 and MN2 are made close to π*VDD. Since the current flowing through MN1 and MN2 is positively correlated with the gate voltages of MN1 and MN2, on the basis of ensuring that the gate voltage is within the gate operating voltage range, the capacitance values of C12 and C22 can be adjusted to the maximum value to make the primary driving ability of the isolated power supply the largest, and thus the load-carrying ability of the isolated power supply is the largest.

[0103] When the input voltage VDD is relatively large, for example, when VDD*π > Vwork is satisfied, the output signal of the switch control circuit controls the switches of S1 and S2 to be disconnected. According to Formulas 3 and 4, it can be known that at this time, the gate voltage of the NMOS transistor decreases, which can avoid the gate voltages of MN1 and MN2 from being too high and being broken down. If there are multiple series-connected structures of switched capacitors in parallel between the gate of one NMOS transistor and the drain of another NMOS transistor, the switches in the switch array (such as C12 and C22) can also be correspondingly controlled to be closed. By reasonably setting the capacitance values of C12 and C22, the gate voltages of MN1 and MN2 can be maintained within a certain range of Vwork, thereby ensuring the load-carrying capacity of the isolated power supply.

[0104] Exemplarily, assume that the input DC voltage varies within the range of 3 - 5V, the load-carrying capacity requirement of the isolated power supply is 60mA, and the gate operating voltage of the NMOS transistors MN1 and MN2 is 5V. When the input DC voltage is 3V, according to Formulas 3 and 4, by connecting C12 and C22 to the gates of the NMOS transistors and reasonably setting their capacitance values, the gate voltages of MN1 and MN2 are made close to 5V, avoiding MN1 and MN2 from being broken down. When the input voltage is 5V, according to Formulas 3 and 4, by controlling all the switches in the switch array to be disconnected or some switches to be closed, and reducing the capacitance values of the capacitors connected to the closed switches, the gate voltages of MN1 and MN2 are still made close to 5V, avoiding MN1 and MN2 from being broken down. Therefore, when the input DC voltage is 3V and 5V, the load-carrying capacity of the isolated power supply can be ensured to reach 60mA. Thus, when the input DC voltage VDD varies within a certain range, the gate voltage adjustment circuit with the above structure can both ensure the load-carrying capacity of the isolated power supply and avoid the circuit from being broken down and damaged.

[0105] As a possible implementation, as Figure 4 shown, the gate voltages VG5 and VG6 of MN1 and MN2 are respectively as shown in Formulas 5 and 6:

[0106]

[0107]

[0108] When the input DC voltage VDD is relatively small, for example, when VDD*π < Vwork is satisfied, the output signal of the switch control circuit controls S3 and S4 to be in the off state. According to Formulas 5 and 6, it can be known that the gate voltages of MN1 and MN2 can be increased to make them close to π*VDD.

[0109] When the input DC voltage VDD is large, for example, if VDD*π>Vwork, the switch control circuit controls S3 and S4 to be in the closed state. According to formulas 5 and 6, by reasonably setting the capacitance values ​​of C3 and C4 connected to the circuit, the capacitance values ​​of C3 and C4 can be adjusted to the minimum value while ensuring circuit safety. Since the current flowing through MN1 and MN2 is positively correlated with the gate voltage of MN1 and MN2, the isolation power supply still has a large load-carrying capacity, and the gate voltage of MN1 and MN2 is close to Vwork, avoiding excessive gate voltage and breakdown of NMOS transistors MN1 and MN2.

[0110] In this embodiment, such as Figure 3 and Figure 4 As shown, the switch control circuit 10 is connected to the control terminals of each switch in the switch array 200, which enables precise control of the closing or opening of each switch, making the gate voltage regulation of the NMOS transistor more accurate.

[0111] Optionally, in one embodiment, such as Figure 5 or Figure 6 As shown, the switch control circuit 10 includes a proportional voltage divider circuit 101, a comparison adjustment circuit 102, and a reference circuit 103, wherein:

[0112] The proportional voltage divider circuit 101 and the reference circuit 103 are respectively connected to the comparison adjustment circuit 102, which is also connected to the switch array 200.

[0113] The proportional voltage divider circuit 101 is used to divide the input DC voltage to obtain a divided voltage;

[0114] The comparison adjustment circuit 102 is used to control the switch array 200 to close or open based on the voltage divided by the proportional voltage divider circuit 101 and the reference voltage output by the reference circuit 103.

[0115] In this embodiment, the proportional voltage divider circuit 101 divides the input DC voltage VDD to obtain a divided voltage VDIV. The divided voltage VDIV and the reference voltage VREF provided by the reference circuit 103 are jointly input to the comparison and adjustment circuit 102. The comparison and adjustment circuit 102 compares the two voltages and outputs a signal to control the state of each switch in the switch array 200. Each switch in the switch array 200 should be a switch capable of changing its conduction state according to the signal output by the comparison and adjustment circuit 102.

[0116] As one possible implementation, the switches in the switch array 200 are selected as MOSFET switches.

[0117] Since the input DC voltage VDD is detected, the voltage detection circuit used in this embodiment is easy to implement. The proportional voltage divider circuit 101 can precisely divide VDD as needed. The divided voltage VDIV and the reference voltage VREF are compared and adjusted by a signal output from the circuit to precisely regulate the state of switches (such as S1 and S2). This ensures the load-carrying capacity of the isolated power supply when the input DC voltage VDD is low, and prevents MN1 and MN2 from breaking down when the input DC voltage VDD is high.

[0118] In one possible implementation, the comparison regulation circuit 102 includes a plurality of voltage comparators, the number of which is the same as the number of switches in the switch array 200, wherein:

[0119] The output of each voltage comparator is connected to each switch in the switch array 200, and the proportional voltage divider circuit 101 and the reference circuit 103 are connected to the input of each voltage comparator.

[0120] In this embodiment, the proportional voltage divider circuit 101 can employ a resistor divider network (such as...) Figure 7 The circuit is constructed by connecting R1 to Rn+1 in series. VDD is divided into multiple voltages (VDIV1 to VDIVn) and then input to the input of each voltage comparator.

[0121] Among them, such as Figure 8 As shown, the comparison adjustment circuit 102 is implemented by multiple comparators. The number of comparators is the same as the number of switches in the switch array 200. Each comparator compares the input voltage divider (VDIV1 to VDIVn) with the reference voltage VREF and outputs a signal to control the corresponding switch state.

[0122] Optionally, the proportional voltage divider circuit 101 includes at least two resistors connected in series, and each pair of resistors connected in series forms a common contact point, which is used as the output terminal of the proportional voltage divider circuit 101.

[0123] The input of each voltage comparator is connected to the output of the proportional voltage divider circuit 101.

[0124] For example, such as Figure 7 As shown, resistors R1 to Rn+1 are connected in series to divide VDD into n parts, resulting in n voltage dividers from VDIV1 to VDIVn. One end of the first resistor R1 is used to receive the input DC voltage VDD, and one end of the last resistor Rn+1 is connected to ground. The output voltage VDIVk of each output terminal of the proportional voltage divider circuit is shown in Equation 7.

[0125]

[0126] Where Ri represents the resistance value of the i-th resistor, k represents the output number of the output terminal used to output VDIVk, the comparison and adjustment circuit is implemented by n comparators, and the number of switches in the switch array is also n. Each comparator compares the divided voltage VDIVk with the reference voltage VREF and outputs a signal to control the state of the corresponding switch. Since VDD is a DC voltage and the divided voltage VDIVk is also a DC voltage, it is convenient for the comparators to perform comparison processing.

[0127] As one possible implementation method, such as Figure 8 As shown, multiple sets of switched capacitors are connected in series. Any set of switched capacitors in series (such as C12A, S1A and C22A, S2A) is connected to the gates of two NMOS transistors in the same way. For example, C12A and S1A are connected to MN1, and C22A and S2A are connected to MN2. A comparator is used to control the resistors in the series structure of the same set of switched capacitors, thereby reducing the number of comparators and further simplifying the circuit structure.

[0128] As one possible implementation, such as Figure 9 and Figure 10 As shown, resistors R1 and R2 are connected in series. One end of R1 is used for the input DC voltage VDD, and one end of resistor R2 is connected to ground. The output voltage of the proportional voltage divider circuit is shown in Formula 8.

[0129]

[0130] At this point, n reference voltages are set, namely VREF1 to VREFn. The comparison and adjustment circuit is implemented by n comparators. The number of switches in the switch array is n. The same voltage divider voltage VDIV and different reference voltage VREFk (VREFk represents any one of the voltages from VREF1 to VREFn) are input to each comparator, so that the corresponding voltage divider voltage VDIV and the corresponding reference voltage VREFk are compared by each comparator, and the corresponding control signal is output to control the state of the corresponding switches S1k and S2k.

[0131] like Figure 5 and Figure 6 As shown, the present invention also provides an isolated power supply, including an NMOS cross-coupled oscillation circuit, an isolation transmission transformer, and a gate voltage regulation circuit for the isolated power supply as described in the above embodiments. The NMOS cross-coupled oscillation circuit is connected to the gate voltage regulation circuit and the isolation transmission transformer, respectively.

[0132] In this embodiment, the isolated power supply circuit includes a cross-coupled oscillator circuit with an NMOS transistor (NMOS cross-coupled oscillator circuit), an isolated transmission transformer, and a switch control circuit. The NMOS cross-coupled oscillator circuit is used to convert the input DC voltage VDD into an AC voltage at a certain frequency. The AC voltage is applied to the primary coil of the isolated transmission transformer to generate an AC current and a changing magnetic field. After coupling through the isolated transmission transformer, an AC voltage is induced in the secondary coil, thereby realizing the isolated output function of the isolated power supply.

[0133] For example, the oscillation inductor of the cross-coupled oscillator circuit with NMOS transistors can be implemented using the primary winding of an isolation transmission transformer. The primary winding adopts a center-tapped structure, with the center tap connected to an external DC voltage source. One end of the primary winding is connected to the drain of one NMOS transistor, and the other end is connected to the drain of another NMOS transistor. The isolation power supply includes C11, C21, Cg1, Cg2, C12, and C22 as oscillation capacitors. C12 and C22 are connected in parallel across C11 and C21 via switches S1 and S2, respectively. Each switch in the switch array 200 corresponds to one capacitor, and C12 and C22 are selected as capacitors with adjustable capacitance values.

[0134] Alternatively, C3 and C4 can be connected in parallel across Cg1 and Cg2 via switches S3 and S4 respectively, thereby achieving the gate voltage regulation function.

[0135] Optionally, it may also include a rectifier filter circuit, a logic drive circuit, and a feedback control circuit, wherein:

[0136] The primary winding of the isolation transmission transformer is connected to an external DC voltage source. The primary winding is also connected to the drain of the NMOS transistor in the NMOS cross-coupled oscillator circuit. The external DC voltage source is used to input DC voltage VDD to the isolation power supply.

[0137] The secondary coil of the isolation transmission transformer is connected to the rectifier and filter circuit;

[0138] The rectifier and filter circuit is connected to the logic drive circuit through the feedback control circuit, and the logic drive circuit is connected to the gate of the NMOS transistor.

[0139] In this embodiment, the isolated power supply includes an NMOS cross-coupled oscillator circuit, an isolation transmission transformer, a rectifier and filter circuit, a proportional voltage divider circuit, a reference circuit, a comparison and adjustment circuit, and a logic drive circuit. The feedback control circuit includes a modulation circuit and an isolator circuit. The NMOS cross-coupled oscillator circuit converts the DC voltage VDD of the input isolated power supply into an AC voltage at a certain frequency. This AC voltage is applied to the primary coil of the isolation transmission transformer to generate an AC current and a changing magnetic field. After coupling through the isolation transmission transformer, an AC voltage is induced in the secondary coil. The AC voltage is converted into a DC voltage VISO after passing through the rectifier and filter circuit. The modulation circuit and the isolator circuit are used to achieve stable closed-loop control of the output voltage.

[0140] The gate voltage regulation circuit and isolation power supply described above regulate the gate voltage of the NMOS transistor based on the input DC voltage. The circuit implementation is simple and low-cost. Furthermore, the gate voltage regulation is achieved by using a switch control circuit to control the closing or opening of the switch array, thereby adjusting the connection between the capacitor array and the NMOS transistor. This allows the capacitance value of the capacitors connected to the NMOS transistor to be adjusted according to changes in the input DC voltage, thus ensuring the primary-side driving capability and DC voltage input width of the isolation power supply and effectively avoiding any impact on the load-carrying capacity of the isolation power supply.

[0141] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A gate voltage regulation circuit for an isolated power supply, characterized in that, It includes a switch control circuit and a switched-capacitor array for externally connecting an NMOS cross-coupled oscillator circuit. The NMOS cross-coupled oscillator circuit includes NMOS transistors, where: The switched-capacitor array includes a switch array and a first capacitor array. The first capacitor array is connected to the NMOS transistors through the switch array, and the switch array is connected to the switch control circuit; The switch control circuit is configured to adjust the gate voltage of the NMOS transistors by controlling the closing or opening of the switch array according to an input DC voltage; Adjusting the gate voltage of the NMOS transistors by controlling the closing or opening of the switch array according to the input DC voltage includes: In response to VDD*π < Vwork, controlling each switch in the switch array to close or open to increase the gate voltage of the NMOS transistors; In response to VDD*π > Vwork, controlling each switch in the switch array to close or open to decrease the gate voltage of the NMOS transistors; Where, VDD represents the DC voltage, Vwork represents the gate operating voltage of the NMOS transistors, and π represents pi.

2. The gate voltage regulation circuit for an isolated power supply according to claim 1, characterized in that, The switch array includes a first switch and a second switch. The first capacitor array includes a first capacitor and a second capacitor. The NMOS transistors include a first NMOS transistor and a second NMOS transistor, where: One end of the first capacitor is connected to the drain of the second NMOS transistor, and the other end of the first capacitor is connected to the gate of the first NMOS transistor through the first switch; One end of the second capacitor is connected to the drain of the first NMOS transistor, and the other end of the second capacitor is connected to the gate of the second NMOS transistor through the second switch; The first switch and the second switch are respectively connected to the switch control circuit.

3. The gate voltage regulation circuit for an isolated power supply according to claim 1, characterized in that, The switch array includes a third switch and a fourth switch. The first capacitor array includes a third capacitor and a fourth capacitor. The NMOS transistors include a first NMOS transistor and a second NMOS transistor, where: One end of the third capacitor is connected to the gate of the first NMOS transistor, and the other end of the third capacitor is grounded through the third switch; One end of the fourth capacitor is connected to the gate of the second NMOS transistor, and the other end of the fourth capacitor is grounded through the fourth switch; The third switch and the fourth switch are respectively connected to the switch control circuit.

4. The gate voltage regulation circuit for an isolated power supply according to claim 2 or 3, characterized in that, The switched-capacitor array further includes a second capacitor array. The second capacitor array includes a first oscillation capacitor, a second oscillation capacitor, a third oscillation capacitor, and a fourth oscillation capacitor, where: The drain of the first NMOS transistor is connected to the gate of the second NMOS transistor through the second oscillation capacitor, and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor through the first oscillation capacitor; The source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is grounded through the third oscillation capacitor; ​ 5. The gate voltage regulation circuit for an isolated power supply according to claim 1, characterized in that, The switching control circuit includes a proportional voltage divider circuit, a comparison adjustment circuit, and a reference circuit, wherein: The proportional voltage divider circuit and the reference circuit are respectively connected to the comparison adjustment circuit, and the comparison adjustment circuit is also connected to the switch array; The proportional voltage divider circuit is used to divide the input DC voltage to obtain a divided voltage. The comparison adjustment circuit is used to control the switch array to close or open based on the voltage divided by the proportional voltage divider circuit and the reference voltage output by the reference circuit.

6. The gate voltage regulation circuit for an isolated power supply according to claim 5, characterized in that, The comparison and adjustment circuit includes multiple voltage comparators, the number of which is the same as the number of switches in the switch array, wherein: The output of each voltage comparator is connected to each switch in the switch array, and the proportional voltage divider circuit and the reference circuit are connected to the input of each voltage comparator.

7. The gate voltage regulation circuit for an isolated power supply according to claim 6, characterized in that, The proportional voltage divider circuit includes at least two resistors connected in series, and each pair of resistors connected in series forms a common connection point, which is used as the output terminal of the proportional voltage divider circuit. The input terminal of each voltage comparator is connected to the output terminal of the proportional voltage divider circuit.

8. An isolated power supply, characterized in that, The device includes an NMOS cross-coupled oscillator circuit, an isolation transmission transformer, and a gate voltage regulation circuit for an isolated power supply as described in any one of claims 1 to 7, wherein the NMOS cross-coupled oscillator circuit is connected to the gate voltage regulation circuit and the isolation transmission transformer, respectively.

9. The isolated power supply according to claim 8, characterized in that, It also includes rectifier filter circuits, logic drive circuits, and feedback control circuits, among which: The primary winding of the isolation transmission transformer is connected to an external DC voltage source, and the primary winding is also connected to the drain of the NMOS transistor in the NMOS cross-coupled oscillation circuit. The external DC voltage source is used to input DC voltage to the isolation power supply. The secondary coil of the isolation transmission transformer is connected to the rectifier filter circuit; The rectifier filter circuit is connected to the logic drive circuit through the feedback control circuit, and the logic drive circuit is connected to the gate of the NMOS transistor.

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