operational amplifier

Abstract

This invention discloses an operational amplifier, including an input stage circuit, an intermediate stage circuit, an output stage circuit, and a bias circuit. The input stage circuit includes a first differential pair transistor, which amplifies the input signal. Since the first differential pair transistor can eliminate noise when amplifying differential signals, it can effectively reduce noise and reduce the interference of external noise on the operational amplifier. The first differential pair transistor can also reduce the offset voltage, thereby reducing the impact of offset voltage on the operational amplifier. The bias circuit provides bias current to the input stage circuit, intermediate stage circuit, and output stage circuit to ensure the normal operation of the input stage circuit, intermediate stage circuit, and output stage circuit. The input stage circuit, intermediate stage circuit, and output stage circuit realize three-stage amplification of the input differential signal, thereby achieving high gain of the operational amplifier. Therefore, the operational amplifier of this invention can effectively reduce noise, reduce offset voltage, and achieve high gain.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, and more particularly to an operational amplifier. Background Technology

[0002] In analog circuits, operational amplifiers are widely used for signal acquisition, amplification, and computation. When designing operational amplifiers, it is necessary to consider effects such as low power consumption, high gain, low noise, and low offset. Currently, the design of operational amplifiers often employs complex chopping and automatic zeroing techniques, resulting in complex structures. Furthermore, traditional two-stage amplifiers are difficult to achieve high gain and simultaneously achieve high gain, low noise, and low offset. Summary of the Invention

[0003] The purpose of this invention is to provide an operational amplifier that can effectively reduce noise, reduce offset voltage, and achieve high gain.

[0004] To achieve the above objectives, the present invention provides an operational amplifier, comprising:

[0005] The input stage circuit includes a first differential pair transistor, which is used to receive a first voltage signal and a second voltage signal. The first voltage signal and the second voltage signal are differential signals, and the first differential pair transistor is used to amplify the first voltage signal and the second voltage signal.

[0006] An intermediate stage circuit, wherein the input terminal of the intermediate stage circuit is connected to the output terminal of the input stage circuit, is used to amplify the output signal of the input stage circuit;

[0007] An output stage circuit, wherein the input terminal of the output stage circuit is connected to the output terminal of the intermediate stage circuit, and the output stage circuit is used to amplify the output signal of the intermediate stage circuit; and

[0008] A bias circuit is provided to provide bias current to the input stage circuit, the intermediate stage circuit, and the output stage circuit.

[0009] Optionally, the input stage circuit further includes a first transistor for providing bias current to the first differential pair transistors, the first differential pair transistors including a second transistor and a third transistor.

[0010] The control terminal of the first transistor is connected to the bias circuit to control the operation of the first transistor. The input terminal of the first transistor is connected to the power supply. The output terminal of the first transistor is connected to the input terminals of the second transistor and the third transistor. The control terminal of the second transistor is used to receive the first voltage signal. The control terminal of the third transistor is used to receive the second voltage signal. The output terminals of the first transistor and the third transistor are connected to the input terminals of the intermediate stage circuit.

[0011] Optionally, the intermediate stage circuit includes a fourth transistor and a second differential pair, the fourth transistor being used to provide bias current to the second differential pair, the second differential pair including a fifth transistor and a sixth transistor;

[0012] The control terminal of the fourth transistor is connected to the bias circuit to control the operation of the fourth transistor, and the input terminal of the fourth transistor is connected to the power supply; the output terminal of the fourth transistor is connected to the input terminals of the fifth transistor and the sixth transistor, the control terminal of the fifth transistor is connected to the output terminal of the second transistor, and the control terminal of the sixth transistor is connected to the output terminal of the third transistor.

[0013] Optionally, the input stage circuit further includes a fifteenth transistor and a sixteenth transistor. The control terminal of the fifteenth transistor is connected to the control terminal of the sixth transistor and is also connected to the output terminal of the second transistor. The input terminal of the fifteenth transistor is connected to the output terminal of the second transistor, and the output terminal of the fifteenth transistor is grounded. The input terminal of the sixteenth transistor is connected to the output terminal of the third transistor, and the output terminal of the sixteenth transistor is grounded.

[0014] Optionally, the intermediate stage circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The input terminals of the seventh and eighth transistors are connected to a power supply. The control terminals of the seventh and eighth transistors are connected to the output terminal of the seventh transistor. The output terminal of the seventh transistor is connected to the input terminal of the ninth transistor. The output terminal of the eighth transistor is connected to the input terminal of the tenth transistor. The control terminals of the ninth and tenth transistors are connected to the bias circuit to control the operation of the ninth and tenth transistors. The output terminal of the ninth transistor is connected to the output terminal of the fifth transistor. The output terminal of the tenth transistor is connected to the output terminal of the sixth transistor. The output terminal of the eighth transistor is connected to the input terminal of the output stage circuit.

[0015] Optionally, the intermediate stage circuit further includes an eleventh transistor and a twelfth transistor. The control terminals of the eleventh transistor and the twelfth transistor are connected to the bias circuit to control the operation of the eleventh transistor and the twelfth transistor. The input terminal of the eleventh transistor is connected to the output terminal of the ninth transistor, and the output terminal of the eleventh transistor is grounded. The input terminal of the twelfth transistor is connected to the output terminal of the tenth transistor, and the output terminal of the twelfth transistor is grounded.

[0016] Optionally, the output stage circuit includes a thirteenth transistor and a fourteenth transistor. The control terminal of the thirteenth transistor is connected to the output terminal of the eighth transistor, the input terminal of the thirteenth transistor is connected to the power supply, the output terminal of the thirteenth transistor is connected to the input terminal of the fourteenth transistor, the output terminal of the thirteenth transistor serves as the output terminal of the output stage circuit, the control terminal of the fourteenth transistor is connected to the bias circuit to control the operation of the fourteenth transistor, and the output terminal of the fourteenth transistor is grounded.

[0017] Optionally, the bias circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor;

[0018] The input terminals of the seventeenth, eighteenth, and nineteenth transistors are connected to a power supply. The control terminals of the seventeenth, eighteenth, and nineteenth transistors, the first transistor, and the fourth transistor are connected to the output terminal of the seventeenth transistor, which is grounded. The output terminal of the eighteenth transistor is connected to the control terminal and input terminal of the twentieth transistor, which is grounded. The output terminal of the eighteenth transistor is connected to the control terminals of the eleventh, twelfth, and fourteenth transistors. The output terminal of the nineteenth transistor is connected to the control terminal and input terminal of the twenty-first transistor, as well as the control terminals of the ninth and tenth transistors, which is grounded.

[0019] Optionally, the operational amplifier further includes a first compensation circuit, which includes a first resistor and a first capacitor connected in series between the control terminal of the fifth transistor and the output terminal of the tenth transistor.

[0020] Optionally, the operational amplifier further includes a second compensation circuit, which includes a second resistor and a second capacitor connected in series between the output of the tenth transistor and the output of the thirteenth transistor.

[0021] In the operational amplifier of this invention, the first differential pair transistors of the input stage circuit amplify the input differential signal. Since the first differential pair transistors can eliminate noise when amplifying the differential signal, they can effectively reduce noise and reduce the interference of external noise on the operational amplifier. The first differential pair transistors can also reduce the offset voltage, thereby reducing the impact of the offset voltage on the operational amplifier. The bias circuit provides bias current to the input stage circuit, intermediate stage circuit, and output stage circuit to ensure that the input stage circuit, intermediate stage circuit, and output stage circuit operate normally. The input stage circuit, intermediate stage circuit, and output stage circuit realize three-stage amplification of the input differential signal, thereby achieving high gain of the operational amplifier. Attached Figure Description

[0022] Figure 1 This is a block diagram of the operational amplifier in an embodiment of the present invention.

[0023] Figure 2 This is a circuit schematic diagram of the operational amplifier in an embodiment of the present invention. Detailed Implementation

[0024] To explain in detail the technical content, structural features, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0025] like Figures 1 to 2 As shown, the present invention discloses an operational amplifier, including an input stage circuit 100, an intermediate stage circuit 200, an output stage circuit 300, and a bias circuit 400.

[0026] The input stage circuit 100 includes a first differential pair transistor, which is used to receive a first voltage signal and a second voltage signal. The first voltage signal and the second voltage signal are differential signals, and the first differential pair transistor is used to amplify the first voltage signal and the second voltage signal.

[0027] The input terminal of the intermediate stage circuit 200 is connected to the output terminal of the input stage circuit 100, and is used to amplify the output voltage of the input stage circuit 100.

[0028] The input terminal of the output stage circuit 300 is connected to the output terminal of the intermediate stage circuit 200, and the output stage circuit 300 is used to amplify the output voltage of the intermediate stage circuit 200.

[0029] The bias circuit 400 is used to provide bias current to the input stage circuit 100, the intermediate stage circuit 200 and the output stage circuit 300.

[0030] In the operational amplifier provided in this embodiment of the invention, the first differential pair transistor of the input stage circuit 100 amplifies the input differential signal. Since the first differential pair transistor can eliminate noise when amplifying the differential signal, it can effectively reduce noise and reduce the interference of external noise on the operational amplifier. The first differential pair transistor can also reduce the offset voltage, thereby reducing the impact of the offset voltage on the operational amplifier. The bias circuit 400 provides bias current to the input stage circuit 100, the intermediate stage circuit 200 and the output stage circuit 300 to enable the input stage circuit 100, the intermediate stage circuit 200 and the output stage circuit 300 to work normally. The input stage circuit 100, the intermediate stage circuit 200 and the output stage circuit 300 realize three-stage amplification of the input differential signal, thereby achieving high gain of the operational amplifier.

[0031] Please see Figure 2 In the operational amplifier of this embodiment, the input stage circuit 100 further includes a first transistor M1, and a first differential pair includes a second transistor M2 and a third transistor M3. The control terminal of the first transistor M1 is connected to the bias circuit 400 to control the operation of the first transistor M1. The input terminal of the first transistor M1 is connected to the power supply VDD, and the output terminal of the first transistor M1 is connected to the input terminals of the second transistor M2 and the third transistor M3. The control terminal of the second transistor M2 is used to receive a first voltage signal V1, and the control terminal of the third transistor M3 is used to receive a second voltage signal V2. The output terminals of the first transistor M1 and the third transistor M3 are connected to the input terminal of the intermediate stage circuit 200. The bias current provided by the first transistor M1 is shunt between the second transistor M2 and the third transistor M3. The control terminal of the first transistor M1 is biased by the bias circuit 400. The first differential pair not only amplifies the input signal and reduces the impact of offset voltage on the operational amplifier, but also achieves optimal device matching due to the excellent symmetry of the differential structure. The first differential pair reduces offset voltage in a structurally simple and easy-to-implement manner.

[0032] In some examples, such as Figure 2As shown, the intermediate stage circuit 200 includes a fourth transistor M4 and a second differential pair. The fourth transistor M4 provides bias current to the second differential pair, which includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the fourth transistor M4 is connected to the bias circuit 400 to control its operation. The input terminal of the fourth transistor M4 is connected to the power supply VDD. The output terminal of the fourth transistor M4 is connected to the input terminals of the fifth transistor M5 and the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the output terminal of the second transistor M2, and the control terminal of the sixth transistor M6 is connected to the output terminal of the third transistor M3. The bias current provided by the fourth transistor M4 is shunt between the fifth transistor M5 and the sixth transistor M6. The control terminal of the fourth transistor M4 is biased by the bias current. The output voltage of the first differential pair is further amplified by the second differential pair, further improving the gain of the operational amplifier. Furthermore, the second differential pair can further reduce noise and offset voltage.

[0033] Specifically, the first transistor M1, the first differential pair, the fourth transistor M4, and the second differential pair are all PMOS transistors. The sources of the first transistor M1 and the fourth transistor M4 are connected to the power supply VDD. The drain of the first transistor M1 is connected to the sources of the second transistor M2 and the third transistor M3 to provide bias current to the second transistor M2 and the third transistor M3. The drain of the fourth transistor M4 is connected to the sources of the fifth transistor M5 and the sixth transistor M6 to provide bias current to the fifth transistor M5 and the sixth transistor M6. The gates of the first transistor M1 and the fourth transistor M4 are connected to the bias circuit 400 to control the operation of the first transistor M1 and the second transistor M2. The gate of the second transistor M2 is connected to the first voltage signal V1, and the gate of the third transistor M3 is connected to the second voltage signal V2, which is out of phase with the first voltage signal V1. The drain of the second transistor M2 is connected to the gate of the fifth transistor M5, and the drain of the third transistor M3 is connected to the gate of the sixth transistor M6. The output voltage of the input stage circuit 100 is further amplified through the fifth transistor M5 and the sixth transistor M6. In this embodiment, the first differential pair and the second differential pair are configured as PMOS transistors, which can effectively reduce the internal noise of the device. Of course, the first transistor M1, the first differential pair, the fourth transistor M4, and the second differential pair are not limited to being PMOS transistors, but can also be configured as NMOS transistors as needed.

[0034] In specific examples, such as Figure 2As shown, the input stage circuit 100 also includes a fifteenth transistor M15 and a sixteenth transistor M16. The control terminal of the fifteenth transistor M15 is connected to the control terminal of the sixth transistor M6 and is also connected to the output terminal of the second transistor M2. The input terminal of the fifteenth transistor M15 is connected to the output terminal of the second transistor M2, and the output terminal of the fifteenth transistor M15 is grounded. The input terminal of the sixteenth transistor M16 is connected to the output terminal of the third transistor M3, and the output terminal of the sixteenth transistor M16 is grounded. Specifically, both the fifteenth transistor M15 and the sixteenth transistor M16 are NMOS transistors. In this embodiment, the open-loop gain of the input stage circuit 100 is:

[0035] A v =g m2 (r o2 ||r o15 )

[0036] Among them, g m2 It is the transconductance of the second transistor M2, r o2 It is the internal resistance of the second transistor M2, r o15 It is the internal resistance of the fifteenth transistor M15;

[0037] The equivalent noise input formula for the input stage circuit 100 is:

[0038]

[0039] Among them, K p K N It is a constant related to integrated circuit technology, C ox It is the gate oxide capacitance per unit area, K is the Boltzmann constant, and T is the temperature.

[0040] Of course, the input stage circuit 100 in this embodiment of the invention is not limited to this structure. It can also be configured to amplify the input differential signal and suppress the input noise by only setting the first differential pair transistor.

[0041] Furthermore, the intermediate stage circuit 200 also includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The input terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply VDD. The control terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the output terminal of the seventh transistor M7. The output terminal of the seventh transistor M7 is connected to the input terminal of the ninth transistor M9. The output terminal of the eighth transistor M8 is connected to the input terminal of the tenth transistor M10. The control terminals of the ninth transistor M9 and the tenth transistor M10 are connected to the bias circuit 400 to control the operation of the ninth transistor M9 and the tenth transistor M10. The output terminal of the ninth transistor M9 is connected to the output terminal of the fifth transistor M5. The output terminal of the tenth transistor M10 is connected to the output terminal of the sixth transistor M6. The output terminal of the eighth transistor M8 is connected to the input terminal of the output stage circuit 300.

[0042] Furthermore, the intermediate stage circuit 200 also includes an eleventh transistor M11 and a twelfth transistor M12. The control terminals of the eleventh transistor M11 and the twelfth transistor M12 are connected to the bias circuit 400 to control the operation of the eleventh transistor M11 and the twelfth transistor M12. The input terminal of the eleventh transistor M11 is connected to the output terminal of the ninth transistor M9, and the output terminal of the eleventh transistor M11 is grounded. The input terminal of the twelfth transistor M12 is connected to the output terminal of the tenth transistor M10, and the output terminal of the twelfth transistor M12 is grounded.

[0043] Specifically, the seventh transistor M7 and the eighth transistor M8 are PMOS transistors, and the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are NMOS transistors. The sources of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply VDD, their gates are connected together and to the drain of the seventh transistor M7, the drain of the seventh transistor M7 is connected to the drain of the ninth transistor M9, the drain of the eighth transistor M8 is connected to the drain of the tenth transistor M10, and the ninth transistor M9 and the twelfth transistor M12 are... The gate of transistor M10 is connected and biased by bias circuit 400. The source of the ninth transistor M9 is connected to the drain of the eleventh transistor M11. The source of the tenth transistor M10 is connected to the drain of the twelfth transistor M12. The gates of the eleventh transistor M11 and the twelfth transistor M12 are connected and biased by bias circuit 400. The sources of the eleventh transistor M11 and the twelfth transistor M12 are grounded. The drains of the eighth transistor M8 and the tenth transistor M10 are connected to the output terminal of intermediate stage circuit 200 and the input terminal of output stage circuit 300.

[0044] exist Figure 2In the example, transistors M4 through M12 together form a folded cascode structure, increasing the input resistance of the intermediate stage circuit 200 to further amplify the signal output from the input stage circuit 100, thereby providing high gain for the intermediate stage circuit 200. Furthermore, the folded cascode structure can shield the input stage circuit 100, preventing it from being affected by the intermediate stage circuit 200 and the output stage circuit 300. Of course, the intermediate stage circuit 200 is not limited to the aforementioned folded cascode structure; for example, it can be composed solely of the second differential pair transistors, as long as it can amplify the output signal of the input stage circuit 100. In addition, the specific selection of PMOS or NMOS transistors for transistors M7, M8, M9, M10, M11, M11, and M12 can be determined according to actual needs, and this embodiment of the invention does not impose any restrictions on this.

[0045] like Figure 2 As shown, the eighth transistor M8 and the tenth transistor M10 provide high impedance at the output of the eighth transistor M8, thereby providing high voltage gain at the drain of the eighth transistor M8, i.e., the output of the intermediate stage circuit 200, resulting in a larger output swing of the intermediate stage circuit 200. When the third transistor M3 feeds its amplified voltage to the gate of the sixth transistor M6, the sixth transistor M6 outputs an amplified signal current at its drain. Almost all of this signal current flows into the tenth transistor M10, thus generating current gain. Since the tenth transistor M10 shares a common gate with the ninth transistor M9, the source of the tenth transistor M10 has low input impedance.

[0046] exist Figure 2 In the example, the open-loop gain of the intermediate stage circuit 200 is:

[0047] A v =g m5 (r o7 ||(g m9 +g mb9 )r o9 (r o11 ||r o5 ))

[0048] Among them, g m5 and g m9 These are the transconductances of the fifth transistor M5 and the ninth transistor M9, respectively. mb9 It is the substrate transconductance of the ninth transistor M9, r o5 r o7 r o9 and r o11 These are the internal resistances of the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the eleventh transistor M11, respectively.

[0049] The output swing of intermediate stage circuit 200 is:

[0050] V DD -(V OD9 +V OD11 +|V Od7 |)

[0051] Among them, V OD9 V Od11 、 and V OD7 These are the overdrive voltages of the ninth transistor M9, the eleventh transistor M11, and the seventh transistor M7, respectively.

[0052] Please continue reading. Figure 2 The output stage circuit 300 includes a thirteenth transistor M13 and a fourteenth transistor M14. The control terminal of the thirteenth transistor M13 is connected to the output terminal of the eighth transistor M8, the input terminal of the thirteenth transistor M13 is connected to the power supply VDD, and the output terminal of the thirteenth transistor M13 is connected to the input terminal of the fourteenth transistor M14. The output terminal of the thirteenth transistor M13 serves as the output terminal of the output stage circuit 300. The control terminal of the fourteenth transistor M14 is connected to the bias circuit 400 to control its operation, and the output terminal of the fourteenth transistor M14 is grounded. The gain of the output stage circuit 300 can be increased through the thirteenth transistor M13 and the fourteenth transistor M14, thereby further increasing the gain of the operational amplifier.

[0053] Specifically, the thirteenth transistor M13 is a PMOS transistor, and the fourteenth transistor M14 is an NMOS transistor. The source of the thirteenth transistor M13 is connected to the power supply VDD, the gate of the thirteenth transistor M13 is connected to the drain of the eighth transistor M8, and the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14. The drain of the thirteenth transistor M13 serves as the output terminal of the output stage circuit 300. The source of the fourteenth transistor M14 is grounded, and the gate of the fourteenth transistor M14 is biased by the bias circuit 400. The gain of the output stage circuit 300 is calculated as follows:

[0054] A v =g m13 (r O13 ||r o14 )

[0055] Among them, g m13 For the transconductance of the fourteenth transistor M14, r o13 The internal resistance of the thirteenth transistor M13 is r. o14 The internal resistance of the fourteenth transistor M14;

[0056] The formula for calculating the output voltage swing of the output stage circuit 300 is as follows:

[0057] V DD -(V OD14 +|V OD13 |)

[0058] Among them, V OD13 and V OD14 These are the overdrive voltages of the thirteenth transistor M13 and the fourteenth transistor M14, respectively. It can be seen that the output stage circuit 300 of the operational amplifier can have a large output swing, a simple structure and a small number of transistors. Moreover, the thirteenth transistor M13 and the fourteenth transistor M14 form a common source structure, which makes the output resistance of the output stage circuit 300 small and the load capacity strong.

[0059] Please continue reading. Figure 2 The bias circuit 400 includes a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21. The input terminals of the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are connected to the power supply VDD. The control terminals of the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the first transistor M1, and the fourth transistor M4 are connected to the output terminal of the seventeenth transistor M17 to provide bias current to the first transistor M1 and the fourth transistor M4 so that the first transistor M1 and the fourth transistor M4 can operate normally. The output terminal of the seventeenth transistor M17 is grounded.

[0060] The output terminal of the eighteenth transistor M18 is connected to the control terminal and input terminal of the twentieth transistor M20. The output terminal of the twentieth transistor M20 is grounded. The output terminal of the eighteenth transistor M18 is connected to the control terminals of the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 to provide bias current to the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 so that the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 can operate normally.

[0061] The output of the nineteenth transistor M19 is connected to the control and input terminals of the twenty-first transistor M21, as well as the control terminals of the ninth transistor M9 and the tenth transistor M10, to provide bias current to the ninth transistor M9 and the tenth transistor M10 so that the ninth transistor M9 and the tenth transistor M10 can operate normally. The output of the twenty-first transistor M21 is grounded.

[0062] The seventeenth transistor M17, eighteenth transistor M18, nineteenth transistor M19, twentieth transistor M20, and twenty-first transistor M21 of the bias circuit 400 provide the required bias current to the input stage circuit 100, intermediate stage circuit 200, and output stage circuit 300, enabling the operational amplifier to operate normally.

[0063] Specifically, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 can be configured as PMOS transistors, and the twentieth transistor M20 and the twenty-first transistor M21 can be configured as NMOS transistors. Of course, the embodiments of the present invention are not limited to this, and the specific selection of each transistor can be set according to actual needs.

[0064] The operational amplifier achieves high gain through three stages of amplification: input stage circuit 100, intermediate stage circuit 200, and output stage circuit 300. However, this also leads to a decrease in the closed-loop stability of the operational amplifier, which may cause it to malfunction. Therefore, it is necessary to supplement the operational amplifier to improve its stability.

[0065] To improve the stability of the operational amplifier, the operational amplifier also includes a first compensation circuit. The first compensation circuit includes a first resistor R1 and a first capacitor C1 connected in series. The first compensation circuit is connected in series between the control terminal of the fifth transistor M5 and the output terminal of the tenth transistor M10. It can improve the stability of the input stage circuit 100 and the intermediate stage circuit 200, compensate for the phase margin, enable the operational amplifier to work normally and stably, and avoid oscillation.

[0066] Furthermore, the operational amplifier may also include a second compensation circuit, which includes a second resistor R2 and a second capacitor C2 connected in series. This second compensation circuit is connected between the output terminals of the tenth transistor M10 and the thirteenth transistor M13, improving the stability between the intermediate stage circuit 200 and the output stage circuit 300, thereby enabling the operational amplifier to operate normally and stably and avoiding oscillations. In this embodiment of the invention, only the first compensation circuit or only the second compensation circuit may be provided; alternatively, both the first and second compensation circuits may be provided simultaneously.

[0067] The above-disclosed examples are merely preferred embodiments of the present invention, intended to facilitate understanding and implementation by those skilled in the art. They should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. An operational amplifier, characterized in that, include: The input stage circuit includes a first differential pair transistor, which is used to receive a first voltage signal and a second voltage signal. The first voltage signal and the second voltage signal are differential signals, and the first differential pair transistor is used to amplify the first voltage signal and the second voltage signal. An intermediate stage circuit, wherein the input terminal of the intermediate stage circuit is connected to the output terminal of the input stage circuit, is used to amplify the output signal of the input stage circuit; An output stage circuit, wherein the input terminal of the output stage circuit is connected to the output terminal of the intermediate stage circuit, and the output stage circuit is used to amplify the output signal of the intermediate stage circuit; as well as A bias circuit is provided to supply bias current to the input stage circuit, the intermediate stage circuit, and the output stage circuit; The input stage circuit further includes a first transistor for providing bias current to the first differential pair transistors, the first differential pair transistors including a second transistor and a third transistor; The control terminal of the first transistor is connected to the bias circuit to control the operation of the first transistor. The input terminal of the first transistor is connected to the power supply. The output terminal of the first transistor is connected to the input terminals of the second transistor and the third transistor. The control terminal of the second transistor is used to receive the first voltage signal. The control terminal of the third transistor is used to receive the second voltage signal. The output terminals of the first transistor and the third transistor are connected to the input terminal of the intermediate stage circuit. The intermediate stage circuit includes a fourth transistor and a second differential pair, the fourth transistor being used to provide bias current to the second differential pair, and the second differential pair including a fifth transistor and a sixth transistor. The control terminal of the fourth transistor is connected to the bias circuit to control the operation of the fourth transistor, and the input terminal of the fourth transistor is connected to the power supply; the output terminal of the fourth transistor is connected to the input terminals of the fifth transistor and the sixth transistor, the control terminal of the fifth transistor is connected to the output terminal of the second transistor, and the control terminal of the sixth transistor is connected to the output terminal of the third transistor. The intermediate stage circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The input terminals of the seventh and eighth transistors are connected to a power supply. The control terminals of the seventh and eighth transistors are connected to the output terminal of the seventh transistor. The output terminal of the seventh transistor is connected to the input terminal of the ninth transistor. The output terminal of the eighth transistor is connected to the input terminal of the tenth transistor. The control terminals of the ninth and tenth transistors are connected to the bias circuit to control the operation of the ninth and tenth transistors. The output terminal of the ninth transistor is connected to the output terminal of the fifth transistor. The output terminal of the tenth transistor is connected to the output terminal of the sixth transistor. The output terminal of the eighth transistor is connected to the input terminal of the output stage circuit. The intermediate stage circuit also includes an eleventh transistor and a twelfth transistor. The control terminals of the eleventh transistor and the twelfth transistor are connected to the bias circuit to control the operation of the eleventh transistor and the twelfth transistor. The input terminal of the eleventh transistor is connected to the output terminal of the ninth transistor, and the output terminal of the eleventh transistor is grounded. The input terminal of the twelfth transistor is connected to the output terminal of the tenth transistor, and the output terminal of the twelfth transistor is grounded.

2. The operational amplifier according to claim 1, characterized in that, The input stage circuit further includes a fifteenth transistor and a sixteenth transistor. The control terminal of the fifteenth transistor is connected to the control terminal of the sixth transistor and is also connected to the output terminal of the second transistor. The input terminal of the fifteenth transistor is connected to the output terminal of the second transistor, and the output terminal of the fifteenth transistor is grounded. The input terminal of the sixteenth transistor is connected to the output terminal of the third transistor, and the output terminal of the sixteenth transistor is grounded.

3. The operational amplifier according to claim 1, characterized in that, The output stage circuit includes a thirteenth transistor and a fourteenth transistor. The control terminal of the thirteenth transistor is connected to the output terminal of the eighth transistor. The input terminal of the thirteenth transistor is connected to the power supply. The output terminal of the thirteenth transistor is connected to the input terminal of the fourteenth transistor. The output terminal of the thirteenth transistor serves as the output terminal of the output stage circuit. The control terminal of the fourteenth transistor is connected to the bias circuit to control the operation of the fourteenth transistor. The output terminal of the fourteenth transistor is grounded.

4. The operational amplifier according to claim 3, characterized in that, The bias circuit includes the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty-first transistor; The input terminals of the seventeenth, eighteenth, and nineteenth transistors are connected to a power supply. The control terminals of the seventeenth, eighteenth, and nineteenth transistors, the first transistor, and the fourth transistor are connected to the output terminal of the seventeenth transistor, which is grounded. The output terminal of the eighteenth transistor is connected to the control terminal and input terminal of the twentieth transistor, which is grounded. The output terminal of the eighteenth transistor is connected to the control terminals of the eleventh, twelfth, and fourteenth transistors. The output terminal of the nineteenth transistor is connected to the control terminal and input terminal of the twenty-first transistor, as well as the control terminals of the ninth and tenth transistors, which is grounded.

5. The operational amplifier according to claim 3, characterized in that, It also includes a first compensation circuit, which includes a first resistor and a first capacitor connected in series, and is connected in series between the control terminal of the fifth transistor and the output terminal of the tenth transistor.

6. The operational amplifier according to claim 3, characterized in that, It also includes a second compensation circuit, which includes a second resistor and a second capacitor connected in series, and the second compensation circuit is connected in series between the output terminal of the tenth transistor and the output terminal of the thirteenth transistor.

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