A differential dynamic operational amplifier applied to noise shaping SAR ADC

Abstract

The application discloses a differential dynamic operational amplifier applied to a noise shaping SAR ADC, comprising a dynamic amplification circuit, a flicker noise suppression circuit, a gain linear calibration circuit and a common-mode voltage detection circuit, wherein the common-mode voltage detection circuit is connected with the dynamic amplification circuit and the gain linear calibration circuit respectively, the gain linear calibration circuit is connected with the dynamic amplification circuit, and the dynamic amplification circuit is connected with the flicker noise suppression circuit; the application has the advantages that stability and precision are improved, low power consumption is ensured, and the energy efficiency of a noise shaping SAR ADC system is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a differential dynamic operational amplifier applied to a noise-shaping SAR ADC. Background Technology

[0002] Integrated circuits are the foundation and core of electronic information technology, holding a crucial strategic position and playing an irreplaceable key role in the information industry. In the real world, the vast majority of signals are analog signals, such as sound and temperature, while most signals used for transmission, storage, calculation, and display are digital signals. An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. It serves as the interface between the analog and digital domains and plays a wide and irreplaceable role. Operational amplifiers are key circuit units in high-performance ADCs, and their performance often determines the performance of the data converter system.

[0003] With the continuous development of technologies such as the Internet of Things, wireless communication, and high-performance computing, the requirements for ADC performance are constantly increasing. The demand for high-precision, low-power, and high-speed ADCs is becoming unprecedentedly strong. In recent years, to further improve ADC performance, hybrid architectures have become a hot topic in ADC research. By combining the strengths and weaknesses of different types of ADC structures, performance can be significantly improved. Successive Approximate Register (SAR) ADCs, mainly composed of DACs, comparators, and digital logic circuits, are one of the high-demand architectures for medium-resolution and bandwidth applications. Their main advantages are high energy efficiency, strong adaptability to advanced processes, and simple structure. However, due to the influence of process deviations in integrated circuit manufacturing, their accuracy is often limited to below 12 bits. Sigma-Delta ADCs are currently the most widely used high-precision ADC structure. By employing oversampling, noise shaping, and digital decimation filtering techniques, they reduce the design requirements of analog circuits and achieve high resolutions that other types of ADCs cannot reach. However, due to the use of oversampling technology, Sigma-Delta ADCs have lower signal bandwidth and are mainly used in low-bandwidth applications. Noise-shaping SAR ADCs combine the advantages of SAR and Sigma-Delta ADCs. For example, the paper "H. Ghaedrahmati, J. Zhou and L. Shi, Gain-boosted Complementary Dynamic Residue Amplifier for a 160MS / s 61dB SNDR Noise-Shaping SAR ADC," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, pp. 141-144" describes an emerging oversampling ADC architecture that is popular in high-speed, high-resolution ADC designs. To improve the stability and accuracy of noise-shaping SAR ADCs, integrating the margin voltage is a crucial operation. Using an active integrator to integrate the margin voltage is the mainstream technique in this research field; however, the power consumption of the active integrator circuit becomes a technical bottleneck. Furthermore, the static operational amplifier of a noise-shaping SAR ADC relies on multiple quiescent currents to maintain the stable operating point of key MOSFETs, resulting in high power consumption and self-heating effects. Therefore, while improving stability and accuracy, existing noise-shaping SAR ADCs cannot guarantee low power consumption, resulting in low energy efficiency of noise-shaping SAR ADC systems. Summary of the Invention

[0004] The technical problem to be solved by this invention is that existing noise-shaping SAR ADCs cannot guarantee low power consumption while improving stability and accuracy, resulting in low energy efficiency of the noise-shaping SAR ADC system.

[0005] This invention solves the above-mentioned technical problems through the following technical means: a differential dynamic operational amplifier applied to a noise-shaping SARADC, comprising a dynamic amplification circuit, a flicker noise suppression circuit, a gain linearity calibration circuit, and a common-mode voltage detection circuit. The common-mode voltage detection circuit is connected to both the dynamic amplification circuit and the gain linearity calibration circuit. The gain linearity calibration circuit is connected to the dynamic amplification circuit, and the dynamic amplification circuit is connected to the flicker noise suppression circuit. The dynamic amplification circuit inserts a pair of cross-coupled NMOS transistors in the discharge path to improve the output common-mode voltage drop rate. The common-mode voltage detection circuit detects the output common-mode voltage. When the output common-mode voltage drops to the detection threshold of the common-mode detection circuit, it outputs a feedback control signal to cut off the dynamic amplification circuit and stop it from working. The gain linearity calibration circuit positively amplifies the difference in the initial time amplitude of the input signal and feeds it back to the dynamic amplification circuit to adjust the duration of the amplification process, thereby turning the amplification process time into a function of the input signal amplitude and suppressing the nonlinearity of the gain of the dynamic amplification circuit. The flicker noise suppression circuit suppresses the flicker noise of the dynamic amplification circuit.

[0006] The dynamic amplifier circuit of this invention inserts a pair of cross-coupled NMOS transistors in the discharge path to increase the output common-mode voltage drop speed and open-loop gain, thereby improving control accuracy. The common-mode voltage detection circuit detects the output common-mode voltage. When the output common-mode voltage drops to the detection threshold of the common-mode detection circuit, it outputs a feedback control signal to cut off the dynamic amplifier circuit and stop it from working, which can effectively save power consumption. The gain linearity calibration circuit suppresses the nonlinearity of the dynamic amplifier circuit gain, and the flicker noise suppression circuit suppresses the flicker noise of the dynamic amplifier circuit, effectively improving circuit stability. The entire circuit improves stability and accuracy while ensuring low power consumption, thus improving the energy efficiency of the noise-shaping SAR ADC system.

[0007] Furthermore, the dynamic amplification circuit includes a differential input pair, a pseudo-differential input pair, a tail current source switching MOSFET M3 controlled by a common-mode voltage detection circuit and a gain linearity calibration circuit, and a tail current source MOSFET M2 controlled by an external clock. The cross-coupled NMOS transistors are MOSFETs M6 and M7, the differential input pair includes MOSFETs M4 and M5, and the pseudo-differential input pair includes MOSFETs M8 and M9. The sources of MOSFETs M8 and M9 are both connected to the power supply VDD. The drains of S-channel transistors M8 and M9 are connected to the drains of MOSFETs M6 and M7 respectively. The sources of MOSFETs M6 and M7 are connected to the drains of MOSFETs M4 and M5 respectively. The sources of MOSFETs M4 and M5 are both connected to the drain of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M2. The source of MOSFET M2 is grounded. The gates of MOSFETs M4 and M8 are both connected to voltage VIP. The gates of MOSFETs M5 and M9 are both connected to voltage VIN.

[0008] Furthermore, the dynamic amplification circuit also includes switches S4 and S5 controlled by a common-mode voltage detection circuit, and reset switches S2, S3, S6, and S7 controlled by an external clock. The positive terminals of switches S6 and S7 are both connected to the power supply VDD, the negative terminal of switch S6 is connected to the source of MOSFET M8, and the negative terminal of switch S7 is connected to the drain of MOSFET M9. The positive terminal of switch S4 is grounded, and the negative terminal of switch S4 is connected to the connection between MOSFET M8 and MOSFET M6. The positive terminal of switch S5 is grounded, and the negative terminal of switch S5 is connected to the connection between MOSFET M9 and MOSFET M7. The negative terminals of switches S2 and S3 are both connected to the power supply VDD, the positive terminal of switch S2 is connected to the connection between MOSFET M6 and MOSFET M4, and the positive terminal of switch S3 is connected to the connection between MOSFET M7 and MOSFET M5.

[0009] Furthermore, the dynamic amplification circuit also includes load capacitors C1 to C4. The upper plate of load capacitor C3 is connected to the positive terminal of switch S4, and a node Von is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C4 is connected to the positive terminal of switch S5, and a node Vop is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C1 is connected to the positive terminal of switch S2, and the connection point serves as node Vxn, while the lower plate is grounded. The upper plate of load capacitor C2 is connected to the positive terminal of switch S3, and the connection point serves as node Vxp, while the lower plate is grounded.

[0010] Furthermore, the common-mode voltage detection circuit includes a reset switch S8 controlled by an external clock, DC blocking capacitors C5 and C6 for detecting the common-mode voltage at the output terminal, and a feedback signal generation circuit composed of a first inverter and a second inverter cascaded together. The positive terminal of the switch S8 is connected to the power supply VDD. The input terminal of the feedback signal generation circuit, the negative terminal of the switch S8, the upper plate of the DC blocking capacitor C5, and the upper plate of the DC blocking capacitor C6 are connected, and the connection point is designated as node CM. The lower plate of the DC blocking capacitor C5 is connected to the negative terminal of the switch S4, and the connection point is designated as node Vo1. The lower plate of the DC blocking capacitor C6 is connected to the negative terminal of the switch S5, and the connection point is designated as node Vo2.

[0011] Furthermore, the gain linearity calibration circuit includes a PMOS transistor M12 and an NMOS transistor M10 controlled by the output of a first inverter, a negative feedback PMOS transistor M11 controlled by the common-mode voltage output from the common-mode voltage detection circuit, and a reset switch S9 controlled by an external clock. The source of the PMOS transistor M12 is connected to the power supply VDD, the gate of the PMOS transistor M12 is connected to the gate of the NMOS transistor M10 and receives the control signal output from the output node INVB of the first inverter, the drain of the PMOS transistor M12 is connected to the source of the negative feedback PMOS transistor M11, the gate of the negative feedback PMOS transistor M11 receives the common-mode voltage output from node CM of the common-mode voltage detection circuit, the drain of the negative feedback PMOS transistor M11 is connected to the drain of the NMOS transistor M10 and the negative terminal of the switch S9, the positive terminal of the switch S9 is connected to the voltage Vinit, and the source of the NMOS transistor M10 is grounded.

[0012] Furthermore, the flicker noise suppression circuit includes a resistor R1 that generates the gate bias voltage of MOS transistor M2, an NMOS transistor M1, and a switch S1 controlled by an external clock. One end of the resistor R1 is connected to the power supply VB, and the other end of the resistor R1, the drain of NMOS transistor M1, the gate of NMOS transistor M1, the gate of MOS transistor M2, and the positive terminal of switch S1 are connected. The negative terminal of switch S1 is grounded, and the source of NMOS transistor M1, the negative terminal of switch S1, and the source of MOS transistor M2 are all grounded.

[0013] Furthermore, when the external clock is high, switches S1-S3 and S6-S9 are turned on, and nodes Vo1, Vo2, Vxn, Vxp, and CM are reset to the high level VDD. The first inverter output node INVB is low, PMOS transistor M12 is turned on, and NMOS transistor M10 is turned off. The second inverter output node INV is high, and switches S3 and S4 are turned on. Output nodes Von and Vop are also reset to the high level VDD. Since switch S9 is turned on, the gate of MOS transistor M2 is reset to the low level ground. MOS transistor M2 is in the cutoff region, and the differential dynamic operational amplifier used in the noise-shaping SAR ADC is in the off state. The gate of MOS transistor M3 is reset to the initial voltage Vinit. At this time, the common mode level of output nodes Von and Vop is VDD, that is, the voltage of node CM is VDD.

[0014] Furthermore, when the external clock is low, switches S1-S3 and S6-S9 are turned off. Since the voltage at node CM is still high, switches S4 and S5 are still conducting. Because switch S1 is off, NMOS transistor M1 is turned on. The bias voltage generated by NMOS transistor M1 and resistor R1 is applied to the gate of MOS transistor M2, and MOS transistor M2 is turned on. At this time, node INVB is low, PMOS transistor M12 is turned on, and NMOS transistor M10 is turned off. Since the gate voltage of MOS transistor M3 is reset to voltage Vinit, it is in the conducting state, providing current for the dynamic amplifier circuit to work. The dynamic amplifier circuit begins to enter the amplification working state.

[0015] Furthermore, the amplification operation of the dynamic amplifier circuit includes a first amplification stage, a second amplification stage, and a third amplification stage. In the first amplification stage, at the beginning, MOSFETs M6 and M7 are in the cutoff region. Assuming that voltage VIP is greater than voltage VIN, the voltage drop rate at node Vxn is faster than that at node Vxp until MOSFET M6 is turned on, at which point the first amplification stage ends. In the second amplification stage, at the beginning, MOSFET M6 is turned on but MOSFET M7 remains off until M7 is turned on, at which point the second amplification stage ends. In the third amplification stage, at the beginning, both cross-coupled MOSFETs M6 and M7 are in the on state. The voltage drop rates at nodes Von and Vxp are the same, and the voltage drop rates at nodes Vop and Vxn are also the same. The third amplification stage ends when the output common-mode voltage CM reaches VDD / 2.

[0016] The advantages of this invention are:

[0017] (1) The dynamic amplifier circuit of the present invention inserts a pair of cross-coupled NMOS transistors in the discharge path to improve the output common-mode voltage drop speed and open-loop gain, thereby improving control accuracy. The common-mode voltage detection circuit detects the output common-mode voltage. When the output common-mode voltage drops to the detection threshold of the common-mode detection circuit, it outputs a feedback control signal to cut off the dynamic amplifier circuit and stop it from working, which can effectively save power consumption. The gain linear calibration circuit suppresses the nonlinearity of the gain of the dynamic amplifier circuit and the flicker noise suppression circuit suppresses the flicker noise of the dynamic amplifier circuit, effectively improving the stability of the circuit. The entire circuit improves stability and accuracy while ensuring low power consumption and improving the energy efficiency of the noise-shaping SAR ADC system.

[0018] (2) The dynamic amplifier circuit of this invention amplifies the differential signal by inserting a pair of cross-coupled NMOS transistors in the discharge path, which effectively improves the output common-mode voltage drop speed and increases the open-loop gain. At the same time, a pair of pseudo-differential PMOS input transistors is added to the original NMOS input pair. The common-mode current of the PMOS input pair is used as a bypass current, and the differential-mode current can effectively increase the transconductance, further improving the open-loop gain of the amplifier.

[0019] (3) The common-mode voltage detection circuit used in this invention has the advantages of simple circuit structure, fast response speed and low power consumption. When the output common-mode voltage is lower than the detection threshold voltage, the amplifier tail current source (MOS transistor M2) is turned off, which can effectively save power consumption.

[0020] (4) In order to solve the problem that the gain of the dynamic amplifier circuit decreases as the amplitude of the input differential signal increases, the present invention designs a gain linear calibration circuit based on time-domain linearization technology, which automatically adjusts the duration of the amplification process to be proportional to the amplitude of the input signal. The larger the amplitude of the input differential signal, the longer the duration of the amplification process, and the higher the gain. The nonlinearity of the gain of the dynamic amplifier circuit is suppressed.

[0021] (5) In order to reduce the flicker noise of the tail current tube, the present invention uses a switching biasing technique, which reduces the flicker noise of the tail current tube from the physical source by cyclically switching the working state of the biasing circuit, thereby improving the circuit stability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the noise-shaping SAR ADC structure used in the differential dynamic operational amplifier provided in the embodiments of the present invention;

[0023] Figure 2 This is the circuit schematic of a traditional differential dynamic operational amplifier;

[0024] Figure 3The circuit schematic of a differential dynamic operational amplifier applied to a noise-shaping SAR ADC is provided in an embodiment of the present invention.

[0025] Figure 4 A graph showing the relationship between the common-mode current Icm,n and the differential input voltage in a differential dynamic operational amplifier applied to a noise-shaping SAR ADC, provided in an embodiment of the present invention.

[0026] Figure 5 A graph showing the relationship between feedback voltage VF, output common-mode voltage CM, and input signal amplitude in a differential dynamic operational amplifier applied to a noise-shaping SAR ADC, provided in an embodiment of the present invention;

[0027] Figure 6 This is an overall timing diagram of a differential dynamic operational amplifier applied to a noise-shaping SAR ADC, provided in an embodiment of the present invention.

[0028] Figure 7 The transient simulation diagram is provided for a differential dynamic operational amplifier applied to a noise-shaping SAR ADC according to an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] like Figure 3As shown, a differential dynamic operational amplifier for noise-shaping SAR ADC includes a common-mode voltage detection circuit 1, a dynamic amplification circuit 2, a gain linearity calibration circuit 3, and a flicker noise suppression circuit 4. The common-mode voltage detection circuit 1 is connected to both the dynamic amplification circuit 2 and the gain linearity calibration circuit 3. The gain linearity calibration circuit 3 is connected to the dynamic amplification circuit 2, and the dynamic amplification circuit 2 is connected to the flicker noise suppression circuit 4. The dynamic amplification circuit 2 inserts a pair of cross-coupled NMOS transistors in the discharge path to improve the output common-mode voltage drop rate. The common-mode voltage detection circuit 1 detects the output common-mode voltage. When the output common-mode voltage drops to the detection threshold of the common-mode detection circuit, it outputs a feedback control signal to cut off the dynamic amplification circuit 2 and stop its operation. The gain linearity calibration circuit 3 positively amplifies the difference in the initial time amplitude of the input signal and feeds it back to the dynamic amplification circuit 2 to adjust the duration of the amplification process, thereby turning the amplification process time into a function of the input signal amplitude and suppressing the nonlinearity of the gain of the dynamic amplification circuit 2. The flicker noise suppression circuit 4 suppresses the flicker noise of the dynamic amplification circuit 2.

[0031] The dynamic amplifier circuit 2 includes a differential input pair, a pseudo-differential input pair, a tail current source switching MOSFET M3 jointly controlled by the common-mode voltage detection circuit 1 and the gain linearity calibration circuit 3, and a tail current source MOSFET M2 controlled by an external clock. The cross-coupled NMOS transistors are MOSFETs M6 and M7, the differential input pair includes MOSFETs M4 and M5, and the pseudo-differential input pair includes MOSFETs M8 and M9. The sources of MOSFETs M8 and M9 are both connected to the power supply VDD. The drains of transistors M8 and M9 are connected to the drains of MOSFETs M6 and M7 respectively. The sources of MOSFETs M6 and M7 are connected to the drains of MOSFETs M4 and M5 respectively. The sources of MOSFETs M4 and M5 are both connected to the drain of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M2. The source of MOSFET M2 is grounded. The gates of MOSFETs M4 and M8 are both connected to voltage VIP. The gates of MOSFETs M5 and M9 are both connected to voltage VIN.

[0032] The dynamic amplification circuit 2 also includes switches S4 and S5 controlled by the common-mode voltage detection circuit 1, and reset switches S2, S3, S6, and S7 controlled by an external clock. The positive terminals of switches S6 and S7 are connected to the power supply VDD, the negative terminal of switch S6 is connected to the source of MOSFET M8, and the negative terminal of switch S7 is connected to the drain of MOSFET M9. The positive terminal of switch S4 is grounded, and the negative terminal of switch S4 is connected to the connection between MOSFET M8 and MOSFET M6. The positive terminal of switch S5 is grounded, and the negative terminal of switch S5 is connected to the connection between MOSFET M9 and MOSFET M7. The negative terminals of switches S2 and S3 are both connected to the power supply VDD. The positive terminal of switch S2 is connected to the connection between MOSFET M6 and MOSFET M4, and the positive terminal of switch S3 is connected to the connection between MOSFET M7 and MOSFET M5.

[0033] The dynamic amplification circuit 2 further includes load capacitors C1 to C4. The upper plate of load capacitor C3 is connected to the positive terminal of switch S4, and a node Von is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C4 is connected to the positive terminal of switch S5, and a node Vop is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C1 is connected to the positive terminal of switch S2, and the connection point serves as node Vxn, while the lower plate is grounded. The upper plate of load capacitor C2 is connected to the positive terminal of switch S3, and the connection point serves as node Vxp, while the lower plate is grounded.

[0034] The common-mode voltage detection circuit 1 includes a reset switch S8 controlled by an external clock, DC blocking capacitors C5 and C6 for detecting the common-mode voltage at the output terminal, and a feedback signal generation circuit composed of a first inverter NOT1 and a second inverter NOT2 cascaded together. The positive terminal of the switch S8 is connected to the power supply VDD. The input terminal of the feedback signal generation circuit, the negative terminal of the switch S8, the upper plate of the DC blocking capacitor C5, and the upper plate of the DC blocking capacitor C6 are connected, and the connection point is designated as node CM. The lower plate of the DC blocking capacitor C5 is connected to the negative terminal of the switch S4, and the connection point is designated as node Vo1. The lower plate of the DC blocking capacitor C6 is connected to the negative terminal of the switch S5, and the connection point is designated as node Vo2.

[0035] The gain linear calibration circuit 3 includes a PMOS transistor M12 and an NMOS transistor M10 controlled by the output of the first inverter NOT1, a negative feedback PMOS transistor M11 controlled by the common-mode voltage output from the common-mode voltage detection circuit 1, and a reset switch S9 controlled by an external clock. The source of the PMOS transistor M12 is connected to the power supply VDD, the gate of the PMOS transistor M12 is connected to the gate of the NMOS transistor M10 and receives the control signal output from the output node INVB of the first inverter NOT1, the drain of the PMOS transistor M12 is connected to the source of the negative feedback PMOS transistor M11, the gate of the negative feedback PMOS transistor M11 receives the common-mode voltage output from node CM of the common-mode voltage detection circuit 1, the drain of the negative feedback PMOS transistor M11 is connected to the drain of the NMOS transistor M10 and the negative terminal of the switch S9, the positive terminal of the switch S9 is connected to the voltage Vinit, and the source of the NMOS transistor M10 is grounded.

[0036] The flicker noise suppression circuit 4 includes a resistor R1 that generates the gate bias voltage of MOS transistor M2, an NMOS transistor M1, and a switch S1 controlled by an external clock. One end of the resistor R1 is connected to the power supply VB. The other end of the resistor R1, the drain of NMOS transistor M1, the gate of NMOS transistor M1, the gate of MOS transistor M2, and the positive terminal of switch S1 are connected. The negative terminal of switch S1 is grounded. The source of NMOS transistor M1, the negative terminal of switch S1, and the source of MOS transistor M2 are all grounded.

[0037] Among them, MOSFETs M1-M7 and M10 are NMOS transistors, while MOSFETs M8 and M9, and MOSFETs M11 and M12 are PMOS transistors. The substrates of all NMOS devices are grounded, and the substrates of all PMOS devices are connected to the power supply VDD. Switches S1-S9 can be implemented using a single MOSFET or complementary CMOS switches, and are turned on in the high-level state. For ease of description, see attached... Figure 3 In the diagram, switches S1-S9 are denoted by a "-" symbol, indicating the negative terminal, and "+" symbol, indicating the positive terminal. Switches S1-S3 and S6-S9 are controlled by an external clock signal CLK, while switches S4 and S5 are controlled by the output of the second inverter NOT2.

[0038] The working state of the present invention is described in detail below:

[0039] During the reset phase, CLK is high, switches S1-S3 and S6-S9 are turned on, and nodes Vo1, Vo2, Vxn, Vxp, and CM are reset to high level VDD. The output node INVB of the first inverter NOT1 is low, MOSFET M12 is turned on, and MOSFET M10 is turned off. The output node INV of the second inverter NOT2 is high, switches S3 and S4 are turned on, and output nodes Von and Vop are also reset to high level VDD. Because switch S9 is turned on, the gate of MOSFET M2 is reset to low level ground, MOSFET M2 is in the cutoff region, and the differential dynamic operational amplifier is in the off state to save power. The gate of MOSFET M3 is reset to the initial voltage Vinit. At this time, the common mode level of output nodes Von and Vop is VDD, that is, the voltage of node CM is VDD.

[0040] In the amplification phase, CLK is low, and switches S1-S3 and S6-S9 are off. Since the voltage at the initial node CM is still high, switches S4 and S5 remain on. Because switch S1 is off, MOSFET M1 is on. The bias voltage generated by MOSFET M1 and resistor R1 is applied to the gate of MOSFET M2, causing MOSFET M2 to turn on. At this time, INVB is low, MOSFET M12 is on, and MOSFET M10 is off. Since the gate voltage of MOSFET M3 is reset to Vinit, it is now on, providing current for the dynamic amplifier. The dynamic amplifier then enters the amplification phase.

[0041] The amplification phase of a dynamic amplifier can be divided into three stages. In the first amplification stage, due to the reset phase, the source and drain terminals of MOSFETs M6 and M7 are pulled to the power supply VDD. Cross-coupled MOSFETs M6 and M7 are in the cutoff region, and the current integrates across the load capacitors C1 and C2. Assuming the input signal VIP voltage is greater than VIN, the voltage drop at node Vxn is faster than at node Vxp until MOSFET M6 turns on, ending the first amplification stage. The duration of the first amplification stage can be expressed as:

[0042]

[0043] In equation (1), V th,n I0 is the threshold voltage of the cross-coupled NMOS transistor, and I1 is the current flowing through MOS transistor M4. During the second amplification stage, MOS transistor M6 is turned on but M7 remains off. Since the voltage at output node Vop is still VDD, the voltage at node Vxn remains at (VDD - V0). th,nCurrents I1-I3 integrate across capacitor C3, while current I2 continues to integrate across capacitor C2. At this point, MOSFET M8 is in the linear region, and current I3 is related to the voltage at node Von. The second amplification stage ends when MOSFET M7 turns on. The duration of the second amplification stage can be expressed as:

[0044]

[0045] In equation (2), I2 is the current flowing through MOSFET M5. The third amplification stage begins when MOSFET M7 is turned on and ends when the output common-mode voltage CM reaches approximately VDD / 2. The voltage at node CM can be expressed as:

[0046]

[0047] In equation (3), C is the DC blocking capacitor for detecting the common-mode voltage of the output, i.e., C5 = C6 = C. X The parasitic capacitance at node CM is given by parasitic C. X Much smaller than the DC blocking capacitor (C5 / C6), CM is approximately the common-mode voltage of nodes Vo1 and Vo2. When the voltage at CM drops to the inverter threshold, the output INVB of the first inverter NOT1 becomes high, and the output INV of the second inverter NOT2 becomes low, causing MOSFET M12 to turn off, MOSFET M10 to turn on, and the bias voltage of the gate of MOSFET M3 to be pulled down to low ground. MOSFET M3 is in the cutoff region, the tail current source is cut off, and the voltages at nodes Vo1 and Vo2 are sampled onto the load capacitors C3 and C4. At the same time, switches S4 and S5 are turned off to prevent charge leakage on the load capacitors, and the overall amplification process ends. During the third amplification stage, since the cross-coupled NMOS transistors M6 and M7 are both in the on state, the voltage drop rate at nodes Von and Vxp is the same. Similarly, the voltage drop rate at nodes Vop and Vxn is also the same. The duration of the third amplification stage can be expressed as:

[0048]

[0049]

[0050] In equation (4), Vcm is the trigger level of the common-mode detection circuit, typically around VDD / 2. Because MOSFETs M8 and M9 are relatively small, their overdrive voltages are also small, so currents I3 and I4 are much smaller than currents I1 and I2. Therefore, the dynamic amplifier remains in dynamic operating mode. The gain of dynamic amplifier circuit 2 can be expressed as:

[0051]

[0052] In equation (6), gm,n For the transconductance of the NMOS input pair transistors (M4 / M5), g m,p This refers to the transconductance of the pseudo-differential PMOS input pair (M8 / M9). As can be seen from the gain expression, adding this pseudo-differential input pair increases the effective transconductance of the circuit. Furthermore, its common-mode current reduces the denominator of the gain expression, thus effectively improving the open-loop gain. Inserting a pair of cross-coupled NMOS transistors (M6 / M7) into the discharge path effectively accelerates the decrease in the output common-mode voltage, further improving the gain. The overall timing diagram of the dynamic operational amplifier is attached. Figure 6 As shown.

[0053] Typically, the gain of a dynamic amplifier decreases as the input signal amplitude increases because the differential current of the input pair MOSFETs is not linearly related to the input signal amplitude. Assuming the input pair MOSFETs are ideal, then I1(VICM + 1 / 2ΔVIN) + I2(VICM - 1 / 2ΔVIN) should be a constant, where ΔVIN = VIP - VIN, and VICM is the common-mode input voltage. However, in reality, due to the different drain voltages of input pair MOSFETs M4 and M5, the above statement is incorrect. The common-mode current expression for the input pair MOSFETs is:

[0054]

[0055] Since ΔVIN is always opposite to (Vxn-Vxp), when the amplitude of the differential input signal increases, I cm,n Reduce, as shown in the appendix Figure 4 As shown. When ΔVIN is negative, the result is the opposite. Based on the above, the relationship between CM, VF, and the amplitude of the differential input signal ΔVIN is shown in the attached figure. Figure 5 As shown. When the input signal amplitude is small, a larger I 1+ The value of I2 causes CM to drop faster in the initial time. MOSFET M11 provides a negative feedback loop gain, leading to an increase in VF, which in turn increases the value of I1+I2. During amplification, the small difference in the initial time between the two cases (different differential input signal amplitudes) is amplified by positive feedback. Through this feedback, the duration of the amplification process is automatically adjusted to be proportional to the differential input amplitude. The drop in VF at the beginning of the amplification process is caused by the sudden grounding of the source of MOSFET M3 after CLK goes low. At this time, node VF is floating and MOSFET M11 is not yet turned on, so the initial voltage still needs to be higher than the threshold voltage of MOSFET M3 after the drop. With the same input signal amplitude, a longer amplification time means a higher gain. Therefore, as the gain is a function of the input signal amplitude, the nonlinearity of the dynamic operational amplifier gain is suppressed.

[0056] Furthermore, for integrators based on traditional operational amplifiers, only the flicker noise of the input transistor pair is generally considered. Due to the amplifier's high common-mode rejection ratio, the flicker noise on the tail current source can be ignored. However, for dynamic operational amplifiers, due to the reset mechanism, the charge accumulated on the reset phase integrator introduces a differential voltage on the gate of the input transistor pair. In this case, flicker noise on the tail current can appear at the output node. Therefore, this invention adds a switching switch to the gate of MOSFET M1. The bias voltage of MOSFET M2 is generated through resistor R1 and MOSFET M1 and is only used during amplification. During reset, the gate of MOSFET M1 is grounded, and its operating state is in the cutoff region. By cyclically switching the operating state of MOSFET M1 between the strong inversion region and the cutoff region, flicker noise can be reduced at its physical source.

[0057] In addition, Figure 1 This is a schematic diagram of the noise-shaping SAR ADC structure used in the high-gain, high-linearity, low-power differential dynamic operational amplifier of the present invention. In the loop filter of the noise-shaping SAR ADC, the present invention constructs an integrator circuit to integrate the margin voltage, so that the loop filter circuit has better noise-shaping capability.

[0058] Appendix Figure 2 The circuit diagram is that of a traditional differential dynamic operational amplifier. Compared with the traditional differential dynamic operational amplifier, the differential dynamic operational amplifier proposed in this invention adds a pair of cross-coupled NMOS transistors and a pseudo-differential PMOS input pair to improve the open-loop gain of the dynamic amplifier. Furthermore, to address the problem that the gain of the dynamic amplifier decreases as the input signal amplitude increases, a gain linearity calibration circuit 3 is designed. To reduce the flicker noise of the tail current source, a switching bias circuit is designed to reduce flicker noise at its physical source.

[0059] Appendix Figure 7 The transient simulation diagram shows the high-gain, high-linearity, and low-power differential dynamic operational amplifier of this invention. With a differential input signal Vin of 2mV, the output signal Vout is 40.6mV, achieving a gain of 20 times (open-loop gain of 26dB) and a settling time of approximately 4.7ns. This meets the requirements of a high-speed, high-precision noise-shaping SAR ADC for a dynamic operational amplifier. There is a trade-off between the settling time and open-loop gain of the dynamic operational amplifier; a longer settling time leads to increased gain, while a shorter settling time reduces the open-loop gain. The choice can be made based on actual needs in specific applications.

[0060] Through the above technical solutions, compared with traditional dynamic operational amplifiers, the dynamic amplifier circuit 2 proposed in this invention inserts a pair of cross-coupled NMOS transistors in the discharge path, effectively improving the output common-mode voltage drop speed and increasing the open-loop gain. Simultaneously, based on the original NMOS input pair, a pair of pseudo-differential PMOS input pairs is added. The common-mode current of the PMOS input pair serves as a bypass current, and the differential-mode current effectively increases the transconductance, further improving the amplifier's open-loop gain. The common-mode voltage detection circuit 1 has advantages such as simple circuit structure, fast response speed, and low power consumption. When the output common-mode voltage is lower than the detection threshold voltage, the amplifier's tail current source is turned off, effectively saving power. To address the problem of dynamic amplifier gain decreasing with increasing input differential signal amplitude, a gain linearity calibration circuit 3 is designed based on time-domain linearization technology. This automatically adjusts the duration of the amplification process to be proportional to the input signal amplitude. The larger the input differential signal amplitude, the longer the amplification process duration, and the higher the gain, thus suppressing the nonlinearity of the dynamic amplifier gain. To reduce the flicker noise of the tail current transistor, a switching bias technique is used. By cyclically switching the operating state of the bias circuit, the flicker noise of the tail current transistor is reduced at its physical source. Therefore, the dynamic operational amplifier circuit proposed in this invention has the characteristics of high open-loop gain, good gain linearity, and low overall power consumption. The integrator built based on this dynamic amplifier has low power consumption and high integration accuracy. The corresponding loop filter has strong noise shaping capability, which can effectively improve the accuracy and energy efficiency of the noise-shaped SAR ADC.

[0061] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A differential dynamic operational amplifier for use in noise-shaping SAR ADCs, characterized in that, The system includes a dynamic amplifier circuit, a flicker noise suppression circuit, a gain linearity calibration circuit, and a common-mode voltage detection circuit. The common-mode voltage detection circuit is connected to both the dynamic amplifier circuit and the gain linearity calibration circuit. The gain linearity calibration circuit is connected to the dynamic amplifier circuit, and the dynamic amplifier circuit is connected to the flicker noise suppression circuit. The dynamic amplifier circuit inserts a pair of cross-coupled NMOS transistors in the discharge path to increase the output common-mode voltage drop rate. The common-mode voltage detection circuit detects the output common-mode voltage. When the output common-mode voltage drops to the detection threshold of the common-mode detection circuit, it outputs a feedback control signal to cut off the dynamic amplifier circuit and stop it from working. The gain linearity calibration circuit positively amplifies the difference in the initial time amplitude of the input signal and feeds it back to the dynamic amplifier circuit to adjust the duration of the amplification process, thereby turning the amplification process time into a function of the input signal amplitude and suppressing the nonlinearity of the gain of the dynamic amplifier circuit. The flicker noise suppression circuit suppresses flicker noise in the dynamic amplifier circuit; The dynamic amplifier circuit includes a differential input pair, a pseudo-differential input pair, a tail current source switching MOSFET M3 controlled by a common-mode voltage detection circuit and a gain linearity calibration circuit, and a tail current source MOSFET M2 controlled by an external clock. The cross-coupled NMOS transistors are MOSFETs M6 and M7. The differential input pair includes MOSFETs M4 and M5, and the pseudo-differential input pair includes MOSFETs M8 and M9. The sources of MOSFETs M8 and M9 are both connected to the power supply VDD. The drains of M8 and M9 are connected to the drains of MOSFETs M6 and M7 respectively. The sources of MOSFETs M6 and M7 are connected to the drains of MOSFETs M4 and M5 respectively. The sources of MOSFETs M4 and M5 are connected to the drain of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M2. The source of MOSFET M2 is grounded. The gates of MOSFETs M4 and M8 are connected to voltage VIP. The gates of MOSFETs M5 and M9 are connected to voltage VIN. The dynamic amplification circuit also includes switches S4 and S5 controlled by a common-mode voltage detection circuit, and reset switches S2, S3, S6, and S7 controlled by an external clock. The positive terminals of switches S6 and S7 are connected to the power supply VDD, the negative terminal of switch S6 is connected to the source of MOSFET M8, and the negative terminal of switch S7 is connected to the drain of MOSFET M9. The positive terminal of switch S4 is grounded, and the negative terminal of switch S4 is connected to the connection between MOSFET M8 and MOSFET M6. The positive terminal of switch S5 is grounded, and the negative terminal of switch S5 is connected to the connection between MOSFET M9 and MOSFET M7. The negative terminals of switches S2 and S3 are both connected to the power supply VDD, the positive terminal of switch S2 is connected to the connection between MOSFET M6 and MOSFET M4, and the positive terminal of switch S3 is connected to the connection between MOSFET M7 and MOSFET M5.

2. The differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 1, characterized in that, The dynamic amplification circuit also includes load capacitors C1 to C4. The upper plate of load capacitor C3 is connected to the positive terminal of switch S4, and a node Von is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C4 is connected to the positive terminal of switch S5, and a node Vop is set on the connection line, while the lower plate is grounded. The upper plate of load capacitor C1 is connected to the positive terminal of switch S2, and the connection point serves as node Vxn, while the lower plate is grounded. The upper plate of load capacitor C2 is connected to the positive terminal of switch S3, and the connection point serves as node Vxp, while the lower plate is grounded.

3. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 2, characterized in that, The common-mode voltage detection circuit includes a reset switch S8 controlled by an external clock, DC blocking capacitors C5 and C6 for detecting the common-mode voltage at the output terminal, and a feedback signal generation circuit composed of a first inverter and a second inverter cascaded together. The positive terminal of the switch S8 is connected to the power supply VDD. The input terminal of the feedback signal generation circuit, the negative terminal of the switch S8, the upper plate of the DC blocking capacitor C5, and the upper plate of the DC blocking capacitor C6 are connected, and the connection point is designated as node CM. The lower plate of the DC blocking capacitor C5 is connected to the negative terminal of the switch S4, and the connection point is designated as node Vo1. The lower plate of the DC blocking capacitor C6 is connected to the negative terminal of the switch S5, and the connection point is designated as node Vo2.

4. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 3, characterized in that, The gain linear calibration circuit includes a PMOS transistor M12 and an NMOS transistor M10 controlled by the output of a first inverter, a negative feedback PMOS transistor M11 controlled by the common-mode voltage output from the common-mode voltage detection circuit, and a reset switch S9 controlled by an external clock. The source of the PMOS transistor M12 is connected to the power supply VDD, the gate of the PMOS transistor M12 is connected to the gate of the NMOS transistor M10 and receives the control signal output from the output node INVB of the first inverter, the drain of the PMOS transistor M12 is connected to the source of the negative feedback PMOS transistor M11, the gate of the negative feedback PMOS transistor M11 receives the common-mode voltage output from node CM of the common-mode voltage detection circuit, the drain of the negative feedback PMOS transistor M11 is connected to the drain of the NMOS transistor M10 and the negative terminal of the switch S9, the positive terminal of the switch S9 is connected to the voltage Vinit, and the source of the NMOS transistor M10 is grounded.

5. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 4, characterized in that, The flicker noise suppression circuit includes a resistor R1 that generates the gate bias voltage of MOS transistor M2, an NMOS transistor M1, and a switch S1 controlled by an external clock. One end of the resistor R1 is connected to the power supply VB. The other end of the resistor R1, the drain of NMOS transistor M1, the gate of NMOS transistor M1, the gate of MOS transistor M2, and the positive terminal of switch S1 are connected. The negative terminal of switch S1 is grounded. The source of NMOS transistor M1, the negative terminal of switch S1, and the source of MOS transistor M2 are all grounded.

6. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 5, characterized in that, When the external clock is high, switches S1-S3 and S6-S9 are turned on, and nodes Vo1, Vo2, Vxn, Vxp, and CM are reset to the high level VDD. The output node INVB of the first inverter is low, PMOS transistor M12 is turned on, and NMOS transistor M10 is turned off. The output node INV of the second inverter is high, and switches S3 and S4 are turned on. Output nodes Von and Vop are also reset to the high level VDD. Since switch S9 is turned on, the gate of MOS transistor M2 is reset to the low level ground. MOS transistor M2 is in the cutoff region, and the differential dynamic operational amplifier used in the noise-shaping SAR ADC is in the off state. The gate of MOS transistor M3 is reset to the initial voltage Vinit. At this time, the common mode level of output nodes Von and Vop is VDD, that is, the voltage of node CM is VDD.

7. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 5, characterized in that, When the external clock is low, switches S1-S3 and S6-S9 are turned off. Since the voltage at node CM is still high, switches S4 and S5 are still conducting. Because switch S1 is turned off, NMOS transistor M1 is turned on. The bias voltage generated by NMOS transistor M1 and resistor R1 is applied to the gate of MOS transistor M2, and MOS transistor M2 is turned on. At this time, node INVB is low, PMOS transistor M12 is turned on, and NMOS transistor M10 is turned off. Since the gate voltage of MOS transistor M3 is reset to voltage Vinit, it is now in the conducting state, providing current for the dynamic amplifier circuit. The dynamic amplifier circuit begins to enter the amplification working state.

8. A differential dynamic operational amplifier for noise-shaping SAR ADC according to claim 7, characterized in that, The amplification operation of the dynamic amplifier circuit includes a first amplification stage, a second amplification stage, and a third amplification stage. In the first amplification stage, at the beginning, MOSFETs M6 and M7 are in the cutoff region. Assuming that voltage VIP is greater than voltage VIN, the voltage drop rate at node Vxn is faster than that at node Vxp, until MOSFET M6 turns on, and the first amplification stage ends. In the second amplification stage, at the beginning, MOSFET M6 is on but MOSFET M7 remains off, until M7 turns on, and the second amplification stage ends. In the third amplification stage, at the beginning, both cross-coupled MOSFETs M6 and M7 are on, the voltage drop rates at nodes Von and Vxp are the same, and the voltage drop rates at nodes Vop and Vxn are also the same. The third amplification stage ends when the output common-mode voltage CM reaches VDD / 2.

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