A PWM signal generation method and apparatus

Abstract

The PWM signal generation method and device provided by the application are applied to the field of power electronics technology, the method first controls a clock device to output a first clock signal and a second clock signal, then counts the first clock signal and the second clock signal in a preset number mode respectively, controls a phase adjustment device to adjust the phase of the second clock signal according to a preset phase difference during the counting process, and finally controls a signal generation device to output a current period PWM signal according to the counting value of the second clock signal or the counting values of the first clock signal and the second clock signal. Since the phase of the second clock signal changes, the corresponding signal width changes under the condition of using the same counting value, and further, since the preset phase difference is smaller than the clock period, the change of the signal width is correspondingly smaller than the clock period, that is, the PWM signal with a resolution smaller than the clock period and higher accuracy is realized, thereby meeting the actual application requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a PWM signal generation method and device. BACKGROUND

[0002] In some application scenarios in the field of power electronics, a given high-precision PWM signal is required for power electronic switching devices to achieve more accurate action control of the power electronic switching devices, and specifically, the resolution of the PWM signal can reach about 200 ps. The PWM signal is represented by the duration of high and low levels, and the duration of high and low levels is adjusted to control the on-off time of the power electronic switching device. Therefore, the finer the resolution of the PWM signal level width adjustment is, the easier the fine output adjustment is.

[0003] For a PWM signal generation method based on an FPGA (Field Programmable Gate Array, programmable logic device), the clock signal output by the clock device inside the FPGA is usually counted, and the signal period of the clock signal is fixed. The product of the signal period and the count value is the corresponding time, and the count value of the required clock signal is adjusted to control the duration of the high and low levels of the PWM signal. That is, the minimum adjustment resolution of the PWM signal, that is, the minimum adjustment amount of the pulse width, corresponds to the signal period of the clock signal.

[0004] However, in the prior art, the clock period of the clock signal is basically fixed, and the minimum is 10 ns or 5 ns, resulting in a minimum resolution of 5 ns for the PWM signal width adjustment, which is difficult to achieve high-precision PWM signal output and cannot meet the actual application requirements. SUMMARY

[0005] The present application provides a PWM signal generation method and device, which adjusts the phase of the clock signal to achieve finer adjustment of the level duration under the same count value, realizes high-precision PWM signal output, and meets the actual application requirements.

[0006] To achieve the above-mentioned purposes, the technical solutions provided by the present application are as follows:

[0007] In one aspect, the present application provides a PWM signal generation method, comprising:

[0008] controlling a clock device to output a first clock signal and a second clock signal;

[0009] counting the first clock signal and the second clock signal in a pre-designed manner, respectively;

[0010] controlling the phase adjusting device to adjust the phase of the second clock signal by a preset phase difference during the counting process;

[0011] wherein the preset phase difference is less than a clock period of the second clock signal;

[0012] controlling the signal generating device to output the PWM signal of the current period according to the count value of the second clock signal, or the count values of the first clock signal and the second clock signal.

[0013] Optionally, the controlling the phase adjusting device to adjust the phase of the second clock signal by a preset phase difference during the counting process comprises:

[0014] controlling the phase adjusting device to adjust the phase of the second clock signal by a first preset phase difference when the count value of the second clock signal is less than a preset half-period count value;

[0015] wherein the preset half-period count value is set based on a duty cycle of the PWM signal.

[0016] Optionally, the controlling the signal generating device to output the PWM signal of the current period according to the count values of the first clock signal and the second clock signal comprises:

[0017] controlling the signal generating device to perform level switching of the PWM signal of the current period according to the count value of the second clock signal;

[0018] controlling the signal generating device to stop outputting the PWM signal of the current period according to the count value of the first clock signal.

[0019] Optionally, the controlling the signal generating device to perform level switching of the PWM signal of the current period according to the count value of the second clock signal comprises:

[0020] controlling the signal generating device to output a first level of the PWM signal of the current period before the count value of the second clock signal reaches the preset half-period count value;

[0021] controlling the signal generating device to switch the first level to a second level of the PWM signal of the current period when the count value of the second clock signal reaches the preset half-period count value;

[0022] controlling the signal generating device to maintain outputting the second level when the count value of the second clock signal is greater than or equal to the preset half-period count value and the count value of the first clock signal is less than a preset full-period count value.

[0023] Optionally, the controlling the signal generation device to stop outputting the PWM signal of the current period according to the count value of the first clock signal comprises:

[0024] controlling the signal generation device to stop outputting the second level when the count value of the first clock signal reaches a preset full-period count value.

[0025] Optionally, the method further comprises: clearing the count value of the first clock signal and the count value of the second clock signal when the count value of the first clock signal is equal to the preset full-period count value.

[0026] Optionally, the controlling the phase adjustment device to adjust the phase of the second clock signal by the preset phase difference during the counting process comprises:

[0027] controlling the phase adjustment device to adjust the phase of the second clock signal according to a second preset phase difference when the count value of the second clock signal is greater than or equal to a preset half-period count value and less than the preset full-period count value.

[0028] Optionally, the process of outputting the PWM signal of the current period according to the count value of the second clock signal comprises:

[0029] controlling the signal generation device to perform level switching of the PWM signal of the current period according to the count value of the second clock signal;

[0030] controlling the signal generation device to stop outputting the PWM signal of the current period according to the count value of the second clock signal.

[0031] Optionally, the controlling the signal generation device to perform level switching of the PWM signal of the current period according to the count value of the second clock signal comprises:

[0032] controlling the signal generation device to output a first level of the PWM signal of the current period before the count value of the second clock signal reaches the preset half-period count value;

[0033] controlling the signal generation device to switch the first level to a second level of the PWM signal of the current period when the count value of the second clock signal is equal to the preset half-period count value;

[0034] controlling the signal generation device to maintain outputting the second level when the count value of the second clock signal is greater than or equal to the preset half-period count value and less than the preset full-period count value.

[0035] Optionally, the controlling the signal generation device to stop outputting the PWM signal of the current period according to the count value of the second clock signal comprises:

[0036] In a case where the count value of the second clock signal reaches the preset full cycle count value, the signal generation device is controlled to stop outputting the second level.

[0037] Optionally, the method further comprises: in a case where the count value of the second clock signal reaches the preset full cycle count value, clearing the count value of the second clock signal.

[0038] Optionally, in the process of controlling the signal generation device to output the first level of the PWM signal of the current cycle, the phase adjustment device is controlled to adjust the phase of the second clock signal according to a third preset phase difference.

[0039] Optionally, the preset counting mode comprises one of increment counting, decrement counting, increment-decrement counting and decrement-increment counting.

[0040] The second aspect of the present application provides a PWM signal generation device, comprising: a clock device, a phase adjustment device, a signal generation device and a main controller, wherein,

[0041] The first output end of the clock device is connected with the signal generation device;

[0042] The second output end of the clock device is connected with the signal generation device through the phase adjustment device;

[0043] The main controller is connected with the clock device, the phase adjustment device and the signal generation device respectively;

[0044] The main controller executes the PWM signal generation method according to any one of the preceding aspects.

[0045] The PWM signal generation method provided by the present application first controls the clock device to output a first clock signal and a second clock signal, then counts the first clock signal and the second clock signal according to a preset counting mode, and controls the phase adjustment device to adjust the phase of the second clock signal according to a preset phase difference during the counting process; finally, according to the count value of the second clock signal or the count values of the first clock signal and the second clock signal, the signal generation device outputs the PWM signal of the current cycle. Due to the change of the phase of the second clock signal, the corresponding signal width changes under the same count value. Further, since the preset phase difference is less than the clock cycle, the change of the signal width is correspondingly less than the clock cycle, that is, a PWM signal with resolution less than the clock cycle and higher accuracy is realized, thereby meeting the actual application requirements. BRIEF DESCRIPTION OF DRAWINGS

[0046] ​In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0047] Figure 1 is a flow chart of a PWM signal generation method provided by an embodiment of the present application;

[0048] Figures 2a-2d is a waveform schematic diagram of a first PWM signal generation process provided by an embodiment of the present application;

[0049] Figures 3a-3d is a waveform schematic diagram of a second PWM signal generation process provided by an embodiment of the present application;

[0050] Figures 4a-4d is a waveform schematic diagram of a third PWM signal generation process provided by an embodiment of the present application;

[0051] Figures 5a-5d is a waveform schematic diagram of a fourth PWM signal generation process provided by an embodiment of the present application;

[0052] Figures 6a-6d is a waveform schematic diagram of a fifth PWM signal generation process provided by an embodiment of the present application;

[0053] Figures 7a-7d is a waveform schematic diagram of a sixth PWM signal generation process provided by an embodiment of the present application;

[0054] Figures 8a-8d is a waveform schematic diagram of a seventh PWM signal generation process provided by an embodiment of the present application;

[0055] Figures 9a-9d is a waveform schematic diagram of an eighth PWM signal generation process provided by an embodiment of the present application;

[0056] Figures 10a-10d is a waveform schematic diagram of a ninth PWM signal generation process provided by an embodiment of the present application;

[0057] Figures 11a-11d is a waveform schematic diagram of a tenth PWM signal generation process provided by an embodiment of the present application;

[0058] Figures 12a-12d is a waveform schematic diagram of an eleventh PWM signal generation process provided by an embodiment of the present application;

[0059] Figures 13a-13dis a waveform schematic diagram of a 12th PWM signal generation process provided by an embodiment of the present application.

[0060] Figure 14 is a structural schematic diagram of a PWM signal generation device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0062] The PWM signal generation method provided by the present application is applied to an electronic device, and in the case of implementing a PWM signal generation device based on an FPGA, can be specifically applied to a main controller of the signal generation device. Of course, in actual application, it can also be applied to other controllers capable of controlling the PWM generation process. Referring to Figure 1 , Figure 1 is a flowchart of a PWM signal generation method provided by an embodiment of the present application. The flow of the PWM signal generation method provided by the present embodiment can include:

[0063] S100, controlling a clock device to output a first clock signal and a second clock signal.

[0064] In existing applications, the clock device can output a clock signal according to a preset signal period, and the corresponding time length can be determined by counting the clock signal. The PWM signal generation method provided by the present embodiment controls the clock device to output a first clock signal and a second clock signal. In actual application, in order to simplify the counting process of the subsequent steps, the frequencies of the first clock signal and the second clock signal are the same, that is, the signal periods are the same, and before the phase of the second clock signal is adjusted, the phases of the first clock signal and the second clock signal are also the same.

[0065] It should be noted that the first clock signal and the second clock signal have different roles in the present application, which will be described in detail in the subsequent content, and will not be described here.

[0066] S110, counting the first clock signal and the second clock signal respectively according to a preset counting manner.

[0067] Optionally, the pre-design counting manner described in the embodiment can be any one of increment counting, decrement counting, increment-decrement counting and decrement-increment counting. In actual application, the specific selection of the pre-design counting manner is not limited by the application, and the specific counting implementation process of various counting manners will be illustrated in subsequent content by specific examples, which will not be described in detail here.

[0068] S120, controlling the phase adjusting device to adjust the phase of the second clock signal according to the preset phase difference during the counting process.

[0069] According to the basic knowledge of the PWM signal, the PWM signal belongs to a square wave signal that is repeatedly reproduced according to a fixed period. The PWM signal of any period includes a certain length of high level and a certain length of low level, and the signal generation process of each period is consistent. The embodiment introduces the generation process of the PWM signal of the current period. As for the PWM signal of the subsequent period after the current period, the PWM signal generation method provided by the embodiment can be repeatedly executed. Based on this, the counting process described in this step refers to the counting process corresponding to the generation of the PWM signal of the current period.

[0070] It can be understood that if the phase of the clock signal is adjusted before starting counting, and the counting is started after the phase adjustment is completed, it has no effect on the counting process. Since the signal period of a single clock signal is not changed, the product of the clock signal and the counting value will not change, that is, the corresponding statistical time length will not change. However, changing the phase of the clock signal during the counting process will cause the counting value to change in advance or delay, so that the corresponding statistical time length is different under the same counting value, thereby realizing the adjustment of the level width of the PWM signal.

[0071] The phase adjusting device in the existing application can realize high-resolution phase adjustment. In general, it can realize a phase change of less than 100 ps, which is much lower than the high-precision resolution requirement of 200 ps in the existing application. Therefore, as long as the preset phase difference is less than the clock period of the second clock signal, the PWM signal adjustment with a resolution higher than that of the existing application can be realized.

[0072] Further, for the implementation requirements of high-precision PWM signals mainly include two aspects, one is the high-precision PWM signal edge, that is, the time of high-low level flip transition in the PWM signal is more accurate and detailed adjustment, in this case, the period of the PWM signal is unchanged, therefore, it can also be understood as more accurate adjustment of the duty cycle of the PWM signal; The second is the high-precision PWM signal period adjustment, based on the composition of the PWM signal, in this case, the width of the high level of the PWM signal can be adjusted, or the width of the low level of the PWM signal can be adjusted, at present, in the case of only period adjustment, the time of level flip of the PWM signal cannot be changed, that is, the process of period adjustment can only occur in the second half of the PWM signal. Based on this, the selection of the timing and the preset phase difference of the phase adjustment of the second clock signal is different under different application requirements. In order to distinguish, the preset phase difference when the edge adjustment is carried out is defined as the first preset phase difference, and the preset phase difference when the period adjustment is carried out is defined as the second preset phase difference. Of course, whether it is the first preset phase difference or the second preset phase difference, the corresponding time length is less than the period length of the clock signal.

[0073] Based on the foregoing, for the application requirement of high-precision PWM signal period, the phase adjustment device should be controlled to adjust the phase of the second clock signal according to the second preset phase difference when the count value of the second clock signal is greater than or equal to the preset half-period count value and less than the preset full-period count value, wherein the preset full-period count value is the clock signal count value corresponding to a complete PWM signal.

[0074] For the application requirement of high-precision PWM signal edge, the phase adjustment device should be controlled to adjust the phase of the second clock signal according to the first preset phase difference when the count value of the second clock signal is less than the preset half-period count value, wherein the preset half-period count value is set based on the duty cycle of the PWM signal. As described above, the signal count value corresponding to a complete PWM signal is the preset full-period count value, and the product of the preset full-period count value and the duty cycle is the preset half-period count value. Therefore, the preset half-period count value can also be understood as the count value of the clock signal corresponding to the level flip within the period of the PWM signal.

[0075] In addition to the above two typical implementation requirements, it can also be required to adjust the edge and period of the PWM signal at the same time. In this case, the above cases need to be implemented comprehensively, which will be described in subsequent embodiments. Here, it is not described in detail.

[0076] S130, according to the count value of the second clock signal, or the count values of the first clock signal and the second clock signal, the signal generation device outputs the PWM signal of the current period.

[0077] As described before, the implementation requirements of high-precision PWM signal include two aspects of high-precision PWM signal edge and high-precision PWM signal period adjustment, and the signal period adjustment is mainly completed according to the count value of the second clock signal, and the signal edge adjustment needs to combine the count value of the first clock signal and the count value of the second clock signal to be implemented. Of course, in actual application, it is also possible to adjust the edge and the period of the PWM signal at the same time, and the present application can also complete this adjustment process.

[0078] It should be noted that the counting of the clock signal and the level output of the PWM signal are carried out at the same time, that is, the signal generation device outputs the first level of the PWM signal synchronously when the counting of the clock signal starts, and in the subsequent counting process, the first level is switched to the second level or the generation of the current period of the PWM signal is ended and the generation of the next period of the PWM signal is further started according to the specific count value. Therefore, the control of the signal generation device to output the PWM signal according to the specific count value in the present step is actually throughout the whole PWM signal generation process.

[0079] It can be understood that the first level mentioned in the foregoing can be a high level or a low level, and correspondingly, in the case that the first level is a high level, the second level is a low level, and in the case that the first level is a low level, the second level is a high level.

[0080] In summary, the PWM signal generation method provided by the embodiment of the present application adjusts the phase of the second clock signal in the counting process. Since the phase of the second clock signal changes, the corresponding signal width changes under the condition of using the same count value, and further, since the preset phase difference is less than the clock period, the change of the signal width will be less than the clock period, that is, the PWM signal with resolution less than the clock period and higher precision is realized.

[0081] Further, by selecting the phase adjustment opportunity, at least one of the edge adjustment and the period adjustment can be specifically realized, which fully meets the actual application requirements.

[0082] The process of outputting the PWM signal by the PWM signal generation method provided by the application will be described below in combination with specific waveform diagrams. It should be noted that, as described above, there are various ways of counting the clock signal, and there are various types of PWM signal, and in addition, there are various high-precision adjustment requirements of the PWM signal, and various specific embodiments can be combined, and the subsequent content will summarize the adjustment processes of similar types and be highlighted. Among them, the first type of PWM signal refers to outputting low level in the first half cycle and outputting high level in the second half cycle; correspondingly, the second type of PWM signal refers to outputting high level in the first half cycle and outputting low level in the second half cycle.

[0083] In subsequent embodiments, clk1 represents the first clock signal, clk2 represents the second clock signal; counter represents the counting value of the clock signal, which can represent the counting of the first clock signal or the counting of the second clock signal in specific embodiments, which will be described in specific embodiments; PWM_1 and PWM_1' are reference waveform diagrams given for the convenience of understanding the scheme, and are not the waveform diagrams of the actually output PWM signal, and only the corresponding waveform under the Final output label represents the actually output PWM signal.

[0084] Based on the above description, refer to Figure 2a , Figure 2a A generation process of the first type of PWM signal using incremental counting to achieve high-precision edge adjustment is shown.

[0085] As shown in FIG. 2, the number of clock signals is counted by using incremental counting while the control clock device outputs the first clock signal and the second clock signal at the same time. It can be understood that, in the case where the first clock signal and the second clock signal have the same frequency, since the first preset phase difference is smaller than the clock period of the second clock signal, the preset half cycle counting value corresponding to the first clock signal and the preset half cycle counting value corresponding to the second clock signal are actually the same, except that the time when they actually reach the preset half cycle counting value will be different, of course, which is also the key to achieving high-precision signal edge adjustment of the application. Therefore, counter in FIG. 2 can represent the counting requirement of the first clock signal and the second clock signal at the same time, wherein N represents the preset half cycle counting value, and pe and 0 represent the preset full cycle counting value in different cases. It can be understood that, in the case of incremental counting of the clock signal, pe represents the preset full cycle counting value, and on the contrary, in the case of decremental counting of the clock signal, 0 represents the preset full cycle counting value.

[0086] During the high-precision PWM signal edge adjustment process, the control signal generation device stops the output of the PWM signal for the current cycle according to the count value of the first clock signal. That is, the total pulse width of the PWM signal for the current cycle (including the width of the high level and the width of the low level) is determined according to the count value of the first clock signal. At the same time, the timing of level switching within the current cycle is determined according to the count value of the second clock signal.

[0087] like Figure 2a As shown, before the count value of the second clock signal reaches the preset half-cycle count value N, the control signal generation device outputs the first level of the PWM signal of the current cycle, i.e., a low level, and during the process of the count value of the second clock signal reaching the preset half-cycle count value N, the control device shifts the phase of the second clock signal backward by a first preset phase difference T. PS1 Because the clock signal phase shifts backward, the time it takes for the count value to reach the preset half-cycle count value shifts backward, thus lengthening the corresponding duration of the first level and increasing the level width from T before the phase shift. L， The final output T L +T PS1， Of course, since the phase of the first clock signal is not adjusted, the total width of the PWM signal in the current cycle will not be affected.

[0088] When the count value of the second clock signal equals the preset half-cycle count value, it indicates that the expected width of the first level has been reached. The control signal generation device then switches the first level to the second level of the PWM signal for the current cycle, i.e., outputs... Figure 2a The high level is shown. Furthermore, when the count value of the second clock signal is greater than or equal to the preset half-cycle count value and the count value of the first clock signal is less than the preset full-cycle count value, the control signal generating device maintains the output of the second level, that is, realizes the continuous output of the high level.

[0089] Finally, when the count value of the first clock signal reaches the preset full-cycle count value, the control signal generating device stops outputting the second level. Referring to Figure 2 and the foregoing, this embodiment controls the period of the PWM signal in the current cycle by controlling the count value of the first clock signal. Since the first clock signal is not phase-shifted, the period of the final output PWM signal remains unchanged. However, compared to the reference PWM waveform shown in PWM_1 in Figure 2, the width of the high level of the final output PWM signal is reduced to T. H -T PS1 The timing of the PWM signal transmission level flipping edge was adjusted by T. PS1 Compared to edge adjustment in existing technologies that requires a minimum change of one clock cycle, the corresponding duration clearly has a smaller resolution and higher precision in edge adjustment.

[0090] forFigures 2b-2d For the specific adjustment process, please refer to the above. Figure 2a The implementation details will not be elaborated here. Among them, Figure 2b This illustrates the process of edge-leading a first-type PWM signal. Figure 2c This illustrates the process of edge-shifting the second type of PWM signal. Figure 2d This illustrates the process of edge-forwarding a second type of PWM signal.

[0091] Optional, see Figures 3a-3d This illustrates the process of achieving high-precision PWM edge adjustment using a decrementing counting method.

[0092] The PWM signal period is controlled by a decrementing count using the first clock signal. The PWM signal level is then controlled to flip when the count on the second clock signal reaches a preset half-cycle count value N. For Figure 3a and Figure 3b Before time N, it is assumed that the high-precision pulse width T to be achieved has been determined. PS1 The second clock signal is shifted forward or backward by a phase T. PS1 Then the width of the high or low level of the equivalent PWM signal in the current cycle is adjusted to (T H / T L ±T PS1 ).

[0093] for Figure 3c and Figure 3d Before time 1, assuming the second clock signal has been phase-shifted forward or backward by TPS2 according to the desired high-precision pulse width TPS2, the equivalent PWM signal high or low level width is adjusted to (TH / TL±TPS2). The first type represents a high level output when the counter is greater than N, and the second type represents a low level output when the counter is greater than N.

[0094] Optional, Figures 4a-4d This illustrates the process of outputting a PWM signal using an incrementing and decrementing counting method, i.e., first incrementing and then decrementing. Similar to the previous embodiment, the first clock signal is used to complete the full cycle of the PWM signal (i.e., counting a preset full-cycle count value) using the incrementing and decrementing counting method. The second clock signal is used to complete the counting of level flips within the PWM signal cycle. The PWM signal level flips when the incrementing count reaches a preset half-cycle count value N, and correspondingly, the PWM signal level flips when the decrementing count reaches the preset half-cycle count value N.

[0095] Before the increment count reaches N, it is assumed that the desired high-precision pulse width T has already been determined. PS1 The second clock signal is shifted forward or backward by a phase T. PS1then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS1 ) respectively.

[0096] Before the moment when the decrement count is N, it is assumed that the high precision pulse width T PS2 , the second clock signal is phase shifted forward or backward by T PS2 , then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS2 ) respectively. The first type represents that when the counter is greater than N, the high level is output, and the second type represents that when the counter is greater than N, the low level is output.

[0097] Optionally, Figures 5a-5d The process of outputting the PWM signal by using the decrement-increment count, i.e., the count mode of first decreasing and then increasing, is shown. Similar to the foregoing embodiments, the full period of the PWM signal is completed by using the first clock signal through the decrement-increment count, i.e., the count of the preset full period count value, and the count of the level inversion within the PWM signal period is completed by using the second clock signal, the PWM signal level inversion is performed at the moment when the decrement count is the preset half period count value N, and correspondingly, the PWM signal level inversion is performed at the moment when the increment count is the preset half period count value N.

[0098] Before the moment when the decrement count is N, it is assumed that the high precision pulse width T PS1 , the second clock signal is phase shifted forward or backward by T PS1 , then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS1 ) respectively.

[0099] Before the moment when the increment count is N, it is assumed that the high precision pulse width T PS2 , the second clock signal is phase shifted forward or backward by T PS2 , then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS2 ) respectively. The first type represents that when the counter is greater than N, the high level is output, and the second type represents that when the counter is greater than N, the low level is output.

[0100] Optionally, the foregoing embodiments of FIG. 2-FIG. 5 respectively show the implementation process of performing the high precision adjustment of the PWM signal edge, and for any embodiment, when the count value of the first clock signal is equal to the preset full period count value, the count value of the first clock signal and the count value of the second clock signal can be cleared, and the output of the PWM signal of the next period is further developed.

[0101] The following describes the process of high-precision adjustment of the PWM signal period:

[0102] See Figures 6a-6d As mentioned earlier, PWM_1 shown in any waveform diagram is not the actual output PWM signal; PWM_1' is the actual output PWM signal. By comparing PWM_1 and PWM_1', the periodic change of the PWM signal can be clearly shown. In this embodiment, counter represents the counting method for the second clock signal. It should be noted that since the process of adjusting the PWM signal period can be achieved solely by the second clock signal, in order to reduce overall energy consumption, the clock device can be controlled to output only the second clock signal. Of course, from the perspective of simplifying the control logic, this difference can also be ignored, and the first clock signal and the second clock signal can be output simultaneously as described above, and both can be counted at the same time.

[0103] by Figure 6a For example, while controlling the clock device to output the second clock signal, the number of clock signals is counted by incrementing the count, and the signal generation device is controlled to switch the level of the PWM signal of the current cycle according to the count value of the second clock signal, and the output of the PWM signal of the current cycle is stopped.

[0104] Specifically, such as Figure 6a As shown, before the count value of the second clock signal reaches the preset half-cycle count value N, the control signal generating device outputs the first level of the PWM signal of the current cycle, that is, the low level; when the count value of the second clock signal is equal to the preset half-cycle count value N, the control signal generating device switches the first level to the second level of the PWM signal of the current cycle, that is, switches from the low level to the high level.

[0105] Furthermore, when the count value of the second clock signal is greater than or equal to the preset half-cycle count value N and less than the preset full-cycle count value pe, the control signal generating device maintains the output of the second level, and during the process of maintaining the output of the second level, controls the second clock signal to shift backward by a distance equal to the second preset phase difference T. PS When the count value of the second clock signal reaches the preset full-cycle count value, the control signal generating device stops outputting the second level and ends the output of the PWM signal for the current cycle.

[0106] It is understandable that because the phase of the second clock signal shifts backward, the duration corresponding to the count value of the second clock signal changes, thus affecting the time elapsed relative to the clock signal. Figure 6a The period of PWM_1 shown in the figure has changed, that is, the period of the PWM signal has been lengthened, and the change in period is T. PSThe corresponding time length. As mentioned above, since the second preset phase difference is less than the signal period of the second clock signal, the PWM signal period adjustment less than the clock signal period is realized.

[0107] Further, in the case that the count value of the second clock signal reaches the preset full period count value, the output of the current period PWM signal is completed, and the count value of the second clock signal can be cleared to zero, so as to prepare for the output of the next period PWM signal.

[0108] For the specific adjustment process of Figures 6b-6d , please refer to the above Figure 6a implementation, which will not be repeated here. Among them, Figure 6b shows the process of extending the period of the second type of PWM signal, Figure 6c shows the process of shortening the period of the first type of PWM signal, Figure 6d shows the process of shortening the period of the second type of PWM signal. Among them, T PR represents the PWM signal period before the period adjustment, T PR ±T PS represents the period of the PWM signal after the period adjustment.

[0109] Optionally, based on the above content, please refer to Figures 7a-7d , which shows the process of realizing high-precision PWM period adjustment by using the decreasing count mode.

[0110] The count of the PWM signal period adjustment process is completed by the decreasing count mode. When the count value of the second clock signal reaches the preset half period count value N, the PWM signal is controlled to perform level inversion, and when the count value decreases to 0, the signal generation device stops outputting the second level, realizing the period adjustment of the current period PWM signal. At the beginning of the next period, that is, at the time when the count is pe, the next PWM signal is started to be output. By shifting the second clock signal forward or backward by T PS , the equivalent PWM signal period realizes high-precision period adjustment (T PR ±T PS ). The first type represents that when the counter is greater than or equal to N, the high level is output, and the second type represents that when the counter is greater than or equal to N, the low level is output.

[0111] Optionally, please refer to Figures 8a-8d , which shows the process of realizing high-precision PWM signal period adjustment by using the increasing and decreasing count mode.

[0112] The high-precision adjustment of the PWM signal period is completed by means of increment and decrement counting, as shown in the figure, the PWM signal flips to high / low level at the moment of increment counting N, the PWM signal flips to low / high level at the moment of decrement counting N, at any moment in the whole counting period except 0, the FPGA internal clock is phase-shifted forward or backward by T PS , the equivalent PWM signal period realizes high-precision period adjustment (T PR ±T PS ). The first type represents that high level is outputted when the counter is greater than N, and the second type represents that low level is outputted when the counter is greater than N.

[0113] Optionally, referring to Figures 9a-9d , the process of realizing high-precision PWM signal period adjustment by means of decrement and increment counting is shown.

[0114] The high-precision adjustment of the PWM signal period is completed by means of increment and decrement counting, as shown in the figure, the PWM signal flips to high / low level at the moment of increment counting N, the PWM signal flips to low / high level at the moment of decrement counting N, at any moment in the whole counting period except 0, the FPGA internal clock is phase-shifted forward or backward by T PS , the equivalent PWM signal period realizes high-precision period adjustment (T PR ±T PS ). The first type represents that high level is outputted when the counter is greater than N, and the second type represents that low level is outputted when the counter is greater than N.

[0115] Further, the embodiment of the present application also provides a signal generation method capable of simultaneously adjusting the edge and period of the PWM signal.

[0116] Based on the foregoing, when the edge of the PWM signal is adjusted, the phase of the second clock signal needs to be adjusted in the corresponding first half period of the PWM signal, and the counting value of the first clock signal is relied on to ensure that the period of the PWM signal does not change, and correspondingly, if the edge and the period are simultaneously adjusted, the first clock signal is no longer needed to ensure that the period of the PWM signal does not change, therefore, the edge and the period of the PWM signal are simultaneously adjusted, only the second clock signal is relied on.

[0117] As described above, the edge adjustment must be completed in the first half period of the PWM signal, that is, in the process that the counting value of the second clock signal is less than the preset half period counting value, that is, the current period PWM signal is in the first level, the phase adjustment device adjusts the phase of the second clock signal according to the third preset phase difference. Of course, the third preset phase difference is already less than the signal period of the second clock signal.

[0118] Through the above adjustment, the length of time for the second clock signal count value to reach the preset half cycle count value can be changed, and high-precision adjustment of the PWM signal edge is realized. The specific implementation principle can be referred to the foregoing content, which will not be repeated here.

[0119] When the second clock signal count value reaches the preset half cycle count value, the control signal generation device switches the level of the PWM signal, i.e., from the first level to the second level.

[0120] In the case where the second clock signal count value is greater than or equal to the preset half cycle count value and less than the full cycle count value, the control signal generation device maintains the output of the second level, and in the case where the second clock signal count value reaches the preset full cycle count value, the control signal generation device stops outputting the second level, completing the simultaneous adjustment of the PWM signal edge and cycle.

[0121] Based on the foregoing content, referring to Figures 10a-10d , the generation process of the reference waveform of the PWM signal before adjustment is shown by using the first clock signal in the form of incrementing count. At the moment when the count is N, the PWM signal flips to high / low level. When the count reaches the preset full cycle count value, the output of the current cycle PWM signal is stopped. The width of the high level of the obtained current cycle PWM signal is T H , and the width of the low level is T L . Based on the foregoing description of the phase shift moment, the second clock signal is phase shifted forward or backward by T PS , and the equivalent PWM signal cycle realizes high-precision cycle adjustment (T PR ±T PS ).

[0122] Before reaching the preset full cycle count value, it is assumed that the high-precision pulse width T PS1 to be realized has been achieved. The second clock signal is phase shifted forward or backward by T PS1 , and the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS1 (±T PS )). At the beginning of the next cycle, the second clock signal is right shifted by T c -T ps1 to restore alignment with the first clock signal (of course, the clock device can also be controlled to re-output the first clock signal and the second clock signal). T c is the cycle of the first clock clk1.

[0123] Before the second clock signal count value reaches the preset half cycle count value, it is assumed that the high-precision pulse width T PS2 to be realized has been achieved. The second clock signal is phase shifted forward or backward by T PS2, the high or low level width of the equivalent PWM signal is adjusted to (T H / T L ±T PS2 (±T PS )), at the beginning of the new period, the second clock signal is right shifted by T c -T ps2 to restore alignment with the first clock signal. Here, the change of duty cycle needs to consider the influence of T PS during the period adjustment, according to the value, adjust the size of T PS1 , T PS2 to achieve the final PWM signal edge adjustment effect, the first type represents when the counter is greater than N, output high level, the second type represents when the counter is greater than N, output low level.

[0124] Optionally, see Figures 11a-11d , by using the first clock signal in the form of decreasing count to show the generation process of the reference waveform of the PWM signal before adjustment, at the moment when the count is N, the PWM signal flips to high / low level, when the count reaches the preset full period count value, stop outputting the PWM signal of the current period, the width of the high level of the obtained PWM signal of the current period is T H , and the width of the low level is T L . Based on the foregoing description of the phase shift moment, the second clock signal is forward or backward phase shifted by T PS , then the high precision period adjustment (T PR ±T PS ) of the equivalent PWM signal period is realized.

[0125] Before reaching the preset full period count value, it is assumed that the second clock signal has been forward or backward phase shifted by T PS1 according to the high precision pulse width T PS1 to be realized, then the high or low level width of the equivalent PWM signal is adjusted to (T H / T L ±T PS1 (±T PS )), at the beginning of the new period, the second clock signal is right shifted by T c -T ps1 to restore alignment with the first clock signal, T c is the period of the first clock clk1.

[0126] Before reaching the preset half period count value, it is assumed that the second clock signal has been forward or backward phase shifted by T PS2 according to the high precision pulse width T PS2 to be realized, then the high or low level width of the equivalent PWM signal is adjusted to (T H / T L ±TPS2 (±T PS ), at the beginning of the next cycle, the second clock signal is right shifted by T c -T ps2 is recovered to align with the first clock signal. Here the high level width, low level width change needs to consider the influence of T PS , according to the value, adjust the size of T PS1 , T PS2 to achieve the final PWM signal edge adjustment effect, the first type represents when the counter is greater than N, output high level, the second type represents when the counter is greater than N, output low level.

[0127] Optionally, see Figures 12a-12d , by increasing and then decreasing the count, the first clock signal is used to show the generation process of the reference waveform of the PWM signal before adjustment, for any adjustment, the width of the high level of the PWM signal is T H , and the width of the low level is T L . Based on the foregoing phase shift moment description, the second clock signal is forward or backward shifted by T PS , then the equivalent PWM signal period realizes high-precision period adjustment (T PR ±T PS ).

[0128] Before the N count down moment, it is assumed that the high-precision pulse width T PS1 to be achieved has been adjusted according to the second clock signal, which is forward or backward shifted by T PS1 , then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS1 (±T PS )), at the beginning of the new cycle, the second clock signal is right shifted by T c -T ps1 is recovered to align with the first clock signal, and T c is the period of the first clock clk1.

[0129] Before the N count up moment, it is assumed that the high-precision pulse width T PS2 to be achieved has been adjusted according to the second clock signal, which is forward or backward shifted by T PS2 , then the equivalent PWM signal high or low level width is adjusted to (T H / T L ±T PS2 (±T PS )), at the beginning of the new cycle, the second clock signal is right shifted by T c -T ps2 is recovered to align with the first clock signal, and T cis the period of the first clock clk1. Here, the change of duty cycle needs to consider the influence of T PS , adjust T PS1 , T PS2 according to the value to achieve the final PWM signal edge adjustment effect, the first type represents when the counter is greater than N, output high level, the second type represents when the counter is greater than N, output low level.

[0130] Optionally, see Figures 13a-13d , by first reducing and then increasing the count to use the first clock signal to show the generation process of the reference waveform of the PWM signal before adjustment, without any adjustment, the width of the high level of the PWM signal is T H , the width of the low level is T L . Based on the foregoing description of the phase shift moment, the second clock signal is phase shifted forward or backward T PS , then the equivalent PWM signal period achieves high-precision period adjustment (T PR ± T PS ).

[0131] Before the N count is increased, it is assumed that the second clock signal has been phase shifted left or right T H according to the high-precision pulse width T L to be achieved, then the equivalent PWM signal high or low level width is adjusted to (T PS1 / T PS ± T c (± T ps2 )), at the beginning of the next period, the second clock signal is right shifted T c -T PS2 to restore alignment with the first clock signal, T PS2 is the period of the first clock clk1.

[0132] Before the N count is reduced, it is assumed that the second clock signal has been phase shifted left or right T PS according to the high-precision pulse width T c to be achieved, then the equivalent PWM signal high or low level width is adjusted to (T ps2 / T c ± T PS (± T PS1 )), at the beginning of the next period, the second clock signal is right shifted T PS2 -T to restore alignment with the first clock signal, T

[0001] is the period of the first clock clk1. Here, the change of duty cycle needs to consider the influence of T , adjust T , TPS2 The size of the counter is used to achieve the final PWM signal edge adjustment effect, the first type represents that a high level is output when the counter is greater than N, and the second type represents that a low level is output when the counter is greater than N.

[0133] It should be noted that in any of the above embodiments, the first clock signal and the second clock signal have the same frequency, and before the second clock signal is phase-shifted, the phases of the two are also the same. However, as an optional implementation, the frequencies of the first clock signal and the second clock signal can be different, and for the same expected output PWM signal, only the corresponding preset count values of the first clock signal and the second clock signal need to be set.

[0134] Optionally, referring to Figure 14 , Figure 14 is a structural block diagram of a PWM signal generation device provided by an embodiment of the present application. The PWM signal generation device provided by the embodiment includes a clock device, a phase adjustment device, a signal generation device, and a main controller, wherein

[0135] The first output end of the clock device is connected with the signal generation device;

[0136] The second output end of the clock device is connected with the signal generation device through the phase adjustment device;

[0137] The main controller is connected with the clock device, the phase adjustment device, and the signal generation device respectively;

[0138] The main controller executes the PWM signal generation method provided by any of the above embodiments.

[0139] The embodiments in the present application are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0140] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with the above disclosed method and technical content without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical solution of the present application, all still belong to the protection scope of the technical solution of the present application.

Claims

1. A PWM signal generation method characterized by, The application relates to a clock signal control method and device. The application comprises: controlling a clock device to output a first clock signal and a second clock signal; wherein the first clock signal and the second clock signal have the same frequency, and the first clock signal and the second clock signal have the same phase before the phase of the second clock signal is adjusted; counting the first clock signal and the second clock signal in a pre-designed manner respectively; controlling a phase adjustment device to adjust the phase of the second clock signal by a preset phase difference when the counting value of the second clock signal is less than a preset full cycle counting value; wherein the preset phase difference is less than the clock cycle of the second clock signal; controlling a signal generation device to output a current cycle PWM signal according to the counting value of the second clock signal, or the counting values of the first clock signal and the second clock signal; wherein the signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the first clock signal.

2. The PWM signal generation method according to claim 1, characterized by, The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal. The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal. The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal.

3. The PWM signal generation method according to claim 1, characterized by, The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal. The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal. The signal generation device outputs the current cycle PWM signal according to the counting value of the second clock signal, which comprises: controlling the signal generation device to switch the level of the current cycle PWM signal according to the counting value of the second clock signal; and controlling the signal generation device to stop the output of the current cycle PWM signal according to the counting value of the second clock signal. ​ 4. The PWM signal generation method according to claim 1, characterized by, The control of the signal generation device to stop outputting the PWM signal of the current period according to the count value of the first clock signal comprises: controlling the signal generation device to stop outputting a second level when the count value of the first clock signal reaches a preset full-period count value.

5. The PWM signal generation method according to claim 4, characterized by, Further comprising: clearing the count value of the first clock signal and the count value of the second clock signal when the count value of the first clock signal is equal to the preset full-period count value.

6. The PWM signal generation method according to claim 1, characterized by, The control of the phase adjustment device to adjust the phase of the second clock signal by a preset phase difference when the count value of the second clock signal is less than a preset full-period count value comprises: controlling the phase adjustment device to adjust the phase of the second clock signal by a second preset phase difference when the count value of the second clock signal is greater than or equal to a preset half-period count value and less than a preset full-period count value.

7. The PWM signal generation method according to claim 1, characterized by, The control of the signal generation device to switch the level of the PWM signal of the current period according to the count value of the second clock signal comprises: controlling the signal generation device to output a first level of the PWM signal of the current period before the count value of the second clock signal reaches a preset half-period count value; controlling the signal generation device to switch the first level to a second level of the PWM signal of the current period when the count value of the second clock signal is equal to the preset half-period count value; controlling the signal generation device to maintain outputting the second level when the count value of the second clock signal is greater than or equal to the preset half-period count value and less than a preset full-period count value.

8. The PWM signal generation method according to claim 1, characterized by, The control of the signal generation device to stop outputting the PWM signal of the current period according to the count value of the second clock signal comprises: controlling the signal generation device to stop outputting a second level when the count value of the second clock signal reaches a preset full-period count value.

9. The PWM signal generation method according to claim 8, characterized by, Further comprising: clearing the count value of the second clock signal when the count value of the second clock signal reaches the preset full-period count value.

10. The PWM signal generation method according to claim 7, characterized by, controlling the phase adjustment device to adjust the phase of the second clock signal by a third preset phase difference during the process of controlling the signal generation device to output the first level of the PWM signal of the current period.

11. The PWM signal generation method according to any one of claims 1 to 10, characterized by, The preset count mode comprises one of increment count, decrement count, increment-decrement count and decrement-increment count.

12. A PWM signal generating apparatus characterized by comprising: comprising: a clock device, a phase adjustment device, a signal generation device and a main controller, wherein, a first output end of the clock device is connected with the signal generation device; a second output end of the clock device is connected with the signal generation device through the phase adjustment device; the main controller is connected with the clock device, the phase adjustment device and the signal generation device respectively; the main controller executes the PWM signal generation method of any one of claims 1-11.

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