Method for improving tracking performance of clock data recovery circuit and system applicable thereto

Abstract

The present invention provides a clock data recovery system, including a phase detector and an adaptive pulse width control (APWC) module. The phase detector is used to sample a data signal to obtain a plurality of sampled values. The APWC module is used to provide a bandwidth adjustment signal to the phase detector according to a data conversion rate obtained from the sampled values. Wherein the phase detector adjusts the pulse width of the output signal according to the bandwidth adjustment signal.

Description

Technical Field

[0001] The present invention relates to a control method for a clock data recovery circuit and a system applicable thereto, and more particularly to a method and a system for improving the tracking performance of a clock data recovery circuit. Background Art

[0002] A clock data recovery (CDR) circuit is often used in high-speed transmission applications, and is generally used to recover the phase and / or frequency information of an input data signal by, for example, obtaining the rising / falling edges of the data signal. Existing CDR circuits, such as Figure 1 shown, for example, include a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO).

[0003] Generally speaking, most clock data recovery circuits applied to high-speed transmission use a bang-bang (BB) phase detector to perform phase detection and / or correction of the CDR circuit. When the bang-bang phase detector-clock data recovery (BBPD-CDR) is applied to different data types, if the tracking ability of the BBPD-CDR is insufficient (for example, the tracking ability for frequency), it will result in insufficient jitter tolerance, which affects the stability of the clock recovery loop. Although various coding formats can be used to reduce the impact, it will result in additional coding overhead. Therefore, how to improve the tracking ability of the clock data recovery circuit will be a major goal in the research and development of this field. Summary of the Invention

[0004] The present invention provides a clock data recovery system, including a phase detector and an adaptive pulse width control (APWC) module. The phase detector is used to sample a data signal to obtain a plurality of sampled values. The APWC module is used to provide a bandwidth adjustment signal to the phase detector according to a data conversion rate obtained from the sampled values. Wherein the phase detector adjusts the pulse width of the output signal according to the bandwidth adjustment signal.

[0005] The present invention provides a control method for a clock data recovery circuit, including: sampling a data signal through a phase detector and obtaining a plurality of sampled values; calculating a data conversion rate of the data signal according to the sampled values; and adjusting the output pulse width of the phase detector according to the data conversion rate.

[0006] In one embodiment, the phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data conversion rate.

[0007] In one embodiment, the input of the pulse width adjustment module further includes a clock signal, and the adjustment clock signal lags behind the clock signal.

[0008] In one embodiment, the amplitude by which the adjustment clock signal lags behind the clock signal is between 0.5UI and 1.5UI.

[0009] In one embodiment, when the data conversion rate is in a first interval, the phase detector outputs a first pulse width; when the data conversion rate is in a second interval, the phase detector outputs a second pulse width; when the data conversion rate is in a third interval, the phase detector outputs a third pulse width.

[0010] In one embodiment, the first interval is between 100% and 50%; the second interval is between 50% and 30%; the third interval is below 30%.

[0011] As described above, the first pulse width adjustment module receives the clock signal and the first adjustment clock signal and outputs an adjustment signal, thereby providing an appropriate pulse width. When the charge pump charges or discharges according to the appropriate pulse width, the generation or influence of jitter in the clock data recovery circuit will be reduced. Thus, the purpose of improving the loop stability of the clock data recovery circuit is achieved. Brief Description of the Drawings

[0012] Figure 1 Schematic diagram of an existing clock data recovery circuit architecture.

[0013] Figure 2 Schematic diagram of the clock data recovery circuit architecture in an embodiment of the present invention.

[0014] Figure 3 Schematic diagram of a phase detector in an embodiment of the present invention.

[0015] Figure 4 Signal timing diagram of a phase detector in an embodiment of the present invention.

[0016] Figure 5 Schematic diagram of a phase detector in an embodiment of the present invention.

[0017] Figure 6 Signal timing diagram of a phase detector in an embodiment of the present invention.

[0018] Figure 7 Flowchart of the control method of the clock data recovery circuit in an embodiment of the present invention.

[0019] Description of Main Component Symbols:

[0020] 10 Clock Data Recovery System

[0021] 100, 300 Phase Detector

[0022] 111 - 1118 Sampling Component

[0023] 121 - 1218 Comparison Component

[0024] 131 - 1318 Pulse Width Adjustment Module

[0025] 141 - 1418 Output Component

[0026] DS Data Signal

[0027] CLK1 - CLK18 Clock Signal

[0028] D1 - D18 Sampling Values

[0029] CS1 - CS18 Control Signals

[0030] AS1 - AS18 Adjustment Signals

[0031] OS1 - OS18 Output Signals

[0032] S1, S2, S3 Steps

[0033] PD Phase Detector

[0034] CP Charge Pump

[0035] LF Loop Filter

[0036] VCO Voltage - Controlled Oscillator

[0037] APWCM Adaptive Pulse Width Control Module Detailed Implementation Manner

[0038] The following will clearly explain the spirit of the present invention with the accompanying drawings and detailed descriptions. After any person skilled in the art understands the embodiments of the present invention, the techniques recorded in the present invention can be changed and modified, which do not deviate from the spirit and scope of the present invention.

[0039] Regarding the use of "first", "second",... etc. in this article, it does not particularly refer to the meaning of order or sequence, nor is it used to limit the present invention. It is only used to distinguish components or operations described with the same technical terms. Regarding the use of "comprising", "including", "having", "containing", etc. in this article, they are all open - ended terms, that is, they mean including but not limited to.

[0040] Regarding the terms used in this document, unless otherwise specified, they generally have the ordinary meanings in the field where each term is used, in the context disclosed herein, and in the specific context. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of the present invention.

[0041] In the drawings, for clarity, the thickness of layers, plates, regions, or spaces, etc. is exaggerated. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, plate, region, or space is referred to as being "on" or "connected to" another element, it can be interpreted as being directly on or connected to the other element, or it can be interpreted as having or there being an intermediate element between the element and the other element. As used herein, "connected" or "coupled" can refer to physical and / or electrical connections. Furthermore, to simplify the drawings and highlight the content presented in the drawings, existing structures or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner.

[0042] As Figure 2 shown, Figure 2 A clock data recovery system 10 using the clock data recovery circuit control method disclosed in the present invention is illustrated. The clock data recovery system 10 includes a phase detector PD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, and an Adaptive Pulse Width Control (APWC) module APWCM. Specifically, the phase detector PD is, for example, a bang-bang phase detector, and preferably a half-rate or multi-rate (such as but not limited to 1 / 4-rate or 1 / 9-rate) bang-bang (BB) phase detector PD. After receiving the data transition rate DTR provided by the phase detector PD, the Adaptive Pulse Width Control module APWCM provides a bandwidth adjustment signal PMS to the phase detector PD according to the data transition rate DTR. The phase detector PD adjusts the bandwidth of the output signal of the phase detector PD according to the bandwidth adjustment signal PMS.

[0043] It should be noted that the definition of the data conversion rate DTR is, for example, the number of data conversions in a unit data length. For example, in a unit data length, the number of conversions from a low level (binary "0") to a high level (binary "1") or from a high level to a low level. The calculation of the data conversion rate DTR can be calculated by the phase detector PD and provided to the adaptive pulse width control module APWCM, or can be calculated by the adaptive pulse width control module APWCM. For example, the adaptive pulse width control module APWCM can calculate the number of data conversions based on the data transmitted by the phase detector PD. The present invention is not limited to the calculation method of the data conversion rate DTR.

[0044] In one embodiment, the adaptive pulse width control module APWCM can adjust the bandwidth of the phase detector PD and divide it into three states according to the data conversion rate DTR. Specifically, as shown in Table 1 below, when the data conversion rate is in the first interval, the phase detector PD outputs a first pulse width; when the data conversion rate is in the second interval, the phase detector PD outputs a second pulse width; when the data conversion rate is in the third interval, the phase detector PD outputs a third pulse width. In a preferred embodiment, the first interval is the range where the data conversion rate is from 100% to 50%; the second interval is the range where the data conversion rate is from 50% to 30%; the third interval is the range where the data conversion rate is less than 30%. In a preferred embodiment, the first pulse width is 0.5UI; the second pulse width is 1UI; the third pulse width is 1.5UI. It should be noted that the above embodiments only illustrate that the data conversion rate can be divided into several intervals and corresponding pulse widths are provided according to the interval to which the data conversion rate belongs. The present invention is not limited to the number and range of the intervals of the data conversion rate and is not limited to the width of the provided pulse widths. Any similar concept of providing different pulse widths according to the data conversion rate should fall within the scope of the present invention.

[0045] Table 1. Corresponding relationship between data conversion rate and pulse width.

[0046] Data conversion rate Pulse width First interval (100% - 50%) First pulse width (0.5UI) Second interval (50% - 30%) Second pulse width (1UI) Third interval (<30%) Third pulse width (1.5UI)

[0047] In one embodiment, taking the data length of a data packet as 9 UI as an example, the maximum number of conversions in a data packet with a length of 9 UI is 9 times and the minimum is 2 times. It can be divided into three intervals and different pulse widths are given for different intervals. For example, the number of conversions in the first interval can be between 9 and 6 times, and the first pulse width can be 0.5 UI. If the bandwidth of the clock data recovery system 10 is calculated to be proportional to the number of data conversions and the pulse width of charge and discharge, the change in the loop bandwidth in this interval is from 4.5 to 3. The number of conversions in the second interval can be between 5 and 4 times, and the second pulse width can be 1 UI. The change in the loop bandwidth in this interval is from 5 to 4; the number of conversions in the third interval can be between 3 and 2 times, and the third pulse width can be 1.5 UI. The change in the loop bandwidth in this interval is from 4.5 to 3. Preferably, the product of the number of conversions and the pulse width (change in loop bandwidth) in each interval is preferably substantially equal or approximate. Based on this setting, when the data conversion rate or the number of data conversions is low, good frequency tracking ability can still be achieved by adjusting the value of the pulse width, thereby optimizing the jitter tolerance of the clock data recovery system.

[0048] In one embodiment, as Figure 3 shown, a phase detector 100 is described, which includes a first sampling element 111, a second sampling element 112, a first comparison element 121, a first pulse width adjustment module 131, and a first output element 141. The first sampling element 111 samples the data signal DS corresponding to the first clock signal CLK1 and outputs a first sampled value D1. The second sampling element 112 samples the data signal DS corresponding to the second clock signal CLK2 and outputs a second sampled value D2. Specifically, the first sampling element 111 and / or the second sampling element 112 can be, but are not limited to, flip-flops or other elements that sample according to clock signals. In addition, the definitions of the sampling elements 111 and 112 corresponding to the clock signals CLK1 and CLK2 are, for example but not limited to, edge-triggered according to the rising edge point and / or the falling edge point of the clock signals CLK1 and CLK2. The data signal DS and the sampled values D1 and D2 are, for example but not limited to, serial digital signals and the bit values in the serial digital signals.

[0049] The first comparison element 121 is coupled to the first sampling element 111 and the second sampling element 112 and receives a first sampling value D1 and a second sampling value D2. Specifically, the first comparison element 121 is, for example but not limited to, a comparator or a logic gate, and preferably an Exclusive OR (XOR) logic gate. When the first sampling value D1 and the second sampling value D2 are different, the first comparison element 121 outputs a first comparison signal CS1. For example, if the value of the first sampling value D1 is the binary value "1" and the value of the second sampling value D2 is the binary value "0", then the first sampling value D1 and the second sampling value D2 are different. The definition of the first comparison signal CS1 is, for example, the comparison result of the first sampling value D1 and the second sampling value D2. For example, when the first sampling value D1 and the second sampling value D2 are different, the first comparison signal CS1 is the binary value "1". Conversely, when the first sampling value D1 and the second sampling value D2 are the same, the first comparison signal CS1 is the binary value "0". It should be noted that the above examples are only for illustrating the embodiments and not for limiting the present invention.

[0050] such as Figure 3 and Figure 4As shown, the first pulse width adjustment module 131 receives the third clock signal CLK3 and the first adjustment clock signal ACK1. For example, the first pulse width adjustment module 131 can be implemented by, but not limited to, a logic circuit or a switch circuit. There is a time interval TS between the positive edge point P3 of the third clock signal CLK3 and the positive edge point PA1 of the first adjustment clock signal ACK1. Specifically, the clock widths (Pulse width, PW) of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are the same as each other. In addition, the positive edge point P1 of the first clock signal CLK1, the positive edge point P2 of the second clock signal CLK2, and the positive edge point P3 of the third clock signal CLK3 lag behind each other in sequence, and the lag amplitude is the lag width DW. Preferably, the lag width DW is 0.5UI. For example, the positive edge point P2 of the second clock signal CLK2 lags behind the positive edge point P1 of the first clock signal CLK1 by an amplitude of 0.5UI, and the positive edge point P3 of the third clock signal CLK3 also lags behind the positive edge point P2 of the second clock signal CLK2 by an amplitude of 0.5UI. It should be noted that the lag width DW by which the clock signals CLK1 - CLK3 of the present invention lag behind each other is not limited to 0.5UI. On the other hand, the present invention is not limited to the number of clock signals. In other words, the present invention can have clock signals CLK1 - CLKX, where the number of clock signals is X, and X is any positive integer greater than 3. In an embodiment, when the phase detector 100 is applied to a clock data recovery circuit with a 1 / N rate architecture, X will be equal to twice N. The first adjustment clock signal ACK1 can be one of the clock signals CLK1 - CLKX that lags behind the third clock signal CLK3. The width of the time interval TS is preferably 0.5UI, 1UI, or 1.5UI. For example, when the lag amplitude of each of the clock signals CLK1 - CLKX in sequence is 0.5UI and the time interval TS between the positive edge point P3 of the third clock signal CLK3 and the positive edge point PA1 of the first adjustment clock signal ACK1 is 0.5UI, the first adjustment clock signal ACK1 can be the fourth clock signal CLK4. Next, the first pulse width adjustment module 131 outputs the first adjustment signal AS1 within the time interval TS. For example, as Figure 3 shown, the first adjustment signal AS1 outputs the binary value "1" within the time interval TS and outputs the binary value "0" in the remaining intervals. In this way, a first adjustment signal AS1 with a width equal to the time interval TS can be generated.

[0051] The first output element 141 is coupled to the first comparison element 121 and the first pulse width adjustment module 131 and receives the first comparison signal CS1 and the first adjustment signal AS1. Specifically, the first output element 141 is, for example, a logic circuit element. The first output element 141 performs a logical operation on the first comparison signal CS1 and the first adjustment signal AS1 and then outputs a first output signal OS1. In one embodiment, the logical operation is an AND logical operation. In this embodiment, for example, when both the first comparison signal CS1 and the first adjustment signal AS1 are binary value "1", the first output signal OS1 is binary value "1". In addition, in one embodiment, the first output signal OS1 output by the first output element 141 can be provided to a charge pump connected at the back end. In this embodiment, the first output signal OS1 is, for example, an up signal or a down signal provided to the charge pump. The first output element 141 can adjust the first comparison signal CS1 according to the width of the first adjustment signal AS1. Through the above phase detector 100, the clock data recovery circuit can provide an appropriate charging and / or discharging time for the charge pump, reducing the integral response of the loop filter. Thus, the entire clock data recovery circuit reduces jitter generation through this setting.

[0052] In one embodiment, the present invention can be applied to a clock data recovery circuit with a 1 / N rate architecture where N is greater than 2 by increasing the number of phase detectors and clock signals. Figure 5 and Figure 6 A phase detector 300 applied to a 1 / 9 rate architecture and its related timing diagram are described. When applied to a 1 / 9 rate architecture, there are a total of 18 groups of clock signals CLK1 - CLK18, 18 groups of sampling elements 111 - 1118, 18 groups of comparison elements 121 - 1218, 18 groups of pulse width adjustment modules 131 - 1318, and 18 groups of output elements 141 - 1418. The clock signals CLK1 - CLK18 lag behind each other in sequence, and the lag amplitude is 0.5UI. The pulse width of each clock signal CLK1 - CLK18 is 4.5UI. After the data signal DS is sampled by the sampling elements 111 - 1118 corresponding to the clock signals CLK1 - CLK18 respectively, the sampled values D1 - D18 are provided to the comparison elements 121 - 1218 for comparison. It should be noted that each comparison element 121 - 1218 only inputs two adjacent sampled values. For example, the sampled values input by the comparison element 121 are D1 and D2. When the sampled value reaches the last bit (in this embodiment, it is the sampled value D18), the next sampled value is the first bit of the sampled value (in this embodiment, it is the sampled value D1). For example, the sampled values input by the comparison element 1218 are D18 and D1. In addition, Figure 5 For the sake of clear drawing representation, the circuit connections in the drawing are simplified. For example, Figure 5The sampling element 113 shown is only for illustrating the connection manner of the sampling element 113, and it is not necessary to have two sampling elements 113. The remaining processes of the phase detector 300 are the same as those of the foregoing embodiments, and will not be described herein again. However, the present invention is not limited to the architecture for 1 / 9 rate, and the present invention can be applied to various architectures by increasing or decreasing the number of elements.

[0053] As Figure 7 shown, the present invention provides a control method for a clock data recovery circuit, comprising: step S1 sampling a data signal by a phase detector and obtaining a plurality of sampling values; step S2 calculating a data conversion rate according to the sampling values; and step S3 adjusting an output pulse width of the phase detector according to the data conversion rate.

[0054] The present invention has been described by the above related embodiments. However, the above embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims

1. A clock data recovery system, characterized in that, Comprising: A phase detector for sampling a data signal to obtain a plurality of sampled values; And An adaptive pulse width control module for providing a bandwidth adjustment signal to the phase detector according to a data conversion rate obtained from the sampled values, where the data conversion rate is the number of data conversions in a unit data length; Wherein, the phase detector adjusts the pulse width of the output signal according to the bandwidth adjustment signal.

2. The clock data recovery system according to claim 1, wherein The phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data conversion rate.

3. The clock data recovery system according to claim 2, wherein The input of the pulse width adjustment module further includes a clock signal, and the adjustment clock signal lags behind the clock signal.

4. The clock data recovery system according to claim 3, wherein The amplitude by which the adjustment clock signal lags behind the clock signal is above 0.5UI and below 1.5UI.

5. The clock data recovery system according to claim 1, wherein When the data conversion rate is in a first interval, the phase detector outputs a first pulse width; when the data conversion rate is in a second interval, the phase detector outputs a second pulse width; when the data conversion rate is in a third interval, the phase detector outputs a third pulse width.

6. The clock data recovery system according to claim 5, wherein The first interval is from below 100% to above 50%; the second interval is from less than 50% to above 30%; the third interval is less than 30%.

7. A control method for a clock data recovery circuit, characterized in that, Comprising: Sampling a data signal through a phase detector to obtain a plurality of sampled values; Calculating a data conversion rate according to the sampled values, where the data conversion rate is the number of data conversions in a unit data length; and Adjusting the pulse width of the output signal of the phase detector according to the data conversion rate.

8. The control method according to claim 7, wherein The phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data conversion rate.

9. The control method according to claim 8, wherein The input of the pulse width adjustment module further includes a clock signal, and the adjustment clock signal lags behind the clock signal.

10. The control method according to claim 9, characterized in that, The amplitude by which the adjustment clock signal lags behind the clock signal is above 0.5UI and below 1.5UI.

11. The control method according to claim 7, characterized in that, When the data conversion rate is in a first interval, the phase detector outputs a first pulse width; when the data conversion rate is in a second interval, the phase detector outputs a second pulse width; when the data conversion rate is in a third interval, the phase detector outputs a third pulse width.

12. The control method according to claim 11, wherein, The first interval is from below 100% to above 50%; the second interval is from less than 50% to above 30%; the third interval is less than 30%.

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