Semiconductor-superconductor hybrid devices, fabrication and uses thereof

Abstract

A semiconductor-superconductor hybrid device (200) comprises a semiconductor (10), a superconductor (18) and a potential barrier (14) between the superconductor and the semiconductor. The device is configured so that energy level hybridisation between the semiconductor and the superconductor is achieved. The potential barrier is configured to increase the topological gap of the device. The potential barrier allows the degree of hybridisation between the semiconductor and the superconductor to be controlled. Further aspects provide a quantum computer comprising the device, a method of fabricating the device and a method of inducing topological behaviour in the device.

Description

Background Technology

[0001] Topological quantum computing is based on the phenomenon that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can be formed in regions where semiconductors are coupled to superconductors. A non-Abelian anyon is a quasiparticle, meaning it is not a particle itself, but rather an excitation in an electron liquid that behaves at least partially like a particle. MZMs are specific bound states of such quasiparticles. Under certain conditions, these states can be formed in nanowires near the semiconductor-superconductor interface, formed from a section of semiconductor coated with a superconductor. When an MZM is induced in a nanowire, it is said to be in a "topological regime." Inducing this requires a magnetic field, traditionally applied externally, and the nanowire needs to be cooled to the temperature at which superconducting behavior is induced in superconducting materials. It may also involve gated a portion of the nanowire with an electrostatic potential.

[0002] By forming a network of such nanowires and inducing topological modes in certain parts of the network, a qubit can be created that can be manipulated for quantum computing. A qubit is an element on which a measurement can be performed with two possible outcomes, but at any given time (when not measured), the element can actually be in a quantum superposition of two states corresponding to different outcomes.

[0003] To induce MZM, the device is cooled to the temperature at which superconductors (such as aluminum, Al) exhibit superconducting behavior. The superconductor induces a proximity effect in adjacent semiconductors, thereby causing superconductivity to also occur in the region of the semiconductor near the interface between the semiconductor and the superconductor. That is, topological phase behavior is induced in both the adjacent semiconductor and the superconductor. It is in this region of the semiconductor that MZM forms.

[0004] Another condition for inducing the formation of the topological phase that can form the MZM is the application of a magnetic field to enhance spin degeneracy in the semiconductor. Degeneracy in the context of quantum systems refers to the situation where different quantum states have the same energy level. Enhancing degeneracy means making these states adopt different energy levels. Spin degeneracy refers to the situation where different spin states have the same energy level. Spin degeneracy can be enhanced by a magnetic field, resulting in energy level splitting between electrons with different spin polarizations. This is known as the Zeeman effect. The g-factor is the coefficient between the applied magnetic field and spin splitting. Typically, the magnetic field is applied by an external electromagnet. However, US16 / 246287 also discloses a heterostructure in which a layer of ferromagnetic insulator is placed between a superconductor and a semiconductor to apply an internal magnetic field for enhancing spin degeneracy without the need for an external magnet. Examples of ferromagnetic insulators given include EuS, GdN, and Y3Fe5O. 12 Bi3Fe5O 12 Compounds of heavy elements in the form of YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3, and YTiO3 (heavy elements are europium, gadolinium, yttrium, iron, strontium, and rhenium).

[0005] Inducing MZM typically requires gating the nanowire with an electrostatic potential. However, US16 / 120433 discloses a structure that exhibits topological behaviors including MZM without gating. In this case, the nanowire has a complete superconducting shell around its perimeter, eliminating the need for gating.

[0006] like Figure 1 As illustrated in the figure, a large topological gap E is preferred for creating high-quality devices with long MZM lifetimes. g Materials in the topological phase (whether in the region of proximity-induced superconductivity in a semiconductor or in a superconductor) exhibit distinct energy bands: a lower energy band 101 and a higher energy band 102. The lower energy band 101 is where the quasiparticle energy E falls within a lower range, and the higher energy band (or "excitation band") 102 is the higher quasiparticle energy band. Topological gap E g This is the energy window between the lower energy band 101 and the higher energy band 102, where quasiparticles do not exist due to the quantization (discretization) nature of the quasiparticle energy levels. The lower energy band 101, the higher energy band 102, and the topological gap E... g Similar to the valence band, conduction band, and band gap of electrons in a semiconductor. In the higher excitation band 102, quasiparticles can propagate freely through the superconductor (or the adjacent induced region in a semiconductor), similar to electrons in the valence band of a semiconductor.

[0007] Majoranas (whose states form an MZM) form the lower frequency band 101. Majoranas are part of the computational space, i.e., a property of the system used for the quantum computing applications under discussion. In other words, the MZM is an operational element of qubits. On the other hand, particle-like excitations (quasi-particles) in the higher energy band 102 are not part of the computational space. If these quasi-particles cross the topological band gap E due to thermal fluctuations... g Entering the lower energy band 101, they will destroy at least some of the MZM. This is sometimes referred to as "poisoning the MZM." Gap E g This provides protection for MZM against such poisoning. Quasiparticles exist in and pass through the gap E in the higher energy band. g The probability of reaching a lower energy band and Proportional, where T is temperature and k is the Boltzmann constant. Therefore, the larger the topological gap, the more protection the MZM is provided with, shielding it from the poisoning of harmful quasiparticles in the higher energy band 102.

[0008] Stanescu et al. (Physical Review B84, 144522 (2011)) and Winkler et al. (Physical Review B99, 245408 (2019)) provided a more detailed treatment of the operating theory of hybrid semiconductor-superconductor devices. Summary of the Invention

[0009] The aim is to provide a semiconductor-superconductor hybrid device with a large topological gap, and more specifically, with a topological gap as close as possible to the theoretical limit.

[0010] A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a potential barrier between the superconductor and the semiconductor. The device is configured to achieve energy level hybridization between the semiconductor and the superconductor. The potential barrier is configured to increase the topological gap of the device. The potential barrier allows control over the degree of hybridization between the semiconductor and the superconductor. Another aspect provides a quantum computer including the device, a method for fabricating the device, and a method for inducing topological behavior in the device.

[0011] This summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that address any or all of the shortcomings mentioned herein. Attached Figure Description

[0012] To aid in understanding embodiments of this disclosure and to illustrate how these embodiments can be implemented, reference is made to the accompanying drawings, which are provided by way of example only, wherein:

[0013] Figure 1 This is a diagram illustrating the concept of topological gaps;

[0014] Figure 2 This is a cross-sectional view of a first example of a semiconductor-superconductor hybrid device;

[0015] Figure 3 The graphs showing Δ / Δ0 (a measure of the induced superconducting gap) versus Γ / Δ0 (a measure of the coupling strength) are presented for a) semiconductors in non-topological modes at zero magnetic field; b) InSb semiconductors in topological modes; and c) InAs semiconductors in topological modes.

[0016] Figure 4 It shows that in In, as a function of x 1-x Al x A graph showing the experimentally determined band shift between As semiconductors and aluminum superconductors;

[0017] Figure 5a and Figure 5b This is a heatmap showing the maximum topological gap as a function of α (a measure of spin-orbit coupling strength) and x for two semiconductor-superconductor hybrid devices with different barrier thicknesses;

[0018] Figure 6a It is a thermal map illustrating the potential difference at different locations in an illustrative semiconductor-superconductor hybrid device, omitting data for the substructure below the device and the space above the device (cross-shaded area);

[0019] Figure 6b It is along Figure 6a Line a shows a graph of the potential difference as a function of distance d;

[0020] Figure 7a It is about voltage levels; the illustration shows a heat map of the potential difference at different locations in another illustrative semiconductor-superconductor hybrid device, which omits data on the substructure below the device and the space above the device (cross-hatched area);

[0021] Figure 7b It is along Figure 7a Line a shows a graph of the potential difference as a function of distance d;

[0022] Figure 8 This is a cross-sectional view of a second example of a semiconductor-superconductor hybrid device;

[0023] Figure 9This is a flowchart of a method for manufacturing a semiconductor-superconductor hybrid device; and

[0024] Figure 10 This is a flowchart of a method using a semiconductor-superconductor hybrid device.

[0025] Figure 2 and Figure 8 These are illustrative and not to scale. For ease of representation, the relative proportions of components shown in these figures may be exaggerated. Detailed Implementation

[0026] As used in this article, the verb “includes” is used as a shorthand for “includes or consists of”. In other words, while the verb “includes” is intended to be an open term, it is explicitly envisioned that the closed term “consisting of” be used instead, especially when used in conjunction with chemical components.

[0027] Directional terms such as “top,” “bottom,” “left,” “right,” “above,” “below,” “horizontal,” and “vertical” are used in this text for descriptive convenience and are consistent with… Figure 1 and Figure 2 The orientation shown relates to a semiconductor-superconductor hybrid device. To avoid any ambiguity, this terminology is not intended to limit the device's orientation within an external reference frame.

[0028] As used herein, the term "superconductor" refers to a material that, when cooled to below its critical temperature T, becomes a superconductor. c Materials that become superconducting at certain temperatures. The use of this term is not intended to limit the temperature of the device.

[0029] In the context of this disclosure, the term “coupling” specifically refers to the hybridization of energy levels.

[0030] As used herein, a “nanowire” is an elongated member having a width on the nanometer scale and an aspect ratio of at least 100, 500, or 1000. Typical examples of nanowire widths range from 10 to 500 nm, optionally from 50 to 100 nm or 75 to 125 nm. Lengths are typically on the micrometer scale, for example, at least 1 μm or at least 10 μm. In this document, nanowires are typically formed from semiconductor materials.

[0031] The "band shift" between semiconductors and metals is the energy difference between the conduction band of a semiconductor and the Fermi level of a metal.

[0032] Now refer to Figure 2 The first example of explaining the semiconductor-superconductor hybrid device 200.

[0033] The semiconductor-superconductor hybrid device 200 includes a semiconductor 10, a barrier 14 disposed above the semiconductor, and a superconductor 12 disposed above the barrier 14. The semiconductor 10 and the superconductor 12 are separated from each other by the barrier 14.

[0034] In this example, semiconductor 10 is arranged as a nanowire. In this example, semiconductor 10 is a single indium arsenide (InAs). Barrier 14 covers the top and side surfaces of semiconductor 12.

[0035] Superconductor 12 is in the form of a layer above the top surface and the first side surface of the nanowire. In this example, superconductor layer 12 is an aluminum layer. Winkler et al. (cited above) reported that aluminum is strongly coupled to InAs, and the strength of the coupling can vary depending on the thickness of the superconductor layer. For example, the thickness can range from 4 to 10 nm.

[0036] Although this example relates to a single indium arsenide semiconductor and an aluminum superconductor, the principles of this disclosure are applicable to other semiconductor-superconductor pairs.

[0037] Semiconductor 10 and superconductor 12 allow the induction of useful topological behaviors (i.e., useful excitations, such as Majorana zero modes) in the device during operation. Hybridization of the energy levels of semiconductor 10 and superconductor 12 allows for this behavior. Barrier 14 can provide an electric barrier between semiconductor 10 and superconductor 12. Barrier 14 can, for example, control the degree of hybridization. As will be explained in more detail later, the topological gap of the device can be optimized by selecting the physical thickness of barrier 14 and the composition of barrier 14 (which determines the band shift between barrier 14 and superconductor 12).

[0038] A protective layer 18 covers the upper surface of device 200. This layer protects the device from oxidation, especially during the manufacturing process. Protective layer 18 also acts as an electrical insulator to prevent current from flowing from the gate electrode 20 into the device. The material forming protective layer 18 can be any of the various protective materials known in the semiconductor manufacturing industry. Protective layer 18 is typically a dielectric, such as hafnium oxide.

[0039] Device 200 also includes a gate electrode 16, which in this example is disposed on one side of the nanowire. The gate electrode is disposed on a protective layer 18 and separated from the nanowire by an air gap. In this configuration, both the protective layer 18 and the air gap serve to prevent current from flowing from the gate electrode 16 into the superconductor 10 and the semiconductor 12.

[0040] Gate electrode 16 is used to apply an electrostatic field to semiconductor layer 10. Providing this gating allows control over the degree of energy level hybridization between the semiconductor and the superconductor. This can be useful for inducing excitation in a device.

[0041] The configuration of the gate electrode 16 is not particularly limited, as long as the gate electrode can gate the device. The gate electrode can be located anywhere suitable in the device: for example, as in this example, on one side of the nanowire; above the nanowire as in the second example described below; or below the nanowire. The gate electrode 16 can be formed of any suitable material. The gate electrode is typically not superconducting. For example, the gate electrode 16 can be gold or a gold-titanium alloy.

[0042] Device 200 is disposed on a substructure. The substructure provides physical support for the device. The form of the substructure has little to no effect on the operation of the device (if any). In this example, the substructure includes a substrate 20, on which buffer 22 and mask 24 are disposed.

[0043] The properties of substrate 20 are not particularly limited. The substrate can be any of a variety of substrates used in the manufacture of semiconductor devices. Indium phosphide is an illustrative example of a useful substrate material.

[0044] In this example, mask 24 comprises silicon oxide. Various other masks, such as silicon nitride, can be used. Buffer 22 comprises InGaAs. The device in this example is fabricated using selective region growth. Mask 24 and buffer 22 are used during an example of the selective region growth process. Mask 24 and buffer 22 can remain in the finished device without negative impact, but are not necessary for device operation.

[0045] Now refer to Figures 3 to 8 To explain the structure and function of barrier 14.

[0046] Barrier 14 is used to adjust the degree of coupling between semiconductor 10 and superconductor 12, in other words, the degree of energy level hybridization. By controlling the degree of coupling, the topological gap of the device can be optimized. This principle is... Figure 3 The image is shown in the middle.

[0047] Figure 3 The graph shows Δ / Δ0(y-axis) as a function of Γ / Δ0(x-axis), where Δ / Δ0(y-axis) is a measure of the induced superconducting gap in the system, and Γ / Δ0(x-axis) provides a measure of the coupling strength. Δ is the effective gap; Δ0 is the superconducting gap value inside the superconductor; and Γ is the coupling factor. For hybrid systems, the coupling factor provides a measure of the degree of coupling between the semiconductor wavefunction and the superconductor wavefunction.

[0048] The three curves illustrate the induced superconducting gap: (a) a semiconductor in a non-topological mode with zero magnetic field; (b) an InSb semiconductor in a topological mode; and (c) an InAs semiconductor in a topological mode.

[0049] The bandgap in a hybrid system cannot exceed that in a pure superconducting system. Therefore, curves b and c are constrained by curve a.

[0050] Curves b and c define the maximum values. As the level of coupling with the superconductor increases, the topological gap in hybrid systems based on these materials increases to a certain point. However, beyond a certain limit, the hybrid energy states exhibit excessive superconductivity, and the topological gap gradually disappears. The exact location and height of these maximum values ​​vary depending on the semiconductor material chosen.

[0051] In the hybrid semiconductor-superconductor device presented in this paper, the potential barrier mitigates the degree of coupling between the semiconductor and the superconductor. In other words, the barrier controls the coupling along the semiconductor and superconductor. Figure 3 The position of the x-axis. By providing a potential barrier with selected properties, devices with optimized topological gaps can be constructed.

[0052] The physical thickness of the barrier and its composition both contribute to its effect.

[0053] For a given barrier layer composition, increasing the barrier thickness reduces the coupling between the semiconductor and the superconductor.

[0054] For a given barrier thickness, increasing the band shift between the barrier and the superconductor (i.e., the energy gap between the Fermi level of the superconductor and the conduction band of the barrier) reduces the coupling between the semiconductor and the superconductor. In other words, increasing the height of the potential step of the barrier reduces the coupling between the semiconductor and the superconductor. The band shift is determined by the properties of the materials used and can be controlled, for example, by changing the composition of the barrier.

[0055] Therefore, adjusting one or both of the barrier composition and barrier thickness allows for controlled coupling and control of topological gaps.

[0056] Figure 2 The device has a potential barrier including materials of formula IIa:

[0057] In 1-x Al x As

[0058] Where x is in the range of 0.05 to 1. Figure 3 The diagram illustrates the relationship between the band shift of the material and x in the aluminum superconductor, according to this formula. It can be seen that the band shift increases with increasing x.

[0059] As the band shift increases, the barrier thickness required to achieve the maximum topological gap decreases. With x = 1, i.e., when the barrier includes AlAs, the expected optimal layer thickness is very thin, e.g., 1 to 10 atomic layers. Reliable fabrication of such thin layers can be difficult. Choosing relatively low x values ​​is useful, e.g., less than or equal to 0.4, or less than or equal to 0.3.

[0060] Changing x also affects the lattice constant of the material. It is useful for barrier 12 to have a lattice constant similar to that of semiconductor 10. For example, this can facilitate the epitaxial growth of barrier 12 on semiconductor 10 during fabrication. In this example, the semiconductor comprises InAs and the value of x is chosen to be less than or equal to 0.4, or less than or equal to 0.3. For these values, the lattice constant of the material of formula IIa is close to that of InAs.

[0061] Choosing x such that the band shift for the superconductor is positive is likely preferred. Small negative band shifts are permissible. Typically, for materials of Formula IIa, x is at least 0.1.

[0062] In the context of this example, a particularly preferred value for x is in the range of 0.15 to 0.2.

[0063] The thickness of barrier 12 is typically in the range of 2 nm to 30 nm, for example, 5 to 10 nm. As explained earlier, the optimal thickness for providing the maximum topological gap will vary depending on the specific material chosen.

[0064] Figure 5a and Figure 5b The diagram illustrates the reference. Figure 2 The interaction between barrier thickness and barrier composition is described in the example devices. These figures illustrate the calculated study of topological gap as a function of the system's alpha value (a measure of spin-orbit coupling) and the variable x in Equation IIa. The topological gap in such systems is illustrated using heatmaps: the darker the region, the lower the topological gap.

[0065] Figure 5a The diagram illustrates the topological gap in a device with a 5 nm thick barrier. The maximum topological gap is observed when x has a value of approximately 0.25.

[0066] Figure 5b A graph showing the device with a 10nm barrier is presented. In this example, the maximum topological gap is obtained when x is approximately 0.15.

[0067] Additional data used to illustrate the relationship between band shift (determined by the choice of material) and barrier thickness are shown in Figures 6 and 7.

[0068] Figure 6a and Figure 6b The illustration shows a reference. Figure 2 The potential difference within a device with a general structure is described. More specifically, the bottom energy of the conduction band relative to the Fermi level is illustrated. This particular device includes a 5 nm thick barrier comprising In 0.75 Al 0.25 As.

[0069] Figure 6a A heatmap of the potential difference as a function of location within the device is shown. The heatmap is annotated with line A extending from the base of the semiconductor at coordinates (0.00, 0.00) to the upper surface of the superconductor. Cross-shaded areas correspond to the device's substructures and the space surrounding the device; data in these areas are omitted for clarity.

[0070] Figure 6b The diagram illustrates the voltage variation in the device along the distance d of line A. The observed potential difference gradually becomes more negative as it approaches the superconductor. At d = 50 nm, line A crosses the barrier. A sudden increase in the potential difference is observed, indicating that the barrier provides electrical insulation between the semiconductor and the superconductor. The observed potential difference drops to a strongly negative value at the superconductor (d = 55 nm).

[0071] Figure 7a and Figure 7b Similar to Figure 6a and Figure 6b However, the results for the following device are shown, which has a thicker 10 nm barrier and a difference in barrier composition between the barrier and the superconductor due to the use of different In barrier compositions. 0.85 Al 0.15 As produces a lower band shift.

[0072] Figure 7a A thermal diagram of the potential difference as a function of the location within the device is shown, annotated with line B extending from the base of the semiconductor through the potential barrier to the superconductor. Figure 7b The potential difference observed along line A is shown.

[0073] Figure 7b The curve shown has the same Figure 6b A similar overall form applies: the voltage gradually becomes more negative as it moves through the semiconductor toward the superconductor. At a distance d 50 nm along line B, the line reaches the potential barrier. The potential difference at the barrier increases abruptly again. However, due to the lower frequency band shift in this example, the increase is less significant. Figure 6b The degree shown. However, with Figure 6b Compared to the previous example, the area of ​​voltage increase is wider due to the increased barrier thickness.

[0074] Figure 5b and Figure 6b The region below the potential difference curve is therefore determined by the composition of the barrier (whose height is defined by the band shift) and the physical thickness of the barrier. Setting this region to a value greater than 0 can provide an energy barrier that is useful for optimizing coupling and therefore for optimizing topological gaps.

[0075] Although the examples above involve specific combinations of semiconductors, superconductors, and barrier materials, the basic principles of this disclosure are broadly applicable and can be extended to other combinations of materials. Based on the details provided herein, those skilled in the art will be able to obtain additional devices.

[0076] although Figure 2 The example uses aluminum as the superconductor, but any alternative superconductor can be used. Superconductors are typically S-wave superconductors. Examples of S-wave superconductors include indium, tin, and lead. The device structure can vary depending on the superconductor chosen. For example, lead has a larger superconducting gap than aluminum. For a given barrier composition, the optimal barrier thickness for a lead-based device will be greater than that for an aluminum-based device. Simultaneously, for a given barrier thickness, the optimal bandgap for a lead-based device will be larger.

[0077] Figure 2 The example uses a barrier layer with components of formula IIa.

[0078] Alternative barrier layer compositions can be used. One class of useful materials is those of formula IIb:

[0079] In 1-x Ga x As

[0080] Where x is in the range of 0.05 to 1, for example, in the range of 0.1 to 0.4 or 0.15 to 0.3. For a given value of x, the composition of Formula IIb will have a lower band shift than the composition of Formula IIa. Therefore, when using the composition of Formula IIb, the barrier thickness is adjusted upwards. For example, when using the material of Formula IIb, the barrier thickness is typically at least 3 nm, for example, in the range of 3 to 20 nm.

[0081] Other barrier materials can also be used.

[0082] Figure 2 The device uses InAs as the semiconductor. Alternative semiconductors can be used. Specific examples of alternative semiconductors include those of Formula I:

[0083] InAs y Sb 1-y (Formula I)

[0084] Where y is in the range of 0 to 1. In other words, as an alternative to single indium arsenide (y = 1), the semiconductor may include indium antimonide (y = 0), or a ternary mixture containing 50% indium (on a molar basis) with a variable ratio of arsenic to antimony (0 t / m). <y<1)。

[0085] Indium arsenide (InAs) has been found to exhibit good processability during device fabrication and provides good device performance. Indium antimonide (InSb) offers further improvements in device performance, but may be more difficult to use during the fabrication process. Ternary mixtures possess properties between the binary compounds InAs and InSb. When y is in the range of 0 to 0.7 or 0.01 to 0.7, improvements in device performance can be observed compared to InSb. y values ​​in the range of 0.20 to 0.45 provide a particularly good balance between device performance and processability.

[0086] Figure 3 The diagram illustrates that InSb (curve b) has different properties than InAs (curve c). If y is in the range of 0.7 to 1.0, the properties of the ternary mixture of Equation I are expected to be somewhere between curve b and curve c, and if y is in the range of 0.01 to 0.7, the properties of the ternary mixture of Equation I are expected to be enhanced compared to InSb. Figure 3 This indicates that InSb exhibits the optimal topological gap compared to InAs when it achieves a higher degree of coupling with the semiconductor. Therefore, the topological gap in InSb-based devices can be optimized by selecting a thinner barrier than comparable InAs-based devices; and / or by selecting a barrier material with a smaller band shift.

[0087] Other semiconductors can also be used, wherein the configuration of the barrier is appropriately adjusted based on the principles described herein.

[0088] Although Figure 2 The barrier is shown to extend above the top and side surfaces of the semiconductor, but this is not necessary, as long as the barrier exists at least in the region where the superconductor covers the semiconductor.

[0089] The configuration of the substructure and gate electrode can be freely varied.

[0090] Now we will base our discussion on the differences between this example and the first example, and refer to... Figure 8 This is a second example to describe a semiconductor-superconductor hybrid device 800. The same reference numerals are used for the same components.

[0091] The main difference between the second example and the first example is that the semiconductor 810 is arranged in a sandwich structure between the insulating component 815 and the barrier 814, and the device is a top gate rather than a side gate.

[0092] Insulating components 815 are disposed on substructures 20, 22, and 24 of device 800. Substructures 20, 22, and 24 have the same configuration as in the first example. Semiconductor component 810 is disposed above insulating components 815. The top and sides of semiconductor 810 are covered by a barrier 814.

[0093] The insulating component 815 can be conveniently formed of the same material as the barrier 814, but any insulating material can be used. The insulating component 815 can be formed of a semiconductor material, but its semiconductor properties are not used in the context of this device. There is a large energy difference (e.g., at least 30 meV, optionally at least 50 meV) between the conduction band of the semiconductor and the conduction band of the insulating component. When the device is in use, electrons are trapped in the semiconductor layer 810 and do not escape into the insulating component.

[0094] Semiconductor 810 has a defined thickness t. For example, the thickness t can range from 5 nm to 50 nm, optionally from 10 nm to 40 nm, and further optionally from 20 nm to 30 nm. Changing the thickness of the semiconductor layer can change the number of energy levels (subbands) occupied at the interface between the semiconductor and the superconductor. This is useful for tuning the quantum mechanical behavior of the device.

[0095] The thickness of the semiconductor layer can be optimized based on the properties of the selected material to maximize the topological gap. In a specific example where the band offset between the semiconductor's conduction band and the conduction band of the insulating component and barrier is approximately 50 meV and the device's α value is 0.1 eV nm, a semiconductor thickness of approximately 25 nm is particularly preferred. Simulation is a useful method for determining the optimal semiconductor layer thickness for a given device.

[0096] The tops and corners of semiconductor devices are often difficult to manufacture reproducibly. Minor variations in the device structure may exist in these regions. Similarly, substructures may exhibit small variations. Separating the semiconductor from these regions allows for better control over its geometry.

[0097] Figure 8 The device 800 is further shown to be top-gate. A gate electrode 816 is disposed on top of the device. A protective layer 18 is disposed between the gate electrode 816 and the rest of the device components and is used to prevent current from flowing from the gate electrode 816 to the rest of the components.

[0098] A bottom-gate configuration (not shown) is also envisioned. In this configuration, the gate electrode is positioned below the substructure, and the substructure is designed to prevent current from flowing from the gate electrode into the rest of the device.

[0099] Any device described herein can be modified to include a ferromagnetic insulating layer configured to apply a magnetic field to semiconductors and superconductors to enhance spin degeneracy. For example, the ferromagnetic insulating layer can be disposed beneath a superconductor, such as between the superconductor and a potential barrier. The ferromagnetic insulating layer may comprise materials selected from EuS, GdN, and Y3Fe5O. 12 Bi3Fe5O 12YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3, and YTiO3. US16 / 246287 provides a further description of ferromagnetic insulating layers.

[0100] Figure 9 This is a flowchart outlining the steps of an illustrative method for fabricating a semiconductor-superconductor hybrid device as described herein.

[0101] This method typically involves fabricating a semiconductor, then a potential barrier, and then a superconductor. At block 901, a semiconductor is formed. At block 902, a potential barrier is formed on the semiconductor. At block 903, a superconductor is formed on the potential barrier to enable energy level hybridization between the semiconductor and superconductor layers. Additional components may be formed between or in any of steps 901 to 903. In examples where the device includes an insulator, the insulator is formed before the semiconductor.

[0102] The specific techniques used to form the various components are not particularly limited and can be appropriately selected. Those skilled in the art will know of a variety of suitable techniques. Examples include selective region growth; chemical vapor deposition; photolithography; and so on. Techniques that result in the epitaxial growth of components can allow for good contact between these components and can be preferred.

[0103] Figure 10 This is a flowchart outlining an illustrative approach to using a semiconductor-superconductor hybrid device as provided herein.

[0104] The use of such devices typically involves inducing topological behavior (i.e., specific types of electronic excitations) into the device. This can be achieved through energy level hybridization between a semiconductor and a superconductor, resulting in a hybrid energy band exhibiting both semiconductor and superconducting properties. Such excitations can be useful in quantum computing. For example, they can be used to encode qubits (also known as quantum bits). Without being bound by theory, it is believed that the semiconductor-superconductor hybrid device presented in this paper generates Majorana zero modes.

[0105] At box 1001, the semiconductor-superconductor hybrid device is cooled to the temperature at which the superconductor layer becomes superconducting. In other words, the device is cooled to a temperature below the critical temperature T of the superconductor layer. c The temperature is set so that the layer exhibits superconducting behavior (e.g., behaves as if it has zero resistance). Such temperatures are typically on the order of tens of Kelvin or lower. c Depending on the materials used, and in some cases, possibly influenced by the material thickness, the temperature can be selected appropriately.

[0106] At box 1002, a magnetic field is applied to the semiconductor layer. The magnetic field enhances the spin degeneracy in the device, thereby altering the band structure at the interface between the semiconductor and the superconductor. The magnetic field is typically applied externally, for example, using an electromagnet.

[0107] At box 1003, an electrostatic field is applied to the semiconductor layer. Typically, semiconductor-superconductor hybrid devices include a gate electrode, which is used to apply the electrostatic field. Alternatively, the electrostatic field can be applied externally. The electrostatic field can alter the degree of hybridization between the energy levels of the semiconductor and the superconductor. For example, hybridization may be reduced when electrons are drawn from the superconductor by an electrostatic field. This may make lower-energy states—the states of interest—more susceptible to the influence of a magnetic field. This, in turn, can allow the formation of a topological phase in a smaller magnetic field, leading to enhanced properties for quantum computing.

[0108] It should be understood that the above embodiments are described as examples only.

[0109] More generally, according to one aspect disclosed herein, a semiconductor-superconductor hybrid device is provided, comprising: a semiconductor; a superconductor; and a potential barrier between the superconductor and the semiconductor; wherein the device is configured to enable energy level hybridization between the semiconductor and the superconductor; and wherein the potential barrier is configured to increase the topological gap of the device.

[0110] Semiconductor-superconductor hybrid devices may also include a gate electrode configured to apply an electrostatic field to the semiconductor. Electrostatic gatening can be useful for inducing topological behavior in the device. The arrangement of the gate electrode is not particularly limited. The device can be a top gate, a side gate, or a bottom gate. In top-gate and side-gate configurations, a dielectric is typically provided between the gate electrode and other components of the device to prevent current flow. In a side-gate configuration, the dielectric may include an air gap. In a bottom-gate configuration, the gate electrode is arranged beneath the substrate of the device such that the substrate acts as the dielectric.

[0111] Semiconductors may include materials of Formula I:

[0112] InAs y Sb 1-y

[0113] Where y is in the range of 0 to 1. For example, y can be in the range of 0.8 to 1. Particularly preferably, the semiconductor may include InAs. Although the basic principles of this disclosure apply to a very wide range of semiconductors, this class has been specifically studied.

[0114] Superconductors can include aluminum. For example, a superconductor can be an aluminum layer with a thickness ranging from 4 nm to 10 nm. More generally, any superconductor can be used, particularly any S-wave superconductor. One such example is lead. Other examples are indium and tin.

[0115] The barrier can have a thickness and composition that can be selected to tune the energy level hybridization between the semiconductor and the superconductor. As explained above, tuning the degree of hybridization allows for optimization of the device's topological gap.

[0116] The barrier can include high bandgap semiconductors. A material is considered to have a “high bandgap” when the energy level of its conduction band is at least 30 meV higher than that of the material whose semiconductor is used as a hybrid device, preferably 50 meV higher, and more preferably at least 100 meV higher.

[0117] The barrier may include the material of Formula II:

[0118] In 1-x A x As

[0119] Where A is Al or Ga; and x is in the range of 0.05 to 1. Specifically, A can be Al. x is typically in the range of 0.05 to 0.4. For example, x can be in the range of 0.1 to 0.25. For some applications, especially when A is Al, the range of 0.1 to 0.25 may be preferred. Although a wide variety of different barrier materials can be used, this class has been specifically studied. Such materials may have good structural compatibility and lattice matching with semiconductor materials of Formula 1 (e.g., InAs).

[0120] The barrier can have a thickness ranging from 2 nm to 30 nm. The optimal barrier thickness is believed to typically fall within this range, especially for materials of Formula II. For example, the barrier can have a thickness ranging from 5 nm to 10 nm.

[0121] An illustrative example device includes an aluminum superconductor, an InAs semiconductor, a barrier thickness of 5 ± 1 nm, and wherein the barrier comprises a material of Formula II, where A is Al and x is 0.25 ± 0.05. In a variant of this example, the semiconductor is a material of Formula I, where y is in the range of 0.8 to 1.

[0122] Another example device comprises an aluminum superconductor, an InAs semiconductor, a barrier thickness of 10 ± 2 nm, and wherein the barrier comprises a material of Formula II, where A is Al and x is 0.15 ± 0.03. In a variant of this example, the semiconductor is a material of Formula I, where y is in the range of 0.8 to 1.

[0123] Any device described herein may include a protective dielectric layer, such as an oxide (e.g., hafnium oxide), for protecting one or more portions of the device from water vapor and / or oxygen; and / or other components for preventing current from flowing from the gate electrode to the device, depending on the configuration of the gate electrode.

[0124] Semiconductors can be placed between a barrier and an insulating component. The barrier and the insulating component can be made of the same material.

[0125] The insulating component can extend from the surface of the substrate. For example, the first insulating component can be integrally formed with the surface of the substrate. In such a configuration, the first insulating layer separates the semiconductor layer from the surface of the substrate and separates the semiconductor layer from a corner where the substrate and the first insulating layer meet. This allows for improved reproducibility of the semiconductor layer during manufacturing, since corners and / or the substrate surface may be difficult to reproduce accurately.

[0126] The thickness of the semiconductor layer can range from 5 nm to 50 nm, optionally from 10 nm to 40 nm, and further optionally from 20 nm to 30 nm. Changing the thickness of the semiconductor layer can alter the number of energy levels (subbands) occupied at the interface between the semiconductor and the superconductor. This is useful for tuning the quantum mechanical behavior of the device. Arranging the semiconductor in a sandwich structure between an insulating component and a potential barrier allows for precise control over its geometry.

[0127] The semiconductor-superconductor hybrid device presented in this paper can be configured as a nanowire.

[0128] The semiconductor-superconductor hybrid device described herein may further include a ferromagnetic insulating layer configured to apply a magnetic field to both the semiconductor and the superconductor, for example, to enhance spin degeneracy. The ferromagnetic insulating layer may be disposed between the superconductor and the potential barrier. The ferromagnetic insulating layer may comprise materials selected from EuS, GdN, and Y3Fe5O4. 12 Bi3Fe5O 12 , YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3 and YTiO3.

[0129] On the other hand, a quantum computer device incorporating the semiconductor-superconductor hybrid device disclosed herein is provided. Improvements in topological gaps are particularly relevant to quantum computing applications. The hybrid device can be used to generate qubits.

[0130] On the other hand, it provides the use of a barrier arranged between the semiconductor and superconductor in a semiconductor-superconductor hybrid device to increase the topological gap of the device.

[0131] Another aspect provides a method for manufacturing a semiconductor-superconductor hybrid device of the present disclosure, comprising: forming a semiconductor; forming a barrier on the semiconductor; and forming a superconductor on the barrier.

[0132] Specific techniques for forming various components can be appropriately selected. For example, at least one of the first insulating layer, the second insulating layer, and the semiconductor layer can be formed by selective region growth. Selective region growth and other techniques involving epitaxial crystal growth allow for very close contacts between components. In the case of semiconductors and superconductors, epitaxial growth can improve energy level hybridization.

[0133] The method may also include forming any of the various additional components described above with reference to the device.

[0134] For example, forming a potential barrier may include the epitaxial growth of the barrier; and forming a superconductor may include the epitaxial growth of the superconductor.

[0135] On the other hand, a method for inducing topological behavior in the semiconductor-superconductor hybrid device or the quantum computer device of the present disclosure is provided, the method comprising: cooling the semiconductor-superconductor hybrid device to a temperature at which the superconductor becomes superconducting; applying a magnetic field to the semiconductor-superconductor hybrid device; and applying an electrostatic field to the semiconductor.

[0136] This method can include inducing anyons, particularly Majorana zero modes, in semiconductor-superconductor hybrid devices. Without being bound by theory, the device presented herein is capable of generating Majorana zero modes. This device can be used in quantum computers, and more particularly in topological quantum computers.

[0137] This disclosure provides the following terms:

[0138] Clause 1. A semiconductor-superconductor hybrid device comprising: a semiconductor; a superconductor; and a potential barrier between the superconductor and the semiconductor; wherein the device is configured to enable energy level hybridization between the semiconductor and the superconductor; and wherein the potential barrier is configured to increase the topological gap of the device.

[0139] Clause 2. The semiconductor-superconductor hybrid device according to Clause 1 further includes a gate electrode configured to apply an electrostatic field to the semiconductor.

[0140] Clause 3. A semiconductor-superconductor hybrid device according to Clause 1 or Clause 2, wherein the semiconductor comprises a material of Formula I:

[0141] InAs y Sb 1-y

[0142] Where y is in the range of 0 to 1.

[0143] Clause 4. The semiconductor-superconductor hybrid device as described in Clause 3, wherein the semiconductor includes InAs.

[0144] Clause 5. A semiconductor-superconductor hybrid device according to any one of Clauses 1 to 4, wherein the superconductor comprises aluminum.

[0145] Clause 6. A semiconductor-superconductor hybrid device according to any one of Clauses 1 to 5, wherein the barrier comprises a material of Formula II:

[0146] In 1-x A x As

[0147] Where A is Al or Ga;

[0148] Where x is in the range of 0.05 to 1.

[0149] Clause 7. The semiconductor-superconductor hybrid device as described in Clause 6, wherein A is Al.

[0150] Clause 8. A semiconductor-superconductor hybrid device as described in Clause 6 or Clause 7, wherein x is in the range of 0.05 to 0.4.

[0151] Clause 9. The semiconductor-superconductor hybrid device as described in Clause 8, wherein x is in the range of 0.1 to 0.25.

[0152] Clause 10. A semiconductor-superconductor hybrid device according to any one of Clauses 1 to 9, wherein the barrier has a thickness in the range of 2 nm to 30 nm.

[0153] Clause 11. The semiconductor-superconductor hybrid device according to Clause 10, wherein the barrier has a thickness in the range of 5 nm to 10 nm.

[0154] Clause 12. A semiconductor-superconductor hybrid device according to any one of Clauses 1 to 11, wherein the semiconductor is arranged between a barrier and an insulating component.

[0155] Clause 13. The semiconductor-superconductor hybrid device as described in Clause 12, wherein the barrier and insulating components comprise the same material.

[0156] Clause 14. A semiconductor-superconductor hybrid device according to any one of Clauses 1 to 13, wherein at least a portion of the semiconductor has a thickness in the range of 5 nm to 50 nm.

[0157] Clause 15. A quantum computing device comprising a semiconductor-superconductor hybrid device according to any one of Clauses 1 to 14.

[0158] Clause 16. Use of a barrier arranged between the semiconductor and superconductor of a semiconductor-superconductor hybrid device to increase the topological gap of the device.

[0159] Clause 17. A method of manufacturing a semiconductor-superconductor hybrid device according to any one of Clauses 1 to 14, comprising: forming a semiconductor; forming a barrier on the semiconductor; and forming a superconductor on the barrier.

[0160] Clause 18. The method according to Clause 17, wherein forming a barrier includes epitaxial growth of the barrier; and wherein forming a superconductor includes epitaxial growth of the superconductor.

[0161] Clause 19. A method for inducing topological behavior in a semiconductor-superconductor hybrid device according to any one of Clauses 1 to 14 or a quantum computer device according to Clause 15, the method comprising: cooling the semiconductor-superconductor hybrid device to a temperature at which the superconductor is superconducting; applying a magnetic field to the semiconductor-superconductor hybrid device; and applying an electrostatic field to the semiconductor.

[0162] Clause 20. The method described in accordance with Clause 19, wherein the topological behavior includes Majorana zero mode.

[0163] Once the disclosure herein is given, other variations or use cases of the disclosed technology may become apparent to those skilled in the art. The scope of this disclosure is not limited to the described embodiments, but only to the appended claims.

Claims

1. A semiconductor-superconductor hybrid device, comprising: semiconductor; superconductor; A potential barrier between the superconductor and the semiconductor, wherein the device is configured to enable energy level hybridization between the semiconductor and the superconductor, and the potential barrier is configured to increase the topological gap of the device; A gate electrode, the gate electrode being configured to apply an electrostatic field to the semiconductor; as well as A ferromagnetic insulating layer between the potential barrier and the superconductor.

2. The semiconductor-superconductor hybrid device according to claim 1, wherein the semiconductor comprises the material InAs. y Sb 1-y , where y is in the range of 0 to 1.

3. The semiconductor-superconductor hybrid device according to claim 2, wherein the semiconductor comprises InAs.

4. The semiconductor-superconductor hybrid device according to claim 1, wherein the superconductor material comprises aluminum.

5. The semiconductor-superconductor hybrid device according to claim 1, wherein the barrier comprises the formula In 1-x A x The material is As, where A is Al or Ga; and where x is in the range of 0.05 to 1.

6. The semiconductor-superconductor hybrid device according to claim 5, wherein A is Al.

7. The semiconductor-superconductor hybrid device according to claim 5, wherein x is in the range of 0.05 to 0.

4.

8. The semiconductor-superconductor hybrid device according to claim 7, wherein x is in the range of 0.1 to 0.

25.

9. The semiconductor-superconductor hybrid device of claim 1, wherein the barrier has a thickness in the range of 2 nm to 30 nm.

10. The semiconductor-superconductor hybrid device of claim 9, wherein the barrier has a thickness in the range of 5 nm to 10 nm.

11. The semiconductor-superconductor hybrid device of claim 10, wherein the semiconductor is disposed between the barrier and the insulating component.

12. The semiconductor-superconductor hybrid device of claim 11, wherein the barrier and the insulating component comprise the same material.

13. The semiconductor-superconductor hybrid device of claim 1, wherein at least a portion of the semiconductor has a thickness in the range of 5 nm to 50 nm.

14. The semiconductor-superconductor hybrid device of claim 1, further comprising a protective layer disposed between the gate electrode and the semiconductor, the superconductor and the barrier.

15. A method of manufacturing a semiconductor-superconductor hybrid device according to any one of claims 1 to 14, comprising: Forming the semiconductor; The potential barrier is formed on the semiconductor; as well as The superconducting material is formed on the potential barrier.

16. The method of claim 15, wherein forming the barrier comprises epitaxial growth of the barrier; and The formation of the superconducting material includes the epitaxial growth of the superconductor.

17. A method for inducing topological behavior in a semiconductor-superconductor hybrid device according to any one of claims 1 to 14, the method comprising: Cool the semiconductor-superconductor hybrid device to the temperature at which the superconductor material becomes superconducting; A magnetic field is applied to the semiconductor-superconductor hybrid device; as well as An electrostatic field is applied to the semiconductor.

18. The method of claim 17, wherein the topological behavior includes Majorana zero mode.

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