DC-coupled amplifier with pre-driver and bias control

Abstract

A DC coupled amplifier includes a pre-driver, an amplifier, and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to generate one or more pre-amplified signals. The amplifier has transistors in a common source and common gate configuration, the transistors are configured to receive and amplify the one or more pre-amplified signals to generate one or more amplified signals, and the amplifier also has an output driver terminal element. The bias control circuit is connected between the pre-driver and the amplifier, and the bias control circuit receives at least one bias current from the output driver terminal element of the amplifier, wherein the pre-driver, the amplifier, and the bias control circuit are all formed on the same die.

Description

Technical Field

[0001] The field of the invention relates to amplifiers, and more particularly to improved distributed amplifiers and improved DC coupled amplifiers. Background Art

[0002] Distributed amplifiers, also known as traveling wave amplifiers, are a common amplifier configuration used for wide bandwidth applications. Figure 1 An example circuit of an exemplary prior art distributed amplifier is shown. Figure 1 The distributed amplifier is a single-ended configuration. As shown, the input node 104 is configured to receive a data signal to be amplified. The input node 104 is connected to an inductor 108A. The opposite terminal of the inductor 108A is connected to the inductor 108B and the first amplifier section 112A. The inductor 108 is located in the circuit portion defined as the input line in this article.

[0003] As shown, amplifier section 112A includes two transistors connecting source to drain. The gate terminal of field effect transistor (FET) 154 is connected to inductor 108A and 108B. Capacitor 162 grounds the gate terminal of FET 150. As shown, the drain terminal of FET 150 is connected to inductor 120A, 120B. The opposite terminal of inductor 120A is connected to output terminal resistor RD 130, which is in turn connected to capacitor 134. Resistor RD 130 may also be referred to as a drain resistor, which is used for impedance matching and setting output impedance. The opposite terminal of capacitor 134 is grounded. Output terminal resistor RD 130 and capacitor 134 establish the output impedance seen from output node 124. Inductor 120A, 120B are located in the circuit portion defined as output line 122.

[0004] The FETs 150, 154 of the amplifier section 112 have parasitic capacitances, and the inductors 108A, 108B, 120A, 120B arranged in the circuit are selected to cancel or offset the parasitic capacitances associated with the amplifier section.

[0005] The arrangement of amplifier section 112A and inductors 108A, 108B, 120A, 120B is repeated with one or more additional amplifier sections 112B and inductors 108C, 108N and 120C and 120N, where N is any integer. Output node 124 is connected to inductor 120N. Inductor 170 is also connected to output node 124 and supply voltage VD 166. Supply voltage 166 provides a DC supply voltage to the circuit for biasing.

[0006] Also part of the distributed amplifier is an input termination resistor 140 and a capacitor 144 which are connected in series to ground to provide input impedance matching. A supply voltage VG150 is provided at the node between the input termination resistor 140 and the capacitor 144.

[0007] Although two amplifier sections 112A, 112B are shown, it is contemplated that any number of sections may be implemented to increase gain or establish other circuit characteristics.

[0008] In operation, an input signal is provided to input node 104, which is in turn provided to first amplifier section 112A, where it is amplified and the amplified signal is presented on output line 122. The process is repeated through one or more additional amplifier sections 112, such that the amplified output signal is presented on output node 124. The input impedance is at least partially set by input termination resistor RG 140 and capacitor 144. Resistor RG 140 may also be referred to as a gate resistor for setting the input impedance. The output impedance is at least partially set by output termination resistor 130 and capacitor 134. Inductors 108A, 108B, 120A, 120B cancel parasitic capacitance of the amplifier section.

[0009] Figure 2 An example circuit arrangement of an exemplary prior art distributed amplifier in a differential mode configuration is shown. Figure 1 104-P and 104-N. The -P and -N designations reflect two separate but similar arrangements of components, which are generally mirrored to form a differential configuration. Likewise, the inductors 108 are separated by the reference numerals -P and -N. Due to the generally similar but repetitive nature of the differential configuration, the arrangement is a mirrored set of components. As is understood in the art, the differential configuration includes two inputs 104-P and 104-N. The inputs 104-P, 104-N receive differential signals that are 180 degrees out of phase with respect to each other. The signal of interest is the difference between the differential signals presented on the inputs 104-P, 104-N. The -P and -N designations reflect two separate but similar arrangements of components, which are generally mirrored to form a differential configuration. Likewise, the inductors 108 are separated by the reference numerals -P and -N. Due to the generally similar but repetitive nature of the differential configuration, the -P and -N designations are similar to the -P and -N designations. Figure 2 Only discussed Figure 2 Different from Figure 1 aspects.

[0010] Figure 2 The differential amplifier sections 208A and 208B are connected to the input lines 110-P and 110-N and the output lines 122-P and 122-N as shown. Each differential amplifier section 208 includes several components. Figure 1As shown, connected between inductor 108A-P and inductor 108B-P is the gate terminal of FET 224A. The drain terminal of FET 224A is connected to the source terminal of FET 228A. As shown, this configuration is mirrored with FET 224B and 228B, so that the gate terminals of FET 228A, 228B are connected, and the source terminals of FET 224A, 224B are connected. This is called the common source configuration of FET 224 and the common gate arrangement of FET 228. The drain terminals of FET 228A and 228B are connected to output lines 122-P and 122-N. Capacitor 232 is connected between ground and the gate terminals of FET 228A, 228B. Current source 220 is connected between ground and the source terminals of FET 224A, 224B. When provided with a differential signal, the node between the current source 220 and the source terminal of the FET 224 becomes a virtual ground. The one or more additional differential amplification sections 208B are similarly configured.

[0011] In operation, a differential signal is presented at inputs 104-P and 104-N and, therefore, to differential amplifier sections 208A, ... 208B, and an amplified version of the input signal is presented at outputs 124-P and 124-N. Figure 1 , a power supply voltage VD 166-P provides bias for the positive side of the amplifier through an inductor 170-P. Voltage VD 166-N and inductor 170-N provide bias for the negative side of the amplifier. In a differential amplifier configuration, either of voltages VD 166-P and 166-N have equal values ​​or can be connected to the same DC voltage source. Furthermore, in this embodiment, inductor 170-P and inductor 170-N are the same, but can be different values ​​in other embodiments. A voltage source VG 150 is provided at the node between resistor 140-P and resistor 140-N to provide gate bias for both sides of the differential amplifier.

[0012] Although the prior art designs, e.g. Figure 1 and Figure 2 Those designs shown in are suitable for certain applications, but improvements would benefit the art. Disclosed herein are improvements to amplifiers and preamplifiers, as described below. Summary of the invention

[0013] In order to overcome the shortcomings of the prior art and provide additional benefits, a DC coupled amplifier including a pre-driver, an amplifier and a bias control circuit is disclosed. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to generate one or more pre-amplified signals. The amplifier has transistors in a common source and common gate arrangement, which are configured to receive and amplify the one or more pre-amplified signals to generate one or more amplified signals, and the amplifier also has an output driver terminal element. In other embodiments, a common source and common gate design is not used, thereby allowing any amplifier configuration other than a common source and common gate configuration. The bias control circuit is connected between the pre-driver and the amplifier, and the bias control circuit receives at least one bias current from the output driver terminal element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on the same die.

[0014] An amplifier system is disclosed herein, including a pre-driver configured to receive one or more input signals and amplify the one or more input signals to produce one or more pre-amplified signals. Another part of this embodiment is an amplifier configured to receive and amplify the one or more pre-amplifier input signals to produce one or more amplified signals. The amplifier may include an output driver terminal element. A bias control circuit is connected between the pre-driver and the amplifier. The bias control circuit receives at least one bias control circuit input current from the output driver terminal element of the amplifier. In this embodiment, the pre-driver, the bias control circuit and the amplifier are formed on the same die.

[0015] In one embodiment, the amplifier system includes a bias control circuit including one or more transistors configured as a level shifter that controls a voltage provided to the pre-driver. The amplifier system die may be a gallium arsenide die. The bias control circuit includes one or more transistors configured to ensure that the pre-driver bias current is insensitive to process variations and bias voltage variations. In one configuration, the pre-driver includes one or more amplifier sections, each of which receives a bias signal from the bias control circuit. Each amplifier section may be formed by two transistors in a common source configuration. In one embodiment, the amplifier is a DC coupled amplifier having transistors connected in common source and common gate. The amplifier system may also include a gain control circuit configured with the pre-driver, so that the gain control circuit controls the gain of the pre-driver based on a gain control signal.

[0016] Also disclosed herein is a method for amplifying a signal with an amplifier. The method includes providing a pre-driver, an amplifier, and a bias control circuit on the same die, and providing one or more input signals to the pre-driver. Then, the one or more input signals are amplified with the pre-driver to generate one or more pre-amplified signals, and the one or more pre-amplified signals are provided to the amplifier, and then the one or more amplifier input signals are amplified to generate one or more amplified signals and one or more bias control circuit input currents. Then the method provides the one or more bias control circuit input currents to the bias control circuit, and generates the one or more bias control signals with the bias control circuit.

[0017] The bias control circuit may include one or more transistors configured as a level shifter that controls a voltage provided to the pre-driver. In one embodiment, the die is a gallium arsenide die. The method may also include providing a gain control circuit and receiving a gain control signal at the gain control circuit to control the gain of the pre-driver. In one embodiment, the pre-driver includes one or more amplifier sections, each amplifier section receiving a bias signal from the bias control circuit. In one configuration, each amplifier section is formed by two transistors in a common source configuration. The amplifier may include an output driver terminal element, and the bias control circuit receives the one or more bias control circuit input currents from the output driver terminal element of the amplifier.

[0018] An amplifier system is also disclosed herein, including a pre-driver, which is configured to receive one or more input signals and pre-amplify the one or more input signals to generate one or more pre-amplified signals. A gain control system is part of the amplifier system and is configured as part of the pre-driver. The gain control system controls the pre-driver gain in response to a gain control signal provided to the gain control system. The amplifier is configured to receive and amplify the one or more pre-amplified signals to generate one or more amplified signals. A bias control circuit is connected between the pre-driver and the amplifier. The bias control circuit receives at least one bias control circuit input current from the amplifier, so that the pre-driver, the gain control circuit, the bias control circuit and the amplifier are formed on the same die.

[0019] In one configuration, the bias control circuit includes one or more transistors configured as a level shifter that controls the voltage provided to the pre-driver. The bias control circuit includes one or more transistors configured to ensure that the pre-driver bias current is insensitive to process variations and bias voltage variations. In one embodiment, the pre-driver includes three amplifier sections, each of which receives a bias signal from the bias control circuit. Each amplifier section can be formed by two transistors in a common source configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The components in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the present invention. In the drawings, like reference numerals designate corresponding parts in different views.

[0021] Figure 1 An example circuit of an exemplary prior art distributed amplifier is shown;

[0022] Figure 2 An example circuit arrangement of an exemplary prior art distributed amplifier in a differential mode configuration is shown;

[0023] Figure 3A is a block diagram of a DC coupled amplifier according to an embodiment of the present invention;

[0024] Figure 3B is a block diagram of a DC coupled amplifier according to another embodiment of the present invention;

[0025] Figure 4 is a circuit diagram showing details of the DC coupled amplifier shown in FIG3;

[0026] Figure 5A is a block diagram illustrating an example environment for using the innovations disclosed herein;

[0027] Figure 5B is a block diagram illustrating another example environment for using the innovations disclosed herein;

[0028] Fig. 6A is a block diagram illustrating an example embodiment of a pre-driver with gain control;

[0029] Figure 6B is a block diagram illustrating an alternative embodiment of a pre-driver with gain control; and

[0030] Figure 7 A graph of gain versus frequency is shown for an amplifier system with variable gain. DETAILED DESCRIPTION

[0031] like Figure 1 and Figure 2The distributed amplifiers shown are typically made of gallium arsenide, silicon germanium, a combination of the two, or any other material or process. Silicon germanium has many performance advantages, such as higher gain and bandwidth, but gallium arsenide inherently provides higher output voltages and lower power consumption. For applications requiring relatively high output voltages and gains, typical prior art applications use a silicon germanium pre-driver stage and a gallium arsenide output driver stage in one package.

[0032] Improvements over prior art applications are possible. One area of ​​improvement over the prior art is in significantly reducing the size and cost of the amplifiers (drivers and pre-drivers). The system improves upon the prior art by reducing the size and cost of the distributed amplifiers (drivers and pre-drivers) while maintaining the same or higher gain levels while also maintaining or increasing bandwidth. This is accomplished by combining the pre-driver and output driver on a single high gain gallium arsenide die compared to the prior art. This significantly reduces the size of the amplifier, reduces the cost of the amplifier, and the integrated driver and pre-driver stages are easier to use.

[0033] Figure 3A A block diagram of an improved DC coupled amplifier 300 is shown, which may be used, for example, to replace Figure 2 The DC coupled amplifier 300 includes an output driver 302, a bias control section 304, and a pre-driver section 306. The pre-driver section 306 and the output driver section 302 are both differential amplifiers and thus include differential inputs as shown. Under bias control, the pre-driver section 306 amplifies its differential input IN through the bias control section 304. Pre and To output amplified differential input IN and The bias control section 304 receives the bias current from the output driver section 302, which will be combined with Figure 4 For explanation. In one embodiment, the bias control 304, pre-driver 306 and output driver 302 are all on the same die. By placing all of these components on the same die, the off-die AC coupling capacitors that would otherwise be required between independent dies can be avoided, thereby saving unit space and cost while maintaining ideal voltage levels and reducing capacitance and inductance values. The capacitors required in the prior art can be 10,000 picofarad capacitors. Preferably, the voltage output by the pre-driver is the same as the voltage input to the driver circuit. In the prior art, the output pre-driver voltage can be 3 volts and the input to the driver amplifier can be 1 volt. To connect these two components, the off-die capacitor is used to pass radio frequency (RF) signals while blocking DC signals.

[0034] Figure 3BA block diagram of an alternative embodiment of a DC coupled amplifier 300 is shown. Figure 3A 6. In this embodiment, the pre-driver 306 includes a gain control module 308 that receives a gain control signal on a control input 312. The gain control signal and the gain control module allow the gain of the pre-driver to be adjusted manually or automatically. The gain control module 308 is discussed in more detail below in conjunction with FIG. 6.

[0035] Pre-driver section

[0036] Figure 4 The pre-driver section 306 is shown in FIG. The pre-driver section 306 amplifies the differential input IN Pre and IN Pre connected to inductor 278 and the gate of FET Q1 266, Connected to inductor 280 and the gate of FET Q2 268. FET Q1 266 and FET Q2 268 form the first stage of the amplifier. Any number of stages may be used. In one embodiment, three stages are utilized. The source terminals of FET 266 and FET 268 are connected in a common source configuration. Current source 270 is connected between ground and the source terminals of FET 266, FET 268. Current source 270 may be a fixed current source or a variable current source. In one embodiment, current source 270 is a resistor. The node VGND associated with current source 270 is a virtual ground, so no signals are present. The nodes labeled VG_PD are also virtual grounds, so no signals are present on these nodes. This labeling is done by Figure 4 The drain of transistor Q1 266 is connected to inductor 262 and resistor 242 , while the drain of transistor Q2 268 is connected to inductor 264 and resistor 244 .

[0037] A second stage of amplification for pre-driver 306 is provided by transistors Q3 272, Q4 274 and current source 276 connected in the same configuration as the first stage of amplification provided by transistors Q1 266, Q2 268 and current source 270. Although two stages of amplification are shown, any number of stages of amplification may be included within pre-driver 306 to provide additional gain.

[0038] A voltage source VG_PD is provided at a voltage source VG_PD node 290B between resistors RG_PD 282 and 284 to provide gate bias for transistors Q1-Q4 266, 268, 272, 274. The pre-driver section 306 generates an amplified output OUT_PD and It is provided to input terminals 104 -P and 104 -N of output driver 302 .

[0039] Bias control section

[0040] The bias control section 304 is Figure 4 The bias control section 304 receives the currents IDP_PD and IDN_PD, and uses these currents to generate a bias current for the pre-driver 306 .

[0041] IDP_PD is directed to the drain of transistor Q5 230 and a first terminal of resistor R1 234. A second terminal of resistor R1 234 is connected to the gate of transistor Q5 230 and a first terminal of resistor R3 240. A second terminal of resistor R3 240 is connected to ground. The source of transistor Q5 is connected to a first terminal of resistor RDP_PD 242, a second terminal of which is connected to the drains of transistors Q1 266 and Q3 272 to provide bias control.

[0042] IDN PD is directed to the drain of transistor Q6 232 and a first terminal of resistor R2 236. A second terminal of resistor R2 236 is connected to the gate of transistor Q6 232 and a first terminal of resistor R4 238. A second terminal of resistor R4 238 is connected to ground. The source of transistor Q6 232 is connected to a first terminal of resistor RDN_PD 244, a second terminal of which is connected to the drains of transistors Q2 268 and Q4 274 to provide bias control.

[0043] The gate voltage of transistors Q5 230 and Q6 232 is clamped by voltage divider resistors R1-R4 and is used to reduce the DC voltage on the drain of transistors Q1-Q4 in the pre-driver section 306. Additionally, transistors Q5-Q7 in the bias control section ensure that the pre-driver bias current is insensitive to process variations and bias voltage variations. FETS Q5 230 and Q6 232 can be referred to as a level shifter, which is part of the bias circuit 304. Q8 248 is a current mirror. A bias voltage is established on transistor Q8 248, and by connecting the gate voltage VG_PD of transistor Q8 248 to the other transistors, transistor Q8 248 mirrors the same bias condition to the other transistors Q1-Q4 with the same VG voltage.

[0044] The bias control portion also includes a transistor Q7 246 having a drain terminal connected to a line receiving a bias current IDP_PD and a first terminal of a transistor R5 250. The gate of the transistor Q7 246 is connected to a second terminal of the resistor R5 250 and a first terminal of a resistor R6 252. The second terminal of the resistor R6 252 is grounded. The source of the transistor Q7 246 is connected to a first terminal of a resistor R7 254. The second terminal of the resistor R7 254 is connected to a drain of the transistor Q8 and a first terminal of a resistor R9 256. The second terminal of the resistor R9 256 is connected to a gate of the transistor Q8 248 and a first terminal of a resistor R10 258. The second terminal of the resistor R10 is an input terminal 290A for setting a voltage VG_PD, which is the same as the voltage VG_PD applied in the pre-driver portion 306 at a node 290B between the resistors 282 and 284. The source of transistor Q8 248 is connected to a first terminal of resistor R8 260, a second terminal of which is connected to ground.

[0045] Transistor Q7 246 and associated resistors R5-R7 act as a level shifter that functions in a similar manner to transistors Q5 and Q6 to reduce the voltage applied to the drains of transistors in the pre-driver portion 306. Transistor Q8 and associated resistors R8-R10 act as a current mirror to set the gate voltage on transistors Q1-Q4 in the pre-driver portion 306.

[0046] The values ​​of resistors RDP_PD 242 and RDN_PD 244 may be adjusted to control the bias current applied to pre-driver 306. In a preferred embodiment, currents IDP_PD and IDN_PD may be set to 15 mA, although other pre-driver currents may be used in other embodiments.

[0047] Output Driver Section

[0048] The output driver section 302 is Figure 4 The output driver section 302 is shown in detail on the right. Figure 2 amplifiers share most components and are compatible with Figure 2Similar components that share reference numerals with the amplifiers of the present invention will not be described further. In addition to these elements, the output driver section also includes resistors RDP 178 and RDN 180 connected to the inductors 120A-P and 120A-N, respectively, and capacitors 182, 184 connected between the resistors 178, 180 and ground. Resistors RDP 178 and RDN 180 are used to set the current to the pre-driver section 306, where transistors Q5 230 and Q6 232 receive the current based on the voltage drop across resistors RDP 178 and RDN 180.

[0049] By adding the pre-driver section 306 and the bias control section 304 to the output driver section 302 and producing them on the same gallium arsenide die, the size of the DC coupled amplifier 300 is reduced while still producing the required gain with a simplified circuit arrangement, thereby avoiding the bandwidth reduction associated with larger FET sizes. In addition, two or more pre-driver sections can be added to achieve significantly higher gains while maintaining the same bandwidth and minimal increase in chip size. These are improvements over the prior art.

[0050] In operation, a differential input signal is provided to the pre-driver section 306 and amplified. The bias current applied to the pre-driver section 306 is obtained using the output driver termination resistors, and the bias control then uses a single common source FET to allow the pre-driver section 306 to operate at a low drain bias voltage (approximately 1V in the preferred embodiment). The pre-driver section 306 outputs the amplified signal to the output driver section 302, which provides further amplification.

[0051] Many use cases utilize distributed amplifiers. Distributed amplifiers are commonly found in optical transmitters to transmit data at high data rates between two locations. Many other use cases rely on distributed amplifiers and gain control elements. The foundation of optical communication systems is the driver amplifier, which amplifies the modulated signal onto an optical modulator or directly onto a laser diode. Figure 5A A block diagram of an example use environment, namely an optical signal transmitter, is shown. This is only one possible use environment, and other use environments can be envisioned.

[0052] like Figure 5AAs shown, a data source 504 provides data for ultimate transmission over the optical fiber 108. To achieve biasing of the driver, a supply voltage source 512 is provided to deliver power to the system. The supply voltage source 512 can be any source, including power from a hardline utility supply, a power supply, a battery, or any other source. The supply voltage source 512 provides a supply voltage to the pre-driver and driver amplifier 520. The pre-driver and driver amplifier 520 also receive data to be transmitted in an optical format from the data source 504. The pre-driver and driver amplifier 520 include one or more amplifiers that are configured to amplify and modulate the data to a level suitable for driving an optical modulator 524 or a laser diode 526. In response to the signal from the driver 520, the optical modulator 524 or the laser diode 526 generates an optical signal 528, which is presented to the fiber optic cable 108 for transmission to a remote location, such as another device in a data center or a remote location in a long-haul application. In Figure 5A In the example configuration of , the components within dashed line 530 are on one or more integrated circuits.

[0053] Figure 5B A block diagram of an example use environment for an alternative embodiment (ie, an optical signal transmitter) is shown. Figure 5A Similar elements are designated with the same reference numerals. In the exemplary embodiment, pre-driver and driver amplifier 520 includes a gain control input 536 that carries a gain control signal to the pre-driver and driver amplifier. FIG6 shows this configuration in more detail.

[0054] Fig. 6A Shown in Figure 4 This is just one possible configuration of a pre-driver with gain control. Fig. 6A , a pre-driver with gain control is shown. The gain control system includes a gain control node 604 configured to receive a gain control signal Vgain. The gain control node 604 is connected to a resistor 608. The opposite terminals of the resistor 608 are connected to the gate 612 of the FET Q9 616 and the gate 620 of the FET Q10 624. Current sources CS1-CS4 are also shown, which are connected as shown in the figure so that each FET Q1, Q2, Q3 and Q4 has its own current source. Fixed or variable resistors can be used as current sources. In one embodiment, CS1 and CS3 can be replaced by a single current source, while CS2 and CS4 can be replaced by a single current source.

[0055] The gain control signal presents a voltage to the gates 612, 620 of the FETs 616, 624, thereby controlling the resistance value across the FETs 616, 624. In this way, the FETs 616, 624 operate as variable resistors, and their resistance values ​​are set by the value of the gain control signal. This arrangement can be referred to as degenerate (or source degenerate) because it reduces the gain of the amplifier. For example, FET Q9616 behaves as a resistor, and the resistance value is controlled by the value of the voltage applied to the gate 612. When turned on, the gate is at a high voltage, establishing a low resistance value, which provides maximum gain. When FET Q9 is turned off due to the low gain control voltage presented at the gate, the resistance value is increased and the minimum gain is provided. In addition, due to the parasitic capacitance between the drain and source terminals of the FETs 612, 620, transistors Q9, Q10 provide frequency balancing. The balanced gain response effectively offsets the high frequency attenuation of external transmission lines or other aspects of the circuit.

[0056] Fig. 6A Also shown in FIG. 6 is an interconnect 630 between node 640A and node 640B. Likewise, an interconnect 634 is located between nodes 644A and 644B. ​​As shown, these interconnects bridge the source of the FET. These connections are optional and may be beneficial in implementing the gain control circuit arrangement.

[0057] In one embodiment, a single transistor is used instead of transistors Q9 616 and Q10 624. Although two pre-driver stages are shown, three dots indicate that additional pre-driver stages can be enabled. In one embodiment, the pre-driver has three stages. It should be noted that transistors Q9 and Q10 act as variable resistors, but can be modeled as variable resistors in parallel with capacitors. Therefore, as the gain control signal changes, the resistance values ​​of transistors Q9 and Q10 change, but the capacitance values ​​of these elements either do not change, or the change is not significant. This provides the benefit of not reducing the gain of the high-frequency components of the input signal at low gain levels and high gain levels. This in turn offsets the inherent characteristics of the transmission line and circuit (i.e., high-frequency signal components are attenuated more than low-frequency signal components). Therefore, the gain changes at low frequencies are greater than at high frequencies, thereby providing additional advantages.

[0058] Figure 6B is a block diagram showing an alternative embodiment of a pre-driver with gain control. Figure 6B In the embodiment, there is no Fig. 6A Likewise, interconnect 630 between node 640A and node 640B is not present. These connections are optional and may facilitate implementation of gain control circuitry.

[0059] Figure 7A gain versus frequency graph for an amplifier system with variable gain is shown. This is only one possible gain versus frequency graph for the amplifier disclosed herein. The horizontal axis 704 represents frequency, while the vertical axis 708 represents gain. Curves 712 are shown for different gain levels. Curve 734 represents a signal at a low gain level, while curve 730 represents a signal at a high gain level. It can be seen that the gain changes more at low frequencies than at high frequencies, which is an additional feature of the gain control circuit. This is desirable because at low gain levels, it is preferred not to reduce the gain of the high frequency component 720, as doing so would cause the high frequency component to be undesirably attenuated. This provides the benefit of frequency dependent equalization with less attenuation at high frequencies when the gain is reduced.

[0060] By studying the following drawings and detailed description, other systems, methods, features and advantages of the present invention will become apparent to those skilled in the art. All these additional systems, methods, features and advantages should be included in this description, within the scope of the present invention, and protected by the appended claims.

[0061] Although various embodiments of the present invention have been described, it will be apparent to those skilled in the art that, within the scope of the present invention, more embodiments and implementations are possible. In addition, the various features, elements and embodiments described herein may be claimed to be protected or combined in any combination or arrangement.

Claims

1. An amplifier system, comprising: a pre-driver configured to receive one or more input signals and amplify the one or more input signals to generate one or more pre-amplified signals; an amplifier configured to receive and amplify the one or more pre-amplified signals from the pre-driver to produce one or more amplified signals, the amplifier also having an output driver terminal element; and a bias control circuit connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias control circuit input current from the output driver terminal element of the amplifier, wherein the pre-driver comprises one or more pre-driver amplifier sections, each pre-driver amplifier section comprising a differential amplifier and receiving a bias current from the bias control circuit, Wherein, the pre-driver, the bias control circuit and the amplifier are formed on the same die. 2 . The amplifier system of claim 1 , wherein the bias control circuit comprises one or more transistors configured as a level shifter that controls a voltage provided to the pre-driver.

3. The amplifier system of claim 1, wherein the die is a gallium arsenide die.

4. The amplifier system of claim 1, wherein the bias control circuit comprises one or more transistors configured to ensure that the bias current provided to the pre-driver is insensitive to process variations and bias voltage variations.

5. The amplifier system of claim 1, wherein each amplifier section is formed from two transistors in a common source configuration.

6. The amplifier system of claim 1, wherein the amplifier is a DC coupled amplifier having cascode connected transistors. 7 . The amplifier system according to claim 1 , further comprising a gain control circuit configured with the pre-driver, the gain control circuit controlling a gain of the pre-driver based on a gain control signal.

8. A method for amplifying a signal using an amplifier, comprising: Providing pre-driver, amplifier and bias control circuitry on the same die; providing one or more input signals to the pre-driver; amplifying the one or more input signals with the pre-driver to generate one or more pre-amplified signals; providing the one or more pre-amplified signals to the amplifier; amplifying the one or more pre-amplified signals with the amplifier to generate one or more amplified signals and one or more bias control circuit input currents, providing the one or more bias control circuit input currents to the bias control circuit; and generating one or more bias control signals with the bias control circuit, The pre-driver includes one or more pre-driver amplifier sections, each pre-driver amplifier section includes a differential amplifier, and the one or more pre-driver amplifier sections receive a bias current from the bias control circuit.

9. The method of claim 8, wherein the bias control circuit comprises one or more transistors configured as a level shifter that controls a voltage provided to the pre-driver.

10. The method of claim 8, wherein the grains are gallium arsenide grains.

11. The method according to claim 8, further comprising: providing a gain control circuit; and A gain control signal is received at the gain control circuit to control the gain of the pre-driver.

12. The method of claim 8, wherein each amplifier section is formed from two transistors in a common source configuration.

13. The method of claim 8, wherein the amplifier further comprises an output driver terminal element, and the bias control circuit receives the one or more bias control circuit input currents from the output driver terminal element of the amplifier.

14. An amplifier system comprising: a pre-driver configured to receive one or more input signals and pre-amplify the one or more input signals to generate one or more pre-amplified signals; a gain control system configured as part of the pre-driver; The gain control system controls the pre-driver gain in response to a gain control signal provided to the gain control system; an amplifier configured to receive and amplify the one or more pre-amplified signals to generate one or more amplified signals; and A bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias control circuit input current from the amplifier, wherein the pre-driver, the gain control circuit, the bias control circuit and the amplifier are formed on one die.

15. The amplifier system of claim 14, wherein the bias control circuit comprises one or more transistors configured as a level shifter that controls a voltage provided to the pre-driver.

16. The amplifier system of claim 14, wherein the bias control circuit comprises one or more transistors configured to ensure that the pre-driver bias current is insensitive to process variations and bias voltage variations.

17. The amplifier system of claim 14, wherein the pre-driver comprises three amplification sections, each amplification section receiving a bias signal from the bias control circuit.

18. An amplifier system as claimed in claim 17, wherein each amplifier section is formed from two transistors in a common source configuration.

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