High precision logarithmic multiplier

Abstract

The application discloses a high-precision logarithmic multiplier, first, input operation number A, B, and pre-process operation number A, B through a pre-processing unit; then, input the XOR result of operation number A, B after pre-processing into an error part processing unit to obtain the final result of the error part (EP); at the same time, input the most significant bits k1 and k2 of operation number A, B after pre-processing into an approximate part calculation unit to obtain the final result of the approximate part (AP); finally, input the EP obtained by the error part processing unit and the AP obtained by the approximate part calculation unit into an adder to obtain the final result P approx The precision and hardware consumption of the approximate multiplier are balanced, and double-sided error distribution is obtained, which is beneficial to reducing the accumulation of errors in multiplication and accumulation-based applications.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of approximate computing, and particularly relates to a high-precision logarithmic multiplier. BACKGROUND

[0002] In recent years, with the continuous improvement of the performance of integrated circuits, power consumption and hardware complexity have become the bottleneck for further performance improvement, and approximate computing has gradually become a new trend to solve this bottleneck problem. Because many applications have certain precision redundancy, such as machine learning, digital signal processing, computer vision, etc. Therefore, by sacrificing a certain precision, the circuit complexity can be simplified, and a high-performance low-power efficient digital system can be designed. The multiplier is an essential and basic operation unit in a digital system, so the approximate multiplier is widely studied.

[0003] The approximate multiplier can be mainly divided into three categories, which are the approximate multiplier based on the traditional multiplier, the approximate multiplier based on the logarithmic approximation, and the approximate multiplier based on Cartesian Genetic Programming (CGP).

[0004] Traditional multipliers are mainly composed of three processes: partial product generation, partial product accumulation and final carry propagation accumulation. There are many related researches on approximate multipliers based on traditional multipliers. Kulkarni proposed UDM (underdesigned multiplier), an approximate 2*2 multiplier as a basic module to compose larger bit-width approximate multipliers. The partial product generated by the approximate 2*2 multiplier is "111" when the input is "11", which introduces a 1 / 16 error rate for the 2*2 multiplier. Kidambi first proposed a truncated multiplier, which divides the partial product accumulation process into the most significant part (MSP) and the less significant part (LSP), and reduces the circuit area by truncating the less significant part. However, this method introduces a large error. Hashemi proposed a dynamic range unbiased multiplier (DRUM), which calculates k bits of the operand using an exact multiplier. The starting bit of the k bits is selected depending on the position of the first one of the operand, and the last bit is complemented by one. If the position of the first one of the operand is less than the highest bit of the k bits, the low k bits of the operand are directly selected for operation. The resource consumption of this method is mainly due to the need for additional circuit to realize dynamic selection of operands. For tree-structured multipliers, there are many researches on approximate compressors. Momeni simplified the implementation logic of the exact 4:2 compressor and proposed two different implementation logics of approximate 4:2 compressors, which tend to low approximation error and lower resource usage. DRUM is an approximate multiplier that can dynamically select the operand bit width to obtain different accuracy. Similar to DRUM is the multiplier for high-order compressor (HOCM) proposed by D. Esposito. HOCM is an approximate multiplier that uses a dynamic selection compressor algorithm. Due to the large difference in accuracy of different types of approximate compressors, HOCM divides the partial product into MSP and LSP when adding the partial product, and divides it into multiple stages. The number of stages can be set by itself. Since the LSP part has little effect on the final result, the LSP of each stage can use approximate compressors to achieve the expected number of partial products of the next stage. For MSP, it has a greater impact on the final result, so each stage of MSP selects whether to use an accurate compressor and the number of accurate compressors, the type and number of approximate compressors according to the algorithm proposed by HOCM.In addition, H. Jiang proposed a novel approximate adder, which is different from the ordinary approximate adder, it will output a sum signal and an error signal for partial product accumulation according to the adjacent two input operands. The error is compensated by adding the result of the calculation of the generated error signal to the original partial sum. A two-stage error compensation strategy is proposed to calculate the error term, the first stage approximate multiplier for calculating the error term is completely calculated by or gates, and the second stage approximate multiplier for calculating the error term is calculated by a part of or gates and approximate adders.

[0005] The approximate multiplier based on Cartesian genetic programming is mainly proposed by Mrazek, which first searches for the most efficient approximate multiplier in the search space based on the combination logic of the exact multiplier by randomly reducing the connection of internal lines, and adds different constraints to narrow the search space for different applications. Although this method can obtain an efficient approximate multiplier, it is very time-consuming.

[0006] The approximate multiplier based on logarithmic approximation is mainly implemented based on the Mitchell algorithm, which proposes to realize the logarithm of binary number by approximating itself. According to the first bit of the binary number, the integer part is determined, and the remaining bits are taken as the decimal part. By converting the operands to the logarithmic domain, the original multiplication operation is converted to addition to realize it, and the result of addition is anti-logarithm operation to obtain the final approximate product. The specific algorithm flow is as follows, first, all binary operands can be represented by formula (1):

[0007]

[0008] Where k represents the position of the first bit of the binary number, Z i represents the value of the i-th bit, j depends on the precision of the binary number to be expressed, for an integer, j is equal to one, x represents the mantissa part. According to this formula, the multiplier and the multiplicand can be represented by formula (2):

[0009]

[0010]

[0011] Therefore, the product of A and B can be represented as:

[0012]

[0013] Taking the logarithm of both sides of the equation, the product of the two numbers can be represented as the sum of the logarithms of the two input operands, that is, formula (4):

[0014] log2(A×B)=k1+k2+log2(1+x1)+log2(1+x2) (4)

[0015] where log2(l+x) can be approximated as x,

[0016] log2(A x B) = k1+k2+x1+x2 (5)

[0017] The final approximate product of the Logarithmic Multiplier (LM) is related to the sum of x1+x2, and the inverse logarithm operation is performed according to whether a carry signal is generated by x1+x2 to obtain an approximate product as shown in equation (6)

[0018]

[0019] Although the Mitchell algorithm can effectively reduce the circuit complexity, it introduces a large approximation error, and many applications cannot accept such a large error. Therefore, many methods have been proposed to improve the precision. Mahalingam proposed an operand decomposition method, in which the original two operands are decomposed into four operands, thereby reducing the number of "1"s in each operand. This means that the opportunity for carry can be reduced to improve the precision of the logarithmic multiplier based on the Mitchell algorithm, but the operand decomposition also means that additional hardware circuits are needed for operand preprocessing. Therefore, Nandan proposed an improved operand decomposition to simplify unnecessary operation logic in the original operand decomposition process. Interval linear approximation is another commonly used method to improve precision. Since the main source of error in the logarithmic multiplier is that the logarithm and inverse logarithm processes cannot be accurately implemented in hardware circuits, the error in each interval is calculated by segmenting the interval, and a compensation constant is set according to different error conditions. The selection of the compensation constant also needs to consider the ease of hardware implementation. Error compensation is performed for different interval ranges to reduce the error. Iterative technique is another scheme to obtain a high-precision approximate multiplier. This technique was first proposed by Z. , which is also based on the Mitchell algorithm, but the binary representation of the operands is transformed, the carry of the mantissa is ignored, and the product of the operands is divided into an approximate part and an error part. The approximate part can be implemented by addition and shift operation, and the error part needs to be implemented by multiplication. Therefore, the error part is re-operated and divided into new approximate and error parts for iteration. When the error part is zero, the algorithm terminates and the accurate multiplication result can be obtained. The specific algorithm flow is as follows:

[0020] In the iterative multiplier (IM), equation (1) can be rewritten as follows:

[0021] x x 2 k = N-2 k (7)

[0022] Substitute formula (7) into formula (3), formula (8) can be obtained, wherein k1 and k2 represent the positions of the most significant bits of A and B respectively:

[0023]

[0024] Equation (8) can be divided into two parts, AP and EP.

[0025]

[0026] AP can be obtained by shift operation and addition operation, while EP needs to be calculated by a multiplier. Therefore, EP is calculated iteratively by applying formula (8). The accurate product can be obtained until EP is zero, which is shown as follows.

[0027]

[0028]

[0029]

[0030] E (0) =C (1) +E (1) (13)

[0031]

[0032]

[0033]

[0034] E (i) =0 (17)

[0035] Compared with the traditional LM, the precision can be significantly improved by iteration. However, the iteration calculation inevitably consumes more hardware resources

[0036] In view of the existence of the above-mentioned approximation error, a compensation algorithm needs to be proposed to improve the precision of the LM, so as to achieve the best balance between precision and hardware consumption. SUMMARY

[0037] The present application aims to provide a high-precision logarithmic multiplier, which improves the precision of the LM and converts the multiplication operation in EP into left shift operation.

[0038] In order to achieve the purpose of the present application, the present application provides a high-precision logarithmic multiplier, which comprises a preprocessing unit, an error part calculation unit (EP calculation unit) and an approximate part calculation unit (AP calculation unit), and the working process is as follows:

[0039] Firstly, the operands A, B are inputted into the pre-processing unit, and the operands A, B are pre-processed by the first detector module and the priority encoder;

[0040] Then, the pre-processed operands A, B are inputted into the data comparison module in the error part processing unit, and the operands A, B are operated by the adjacent one detector module, the priority encoder and the barrel shifter to obtain the final result EP of the error part;

[0041] Meanwhile, the pre-processed most significant bits k1 and k2 of the operands A, B are inputted into the approximate part calculation unit, and the operands A, B are operated by the adder, the decoder and the barrel shifter to obtain the final result AP of the approximate part;

[0042] Finally, the final result P is obtained by operating the EP obtained from the error part processing unit and the AP obtained from the approximate part calculation unit by the adder approx .

[0043] Further, in the pre-processing unit, the two input operands A, B are inputted into the first detector module 1 and the first detector module 2 respectively, and the most significant bits of the operands A, B are extracted in the form of 2 k . Then and are outputted by the priority encoder 1 and the priority encoder 2 respectively; then the operand A is inputted into the barrel shifter 1 to generate . The operand B is inputted into the barrel shifter 2 to generate .

[0044] Further, in the error part calculation unit, the result after the XOR operation is inputted into the data comparison module in the error part calculation unit, if , the intermediate variable , otherwise the intermediate variable . Then Q1 is approximated to 2 k or 2 k+1 by the adjacent one detector module in the error part calculation unit, if the k-1th bit in the binary of Q1 is 1, Q1 is approximated to 2 k+1 , otherwise the k-1th bit is 0, and Q1 is approximated to 2 k , i.e. round(Q1) is 2 k or 2 k+1 ; round(Q1) is outputted by the priority encoder 3 in the error part calculation unit to obtain the most significant bit k or k+1 of Q1, and then Q2 is left shifted by the most significant bit of Q1 by the barrel shifter 3 in the error part calculation unit to realize round(Q1)·Q2.

[0045] Further, in the approximate part calculation unit, the most significant bits k1 and k2 of the operands A and B are passed through adder 1 to generate k1+k2, and then passed through a decoder to generate

[0046] Further, round(Q1)·Q2 obtained by the error part processing unit is added to

[0047] Compared with the prior art, the significant progress of the present application is that: 1) the Normalized Mean Error Distance (NMED), the Mean Relative Error Distance (MRED) and the Worst Case Error (WCE) are lower than other approximate multipliers. The NMED and MRED can be calculated by the following formula:

[0048]

[0049] ED = |P approx -P exact | (27)

[0050]

[0051] where N represents the total number of input operands, M represents the maximum output of the exact multiplier, and P(ED), P(RED) represent the probability of the error occurring. The present application considers the 8-bit multiplier designed in the present application and other 8-bit multipliers. The range of the input operand is 0 to 255, and all possible input operands are simulated to evaluate the performance of the multiplier designed in the present application, and the results are shown in Table I. Compared with the most accurate Improved Logarithmic Multiplier-A (ILM-A), the NMED is reduced by 34%, and the MRED is reduced by 48%, which shows that the multiplier designed in the present application can effectively improve the precision by compensation algorithm. In addition, the larger operands in the EP can obtain the bilateral error distribution as shown in Figure 3 In the application mainly operated by multiply-accumulate, since the errors are positive and negative, the generated errors can cancel each other out, and the over-accumulation of errors can be avoided. ​​​​​​

[0052] 2) In P approx The OR gate replaces the addition operation in the calculation. Table II gives the performance comparison of the OR gate and the conventional adder, both of which are implemented by Verilog and synthesized by ISE 14.7-Webpack on Xilinx xc6slx16-2csg324. The adder uses a carry-lookahead adder (CLA), compared with the CLA, the LUT of the OR gate is reduced by 39%, the delay is reduced by 83%, and the power consumption is also reduced by 74%. Therefore, using the OR gate consumes less resources.

[0053] 3) In the EP calculation unit, the left shift operation replaces the multiplication operation. The present invention selects the larger operand in the EP to be approximated to 2 k or 2 k+1 by the NOD module based on the minimum WCE strategy, and then shifts the smaller operand left by 2 k or 2 k+1 bits to obtain the EP. Compared with the multiplication, the implementation of the shift operation consumes less hardware resources.

[0054] 4) Compared with other multipliers, the designed multiplier of the present application achieves the best balance between precision and hardware consumption. The approximate multiplier of the present application is realized by Verilog hardware description language, and all designs are realized only by combinational logic without pipeline, and are synthesized by ISE 14.7-Webpack. Then the implementation is built on xc6slx16-2csg324 in Xilinx, and all I / Os are allocated to pins, and the power is estimated at a clock frequency of 50 MHz. The comparison results are shown in Table III. The improved logarithmic multiplier A (ILM-A) in Table III refers to the logarithmic multiplier using the original NOD module, and the improved logarithmic multiplier B (ILM-B) refers to the logarithmic multiplier using the simplified NOD module. Compared with ILM-A, the present design has better hardware performance, and the NMED, MRED and WCE are 34%, 48% and 25% lower than ILM-A respectively, and the compensation algorithm can significantly improve the precision of the multiplier without sacrificing hardware resources. Compared with ILM-B, although the power consumption increases by 22%, the range of input operands in the present design is not limited, and the precision is higher than that of ILM-B. Therefore, the present design is suitable for more applications. Compared with the logarithmic multiplier (LM), the NMED, MRED and WCE of the present application are reduced by 53%, 61% and 25% respectively. In addition, the product of PDP and NMED and the product of PDP and MRED are calculated to prove that the present design is efficient. Table III shows that the PDP*NMED and PDP*MRED of the present design are the smallest among the existing logarithmic multipliers. In addition, the relationship between MRED and PDP of the considered logarithmic multipliers is shown in Figure 4 Figure 1.

[0055] To make the functional characteristics and structural parameters of the present application clearer, the following further describes the present application in combination with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0056] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of this application and illustrate embodiments of the present application and the description thereof, and do not constitute an improper limitation of the present application. In the drawings:

[0057] Figure 1 Figure 1 is a schematic diagram of the overall structure of the present application;

[0058] Figure 2 Figure 2 is a schematic diagram of the error part processing unit of the present application;

[0059] Figure 3 Figure 3 is a schematic diagram of the generated bilateral error distribution of the present application.

[0060] Figure 4 MRED vs. PDP for various types of log multipliers

[0061] Figure 5 Gate-level circuit diagram for a first detector module

[0062] Figure 6 Gate-level circuit diagram for a neighboring detector module DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0064] The present application is a high-precision log multiplier, which comprises a preprocessing unit, an error part calculation unit (EP calculation unit), and an approximate part calculation unit (AP calculation unit). The overall flow algorithm 1 is as follows:

[0065] (1). A, B: n-bit input operands, P approx : approximate product of A x B

[0066] (2). First-order detector (LOD): Priority encoder (PE):

[0067] (3). First-order detector (LOD): Priority encoder (PE):

[0068] (4).

[0069] (5).

[0070] (6). round (Q1) · Q2 is calculated by algorithm 2

[0071] (7).

[0072] (8).

[0073] (9). Encoding

[0074] (10).

[0075] The specific workflow is as follows:

[0076] First, input operands A and B, and preprocess operands A and B through the first detector module and priority encoder;

[0077] Next, the XOR result of the preprocessed operands A and B is input into the data comparison module, adjacent detector module, priority encoder, and barrel shifter in the error part processing unit to obtain the final result of the error part (EP), round(Q1)·Q2.

[0078] Simultaneously, the most significant bits k1 and k2 of the preprocessed operands A and B are input into the approximate part calculation unit. After calculation by the adder, decoder, and barrel shifter, the final result of the approximate part (AP) is obtained.

[0079] Finally, the round(Q1)·Q2 obtained from the error part processing unit and the round(Q1)·Q2 obtained from the approximation part processing unit are compared. The result is obtained by performing a bitwise OR operation followed by an adder operation to get the final result P. approx .

[0080] Example 1

[0081] like Figure 1 , Figure 2 As shown, in the data preprocessing unit, two input operands A and B are respectively fed into the first detector module 1 and the first detector module 2, with 2 k Extract the powers of the most significant bits of operands A and B in the form of then and The outputs k1 and k2 are respectively processed by priority encoder 1 and priority encoder 2; then the input operand A and XOR generation Input operand B and XOR generation

[0082] During the error calculation unit processing stage, the XORed result is input into the data comparison module within the error calculation unit. If... Then intermediate variables Conversely, intermediate variables Then, Q1 is approximated as 2 by the adjacent detector module in the error calculation unit. k Or 2 k+1 If the (k-1)th bit in the binary representation of Q1 is 1, then Q1 is approximated as 2. k+1 Conversely, if the (k-1)th bit is 0, then Q1 is approximately 2. kThat is, round(Q1) is 2 k Or 2 k+1 The most significant bit k or k+1 of round(Q1) is output by the priority encoder in the error calculation unit. Then, Q2 is shifted to the left by the barrel shifter in the error calculation unit to achieve round(Q1)·Q2.

[0083] In the approximate computation unit processing stage, the most significant bits k1 and k2 of operands A and B are processed by adder 1 to generate k1+k2, and then processed by decoder to generate... After shifting left by k2 bits using the bucket shifter 1, the result is... After shifting left by k1 positions using the barrel shifter 2, the result is... The two are obtained by adder 2.

[0084] The round(Q1)·Q2 obtained from the error part processing unit and the approximate part processing unit are then compared. or, and The final result is obtained after adding step 3.

[0085] Specifically, in this embodiment, the data comparison module compares two operands, with the larger operand being Q1 and the smaller one being Q2; the adjacent detector module detects the value of bit k-1 of Q1, and if bit k-1 contains a "1", then the larger operand Q1 is overestimated as 2. k+1 Otherwise, the larger operand Q1 will be underestimated to 2. k Then, the barrel shifter shifts Q2 left by k+1 or k bits to obtain round(Q1)·Q2. The priority encoder encodes Q1 into round(Q1); since round(Q1)·Q2 is always greater than... Small, so No carry will occur; an OR gate is used instead of an adder to achieve the addition effect. ORing round(Q1)·Q2 yields the following result. Using OR gates can achieve error compensation and consume fewer resources compared to adders.

[0086] Specifically, in this embodiment, the approximate product P approx Calculation: The final result generated in the EP calculation unit, round(Q1)·Q2, is compared with... Phase or obtain Again with The approximate product P is obtained after adding unit 3. approx . The unique feature is that round(Q1)·Q2 is always greater than small, so no carry is generated, the effect of using OR gate and adder is the same, and the hardware resource is less.

[0087] Specifically, in this embodiment, the purpose of the first detector module (LOD module) is to extract the most significant bit k of the input operands A, B in the form of 2 k . Based on the 4-bit LOD detection module, a high-order LOD module is cascaded. The 4-bit LOD gate circuit is shown in Figure 5 , which has a total of 3 three-input multiplexers and 3 AND gates. The output of each three-input multiplexers is connected to the input of each AND gate. Assuming that the input operand is d, the output result is Z. The third bit (the highest bit) of Z is equal to the third bit (the highest bit) of d, and the second bit of Z is equal to the second bit of d and the output of a three-input multiplexer. The three-input selector outputs 1 when the third bit of d is 0, and outputs 0 when the third bit of d is 1. Similarly, the first bit of Z is equal to the first bit of d and the output of a three-input multiplexer. The three-input selector outputs the output of the first three-input selector when the second bit of d is 0, and outputs 0 when the second bit of d is 1. The lowest bit of Z is equal to the lowest bit of d and the output of a three-input multiplexer. The three-input selector outputs the output of the second multiplexer when the first bit of d is 0, and outputs 0 when the first bit of d is 1.

[0088] Specifically, in this embodiment, the purpose of the priority encoder module is to detect k in 2 k . Assuming that the input operand is D and the output operand is Z, a multiplexer is used. If D is equal to 2 0 , the output Z is 0, D is equal to 2 1 , Z outputs 1, and recursively until D is equal to 2 7 , Z outputs 7.

[0089] Specifically, in this embodiment, the purpose of the barrel shift module is to perform a shift operation. The product of 2 and k2 is to shift 2 k2 bits to the left, and similarly, the product of 2 and k1 is to shift 2 k1 bits to the left.

[0090] Specifically, in this embodiment, the purpose of the decoder module is to convert k1+k2 to Assuming that the input operand is D and the output operand is Z, a multiplexer is used. If D is equal to 0, the output Z is 2 0 , D is equal to 1, Z outputs 2 1 , and recursively until D is equal to 7, Z outputs 27 .

[0091] In particular, in the present embodiment, the adder uses a carry-lookahead adder. The carry-lookahead adder differs from the ordinary adder in that the full adder of the high bit of the ordinary adder waits for the carry information transmitted by the low bit full adder before performing the calculation, and if the number of levels is high, the delay of the combinational logic will be too long. The unique feature of the carry-lookahead adder is that it can directly calculate the carry information from the input operands and transmit it to each level without waiting for the next level to finish calculating the carry. Assuming that the input operands are A, B, the input carry is CIN, the output is S, and the output carry is CO. The principle of the carry-lookahead adder is as follows:

[0092] g = A&B (29)

[0093] p = A|B (30)

[0094] c[0] = g[0]|(p[0]&CIN) (31)

[0095] c i+1 = g i |p i &c i ,i = 1,2,3,...,k-1 (32)

[0096] S = A^B^{c[k-1:0],CIN} (33)

[0097] CO = c[k] (34)

[0098] where the variable c is the carry information of each bit, and a large bit width CLA can be cascaded by small bit width CLAs.

[0099] In particular, in the present embodiment, the purpose of the data comparison module is to compare the sizes of two values Q1 and Q2. As shown in FIG. 4, x and y are input operands, and Q1 and Q2 are obtained by the following equations: Figure 2

[0100]

[0101]

[0102]

[0103]

[0104]

[0105] In particular, in the present embodiment, the purpose of the adjacent detector module (NOD module) is to approximate the input operands A and B to 2​k Or 2 k+1 .like Figure 2 As shown, NOD determines that if bit k-1 of a k-bit operand is 1, then the operand is approximated as 2. k+1 If the k-1 bit is 0, then it is 2. k The gate-level circuit diagram of the 16-bit NOD detection module is as follows: Figure 6 As shown, there are a total of 61 AND gates, 14 OR gates, and 44 NOT gates. Assume the input operand is 1 and the output operand is 0. The calculation method for each bit of the output 0 is shown in the following formula:

[0106] o 16 =I 15 &I 14 (40)

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113]

[0114] Specifically, in this embodiment, the OR gate adds the final result of EP to AP, replacing the addition operation.

[0115] Example 2

[0116] According to equation (9), the error of the logarithmic multiplier in the existing EP calculation unit is caused by EP. Therefore, a compensation algorithm based on WCE is proposed to estimate EP. The larger operand in EP is approximately a power of 2, while the other operand remains unchanged. Thus, multiplication in EP can be replaced by shift operations. Compared to multiplication, shift operations use fewer hardware resources. The details of Algorithm 2 are as follows:

[0117]

[0118]

[0119] else

[0120]

[0121] endif

[0122] Compute the position of the first one bit of k: Q1:

[0123] if k = 0

[0124] EP = Q2

[0125] else if Q1 [k - 1] = 1

[0126] EP = Q2 « (k + 1)

[0127] else

[0128] EP = Q2 « k

[0129] endif

[0130] First, compare the size of the two operands, the larger operand is Q1, and the smaller operand is Q2. Q1 is further processed by the NOD module. If the k-1 bit of Q1 appears the value "1", Q1 is overestimated to 2 k+1 , otherwise, Q1 is underestimated to 2 k , and then EP can be obtained by left shifting the other operand Q2 by k bits or k+1 bits.

[0131] Specifically, in the embodiment, the selection strategy of the operand is based on the WCE minimization principle, and the error of the algorithm is caused by the approximation of the operand. For an n-bit multiplier, the rounding error (RE) under different k values can be expressed as:

[0132]

[0133] k represents the most significant bit of the operand.

[0134] The present application analyzes the WCE under two conditions. The first condition is to select the smaller operand for approximation, that is, According to equation (18), the maximum rounding error is 2 n-3 . Assuming that Q1 is smaller than Q2, the value of Q2 is between 0 and 2 n-1 -1. Therefore, the WCE of the approximate multiplier can be calculated by the following equation:

[0135]

[0136] Therefore, for an 8-bit multiplier, the WCE of the proposed multiplier is 4064.

[0137] The second condition is to select the larger operand for approximation, that is, In order to satisfy Q1 is greater than or equal to Q2, because the maximum value of Q1 is 2 k +2 k-1 , the value of Q2 is between 0 and 2 k+2 k-1 The WCE of the approximate multiplier can be calculated by the following equation:

[0138]

[0139] Therefore, for an 8-bit multiplier, the WCE of the multiplier proposed in the second case is 3072.

[0140] Compared with the first case, the WCE of the second case is smaller. Therefore, in the proposed compensation algorithm, the operand with the larger approximate value in the EP.

[0141] Embodiment 3

[0142] According to equation (9), the AP part of the multiplier is composed of three parts. That is

[0143] First part The operands A and B are processed by the LOD module to generate and After the priority encoder, k1 and k2 are generated. k1 and k2 are processed by adder 1 to generate k1+k2. k1+k2 is finally processed by the decoder to generate

[0144] Second part A and XOR generates After the barrel shifter, it is left-shifted by k2 bits to obtain

[0145] Third part B and XOR generates After the barrel shifter, it is left-shifted by k1 bits to obtain

[0146] After adder 2, it generates The final approximate product

[0147] Approximate product P approx Calculation: The approximate product can be calculated by the following equation:

[0148]

[0149] Obviously, two adders are needed to generate AP, and an additional adder is needed to compensate EP, but since the final result of EP is added to AP without generating a carry, an OR gate can be used instead of an adder to achieve the effect of addition. Specifically as follows:

[0150] Q1 and Q2 are generated by the LOD module, and the larger Q1 is approximately 2k or 2 k+1 Assume The following inequality can be derived:

[0151]

[0152]

[0153]

[0154]

[0155] And round(Q1) • Q2 are in one-hot form, and because round(Q1) • Q2 is less than

[0156] So The sum of round(Q1) • Q2 does not produce a carry. Therefore The sum of round(Q1) • Q2 can be operated by an OR gate instead of an adder. Thus, equation (21) can be written as:

[0157]

[0158] Example 4

[0159] The NMED and MRED of the present application can be calculated by the following equations:

[0160]

[0161] ED = |P approx - P exact | (27)

[0162]

[0163] Where N represents the total number of input operands, M represents the maximum output of the accurate multiplier, and P(ED), P(RED) represent the probability of the occurrence of the error. The present application considers the 8-bit multiplier designed in the present application and other 8-bit multipliers. The range of input operands is from 0 to 255, and all possible input operands are simulated to evaluate the performance of the multiplier designed in the present application, and the results are shown in Table I.

[0164] Table I

[0165] Error measurement of the logarithmic multiplier

[0166]

[0167] Compared with the most accurate improved logarithmic multiplier A (ILM-A), NMED is reduced by 34%, and MRED is reduced by 48%, which shows that the multiplier designed in the application can effectively improve the accuracy by compensating algorithm.

[0168] As Figure 3 shown, Figure 3 The bilateral error distribution diagram generated by the application, the larger operand in the application of overestimating or underestimating EP can obtain the bilateral error distribution as Figure 3 shown. In the application mainly operated by multiply-accumulate, since the error is positive and negative, the generated error may offset each other, and the error accumulation can be avoided.

[0169] In P approx The calculation module uses OR gate instead of addition operation. Table II gives the performance comparison of OR gate and conventional adder, both designs are realized by Verilog, and synthesized by ISE14.7-Webpack on Xilinx xc6slx16-2csg324. The adder uses carry-lookahead adder (CLA), compared with CLA, the LUT of OR gate is reduced by 39%, the delay is reduced by 83%, and the power consumption is also reduced by 74%. Therefore, using OR gate consumes less resources.

[0170] Table II

[0171] Hardware comparison of CLA and OR gate

[0172]

[0173] The approximate multiplier is realized by Verilog hardware description language, and all designs are only realized by combinational logic without pipeline, and synthesized by ISE14.7-Webpack. Then the implementation is built in Xilinx xc6slx16-2csg324, and all I / O is allocated to the pin, and the power is estimated at a clock frequency of 50MHz. The comparison results are shown in Table III.

[0174] Table III

[0175] Hardware indicators of logarithmic multiplier

[0176]

[0177] The improved logarithmic multiplier A (ILM-A) in Table III refers to a logarithmic multiplier using the original NOD module, and the improved logarithmic multiplier B (ILM-B) refers to a logarithmic multiplier using a simplified NOD module. Compared with ILM-A, the present design has better hardware performance, while the NMED, MRED and WCE are 34%, 48% and 25% lower than ILM-A respectively, and the compensation algorithm can significantly improve the accuracy of the multiplier without sacrificing hardware resources. Compared with ILM-B, although the power consumption increases by 22%, the range of input operands in the present design is not limited, and the accuracy is higher than that of ILM-B. Therefore, the present design is suitable for more applications. Compared with the logarithmic multiplier (LM), the NMED, MRED and WCE of the present design are reduced by 53%, 61% and 25% respectively. In addition, the present application also calculates the product of PDP and NMED and the product of PDP and MRED to prove that the present design is efficient. Table III shows that the PDP*NMED and PDP*MRED of the present design are the smallest among the existing logarithmic multipliers.

[0178] In addition, the relationship between the MRED and the PDP of the considered logarithmic multipliers is shown in Figure 4 The different values of PDP-MRED are represented by different dashed lines. The smaller the PDP, the larger the MRED of the approximate multiplier, and then PDP-MRED represents a unit of measure of the performance-price ratio of the multiplier. The smaller the PDP-MRED indicates that the hardware consumes fewer resources under the premise of the same accuracy. The HPLM designed in the present application is located at the lowest dashed line in the figure, which shows that the PDP-MRED of the approximate multiplier designed in the present application is the smallest, that is, the approximate multiplier designed in the present application achieves the best balance between hardware consumption and accuracy.

[0179] It should be noted that, in the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0180] Although embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A high-precision logarithmic multiplier, characterized in that, It includes a preprocessing unit, an error calculation unit, and an approximation calculation unit, and its workflow is as follows: First, operands A and B are input into the preprocessing unit, and operands A and B are preprocessed by the first detector module and the priority encoder. Next, the XOR result of the preprocessed operands A and B is input into the data comparison module in the error part processing unit, and then processed by an adjacent detector module, a priority encoder, and a barrel shifter to obtain the final result EP of the error part; Meanwhile, the most significant bits k1 and k2 of the preprocessed operands A and B are input into the approximation part calculation unit. After the operation of the adder, decoder and barrel shifter, the final result AP of the approximation part is obtained. Finally, the EP obtained from the error processing unit and the AP obtained from the approximation calculation unit are processed by an adder to obtain the final result P. approx ; In the preprocessing unit, two input operands A and B are respectively fed into the first detector module 1 and the first detector module 2, in order to... k Extract the powers of the most significant bits of operands A and B in the form of then and The outputs k1 and k2 are respectively processed by priority encoder 1 and priority encoder 2; then the input operand A and XOR generation Input operand B and XOR generation In the error calculation unit, the result after XOR is input into the data comparison module of the error calculation unit. If Then intermediate variables Conversely, intermediate variables Then, Q1 is approximated as 2 by the adjacent detector module in the error calculation unit. k Or 2 k+1 If the (k-1)th bit in the binary representation of Q1 is 1, then Q1 is approximated as 2. k+1 Conversely, if the (k-1)th bit is 0, then Q1 is approximately 2. k That is, round(Q1) is 2 k Or 2 k+1 The most significant bit k or k+1 of round(Q1) is output by the priority encoder 3 in the error calculation unit. Then, Q2 is shifted left by the barrel shifter 3 in the error calculation unit to achieve round(Q1)·Q2.

2. A high-precision logarithmic multiplier according to claim 1, characterized in that, In the approximate computation unit, the most significant bits k1 and k2 of operands A and B are processed by adder 1 to generate k1+k2, and then processed by decoder to generate... After shifting left by k2 bits using the barrel shifter 1, the result is... After shifting left by k1 positions using the barrel shifter 2, the result is... The two are obtained by adder 2.

3. A high-precision logarithmic multiplier according to claim 1, characterized in that, The round(Q1)·Q2 obtained from the error part processing unit and the approximate part processing unit are then compared. or, and The final result is obtained after adding step 3.

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