A method, system device, and medium for generating a finite field multiplication circuit

Abstract

The application provides a method for generating a finite field multiplication circuit, comprising the following steps: determining the data length of data participating in multiplication operation, and determining a primitive polynomial according to the data length; multiplying the data in a finite field to obtain a multiplication matrix table, generating an intermediate polynomial according to the product items in the multiplication matrix table, and generating a data expander circuit according to the product relationship of each item in the intermediate polynomial; generating a primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and connecting the data expander circuit and the primitive polynomial remainder circuit correspondingly. The method for generating the finite field multiplication circuit can omit the look-up table and the corresponding logical addition operation once for each multiplication operation by analyzing the finite field multiplication operation compared with the common look-up table mode, and the operation is expanded by one step through hardware to obtain the implementation, so that the speed is improved through certain area loss.

Description

Technical Field

[0001] This invention belongs to the field of computer storage, and specifically relates to a method, system, device and medium for generating finite field multiplication circuits. Background Technology

[0002] In the field of computer storage, data storage and transmission often require encoding algorithms for protection or encryption / decryption. These algorithms are typically implemented using additional redundancy, involving aspects of elliptic cryptography. In short, ensuring the coefficients of the encryption equations is chosen is crucial. A common approach is to use the values ​​of the Vandermonde matrix as coefficients. Based on the properties of the Vandermonde matrix, for the equation to have a unique solution, the Vandermonde coefficients must be distinct. Therefore, we arrive at a standard: construct a Vandermonde matrix with all distinct elements as coefficients, and then use the resulting equations for encryption / decryption or encoding / decoding to protect the stored data.

[0003] In practice, directly applying the above method almost inevitably encounters the problem of data overflow. This involves matrix multiplication, a crucial operation in actual computation. Applying real number field operations directly to computer data processing inevitably leads to overflow. Therefore, attention turns to finite fields—fields that do not cause overflow. By placing the entire computation within a finite field, the overflow problem disappears. Furthermore, these operations only involve basic arithmetic operations, making them ideal for finite fields. Additionally, the rules of operation in finite fields are simpler than in other fields like the real number field, making them highly suitable for data computation and processing. Since finite fields do not suffer from overflow, and both the data and results are confined within the finite field, the number of bits used in computer representation can be fixed, preventing data expansion or reduction. Consequently, finite fields are widely used in storage, becoming a necessary and crucial component of storage processing. In practical implementations, the finite field GF(2^n) is commonly used.

[0004] When computing data using finite fields, traditional finite field processing methods are mostly implemented in software, primarily through table lookups. While there are techniques to improve the efficiency of multiplication operations in finite fields, the resource consumption is still too high for processing large amounts of data.

[0005] Therefore, there is an urgent need for a hardware implementation scheme that does not require table lookup. Summary of the Invention

[0006] To address the above problems, this invention proposes a method for generating finite field multiplication circuits, comprising:

[0007] Determine the data length of the data involved in the multiplication operation, and determine the primitive polynomial based on the data length;

[0008] The data is multiplied in a finite field to obtain a multiplication matrix table. An intermediate polynomial is generated based on the product terms in the multiplication matrix table. A data expander circuit is generated based on the product relationship of each term in the intermediate polynomial.

[0009] The primitive polynomial remainder circuit is generated based on the primitive polynomial and the intermediate polynomial, and the data expander circuit and the primitive polynomial remainder circuit are connected accordingly.

[0010] In some embodiments of the present invention, multiplying the data over a finite field to obtain a multiplication matrix table, and generating an intermediate polynomial based on the product terms in the multiplication matrix table includes:

[0011] The data is multiplied bitwise according to its length to obtain a multiplication matrix;

[0012] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0013] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0014] In some embodiments of the present invention, the method further includes:

[0015] The expander circuit is generated by connecting each term of the plurality of polynomials in sequence using an XOR gate logic.

[0016] In some embodiments of the present invention, the method for generating a primitive polynomial remainder circuit based on the primitive polynomial and the intermediate polynomial includes:

[0017] According to the principle of finite field computation, each term of the intermediate polynomial is divided by the primitive polynomial to perform a remainder operation, and each term of the polynomial after the remainder operation is passed through an XOR gate logic in sequence to generate the primitive polynomial remainder circuit.

[0018] In some embodiments of the present invention, multiplying the data in a finite field to obtain a multiplication matrix table includes:

[0019] The data are multiplied in reverse order to obtain a multiplication matrix;

[0020] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0021] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0022] In some embodiments of the present invention, the method further includes:

[0023] The data length of the data involved in the multiplication operation is determined based on the available circuit area of ​​the hardware circuit on the actual chip.

[0024] In some embodiments of the present invention, the method further includes:

[0025] The primitive polynomial is selected based on the circuit area to generate the primitive polynomial remainder circuit.

[0026] Another aspect of the present invention provides a system for generating finite field multiplication circuits, comprising:

[0027] An initialization data module is configured to determine the data length of the data participating in the multiplication operation, and to determine the length of the primitive polynomial and the primitive polynomial based on the data length.

[0028] A data expander circuit generation module is configured to multiply the data in a finite domain to obtain a multiplication matrix table, generate an intermediate polynomial based on the product terms in the multiplication matrix table, and generate a data expander circuit based on the product relationship of each term in the intermediate polynomial.

[0029] A remainder circuit generation module is configured to generate a remainder circuit for the primitive polynomial based on the primitive polynomial and the intermediate polynomial, and to connect the data expander circuit and the primitive polynomial remainder circuit accordingly.

[0030] Another aspect of the present invention provides a computer device comprising:

[0031] At least one processor; and

[0032] A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of any of the methods described in the above embodiments.

[0033] Another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described in the above embodiments.

[0034] This invention proposes a method for generating finite field multiplication circuits. By analyzing finite field multiplication operations and focusing on the concept of Galois field polynomials, this method implements a fast hardware solution for Galois field multiplication. Compared to the conventional lookup table method, each multiplication operation eliminates one lookup in the forward and reverse tables and the corresponding logical addition operation. Instead, the operation is expanded in hardware in one step, achieving a speed improvement despite some area loss. This invention supports different primitive polynomial configurations, and its principle can be extended to finite field operations with wider bit widths (GF(2^m)). No lookup table is required, and the operation requires no firmware support, reducing software development overhead. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart of a method for generating a finite field multiplication circuit is provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of a system structure for generating a finite field multiplication circuit, provided as an embodiment of the present invention.

[0038] Figure 3 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention;

[0040] Figure 5 This invention provides a schematic diagram of a multiplication matrix misalignment for generating finite field multiplication.

[0041] Figure 6 A schematic diagram of a finite field multiplication data extension circuit provided in an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of generating a finite field multiplicative polynomial modulo operation according to an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of a circuit for generating a finite field multiplication modulo operation, provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0045] like Figure 1 As shown, this invention proposes a method for generating finite field multiplication circuits, comprising:

[0046] Step S1: Determine the data length of the data involved in the multiplication operation, and determine the primitive polynomial based on the data length;

[0047] Step S2: Multiply the data in a finite field to obtain a multiplication matrix table, generate an intermediate polynomial based on the product terms in the multiplication matrix table, and generate a data expander circuit based on the product relationship of each term in the intermediate polynomial.

[0048] Step S3: Generate the primitive polynomial remainder circuit based on the primitive polynomial and the intermediate polynomial, and connect the data expander circuit and the primitive polynomial remainder circuit accordingly.

[0049] In some embodiments of the present invention, multiplying the data over a finite field to obtain a multiplication matrix table, and generating an intermediate polynomial based on the product terms in the multiplication matrix table includes:

[0050] The data is multiplied bitwise according to its length to obtain a multiplication matrix;

[0051] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0052] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0053] In some embodiments of the present invention, the method further includes:

[0054] The expander circuit is generated by connecting each term of the plurality of polynomials in sequence using an XOR gate logic.

[0055] In some embodiments of the present invention, the method for generating a primitive polynomial remainder circuit based on the primitive polynomial and the intermediate polynomial includes:

[0056] According to the principle of finite field computation, each term of the intermediate polynomial is divided by the primitive polynomial to perform a remainder operation, and each term of the polynomial after the remainder operation is passed through an XOR gate logic in sequence to generate the primitive polynomial remainder circuit.

[0057] In some embodiments of the present invention, multiplying the data in a finite field to obtain a multiplication matrix table includes:

[0058] The data are multiplied in reverse order to obtain a multiplication matrix;

[0059] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0060] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0061] In some embodiments of the present invention, the method further includes:

[0062] The data length of the data involved in the multiplication operation is determined based on the available circuit area of ​​the hardware circuit on the actual chip.

[0063] In some embodiments of the present invention, the method further includes:

[0064] The primitive polynomial is selected based on the circuit area to generate the primitive polynomial remainder circuit.

[0065] In embodiments of the present invention, the data involved in the multiplication operation refers to the bit width of the input data of the multiplication circuit, typically represented in binary. It refers to the number of bits in the two data items being multiplied. For example, in a multiplication circuit performing finite field multiplication of two 8-bit data items, the input data can be understood as 8 data lines on each side, totaling 16 input lines to the multiplication circuit. The data length can be a power of 2, such as 16 bits, 32 bits, etc., as needed.

[0066] Furthermore, after determining the data length, the data is multiplied into a matrix table for each bit according to the finite field calculation method. The hardware implementation involves expanding the value of each bit of the multiplicand based on the value of each bit of the multiplier. Taking 8-bit data multiplication as an example, input A = a7a6a5a4a3a2a1a0; input B = b7b6b5b4b3b2b1b0; then A*B = (a7a6a5a4a3a2a1a0)*(b7b6b5b4b3b2b1b0). a7-a0 represent the 8th to 1st bits of input data A, and similarly, b7-b0 represent the 8th to 1st bits of input data B. This results in a matrix of 64 multiplied numbers.

[0067] [a7b7,a6b7,a5b7,a4b7,a3b7,a2b7,a1b7,a0b7,a7b6,a6b6...a7b1,a6b1,a5b1,a4b1,a3b1,a2b1,a1b1,a0b1,a7 b0,a6b0,a5b0,a4b0,a3b0,a2b0,a1b0,a0b0]=[A*[b7],A*[b6],A*[b5],A*[b4]A*[b3],A*[B2],A*[b1],A*[b0]]

[0068] Furthermore, based on the aforementioned matrix table, the numbers representing the multiplication of data bits are then added together in a staggered manner according to the carry-over relationship of multiplication to obtain the intermediate polynomial. Specifically, the staggered addition is as follows: Figure 5 As shown, this involves calculating multiple polynomials using the traditional multiplication-to-addition method. Due to the characteristics of finite fields, no carry-over is required. Therefore, using... Figure 5 For example, the first polynomial is a7b7, the second polynomial is a6b7+a6b6, and the third polynomial is a5b7+a6b6+a7b5, that is, according to Figure 5 The dislocation matrices shown are added from bottom to top to form a single polynomial, and all the polynomials are combined into an intermediate polynomial H(x) with 15 polynomials.

[0069] The result of the multiplication operation, i.e., the intermediate polynomial, is as follows:

[0070] H(x)=h(14)X^14+h(13)X^13+h(12)X^12+h(11)X^11+h(10)X^10+h(9)X^9+h(8 )X^8+h(7)X^7+h(6)X^6+h(5)X^5+h(4)X^4+h(3)X^3+h(2)X^2+h(1)X^1+h(0).

[0071] H(x) represents the intermediate polynomial obtained, and H(14) represents the highest-order coefficient, i.e. Figure 5 The leftmost a7b7,h(13) shown represents a6b7+a6b6, and x^14 is the algebraic representation of a polynomial.

[0072] The resulting h[14:0] is the intermediate value of our operation, which is 15 bits. Since a byte is 8 bits, the highest power that can be represented in a finite field is 7 (0-7), so the highest power of the product of the two numbers is 14.

[0073] Furthermore, the data bits involved in the calculation of the polynomial in the coefficients of H(x) are used as inputs to an XOR gate circuit to generate a corresponding data expander circuit. Specifically, for example... Figure 6 As shown, Figure 6In the first row, the coefficient of h(14) is a7b7 (written as A7B7 in the diagram, which has the same meaning). h(14) has only one term, therefore it is an XOR gate logic. Similarly, in the second row, the circuit of h(13) is as described above. The coefficient of h(13) is a6b7+a6b6, so a6b7 and a6b6 are used as inputs to an XOR logic gate for XOR logic operation. Furthermore, h(12) is calculated by passing a5b7 and a6b6 through an XOR logic gate circuit, and the result is then XORed with a7b5. This process is repeated to generate the data expander circuit.

[0074] It should be noted that, since the computation is performed in a finite field, the "+" sign in the polynomial is an XOR logic in the finite field. Therefore, XOR logic gates are used in all data expander circuits.

[0075] The input to the modulo operator is the output of the data expander, i.e., the intermediate calculated value. This intermediate value clearly does not belong to the result within the finite field. Data representation within the finite field is only 8 bits, but the intermediate value has 15 bits. To obtain the final result, the intermediate value calculated by the data expander needs to be moduloed by the selected primitive polynomial. In GF(2^8), 0x11D is generally chosen as the primitive polynomial; this is a conventional choice. Choosing other suitable polynomials is also possible; in this hardware implementation, only minor adjustments are needed in the specific operations.

[0076] Based on the operational characteristics of finite fields, the modulo operation of intermediate values ​​needs to be handled in conjunction with the case of polynomials. It can be transformed into an addition operation between the lower eight bits and the higher seven bits of the value itself. The mathematical principle is as follows:

[0077] First, there is a technique for calculating multiplication in finite field multiplication, which is also recorded in the book "Cryptography and Network Security". Taking the primitive polynomial in the finite field as 0x11D as an example, the primitive polynomial m(x) = x^8 + x^4 + x^3 + x^2 + 1;

[0078] First, we have x^8 mod m(x) = [m(x) – x^8] = x^4 + x^3 + x^2 + 1

[0079] Based on this equation, for the polynomial f(x), we can obtain:

[0080] f(x)=b7x^7+b6x^6+b5x^5+b4x^4+b3x^3+b2x^2+b1x+b0;

[0081] x*f(x)=(b7x^8+b6x^7+b5x^6+b4x^5+b3x^4+b2x^3+b1x^2+b0x)mod m(x).

[0082] If b7 equals 0, then the result is a polynomial less than 8, and no modulo calculation is needed.

[0083] If b7 equals 1, then from the above we have:

[0084] x*f(x)=(b6x^7+b5x^6+b4x^5+b3x^4+b2x^3+b1x^2+b0x)+(x^4+x^3+x+1);

[0085] For hardware implementation, this can be easily calculated using bitwise XOR operations. For exponents of x higher than one, a recursive approach can be used, such as: x^2 * f(x) = x * [x * f(x)]. Similarly, the value of x^m * f(x) can be calculated. However, for a given GF(2^8), based on the results obtained above, it is only necessary to calculate up to X^14.

[0086] From the above calculation, we get h(x)=h(14)x^14+h(13)x^13+h(12)x^12+h(11)x^11+h(10)x^10+h(9)x^9+h(8)x^8+h(7)x^7+h(6)x^6+h(5)x^5+h(4)x^4+h(3)x^3+h(2)x^2+h(1)x^1+h(0).

[0087] Let h(x) be modulo m(x), that is, each term of the polynomial h(x) modulo m(x) and then summed.

[0088] Let: L(x)=h(7)x^7+h(6)x^6+h(5)x^5+h(4)x^4+h(3)x^3+h(3)x^2+h(1)x^1+h(0), we can get:

[0089] H(x) = h(14)x^14 + h(13)x^13 + h(12)x^12 + h(11)x^11 + h(10)x^10 + h(9)x^9 + h(8)x^8 + L(x), where the highest power of L(x) is 7, and the remainder operation result is itself. The coefficients of x^14, x^13, x^12, x^11, x^10, x^9, and x^8 are h(14), h(13), h(12), h(11), h(10), h(9), and h(8). From the result of the multiplication operation in the previous step, these coefficients can all be calculated. In this step, we only need to substitute the result of taking the remainder of the corresponding polynomial with respect to the primitive polynomial, which is equivalent to taking the remainder of the entire operation result with respect to the primitive polynomial.

[0090] Therefore, in this step, it is necessary to calculate the polynomial expressions of x^14, x^13, x^12, x^11, x^10, x^9, and x^8 after taking the remainder of the primitive polynomial. Then, add all the results together and add them to L(x) to obtain the corresponding operation result.

[0091] Once the primitive polynomial is selected, its polynomial expression for higher powers remains fixed. Taking the primitive polynomial m(x) = x^8 + x^4 + x^3 + x^2 + 1 as an example, the following polynomial can be obtained:

[0092] L(x)=x^7+x^6+x^5+x^4+x^3+x^2+x+1

[0093] X^8=x*x^7=x^8 mod m(x)=x^4+x^3+x^2+1

[0094] X^9 = x * x^8 = x^5 + x^4 + x^3 + x

[0095] X^10=x*x^9=x^6+x^5+x^4+x^2

[0096] X^11=x*x^10=x^7+x^6+x^5+x^3

[0097] X^12=x*x^11=x^8+x^7+x^6+x^4=x^7+x^6+x^3+x^2+1

[0098] X^13=x*x12=x^8+x^7+x^4+x^3+x=x^7+x^2+x+1

[0099] X^14=x*x13=x^8+x^3+x^2+x=x^4+x+1

[0100] The blank terms above can be considered as having a coefficient of 0. The actual coefficients of the other terms are obtained from the result of the multiplication operation in the first step. Therefore, by adding them together using the polynomial modulo operation, we obtain the final result after taking the remainder. The circuit structure is as follows: Figure 8 As shown. This completes the calculation.

[0101] Specifically, refer to the above formula or Figure 7 The equation list shown illustrates how the remainder circuit is generated by representing the corresponding coefficients on the right-hand side of the modulo operation. The coefficient for x^7 is h(7), the coefficient for x^6 is h(6), the coefficient for x^5 is h(5), and the coefficient for x^0 (i.e., 1) is h(0). Following the rules of modulo operation in finite fields, the input-output relationship of the modulo operation circuit can be expressed as:

[0102] C[7]=h(7)+h(11)+h(12)+h(13);

[0103] C[6]=h(6)+h(10)+h(11)+h(12);

[0104] C[5]=h(5)+h(9)+h(10)+h(11);

[0105] C[4]=h(4)+h(8)+h(9)+h(10)+h(14);

[0106] C[3]=h(3)+h(8)+h(10)+h(11)+h(12);

[0107] C[2]=h(2)+h(8)+h(10)+h(12)+h(13);

[0108] C[1]=h(1)+h(9)+h(13)+h(14);

[0109] C[0]=h(0)+h(8)+h(12)+h(13)+h(14);

[0110] The above C[7]~C[0] have Figure 7 The coefficients on the right side of the equation shown are obtained by adding them from top to bottom. An empty right side of the equation indicates that the coefficient is 0. Taking C[7] as an example, h(7) in C[7] represents the coefficient of x^7 in the intermediate polynomial H(x), i.e., h(7). h(11) is obtained by taking the modulo of the first non-zero data below x^7, which is h(11). That is, the first term of the polynomial obtained after taking the modulo of h(11) in the 5th row of the figure with the primitive polynomial is x^7.

[0111] For ease of understanding, the above calculation formula can be translated as follows: Figure 7The generation process of ) can be understood as the addition of the coefficients of the data on the right side of the equal sign from top to bottom that are not zero. x^7 is not empty in the first row. Since L(x) represents the lower 8 bits of the intermediate polynomial, its coefficients are h(7) to h(0). Therefore, the first term of its C[7] is h(7), the second term is in the 5th row, the 5th row uses the corresponding intermediate polynomial h(11), then the second term of C[7] is h(11), and so on, the third term is h(12), and the fourth term is h(13).

[0112] C[7]~C[0] is the output result of the finite field multiplication operation of the present invention, that is, the 8-bit input data A and the 8-bit input data B are used to calculate the 8-bit result C.

[0113] Since addition in a finite field is implemented using XOR logic, C[7] to C[0] can also be implemented using XOR logic gates in hardware circuits. By combining the data expander circuit in the above embodiment, the 15 outputs (h(14) to h(0)) of the data expander circuit can be used as inputs to the remainder circuit to generate the hardware implementation circuit for finite field multiplication.

[0114] The above embodiment uses GF(2^8) as an example. In the hardware implementation, it is only necessary to perform a simple XOR operation on the intermediate value according to different bit pairs.

[0115] As for adapting to other primitive polynomials, there will only be slight differences in the position of the XOR operation in the remainder module.

[0116] By determining the value of the externally configured primitive polynomial, relevant operation weight factors are added to the operation. Different primitive polynomials correspond to different operation weight factors, which can realize the modification of the modulo operation configuration according to the configuration of the primitive polynomial, that is, adapting the finite field multiplication operation under different primitive polynomial conditions.

[0117] In some embodiments of the present invention, the size of the data expansion circuit is determined by the input data. In the above embodiments, taking 8-bit input data as an example, the data expansion circuit requires a maximum of 7 calculation layers, and the remainder circuit requires a maximum of 5 calculation layers. The calculation depth of the data expansion circuit and the remainder circuit, as well as the chip area consumed, are determined by the length of the input data. Therefore, in some embodiments, different lengths can be selected as the input data size as needed. Alternatively, multiple sets of 8-bit data expansion circuits and remainder circuits can be generated as needed.

[0118] In some embodiments of the present invention, different primitive polynomials can be selected as needed to generate corresponding remainder circuits. In the above embodiments, the remainder circuit is generated using the primitive polynomial m(x) = x^8 + x^4 + x^3 + x^2 + 1. Different primitive polynomials will generate different remainder circuits. The appropriate primitive polynomial can be reasonably selected to generate the corresponding remainder circuit based on the available area of ​​the hardware circuit in the chip.

[0119] like Figure 2 As shown, another aspect of the present invention proposes a system for generating finite field multiplication circuits, comprising:

[0120] Initialize data module 1, which is configured to determine the data length of the data participating in the multiplication operation, and determine the length of the primitive polynomial and the primitive polynomial based on the data length;

[0121] The data expander circuit generation module 2 is configured to multiply the data in a finite domain to obtain a multiplication matrix table, generate an intermediate polynomial based on the product terms in the multiplication matrix table, and generate a data expander circuit based on the product relationship of each term in the intermediate polynomial.

[0122] The modulo circuit generation module 3 is configured to generate a primitive polynomial modulo circuit based on the primitive polynomial and the intermediate polynomial, and to connect the data expander circuit and the primitive polynomial modulo circuit accordingly.

[0123] like Figure 3 As shown, another aspect of the present invention also provides a computer device comprising:

[0124] At least one processor 21; and

[0125] Memory 22 stores computer instructions 23 executable on processor 21, which, when executed by processor 21, implement a method for generating a finite field multiplication circuit, comprising:

[0126] Determine the data length of the data involved in the multiplication operation, and determine the primitive polynomial based on the data length;

[0127] The data is multiplied in a finite field to obtain a multiplication matrix table. An intermediate polynomial is generated based on the product terms in the multiplication matrix table. A data expander circuit is generated based on the product relationship of each term in the intermediate polynomial.

[0128] The primitive polynomial remainder circuit is generated based on the primitive polynomial and the intermediate polynomial, and the data expander circuit and the primitive polynomial remainder circuit are connected accordingly.

[0129] In some embodiments of the present invention, multiplying the data over a finite field to obtain a multiplication matrix table, and generating an intermediate polynomial based on the product terms in the multiplication matrix table includes:

[0130] The data is multiplied bitwise according to its length to obtain a multiplication matrix;

[0131] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0132] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0133] In some embodiments of the present invention, the method further includes:

[0134] The expander circuit is generated by connecting each term of the plurality of polynomials in sequence using an XOR gate logic.

[0135] In some embodiments of the present invention, the method for generating a primitive polynomial remainder circuit based on the primitive polynomial and the intermediate polynomial includes:

[0136] According to the principle of finite field computation, each term of the intermediate polynomial is divided by the primitive polynomial to perform a remainder operation, and each term of the polynomial after the remainder operation is passed through an XOR gate logic in sequence to generate the primitive polynomial remainder circuit.

[0137] In some embodiments of the present invention, multiplying the data in a finite field to obtain a multiplication matrix table includes:

[0138] The data are multiplied in reverse order to obtain a multiplication matrix;

[0139] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0140] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0141] In some embodiments of the present invention, the method further includes:

[0142] The data length of the data involved in the multiplication operation is determined based on the available circuit area of ​​the hardware circuit on the actual chip.

[0143] In some embodiments of the present invention, the method further includes:

[0144] The primitive polynomial is selected based on the circuit area to generate the primitive polynomial remainder circuit.

[0145] like Figure 4As shown, another aspect of the present invention provides a computer-readable storage medium 401 storing a computer program 402, which, when executed by a processor, implements a method for generating a finite field multiplication circuit, comprising:

[0146] Determine the data length of the data involved in the multiplication operation, and determine the primitive polynomial based on the data length;

[0147] The data is multiplied in a finite field to obtain a multiplication matrix table. An intermediate polynomial is generated based on the product terms in the multiplication matrix table. A data expander circuit is generated based on the product relationship of each term in the intermediate polynomial.

[0148] The primitive polynomial remainder circuit is generated based on the primitive polynomial and the intermediate polynomial, and the data expander circuit and the primitive polynomial remainder circuit are connected accordingly.

[0149] In some embodiments of the present invention, multiplying the data over a finite field to obtain a multiplication matrix table, and generating an intermediate polynomial based on the product terms in the multiplication matrix table includes:

[0150] The data is multiplied bitwise according to its length to obtain a multiplication matrix;

[0151] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0152] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0153] In some embodiments of the present invention, the method further includes:

[0154] The expander circuit is generated by connecting each term of the plurality of polynomials in sequence using an XOR gate logic.

[0155] In some embodiments of the present invention, the method for generating a primitive polynomial remainder circuit based on the primitive polynomial and the intermediate polynomial includes:

[0156] According to the principle of finite field computation, each term of the intermediate polynomial is divided by the primitive polynomial to perform a remainder operation, and each term of the polynomial after the remainder operation is passed through an XOR gate logic in sequence to generate the primitive polynomial remainder circuit.

[0157] In some embodiments of the present invention, multiplying the data in a finite field to obtain a multiplication matrix table includes:

[0158] The data are multiplied in reverse order to obtain a multiplication matrix;

[0159] The multiplication matrix is ​​added in a staggered manner according to the multiplication carry relationship to obtain multiple polynomials;

[0160] The multiple polynomials are combined into an intermediate polynomial, with each term of the intermediate polynomial being used as a separate term.

[0161] In some embodiments of the present invention, the method further includes:

[0162] The data length of the data involved in the multiplication operation is determined based on the available circuit area of ​​the hardware circuit on the actual chip.

[0163] In some embodiments of the present invention, the method further includes:

[0164] The primitive polynomial is selected based on the circuit area to generate the primitive polynomial remainder circuit.

[0165] This invention proposes a method for generating finite field multiplication circuits. By analyzing finite field multiplication operations and focusing on the concept of Galois field polynomials, this method implements a fast hardware solution for Galois field multiplication. Compared to the conventional lookup table method, each multiplication operation eliminates one lookup in the forward and reverse tables and the corresponding logical addition operation. Instead, the operation is expanded in hardware in one step, achieving a speed improvement despite some area loss. This invention supports different primitive polynomial configurations, and its principle can be extended to finite field operations with wider bit widths (GF(2^m)). No lookup table is required, and the operation requires no firmware support, reducing software development overhead.

[0166] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0167] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0168] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0169] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0170] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of the different aspects of the invention as described above exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method of generating a finite field multiplication circuit, characterized by, The method comprises the following steps: determining the data length of data participating in multiplication operation, and determining primitive polynomial according to the data length; multiplying the data in finite field to obtain multiplication matrix table, generating intermediate polynomial according to the product term in the multiplication matrix table, and generating data expander circuit according to the product relationship of each term in the intermediate polynomial; generating primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and connecting the data expander circuit and the primitive polynomial remainder circuit correspondingly; the multiplication of the data in finite field to obtain multiplication matrix table, generating intermediate polynomial according to the product term in the multiplication matrix table comprises: multiplying the data according to the data length to obtain multiplication matrix or multiplying the data in reverse order to obtain multiplication matrix; obtaining a plurality of polynomials by adding the multiplication matrix according to the multiplication carry relationship; combining the plurality of polynomials as each term of the intermediate polynomial to form the intermediate polynomial; generating the expander circuit by connecting each term of the plurality of polynomials in sequence through XOR gate logic; the generation of the primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial comprises: performing remainder operation by dividing each polynomial in the intermediate polynomial by the primitive polynomial according to the calculation principle of finite field, and generating the primitive polynomial remainder circuit by connecting each data in the polynomial after the remainder operation in sequence through XOR gate logic.

2. The method of claim 1, wherein, Further comprising: determining the data length of the data participating in multiplication operation according to the available circuit area of actual chip in hardware circuit.

3. The method of claim 1, wherein, Further comprising: selecting the primitive polynomial according to the circuit area to generate the primitive polynomial remainder circuit.

4. A system for generating a finite field multiplication circuit, the system comprising: The method comprises the following steps: initializing data module, which is configured to determine the data length of data participating in multiplication operation, and determine the length of primitive polynomial and the primitive polynomial according to the data length; data expander circuit generation module, which is configured to multiply the data in finite field to obtain multiplication matrix table, generate intermediate polynomial according to the product term in the multiplication matrix table, and generate data expander circuit according to the product relationship of each term in the intermediate polynomial; remainder circuit generation module, which is configured to generate primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and connect the data expander circuit and the primitive polynomial remainder circuit correspondingly; the data expander circuit generation module is further configured to: multiply the data according to the data length to obtain multiplication matrix or multiply the data in reverse order to obtain multiplication matrix; obtain a plurality of polynomials by adding the multiplication matrix according to the multiplication carry relationship; combine the plurality of polynomials as each term of the intermediate polynomial to form the intermediate polynomial; generate the expander circuit by connecting each term of the plurality of polynomials in sequence through XOR gate logic; the remainder circuit generation module is further configured to: According to the finite field calculation principle, each of the intermediate polynomials is divided by the primitive polynomial to perform a remainder operation, and each of the data in the polynomials after the remainder operation is sequentially passed through an XOR gate logic to generate a primitive polynomial remainder circuit.

5. A computer device, characterized by Comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions, when executed by the processor, implementing the steps of the method of any one of claims 1-3.

6. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 5. The computer program, when executed by the processor, implements the steps of the method of any one of claims 1-3.

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