Control circuit of a memory device

Abstract

This disclosure relates to control circuitry for memory devices. One circuit includes: a first inverter, a second inverter, a first header circuit, and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal sent to a two's complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal sent to a bit line. The first header circuit connects or disconnects a power supply terminal of the first inverter from a positive reference voltage source in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power supply terminal of the second inverter from the positive reference voltage source in response to a write enable signal and the first global write signal.

Description

Technical Field

[0001] This disclosure relates to control circuits for memory devices. Background Technology

[0002] Electronic devices and electronics-based systems require some form of high-speed memory device to store and retrieve information. Random access memory (RAM) is a commonly used memory in integrated circuits. Embedded RAM is particularly popular in high-speed communications, image processing, and system-on-a-chip (SoC) applications. RAM consists of an array of individual memory cells. Users can perform read and write operations on the memory cells of RAM. A typical example of RAM is dynamic random access memory (DRAM), as is well known in the art. Summary of the Invention

[0003] According to one embodiment of this disclosure, a circuit for controlling a memory device is provided, comprising: a first inverter configured to convert a first global write signal into a first local write signal sent to a two's complement bit line; a second inverter configured to convert a second global write signal into a second local write signal sent to a bit line; a first header circuit configured to connect or disconnect a power supply terminal of the first inverter from a positive reference voltage source in response to a write enable signal and the second global write signal; and a second header circuit configured to connect or disconnect a power supply terminal of the second inverter from the positive reference voltage source in response to the write enable signal and the first global write signal.

[0004] According to another embodiment of this disclosure, a circuit for controlling a memory device is provided, comprising: a first inverter configured to convert a first global write signal into a first local write signal; a second inverter configured to convert a second global write signal into a second local write signal; a selection circuit coupled to the first inverter and the second inverter, and the selection circuit being configured to send the first local write signal to a two's complement bit line and send the second local write signal to the bit line in response to a selection signal; and a decoder circuit coupled to the first inverter, the second inverter, and the selection circuit, and the decoder circuit being configured to generate the selection signal and the decoder circuit being configured to pull down the voltage level of the selection signal in response to the first local write signal and the second local write signal.

[0005] According to another embodiment of this disclosure, a method for controlling a memory device is provided, comprising: converting a first global write signal into a first local write signal sent to a two's complement bit line via a first inverter; converting a second global write signal into a second local write signal sent to a bit line via a second inverter; and in a bit write mask mode, disconnecting the power supply terminal of the first inverter from a positive reference voltage source, and disconnecting the power supply terminal of the second inverter from the positive reference voltage source. Attached Figure Description

[0006] When with attachment Figure 1 When reading this document, the following detailed description will best help you understand all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic diagram illustrating a memory device according to various embodiments of the present disclosure.

[0008] Figure 2 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the main I / O circuit.

[0009] Figure 3 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the local I / O circuitry.

[0010] Figure 4 This illustrates various embodiments according to the present disclosure. Figure 3 A schematic diagram of the inverter and header circuit in the local I / O circuit.

[0011] Figure 5 This illustrates various embodiments according to the present disclosure. Figure 1 The signal waveform of the relevant signal generated in the memory device.

[0012] Figure 6 This is a flowchart illustrating various embodiments of a control method according to the present disclosure.

[0013] Figure 7 This is a schematic diagram illustrating another memory device according to various embodiments of the present disclosure.

[0014] Figure 8 This illustrates various embodiments according to the present disclosure. Figure 7 A schematic diagram of the local I / O circuitry.

[0015] Figure 9 This illustrates various embodiments according to the present disclosure. Figure 7The signal waveform of the relevant signal generated in the memory device. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of the invention or any exemplary terminology. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0018] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more related list items.

[0019] As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” etc., should be understood as open-ended, meaning including but not limited to.

[0020] References to "one embodiment," "embodiment," or "some embodiments" in this specification indicate that a particular feature, structure, implementation, or characteristic described in connection with one or more embodiments is included in at least one embodiment of this disclosure. Therefore, the use of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places in the specification does not necessarily refer to the same embodiment. Furthermore, particular features, structures, implementations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Figure 1This is a schematic diagram illustrating a memory device 100 according to various embodiments of the present disclosure. In some embodiments, the memory device 100 is used to write digital data into bit cells BC11 to BCn3 in a memory array CA1. This digital data can be stored in bit cells BC11 to BCn3 and can be read or accessed by the memory device 100 from bit cells BC11 to BCn3 in the memory array CA1.

[0022] like Figure 1 As shown, in some embodiments, the memory array CA1 may include a plurality of bit cells BC11 to BCn3 arranged along n columns and 3 rows. For illustrative purposes, in Figure 1 The diagram shows three rows, but this disclosure is not limited to these. Bit cells in the same column are connected to the same bit line and the same complement bit line. For example, bit cells BC11, BC12, and BC13 in the same column are connected to bit line BL1 and complement bit line BLB1; bit cells BCn1, BCn2, and BCn3 in the same column are connected to bit line BLm and complement bit line BLBm. Bit cells in the same row are connected to the same word line. For example, bit cells BC11 and BCn1 in the same row are connected to word line WL1; bit cells BC12 and BCn2 in the same row are connected to word line WL2; bit cells BC13 and BCn3 in the same row are connected to word line WL3.

[0023] like Figure 1 As shown, the memory device 100 includes a main input / output (I / O) circuit 120 and a local I / O circuit 140. In some embodiments, the main I / O circuit 120 is configured to generate a global write signal GW1 and another global write signal GW2 based on write data WD, a bit write mask signal BWEB, and a clock signal CKD.

[0024] like Figure 1 As shown, the local I / O circuit 140 includes a write driver 142 and a selection circuit 144. The write driver 142 of the local I / O circuit 140 is configured to generate a local write signal LW1 based on a global write signal GW1, and to generate another local write signal LW2 based on a global write signal GW2. The selection circuit 144 is configured to select a target column from the memory array CA1, send the local write signal LW1 to the two's complement bit lines (BLB1 to BLBn), and send the local write signal LW2 to the bit lines (BL1 to BLn) on the target column.

[0025] For example, in the normal write mode of memory device 100, when the write data is to be written to a logic "0" in bit cell BC11, in some embodiments, the main I / O circuit 120 may generate a low-level "L" global write signal GW1 and a high-level "H" global write signal GW2. Therefore, the write driver 142 generates a high-level local write signal LW1 (in response to the global write signal GW1) and a low-level local write signal LW2 (in response to the global write signal GW2). Since the write data is to be written to a logic "0" in bit cell BC11, the select signal YSEL1 is set to the "H" level, and other select signals (e.g., select signal YSELn) are set to the "L" level. Selection circuit 144 turns on NMOS transistor N1 via the "H" level selection signal YSEL1 to send the local write signal LW1 to the two's complement bit line BLB1, and turns on NMOS transistor N2 via the "H" level selection signal YSEL1 to send the local write signal LW2 to bit line BL1. Simultaneously, NMOS transistors N3 and N4 are turned off via the "L" level selection signal YSELn. In this state, word line WL1 is activated, and word lines WL2 to WL3 are deactivated; bit cell BC11 is written according to bit line BL1 at "L" level and two's complement bit line BLB1 at "H" level.

[0026] On the other hand, in the normal write mode of the memory device 100, when the write data is to be a logic "1" in bit cell BC11, in some embodiments, the main I / O circuit 120 can generate global write signals GW1 and GW2 at H / L levels. Therefore, the write driver 142 generates local write signals LW1 and LW2 at L / H levels. The selection circuit 144 sends the local write signal LW1 to the two's complement bit line BLB1 and sends the local write signal LW2 to the bit line BL1. In this case, word line WL1 is activated and word lines WL2 to WL3 are deactivated; bit cell BC1 is written according to bit line BL1 being "H" and two's complement bit line BLB1 being "L".

[0027] As discussed in the normal write mode described above, data can be written to a target bit cell in the memory device 100. When the memory device 100 tends to write one bit of data to a target bit cell, it is necessary to mask other bit cells surrounding the target bit cell from these write signals; otherwise, some write signals may affect these non-target bit cells. In some embodiments, the memory device 100 provides a bit-by-bit write mask function that can protect the data stored in bit cells BC11 to BCn3. Further details on how the bit-by-bit write mask is implemented will be discussed in the following paragraphs.

[0028] Further reference Figure 2 , Figure 3 , Figure 4 and Figure 5 . Figure 2 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the main I / O circuit 120. Figure 3 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the local I / O circuit 140 in the diagram. Figure 4 This illustrates various embodiments according to the present disclosure. Figure 3 A schematic diagram of the inverter INV1 and the header circuit 142a in the local I / O circuit 140. Figure 5 This illustrates various embodiments according to the present disclosure. Figure 1 The signal waveform of the relevant signal generated in the memory device 100. Relative to Figure 1 For the purposes of this embodiment, in order to facilitate understanding, Figure 2 , Figure 3 , Figure 4 and Figure 5 The same elements in the same figure are assigned the same reference numerals.

[0029] like Figure 2 As shown, in some embodiments, the main I / O circuit 120 includes two latches 121 and 122, two inverters 123 and 124, and two AND gates 125 and 126. Latch 121 receives write data WD and is triggered by clock CKD. Latch 122 receives a bit write mask signal BWEB and is triggered by clock CKD. AND gate 125 generates a global write signal GW1 based on the latch write data WDT, the inverted bit write mask signal BXEB, and clock CKD. AND gate 126 generates a global write signal GW2 based on the inverted latched write data WDTB, the inverted bit write mask signal BXEB, and clock CKD.

[0030] like Figure 3 As shown, the write driver 142 in the local I / O circuit 140 includes an inverter INV1, another inverter INV2, header circuitry 142a, and another header circuitry 142b. Inverter INV1 is configured to convert the global write signal GW1 into a local write signal LW1. Inverter INV2 is configured to convert the global write signal GW2 into a local write signal LW2.

[0031] In such Figure 3In some embodiments shown, header circuitry 142a is coupled between the power supply terminal of inverter INV1 and the positive reference voltage source VDD. Header circuitry 142a is configured to connect or disconnect the power supply terminal of inverter INV1 from the positive reference voltage source VDD in response to a write enable signal WE and a global write signal GW2 (after inversion via inverter INV3). Figure 3 As shown, the head circuit 142a includes two PMOS transistors, P1 and P2. Transistor P1 is coupled between the positive reference voltage source VDD and the power supply terminal of inverter INV1. The gate terminal of PMOS transistor P1 is controlled by a global write signal GW2 after being inverted by inverter INV3. PMOS transistor P2 is coupled between the positive reference voltage source VDD and the power supply terminal of inverter INV1, and is connected in parallel with PMOS transistor P1. The gate terminal of PMOS transistor P2 is controlled by a write enable signal WE.

[0032] In such Figure 3 In some embodiments shown, header circuitry 142b is coupled between the power supply terminal of inverter INV1 and the positive reference voltage source VDD. Header circuitry 142b is configured to connect or disconnect the power supply terminal of inverter INV2 from the positive reference voltage source VDD in response to a write enable signal WE and a global write signal GW1 (after inversion via inverter INV4). Figure 3 As shown, the head circuit 142b also includes two PMOS transistors, P3 and P4. Transistor P3 is coupled between the positive reference voltage source VDD and the power supply terminal of inverter INV2. The gate terminal of PMOS transistor P3 is controlled by the global write signal GW1 after being inverted by inverter INV4. PMOS transistor P4 is coupled between the positive reference voltage source VDD and the power supply terminal of inverter INV2, and is connected in parallel with PMOS transistor P3. The gate terminal of PMOS transistor P4 is controlled by the write enable signal WE.

[0033] As an example, in the normal write mode of memory device 100, reference Figure 5 During the time period M1a shown, the write data WD "1" is written to bit cell BC11. In this example, the bit write mask signal is set to "L" level; the reverse bit write mask signal BXEB is set to "H" level; the latched write data WDT is set to "H" level (based on the write data WD "1"); and the reverse latched write data WDTB is set to "L" level (based on the write data WD "1"). When the clock pulse CKD arrives, the global write signal GW1 is activated. Figure 2 The AND gate 125 in the code is set to "H" level (because WDT = H, BXEB = H and CKD = H), as shown below. Figure 5The time period M1a is shown, and the global write signal GW2 passes through... Figure 2 AND gate 126 in the code is set to "L" level (because WDTB = L), as shown below. Figure 5 The time period M1a is shown.

[0034] In normal write mode (where WD = "1", GW1 = H and GW2 = L), refer to Figure 5 During the time period M1a shown, the write enable signal WE is set to the "H" level, thereby turning off PMOS transistors P2 and P4. PMOS transistor P1 is also turned off by the global write signal GW2, which is inverted by inverter INV3. PMOS transistor P3 is turned on by the global write signal GW1, which is inverted by inverter INV4. Since PMOS transistors P1 and P2 in the header circuit 142a are turned off, the header circuit 142a disconnects inverter INV1 from the positive reference voltage source VDD. (Refer to...) Figure 4 , Figure 4 The inverter INV1 shown is a CMOS inverter structure formed by PMOS transistor P5 and NMOS transistor N5. Figure 4 The inverter INV1 formed in the illustrated CMOS inverter structure is shown as an illustrative example. Inverters INV1 and INV2 can be formed by any equivalent inverter structure. In this case (where WD = "1", GW1 = H and GW2 = L), the power supply terminal of inverter INV1 is disconnected from the positive reference voltage source VDD, and the global write signal GW1 turns on the NMOS transistor N5 in inverter INV1, thereby pulling the local write signal LW1 low to ground level, as shown. Figure 5 The time period M1a is shown. Simultaneously, the head circuit 142b connects the inverter INV2 to the positive reference voltage source VDD, causing the inverter INV2 to convert the global write signal GW2 (GW2 = L) into a local write signal LW2 (LW2 = H), as shown. Figure 5 The time period M1a is shown. In this case, in response to the normal write mode with WD = "1", the local write signal LW1 for the two's complement bit line BLB1 is set to the "L" level, and the local write signal LW2 for the bit line BL1 is set to the "H" level, as shown. Figure 5 The time period M1a is shown.

[0035] On the other hand, as an example, in the normal write mode of memory device 100, reference Figure 5During the time period M1b shown, the data WD "0" will be written to bit cell BC11. When the clock pulse CKD arrives, the global write signal GW1 is set to "L" level via AND gate 125 (because WDT = L), as shown. Figure 5 As shown in the time period M1b, the global write signal GW2 is set to "H" level via AND gate 126 (because WDTB=H, BXEB=H and CKD=H), as... Figure 5 The time period M1b is shown.

[0036] In normal write mode (where WD = "0", GW1 = L and GW2 = H), refer to Figure 5 During the time period M1b shown, the write enable signal WE is set to "H" level, thereby turning off PMOS transistors P2 and P4. PMOS transistor P3 is turned off by the global write signal GW1, which is inverted by inverter INV4. PMOS transistor P1 is turned on by the global write signal GW2, which is inverted by inverter INV3. Header circuit 142b disconnects inverter INV2 from the positive reference voltage source VDD. The local write signal LW2 can be pulled low (reference) by the internal transistor (not shown) in inverter INV2. Figure 4 The inverter INV1 in the circuit uses NMOS N5. Simultaneously, the header circuit 142a connects the inverter INV1 to the positive reference voltage source VDD, causing the inverter INV1 to convert the global write signal GW1 (GW1 = L) into a local write signal LW1 (LW1 = H), as shown below. Figure 5 The time period M1b is shown.

[0037] In the bit write mask mode of memory device 100, refer to Figure 5 During the time period M2 shown, the bit write mask signal BWEB is set to "H" level, and the reverse bit write mask signal BXEB is fixed to "L" level. Therefore, regardless of the written data WD, the global write signals GW1 and GW2 are set to "L" level, as shown. Figure 5 The time period M2 is shown. During time period M2, the write enable signal WE is set to the "H" level, thereby turning off PMOS transistors P2 and P4. PMOS transistor P1 is turned off by the global write signal GW2, which is inverted by inverter INV3. PMOS transistor P3 is turned off by the global write signal GW1, which is inverted by inverter INV4. In the bit write mask mode of memory device 100, header circuit 142a disconnects the power supply terminal of inverter INV1 from the positive reference voltage source VDD, and header circuit 142b disconnects the power supply terminal of inverter INV2 from the positive reference voltage source VDD. Further reference Figure 4 The global write signal GW1 turns off the NMOS transistor N5 in the inverter INV1. In this case, the inverter INV1 is disconnected from the positive reference voltage source VDD, and the local write signal LW1 is configured to either a floating state or a high-impedance state (Hi-Z), as shown below. Figure 5 The time period M2 is shown. Similarly, the local write signal LW2 is configured to a floating state or a high-impedance state (Hi-Z) because the inverter INV2 is also disconnected from the positive reference voltage source VDD.

[0038] Based on the above embodiments, in the bit write mask mode of the memory device 100, the main I / O circuit 120 sets both global write signals GW1 and GW2 to the "L" level, and the write driver 142 correspondingly sets both local write signals LW1 and LW2 to a floating state or a high-impedance state (Hi-Z). When the local write signals LW1 and LW2 are sent to a two's complement bit line BLB1 and a bit line BL1 via the selection circuit 144, the local write signals LW1 and LW2 in the floating state or high-impedance state (Hi-Z) will not overwrite or change the bit data stored in a bit cell (e.g., bit cell BC11) connected to the two's complement bit line BLB1 and the bit line BL1, enabling the memory device 100 to provide a bit write mask function for protecting the data in the bit cell. Using the bit write mask function, the bit data stored in the bit cells of the memory device 100 is more stable and reliable.

[0039] In read mode or standby mode of memory device 100, the clock signal CKD is fixed at "L". Therefore, regardless of the write data WD and the bit write mask signal BWEB, both global write signals GW1 and GW2 are set to "L" level, as shown below. Figure 5 The time period M3 is shown.

[0040] In read mode or standby mode of memory device 100, refer to Figure 5During the time period M3 shown, the write enable signal WE is set to the "L" level because the memory device 100 is not currently performing write-related operations. The PMOS transistors P2 and P4 are turned on by the write enable signal WE (WE = L). Header circuit 142a connects the power supply terminal of inverter INV1 to the positive reference voltage source VDD, and header circuit 142b connects the power supply terminal of inverter INV2 to the positive reference voltage source VDD. In this case, inverter INV1 is activated to convert the global write signal GW1 (GW1 = L) to the local write signal LW1 (LW1 = H), and inverter INV2 is activated to convert the global write signal GW2 (GW2 = L) to the local write signal LW2 (LW2 = H). During the read mode or standby mode of the memory device 100, as... Figure 5 As shown in time period M3, the write driver 142 is able to clamp the voltage levels of local write signals LW1 and LW2 to "H" level. Because the voltage levels of local write signals LW1 and LW2 are clamped to "H" level, no additional switching power is consumed during the read mode or standby mode of the memory device 100.

[0041] Please note, Figure 2 In the embodiments described above, the main I / O circuit 120 generates global write signals GW1 and GW2 based on the same clock signal CKD. In other words, the global write signals GW1 and GW2 are in the same time domain associated with the clock signal CKD. In some embodiments, the write enable signal WE is also in the same time domain associated with the clock signal CKD. In the time domain associated with the clock signal CKD, the local I / O circuit 140 switches between the normal write mode, bit write mask mode, read mode, or standby mode as described above, based on the global write signals GW1 / GW2 and the write enable signal WE.

[0042] In some other examples, the bit write mask function is performed based on another control signal from another time domain (e.g., the bit line equalization signal BLEQB), and signal race problems may occur between the control signal in the local time domain (e.g., the global write signal GW1 or GW2) and the control signal from another time domain (e.g., BLEQB). Compared to these examples of control signals from other time domains, referencing the global write signals GW1 / GW2 and the write enable signal WE in the local time domain for the main I / O circuit 120 and local I / O circuit 140 can avoid signal race problems and also avoid transient open-circuit currents caused by signal race problems.

[0043] Further reference Figure 6 . Figure 6This is a flowchart illustrating a control method 200 according to various embodiments of the present disclosure. In some embodiments, Figure 6 The control method 200 in the middle can be used in, for example Figures 1 to 5 The memory device 100 shown in the embodiment is used. Figure 6 As shown, operation S210 is performed to determine the operating mode of memory device 100.

[0044] like Figure 1 , Figure 3 and Figure 6 As shown, when the memory device 100 operates in normal write mode, operation S220 is executed to connect one power supply terminal of inverter INV1 or INV2 to the positive reference voltage source VDD, and disconnect the other power supply terminal of inverter INV1 or INV2 from the positive reference voltage source VDD. (Refer to...) Figure 5 In the example shown for time period M1a or M1b, operation S221 is performed to convert the global write signal GW1 into a local write signal LW1 sent to one of the two's complement bit lines BLB1 to BLBn via inverter INV1. (Refer to the section on...) Figure 5 In the example shown for time period M1a or M1b, operation S222 is performed to convert the global write signal GW2 into a local write signal LW2 sent to one of the bit lines BL1 to BLn via inverter INV2.

[0045] like Figure 1 , Figure 3 and Figure 6 As shown, when the memory device 100 operates in bit write mask mode, operation S230 is executed to disconnect the power supply terminals of inverters INV1 and INV2 from the positive reference voltage source VDD. (Refer to...) Figure 5 In the example of time period M2 shown, operation S231 is performed to set the local write signal LW1 and the local write signal LW2 to a floating state or a Hi-Z state.

[0046] like Figure 1 , Figure 3 and Figure 6 As shown, when the memory device 100 operates in read mode or standby mode, operation S240 is executed to connect the power supply terminals of inverters INV1 and INV2 to the positive reference voltage source VDD. (Refer to...) Figure 5 In the embodiment of time period M3 shown, operation S241 is performed to convert the global write signal GW1 into a local write signal LW1 sent to one of the two's complement bit lines BLB1 to BLBn via inverter INV1. (Refer to the section on...) Figure 5In the embodiment of time period M3 shown, operation S242 is performed to convert the global write signal GW2 into a local write signal LW2 sent to one of the bit lines BL1 to BLn via inverter INV2.

[0047] In the above embodiments, the bit write mask mode in the memory device 100 is implemented by a header circuit 142a between an inverter INV1 and a positive reference voltage source VDD coupled in the write driver 142, and a header circuit 142b between an inverter INV2 and a positive reference voltage source coupled in the write driver 142.

[0048] In some other embodiments, this disclosure is not limited to implementing the header circuitry in the inverters INV1 / INV2 in the write driver 142, but similar header circuitry can be implemented in the decoder for controlling the selection circuitry 144 to enable operating modes including normal write mode, bit write mask mode, and read / standby mode.

[0049] Figure 7 This is a schematic diagram illustrating another memory device 300 according to various embodiments of the present disclosure. In some embodiments, the memory device 300 is used to write digital data into bit cells BC11 to BCn3 in a memory array CA1. This digital data can be stored in bit cells BC11 to BCn3 and can be read or accessed by the memory device 300 from bit cells BC11 to BCn3 in the memory array CA1.

[0050] like Figure 7 As shown, in some embodiments, the memory array CA1 may include a plurality of bit cells BC11 to BCn3 arranged along n columns and 3 rows. Bit cells in the same column are connected to the same bit line and the same complement bit line. For example, bit cells BC11, BC12, and BC13 in the same column are connected to bit line BL1 and complement bit line BLB1; bit cells BCn1, BCn2, and BCn3 in the same column are connected to bit line BLm and complement bit line BLBm. Bit cells in the same row are connected to the same word line. For example, bit cells BC11 and BCn1 in the same row are connected to word line WL1. For illustrative purposes, a diagram is shown. Figure 7 The illustrated embodiment shows bit cells BC11–BCn3 arranged along n columns and 3 rows. In some other embodiments, the memory array CA1 may include different configurations, such as different numbers of columns and rows. Other configurations of the columns and rows of bit cells are within the scope of this disclosure.

[0051] like Figure 7As shown, the memory device 300 includes a main input / output (I / O) circuit 320 and a local I / O circuit 340. In some embodiments, the main I / O circuit 320 is configured to generate a global write signal GW1 and another global write signal GW2 based on write data WD, a bit write mask signal BWEB, and a clock signal CKD. Figure 7 The main I / O circuit 320 in the middle behaves and functions similarly to Figure 1 and Figure 2 The main I / O circuit 120 in the above embodiment is shown. (See reference...) Figure 1 and Figure 2 The details of how the main I / O circuit 320 generates global write signal GW1 and another global write signal GW2 based on the write data WD, the bit write mask signal BWEB and the clock signal CKD in the above embodiment are understood by referring to the main I / O circuit 120, and will not be repeated here.

[0052] like Figure 7 As shown, the local I / O circuit 340 includes a write driver 342, a selection circuit 344, and a decoder 346.

[0053] In some embodiments, the write driver 342 of the local I / O circuit 340 is configured to generate a local write signal LW1 based on a global write signal GW1, and to generate another local write signal LW2 based on a global write signal GW2. The selection circuit 344 is configured to select a target column from the memory array CA1, send the local write signal LW1 to the two's complement bit lines (BLB1 to BLBn), and send the local write signal LW2 to the bit lines (BL1 to BLn) on the target column. The selection circuit 344 is controlled by selection signals YSEL1 to YSELn from the decoder 346.

[0054] In some embodiments, the decoder 346 is configured to generate selection signals YSEL1 to YSELn based on the decoding signal YDEC[n-1:0], the local write signal LW1, and the local write signal LW2.

[0055] For example, the decoded signal YDEC[n-1:0] can be an N-bit signal. Decoder 346 can generate a selection signal YSEL1 based on a single bit from the decoded signal YDEC[n-1:0]. For example, decoder 346 can generate the selection signal YSEL1 by referring to the least significant bit (LSB) of the N-bit decoded signal YDEC[n-1:0], and decoder 346 can generate the selection signal YSELn by referring to the most significant bit (MSB) of the N-bit decoded signal YDEC[N-1:0]. In some embodiments, the generation of selection signals YSEL1 to YSELn by decoder 346 is also influenced by the voltage levels of local write signals LW1 and LW2.

[0056] Figure 8 This illustrates various embodiments according to the present disclosure. Figure 7 A schematic diagram of the local I / O circuit 340 in the diagram. Figure 9 This illustrates various embodiments according to the present disclosure. Figure 7 The signal waveform of the relevant signal generated in the memory device 300. Relative to... Figure 7 For the purposes of this embodiment, in order to facilitate understanding, Figure 8 and Figure 9 The same elements in the same figure are assigned the same reference numerals.

[0057] like Figure 8 As shown, the write driver 342 in the local I / O circuit 140 includes an inverter INV1 and another inverter INV2. Inverter INV1 is configured to convert the global write signal GW1 into a local write signal LW1. Inverter INV2 is configured to convert the global write signal GW2 into a local write signal LW2. Figure 8 As shown, the selection circuit 344 includes NMOS transistor N3 and NMOS transistor N4.

[0058] Note that, for the sake of brevity, Figure 8 The selection circuit 344 shown only illustrates NMOS transistor N3 for sending the local write signal LW1 to the two's complement bit line BLB1, and NMOS transistor N4 for sending the local write signal LW2 to the bit line BL1. However, the selection circuit 344 includes additional NMOS transistors for sending the local write signal LW1 to different two's complement bit lines (e.g., BLBn) in the memory array CA1, and additional NMOS transistors for sending the local write signal LW2 to different bit lines (e.g., BLn) in the memory array CA1. The structure of the selection circuit 344 is known to those skilled in the art. For simplicity and clarity, in... Figure 8 The diagram shows a partial structure of the selection circuit 344 relative to bit line BL1 and complement bit line BLB1. For the same reason, Figure 8 The decoder 346 shown is only a partial structure for generating a selection signal YSEL1 in the selection circuit 344 related to NMOS transistors N3 and N4 (for BL1, BLB1). In some embodiments, the decoder 346 includes, as shown in the diagram... Figure 8 The diagram shows a repeating structure for generating other selection signals (e.g., YSELn) for selection circuit 344.

[0059] like Figure 8As shown, in some embodiments, decoder 346 generates selection signal YSEL1 based on local write signal LW1, local write signal LW2, and one-bit decoding signal YDEC[0]. In some embodiments, the one-bit decoding signal YDEC[0] is the least significant bit from N-bit decoding signal YDEC[N-1:0].

[0060] like Figure 8 As shown, the decoder circuit includes an inverter INV3, another inverter INV4, a header circuit 346a, and a pull-down circuit 346b. Inverter INV4 receives a single-bit decoded signal YDEC[0]. The input of inverter INV3 is coupled to the output of inverter INV4. In some embodiments, the header circuit 346a connects or disconnects the power supply terminal of inverter INV3 from the positive reference voltage source VDD in response to local write signals LW1 and LW2. Figure 8 In some illustrative embodiments, the head circuit 346a includes a PMOS transistor P1 and another PMOS transistor P2. PMOS transistor P1 is coupled between the positive reference voltage source VDD and the power supply terminal of the inverter INV3. The gate terminal of PMOS transistor P1 is controlled by a local write signal LW1. PMOS transistor P2 is coupled between the positive reference voltage supply VDD and the power supply terminal of the inverter INV3. PMOS transistor P2 is connected in parallel with transistor P3.

[0061] In some embodiments, a pull-down circuit 346b is coupled between the output terminal of the decoder circuit 346 and the ground terminal. The output terminal of the decoder circuit 346 is connected to a selection circuit 344 to provide a selection signal YSEL1 to the selection circuit 344. The pull-down circuit 346b is configured to pull down the voltage level of the selection signal YSEL1 in response to local write signals LW1 and LW2. Figure 8 In some illustrative embodiments, pull-down circuit 346b includes NMOS transistor N1 and another NMOS transistor N2. NMOS transistor N1 is coupled between the output terminal and ground terminal of decoder circuit 346. The gate terminal of NMOS transistor N1 is controlled by a local write signal LW1. NMOS transistor N2 is also coupled between the output terminal and ground terminal of decoder circuit 346. NMOS transistor N2 is cascaded with NMOS transistor N1 between the output terminal and ground terminal of decoder circuit 346. The gate terminal of NMOS transistor N2 is controlled by a local write signal LW2.

[0062] To illustrate, in the normal write mode of memory device 300, when the data to be written is a logic "1" to be written to bit cell BC11 (one-bit decoding signal YDEC[0] = 1), refer to Figure 9During the time period M1 shown, the main I / O circuit 320 references WD=1, BWEB=0, and CKD=1, sets the global write signal GW1 to "H" level and the global write signal GW2 to "L" level. (Refer to...) Figure 1 and Figure 2 To understand the details of the main I / O circuit 320, the above-described main I / O circuit 120 is discussed in the embodiments described above. In this case, inverter INV1 converts the global write signal GW1 into a local write signal LW1 at the "L" level, and inverter INV2 converts the global write signal GW2 into a local write signal LW2 at the "H" level. Since the local write signal LW1 is at the "L" level, the NMOS transistor N1 in the pull-down circuit 346b is turned off, so that the pull-down circuit 346b does not pull down the voltage level of the select signal YSEL1. At the same time, since the local write signal LW1 is at the "L" level, the PMOS transistor P1 in the header circuit 346a is turned on, so that the header circuit 346a connects the power supply terminal of inverter INV3 to the positive reference voltage source VDD. In this case, inverters INV4 and INV3 operate normally to generate the select signal YSEL1 at the "H" level according to the one-bit decoded signal YDEC[0]. In this case, as Figure 9 In the normal write mode shown in time period M1, the transistors N3 and N4 in the selection circuit 344 are turned on by the selection signal YSEL1 at the "H" level, so that the local write signal LW1 at the "L" level is sent to the two's complement bit line BLB1 and the local write signal LW2 at the "H" level is sent to the bit line BL1.

[0063] Similarly, when the data to be written is logic "0" in bit cell BC11 (one-bit decoding signal YDEC[0] = 1), the local write signals LW1 and LW2 (with opposite levels) Figure 9 (Not shown in the image) and the selection signal YSEL1 will also be set to "H" level to complete the normal write mode function.

[0064] In the bit write mask mode of memory device 300, reference Figure 9 During the time period M2 shown, regardless of the written data WD, the bit write mask signal BWEB will be set to "H" level, and both global write signals GW1 and GW2 will be set to "L" level by the main I / O circuit 320, as shown. Figure 5The time period M2 is shown. In this case, inverter INV1 converts the global write signal GW1 into a local write signal LW1 at the "H" level, and inverter INV2 converts the global write signal GW2 into a local write signal LW2 at the "H" level. Since both local write signals LW1 and LW2 are at the "H" level, NMOS transistors N1 and N2 in pull-down circuit 346b are turned on to pull down the voltage level of the select signal YSEL1. At the same time, since both local write signals LW1 and LW2 are at the "H" level, PMOS transistors P1 and P2 in header circuit 346a are turned off, thereby disconnecting the power supply terminal of inverter INV3 from the positive reference voltage source VDD. In this case, as shown in Figure 9 In the bit write mask mode shown in the time period M2, the selection signal YSEL1 is fixed to ground level, and the transistors N3 and N4 in the selection circuit 344 are turned off by the selection signal YSEL1 at the "L" level, so that the local write signal LW1 will not be sent to the complement bit line BLB1, and the local write signal LW2 will not be sent to the bit line BL1.

[0065] Based on the above embodiments, in the bit write mask mode of the memory device 300, the voltage levels of the two's complement bit line BLB1 and bit line BL1 are set to a floating state or a high-impedance state (Hi-Z). When the two's complement bit line BLB1 and bit line BL1 are in the floating state or high-impedance state (Hi-Z), they will not overwrite or change the bit data stored in a bit cell (e.g., bit cell BC11), enabling the memory device 300 to provide a bit write mask function for protecting the data in the bit cell. Using the bit write mask function, the bit data stored in the bit cells of the memory device 300 will be more stable and reliable.

[0066] In read mode or standby mode of memory device 300, the clock signal CKD will be fixed at "L". Therefore, regardless of the write data WD and the bit write mask signal BWEB, both global write signals GW1 and GW2 will be set to "L" level, as shown below. Figure 9As shown in the time period M3. In this case, inverter INV1 converts the global write signal GW1 into a local write signal LW1 at the "H" level, and inverter INV2 converts the global write signal GW2 into a local write signal LW2 at the "H" level. Since both local write signals LW1 and LW2 are at the "H" level, NMOS transistors N1 and N2 in pull-down circuit 346b are turned on to pull down the voltage level of the select signal YSEL1. At the same time, since both local write signals LW1 and LW2 are at the "H" level, PMOS transistors P1 and P2 in header circuit 346a are turned off, thereby disconnecting the power supply terminal of inverter INV3 from the positive reference voltage source VDD. In this case, as shown in Figure 9 During the time period M3 shown, in the read mode or standby mode, the selection signal YSEL1 is fixed to ground level, and the transistors N3 and N4 in the selection circuit 344 are turned off by the selection signal YSEL1 at the "L" level, so that the local write signal LW1 will not be sent to the two's complement bit line BLB1, and the local write signal LW2 will not be sent to the bit line BL1.

[0067] Based on the above embodiments, the decoder 346 is a data-aware decoder that generates selection signals YSEL1 to YSELn by referring to the local write signal LW1 and local write signal LW2 related to the written data WD.

[0068] Similar to the above embodiment regarding memory device 100, note that the main I / O circuit 320 and local I / O circuit 340 of memory device 300 generate global write signals GW1 / GW2, local write signals LW1 / LW2, and selection signals YSEL1 to YSELn based on the same clock signal CKD. Based on the signals in the time domain related to the clock signal CKD, the main I / O circuit 320 and local I / O circuit 340 switch between the normal write mode, bit write mask mode, read mode, or standby mode as described in the above embodiment.

[0069] In some other examples, the bit write mask function is performed based on another control signal from another time domain (e.g., the bit line equalization signal BLEQB), and signal race problems may occur between the control signal in the local time domain (e.g., the global write signal GW1 or GW2) and the control signal from another time domain (e.g., BLEQB). Compared to these examples of control signals from other time domains, the local I / O circuitry 340 of the memory device 300, which references the global write signals GW1 / GW2 in the local time domain, can avoid signal race problems and also avoid transient open-circuit currents caused by signal race problems.

[0070] In some embodiments, a circuit includes: a first inverter, a second inverter, a first header circuit, and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal sent to a two's complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal sent to a bit line. The first header circuit connects or disconnects the power supply terminal of the first inverter from a positive reference voltage source in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects the power supply terminal of the second inverter from the positive reference voltage source in response to a write enable signal and the first global write signal.

[0071] In some embodiments, the first header circuit includes a first transistor and a second transistor. The first transistor is coupled between the positive reference voltage source and the power supply terminal of the first inverter. The gate terminal of the first transistor is controlled by the inverted second global write signal. The second transistor is coupled between the positive reference voltage source and the power supply terminal of the first inverter and is connected in parallel with the first transistor. The gate terminal of the second transistor is controlled by the write enable signal. The second header circuit includes a third transistor and a fourth transistor. The third transistor is coupled between the positive reference voltage source and the power supply terminal of the second inverter. The gate terminal of the third transistor is controlled by the inverted first global write signal. The fourth transistor is coupled between the positive reference voltage source and the power supply terminal of the second inverter and is connected in parallel with the third transistor. The gate terminal of the fourth transistor is controlled by the write enable signal.

[0072] In some embodiments, in the bit write mask mode, the first transistor and the second transistor in the first header circuit are turned off, and the third transistor and the fourth transistor in the second header circuit are turned off.

[0073] In some embodiments, in the bit write mask mode, the first local write signal and the second local write signal are configured to be in a floating state or a high impedance state.

[0074] In some embodiments, in a normal write mode, one of the first transistor or the third transistor is turned on, and the other of the first transistor or the third transistor is turned off, while the second transistor and the fourth transistor are turned off.

[0075] In some embodiments, in read mode or standby mode, the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on.

[0076] In some embodiments, in a first mode, one of the first head circuit or the second head circuit is configured to connect one power supply terminal of the first inverter or the second inverter to the positive reference voltage source, and the other of the first head circuit or the second head circuit is configured to disconnect another power supply terminal of the first inverter or the second inverter from the positive reference voltage source. In a second mode, the first head circuit is configured to disconnect the power supply terminal of the first inverter from the positive reference voltage source, and the second head circuit is configured to disconnect the power supply terminal of the second inverter from the positive reference voltage source. In a third mode, the first head circuit is configured to connect the power supply terminal of the first inverter to the positive reference voltage source, and the second head circuit is configured to connect the power supply terminal of the second inverter to the positive reference voltage source.

[0077] In some embodiments, the first mode is a normal write mode, the second mode is a bit write mask mode, and the third mode is a read mode or a standby mode.

[0078] In some embodiments, the circuit further includes a main input / output circuit. The main input / output circuit is configured to generate the first global write signal and the second global write signal based on a reference clock signal. The first global write signal and the second global write signal are in the same time domain relative to the reference clock signal.

[0079] In some embodiments, a circuit includes a first inverter, a second inverter, a selection circuit, and a decoder circuit. The first inverter is configured to convert a first global write signal into a first local write signal. The second inverter is configured to convert a second global write signal into a second local write signal. The selection circuit is coupled to the first inverter and the second inverter. The selection circuit is configured to send the first local write signal to a two's complement bit line and send the second local write signal to a bit line in response to a selection signal. The decoder circuit is coupled to the first inverter, the second inverter, and the selection circuit. The decoder circuit is configured to generate the selection signal and is configured to pull down the voltage level of the selection signal in response to the first local write signal and the second local write signal.

[0080] In some embodiments, the decoder circuitry includes a pull-down circuit coupled between an output terminal and a ground terminal of the decoder circuitry. The pull-down circuitry is configured to pull down the voltage level of the select signal in response to a first local write signal and a second local write signal.

[0081] In some embodiments, the pull-low circuit includes a first transistor and a second transistor. The first transistor is coupled between the output terminal and the ground terminal of the decoder circuit. The gate terminal of the first transistor is controlled by a first local write signal. The second transistor is coupled between the output terminal and the ground terminal of the decoder circuit. The second transistor is connected in series with the first transistor. The gate terminal of the second transistor is controlled by a second local write signal.

[0082] In some embodiments, in bit write mask mode, the first transistor and the second transistor are configured to be turned on to pull the voltage level of the selection signal low to the ground terminal.

[0083] In some embodiments, the decoder circuitry includes a third inverter and a header circuitry. The third inverter is configured to generate a selection signal in response to a decoded bit signal. The header circuitry is configured to connect or disconnect the power supply terminal of the third inverter from a positive reference voltage source in response to a first local write signal and a second local write signal.

[0084] In some embodiments, the header circuitry includes a third transistor and a fourth transistor. The third transistor is coupled between the positive reference voltage source and the power supply terminal of the third inverter. The gate terminal of the third transistor is controlled by the first local write signal. The fourth transistor is coupled between the positive reference voltage source and the power supply terminal of the third inverter and is connected in parallel with the third transistor. The gate terminal of the fourth transistor is controlled by the second local write signal.

[0085] In some embodiments, in bit write mask mode, the third transistor and the fourth transistor are turned off to disconnect the power supply terminal of the third inverter from the positive reference voltage source.

[0086] In some embodiments, a method includes: converting a first global write signal into a first local write signal sent to a two's complement bit line via a first inverter; converting a second global write signal into a second local write signal sent to a bit line via a second inverter; and in a bit write mask mode, disconnecting the power supply terminal of the first inverter from a positive reference voltage source and disconnecting the power supply terminal of the second inverter from the positive reference voltage source.

[0087] In some embodiments, in the bit write mask mode, the first local write signal and the second local write signal are configured to be in a floating state or a high impedance state.

[0088] In some embodiments, the method further includes: in normal write mode, connecting one power supply terminal of the first inverter or the second inverter to the positive reference voltage source, and disconnecting the other power supply terminal of the first inverter or the second inverter from the positive reference voltage source.

[0089] In some embodiments, the method further includes: in a read mode or a standby mode, connecting the power supply terminal of the first inverter to the positive reference voltage source, and connecting the power supply terminal of the second inverter to the positive reference voltage source.

[0090] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

[0091] Example 1. A circuit for controlling a memory device, comprising: a first inverter configured to convert a first global write signal into a first local write signal sent to a two's complement bit line; a second inverter configured to convert a second global write signal into a second local write signal sent to a bit line; a first header circuit configured to connect or disconnect a power supply terminal of the first inverter from a positive reference voltage source in response to a write enable signal and the second global write signal; and a second header circuit configured to connect or disconnect a power supply terminal of the second inverter from the positive reference voltage source in response to the write enable signal and the first global write signal.

[0092] Example 2. The circuit according to Example 1, wherein the first header circuit includes: a first transistor coupled between the positive reference voltage source and the power supply terminal of the first inverter, the gate terminal of the first transistor being controlled by an inverted second global write signal; and a second transistor coupled between the positive reference voltage source and the power supply terminal of the first inverter and connected in parallel with the first transistor, the gate terminal of the second transistor being controlled by the write enable signal; wherein the second header circuit includes: a third transistor coupled between the positive reference voltage source and the power supply terminal of the second inverter, the gate terminal of the third transistor being controlled by an inverted first global write signal; and a fourth transistor coupled between the positive reference voltage source and the power supply terminal of the second inverter and connected in parallel with the third transistor, the gate terminal of the fourth transistor being controlled by the write enable signal.

[0093] Example 3. The circuit according to Example 2, wherein, in the bit write mask mode, the first transistor and the second transistor in the first header circuit are turned off, and the third transistor and the fourth transistor in the second header circuit are turned off.

[0094] Example 4. The circuit according to Example 3, wherein, in the bit write mask mode, the first local write signal and the second local write signal are configured to a floating state or a high impedance state.

[0095] Example 5. The circuit according to Example 2, wherein, in normal write mode, one of the first transistor or the third transistor is turned on, and the other of the first transistor or the third transistor is turned off, while the second transistor and the fourth transistor are turned off.

[0096] Example 6. The circuit according to Example 2, wherein the second transistor and the fourth transistor are turned on in read mode or standby mode.

[0097] Example 7. The circuit according to Example 1, wherein, in a first mode, one of the first head circuit or the second head circuit is configured to connect one power supply terminal of the first inverter or the second inverter to the positive reference voltage source, and the other of the first head circuit or the second head circuit is configured to disconnect the other power supply terminal of the first inverter or the second inverter from the positive reference voltage source; in a second mode, the first head circuit is configured to disconnect the power supply terminal of the first inverter from the positive reference voltage source, and the second head circuit is configured to disconnect the power supply terminal of the second inverter from the positive reference voltage source; and in a third mode, the first head circuit is configured to connect the power supply terminal of the first inverter to the positive reference voltage source, and the second head circuit is configured to connect the power supply terminal of the second inverter to the positive reference voltage source.

[0098] Example 8. The circuit according to Example 7, wherein the first mode is a normal write mode, the second mode is a bit write mask mode, and the third mode is a read mode or a standby mode.

[0099] Example 9. The circuit according to Example 1 further includes: a main input / output circuit configured to generate the first global write signal and the second global write signal with reference to a clock signal, wherein the first global write signal and the second global write signal are in the same time domain with reference to the clock signal.

[0100] Example 10. A circuit for controlling a memory device, comprising: a first inverter configured to convert a first global write signal into a first local write signal; a second inverter configured to convert a second global write signal into a second local write signal; a selection circuit coupled to the first inverter and the second inverter, and the selection circuit configured to send the first local write signal to a two's complement bit line and send the second local write signal to a bit line in response to a selection signal; and a decoder circuit coupled to the first inverter, the second inverter and the selection circuit, and the decoder circuit configured to generate the selection signal and the decoder circuit configured to pull down a voltage level of the selection signal in response to the first local write signal and the second local write signal.

[0101] Example 11. The circuit according to Example 10, wherein the decoder circuit includes: a pull-down circuit coupled between an output terminal and a ground terminal of the decoder circuit, wherein the pull-down circuit is configured to pull down the voltage level of the selection signal in response to the first local write signal and the second local write signal.

[0102] Example 12. The circuit according to Example 11, wherein the pull-low circuit includes: a first transistor coupled between the output terminal and the ground terminal of the decoder circuit, wherein the gate terminal of the first transistor is controlled by the first local write signal; and a second transistor coupled between the output terminal and the ground terminal of the decoder circuit, wherein the second transistor is connected in series with the first transistor, and the gate terminal of the second transistor is controlled by the second local write signal.

[0103] Example 13. The circuit according to Example 12, wherein, in bit write mask mode, the first transistor and the second transistor are configured to be turned on to pull the voltage level of the selection signal low to the ground terminal.

[0104] Example 14. The circuit according to Example 10, wherein the decoder circuit includes: a third inverter configured to generate the selection signal in response to a decode bit signal; and a header circuit configured to connect or disconnect the power supply terminal of the third inverter to a positive reference voltage source in response to a first local write signal and a second local write signal.

[0105] Example 15. The circuit according to Example 14, wherein the head circuit includes: a third transistor coupled between the positive reference voltage source and the power supply terminal of the third inverter, the gate terminal of the third transistor being controlled by the first local write signal; and a fourth transistor coupled between the positive reference voltage source and the power supply terminal of the third inverter and connected in parallel with the third transistor, the gate terminal of the fourth transistor being controlled by the second local write signal.

[0106] Example 16. The circuit according to Example 15, wherein, in bit write mask mode, the third transistor and the fourth transistor are turned off to disconnect the power supply terminal of the third inverter from the positive reference voltage source.

[0107] Example 17. A method for controlling a memory device, comprising: converting a first global write signal into a first local write signal sent to a two's complement bit line via a first inverter; converting a second global write signal into a second local write signal sent to a bit line via a second inverter; and in a bit write mask mode, disconnecting a power supply terminal of the first inverter from a positive reference voltage source and disconnecting a power supply terminal of the second inverter from the positive reference voltage source.

[0108] Example 18. The method according to Example 17, wherein, in the bit write mask mode, the first local write signal and the second local write signal are configured to a floating state or a high impedance state.

[0109] Example 19. The method according to Example 17 further includes: in normal write mode, connecting one power supply terminal of the first inverter or the second inverter to the positive reference voltage source, and disconnecting the other power supply terminal of the first inverter or the second inverter from the positive reference voltage source.

[0110] Example 20. The method according to Example 17 further includes: in read mode or standby mode, connecting the power supply terminal of the first inverter to the positive reference voltage source, and connecting the power supply terminal of the second inverter to the positive reference voltage source.

Claims

1. A circuit for controlling a memory device, comprising: a first inverter configured to convert a first global write signal to a first local write signal sent to a complement bit line; a second inverter configured to convert a second global write signal to a second local write signal sent to a bit line; a first head circuit configured to connect or disconnect a power terminal of the first inverter to a positive reference voltage source in response to a write enable signal and the second global write signal; and a second head circuit configured to connect or disconnect a power terminal of the second inverter to the positive reference voltage source in response to the write enable signal and the first global write signal. the first head circuit comprises:

2. The circuit of claim 1, wherein, a first transistor coupled between the positive reference voltage source and the power terminal of the first inverter, a gate terminal of the first transistor being controlled by the second global write signal after inversion; and a second transistor coupled between the positive reference voltage source and the power terminal of the first inverter in parallel with the first transistor, a gate terminal of the second transistor being controlled by the write enable signal; wherein the second head circuit comprises: a third transistor coupled between the positive reference voltage source and the power terminal of the second inverter, a gate terminal of the third transistor being controlled by the first global write signal after inversion; and a fourth transistor coupled between the positive reference voltage source and the power terminal of the second inverter in parallel with the third transistor, a gate terminal of the fourth transistor being controlled by the write enable signal. in a bit write mask mode, the first transistor and the second transistor in the first head circuit are turned off, and the third transistor and the fourth transistor in the second head circuit are turned off.

3. The circuit of claim 2, wherein, in the bit write mask mode, the first local write signal and the second local write signal are configured to be in a floating state or a high impedance state.

4. The circuit of claim 3, wherein, in a normal write mode, one of the first transistor or the third transistor is turned on, and the other one of the first transistor or the third transistor is turned off, the second transistor and the fourth transistor are turned off.

5. The circuit of claim 2, wherein, in a read mode or a standby mode, the second transistor and the fourth transistor are turned on.

6. The circuit of claim 2, wherein, 7. The circuit of claim 1, wherein, in a first mode, one of the first head circuit or the second head circuit is configured to connect one power terminal of the first inverter or the second inverter to the positive reference voltage source, and the other one of the first head circuit or the second head circuit is configured to disconnect the other power terminal of the first inverter or the second inverter from the positive reference voltage source; in a second mode, the first head circuit is configured to disconnect the power terminal of the first inverter from the positive reference voltage source, and the second head circuit is configured to disconnect the power terminal of the second inverter from the positive reference voltage source; and in a third mode, the first head circuit is configured to connect the power terminal of the first inverter to the positive reference voltage source, and the second head circuit is configured to connect the power terminal of the second inverter to the positive reference voltage source. ​ In a third mode, the first head circuit is configured to connect a power terminal of the first inverter to the positive reference voltage source, and the second head circuit is configured to connect a power terminal of the second inverter to the positive reference voltage source.

8. The circuit of claim 7, wherein, The first mode is a normal write mode, the second mode is a bit write mask mode, and the third mode is a read mode or a standby mode.

9. The circuit of claim 1, further comprising: a main input / output circuit configured to generate the first global write signal and the second global write signal with reference to a clock signal, wherein the first global write signal and the second global write signal are in a same time domain with reference to the clock signal.

10. A circuit for controlling a memory device, comprising: a first inverter configured to convert a first global write signal to a first local write signal; a second inverter configured to convert a second global write signal to a second local write signal; a selection circuit coupled with the first inverter and the second inverter, and the selection circuit is configured to send the first local write signal to a complement bit line and the second local write signal to a bit line in response to a selection signal; and a decoder circuit coupled with the first inverter, the second inverter, and the selection circuit, and the decoder circuit is configured to generate the selection signal, and the decoder circuit is configured to pull down a voltage level of the selection signal in response to the first local write signal and the second local write signal.

11. The circuit of claim 10, wherein, The decoder circuit comprises: a pull-down circuit coupled between an output terminal of the decoder circuit and a ground terminal, wherein the pull-down circuit is configured to pull down the voltage level of the selection signal in response to the first local write signal and the second local write signal.

12. The circuit of claim 11, wherein, The pull-down circuit comprises: a first transistor coupled between the output terminal of the decoder circuit and the ground terminal, wherein a gate terminal of the first transistor is controlled by the first local write signal; and a second transistor coupled between the output terminal of the decoder circuit and the ground terminal, wherein the second transistor is connected in series with the first transistor, and a gate terminal of the second transistor is controlled by the second local write signal.

13. The circuit of claim 12, wherein, In a bit write mask mode, the first transistor and the second transistor are configured to be turned on to pull down the voltage level of the selection signal to the ground terminal.

14. The circuit of claim 10, wherein, The decoder circuit comprises: a third inverter configured to generate the selection signal in response to a decode bit signal; and a head circuit configured to connect or disconnect a power terminal of the third inverter with a positive reference voltage source in response to the first local write signal and the second local write signal.

15. The circuit of claim 14, wherein, The head circuit comprises: a third transistor coupled between the positive reference voltage source and the power terminal of the third inverter, a gate terminal of the third transistor is controlled by the first local write signal; and a fourth transistor coupled between the positive reference voltage source and the power terminal of the third inverter, a gate terminal of the fourth transistor is controlled by the second local write signal. a fourth transistor coupled between the positive reference voltage source and a power supply terminal of the third inverter in parallel with the third transistor, a gate terminal of the fourth transistor being controlled by the second local write signal.

16. The circuit of claim 15, wherein, In a bit write mask mode, the third transistor and the fourth transistor are turned off to disconnect the power supply terminal of the third inverter from the positive reference voltage source.

17. A method for controlling a memory device, comprising: inverting, by a first inverter, a first global write signal to a first local write signal sent to a complement bit line; inverting, by a second inverter, a second global write signal to a second local write signal sent to a bit line; in a bit write mask mode, disconnecting a power supply terminal of the first inverter from a positive reference voltage source and disconnecting a power supply terminal of the second inverter from the positive reference voltage source; and in a normal write mode, connecting one power supply terminal of the first inverter or the second inverter to the positive reference voltage source and disconnecting the other power supply terminal of the first inverter or the second inverter from the positive reference voltage source.

18. The method of claim 17, wherein, In the bit write mask mode, the first local write signal and the second local write signal are configured to be in a floating state or a high impedance state.

19. The method of claim 17, further comprising: in a read mode or a standby mode, connecting the power supply terminal of the first inverter to the positive reference voltage source and connecting the power supply terminal of the second inverter to the positive reference voltage source.

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