Coding control method, memory storage device and memory control circuit unit

Abstract

The present invention provides an encoding control method, a memory storage device, and a memory control circuit unit. The method includes: performing a first encoding operation by an encoding circuit based on write data, a first sub-matrix, and a second sub-matrix in a parity check matrix to generate first parity data; performing a second encoding operation by the encoding circuit based on the write data, the first parity data, and a third sub-matrix, a fourth sub-matrix, and a fifth sub-matrix in the parity check matrix to generate second parity data; and issuing a first write command sequence to instruct the storage of the write data, the first parity data, and the second parity data in a rewritable non-volatile memory module. This method improves the operational flexibility of the memory storage device during data access.

Description

Technical Field

[0001] The present invention relates to a coding control technology, and more particularly to a coding control method, a memory storage device, and a memory control circuit unit. Background Art

[0002] Generally speaking, to maintain data reliability, data is first encoded to generate corresponding error-correcting codes before being stored in a rewritable non-volatile memory module. The error-correcting codes are then stored in the rewritable non-volatile memory module along with the corresponding data. Later, when the data is read from the rewritable non-volatile memory module, the corresponding error-correcting codes can be used to correct any errors that may exist in the data. However, the data length of the error-correcting codes generated by a single encoding circuit cannot be dynamically adjusted, making their use inflexible. Generating error-correcting codes for different data lengths requires multiple encoding circuits, which is not cost-effective. Summary of the Invention

[0003] The present invention provides a coding control method, a memory storage device and a memory control circuit unit, which can generate parity data with different data lengths by a single coding circuit.

[0004] An exemplary embodiment of the present invention provides an encoding control method for a rewritable non-volatile memory module. The encoding control method includes: receiving write data from a host system; performing a first encoding operation by an encoding circuit based on the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate first parity data; performing a second encoding operation by the encoding circuit based on the write data, the first parity data, a third sub-matrix in the parity check matrix, a fourth sub-matrix in the parity check matrix, and a fifth sub-matrix in the parity check matrix to generate second parity data; and sending a first write command sequence to instruct storage of the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module.

[0005] In an exemplary embodiment of the present invention, the first encoding operation includes: providing the write data to a first encoding circuit in the encoding circuit by a first channel switching circuit in the encoding circuit; generating first transient data according to the write data and the first sub-matrix by the first encoding circuit; providing the first transient data to a second encoding circuit in the encoding circuit by a second channel switching circuit in the encoding circuit; and generating the first parity data according to the first transient data and the second sub-matrix by the second encoding circuit.

[0006] In an exemplary embodiment of the present invention, the second encoding operation includes: providing the write data to a first encoding circuit in the encoding circuit by a first channel switching circuit; feeding back the first parity data to the first encoding circuit by the first channel switching circuit; generating second transient data by the first encoding circuit based on the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix; providing the second transient data to a second encoding circuit in the encoding circuit by a second channel switching circuit; and generating the second parity data by the second encoding circuit based on the second transient data and the fifth sub-matrix.

[0007] In an exemplary embodiment of the present invention, the step of generating the second transient data by the first encoding circuit based on the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix includes: generating the first sub-transient data by the first matrix operation circuit in the first encoding circuit based on the write data and the third sub-matrix; generating the second sub-transient data by the first matrix operation circuit based on the first parity data and the fourth sub-matrix; and generating the second transient data by the addition circuit in the first encoding circuit based on the first sub-transient data and the second sub-transient data.

[0008] In an exemplary embodiment of the present invention, the encoding control method further includes: performing, by the encoding circuit, a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix in the parity-check matrix, a seventh sub-matrix in the parity-check matrix, and an eighth sub-matrix in the parity-check matrix to generate third parity data; and sending a second write command sequence to instruct storage of the third parity data in the rewritable non-volatile memory module.

[0009] In an exemplary embodiment of the present invention, the third encoding operation includes: providing the write data to a first encoding circuit in the encoding circuit by a first channel switching circuit in the encoding circuit; feeding back the first parity data and the second parity data to the first encoding circuit by the first channel switching circuit; generating third transient data by the first encoding circuit based on the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix; providing the third transient data to a second encoding circuit in the encoding circuit by a second channel switching circuit in the encoding circuit; and generating the third parity data by the second encoding circuit based on the third transient data and the eighth sub-matrix.

[0010] In an exemplary embodiment of the present invention, the step of generating the third transient data by the first encoding circuit in the encoding circuit based on the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix includes: generating third sub-transient data by the first matrix operation circuit in the first encoding circuit based on the write data and the sixth sub-matrix; generating fourth sub-transient data by the first matrix operation circuit based on the first parity data, the second parity data, and the seventh sub-matrix; and generating the third transient data by the addition circuit in the first encoding circuit based on the third sub-transient data and the fourth sub-transient data.

[0011] In an exemplary embodiment of the present invention, the step of generating the third transient data by the first encoding circuit in the encoding circuit according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix further includes: providing the third sub-transient data and the fourth sub-transient data to the adding circuit by a third channel switching circuit in the first encoding circuit.

[0012] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: receive write data from the host system; send a first write command sequence to instruct to store the write data, first parity data, and second parity data in the rewritable non-volatile memory module. The memory control circuit unit includes an encoding circuit, and the encoding circuit is used to: perform a first encoding operation based on the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate the first parity data; and perform a second encoding operation based on the write data, the first parity data, a third sub-matrix in the parity check matrix, a fourth sub-matrix in the parity check matrix, and a fifth sub-matrix in the parity check matrix to generate the second parity data.

[0013] In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. During the first encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first encoding circuit is configured to generate first transient data based on the write data and the first sub-matrix. The second channel switching circuit is configured to provide the first transient data to the second encoding circuit. The second encoding circuit is configured to generate the first parity data based on the first transient data and the second sub-matrix.

[0014] In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. During the second encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first channel switching circuit is further configured to feed the first parity data back to the first encoding circuit. The first encoding circuit is configured to generate second transient data based on the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix. The second channel switching circuit is configured to provide the second transient data to the second encoding circuit. The second encoding circuit is configured to generate the second parity data based on the second transient data and the fifth sub-matrix.

[0015] In an exemplary embodiment of the present invention, the first encoding circuit includes a first matrix operation circuit and an addition circuit. The first matrix operation circuit is connected to the first channel switching circuit. The addition circuit is connected to the first matrix operation circuit and the second channel switching circuit. In the second encoding operation, the first matrix operation circuit is configured to generate first sub-transient data based on the write data and the third sub-matrix, and to generate second sub-transient data based on the first parity data and the fourth sub-matrix. The addition circuit is configured to generate the second transient data based on the first sub-transient data and the second sub-transient data.

[0016] In an exemplary embodiment of the present invention, the encoding circuit is further configured to perform a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity-check matrix, a seventh sub-matrix of the parity-check matrix, and an eighth sub-matrix of the parity-check matrix to generate third parity data. The memory control circuit unit is further configured to issue a second write command sequence to instruct storage of the third parity data in the rewritable non-volatile memory module.

[0017] In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. In the third encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit. The first encoding circuit is configured to generate third transient data based on the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix. The second channel switching circuit is configured to provide the third transient data to the second encoding circuit. The second encoding circuit is configured to generate the third parity data based on the third transient data and the eighth sub-matrix.

[0018] In an exemplary embodiment of the present invention, the first encoding circuit includes a first matrix operation circuit and an addition circuit. The first matrix operation circuit is connected to the first channel switching circuit. The addition circuit is connected to the first matrix operation circuit and the second channel switching circuit. In the third encoding operation, the first matrix operation circuit is configured to generate third sub-transient data based on the write data and the sixth sub-matrix, and to generate fourth sub-transient data based on the first parity data, the second parity data, and the seventh sub-matrix. The addition circuit is configured to generate the third transient data based on the third sub-transient data and the fourth sub-transient data.

[0019] In an exemplary embodiment of the present invention, the first encoding circuit further includes a third channel switching circuit connected between the first matrix operation circuit and the adding circuit. During the third encoding operation, the third channel switching circuit is configured to provide the third sub-transient data and the fourth sub-transient data to the adding circuit.

[0020] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, an encoding circuit, and a memory management circuit. The host interface is connected to a host system. The memory interface is connected to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the encoding circuit. The memory management circuit is configured to: receive write data from the host system; and send a first write command sequence to instruct storage of the write data, first parity data, and second parity data in the rewritable non-volatile memory module. The encoding circuit is configured to perform a first encoding operation based on the write data, a first sub-matrix of a parity-check matrix, and a second sub-matrix of the parity-check matrix to generate the first parity data; and to perform a second encoding operation based on the write data, the first parity data, a third sub-matrix of the parity-check matrix, a fourth sub-matrix of the parity-check matrix, and a fifth sub-matrix of the parity-check matrix to generate the second parity data.

[0021] In an exemplary embodiment of the present invention, the encoding circuit is further configured to perform a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity-check matrix, a seventh sub-matrix of the parity-check matrix, and an eighth sub-matrix of the parity-check matrix to generate third parity data. The memory management circuit is further configured to issue a second write command sequence to instruct storage of the third parity data in the rewritable non-volatile memory module.

[0022] Based on the above, after receiving write data, the encoding circuit can dynamically generate first parity data and second parity data based on different sub-matrices within the same parity-check matrix. Subsequently, depending on different operational conditions, the first parity data can be used alone or in combination with the second parity data to decode the write data. This improves the operational flexibility of the memory storage device when performing data access. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0029] Figure 7A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;

[0030] Figure 7B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention;

[0031] Figure 8A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;

[0032] Figure 8B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention;

[0033] Figure 9 is a schematic diagram of a decoding process according to an exemplary embodiment of the present invention;

[0034] Figure 10 FIG. 4 is a flowchart of an encoding control method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.

[0037] Figure 1 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be connected to a system bus 110 .

[0039] In one exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0040] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless method.

[0041] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0043] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0044] Figure 4 FIG is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0045] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0046] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0047] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which each cell can store one bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which each cell can store two bits), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which each cell can store three bits), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which each cell can store four bits), other flash memory modules, or other memory modules with similar characteristics.

[0048] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in the memory cell.

[0049] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0050] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of storage cells to be erased together. For example, a physical erase unit is a physical block.

[0051] Figure 5 FIG is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 , a memory interface 53 and an error checking and correction circuit 54 .

[0052] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0053] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0054] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in the form of program code in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area of ​​the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a boot code. When the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory management circuit 51. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0055] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 43 to write data to the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0056] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0057] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection operation). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0058] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0059] In one exemplary embodiment, the ECC circuit 54 may support low-density parity-check (LDPC) codes. For example, the ECC circuit 508 may utilize LDPC codes for encoding and decoding. In one exemplary embodiment, the ECC circuit 54 may also utilize other encoding / decoding algorithms, such as BCH or Reed-Solomon (RS) codes, without limitation.

[0060] In one exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0061] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0062] Figure 6 FIG is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0063] In one exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In one exemplary embodiment, a physical unit may also be composed of multiple consecutive or discontinuous physical addresses. In one exemplary embodiment, a physical unit may also be referred to as a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

[0064] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1) to 610(B) in the idle area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In one exemplary embodiment, the idle area 602 is also called a free pool.

[0065] The memory management circuit 51 can configure logical units 612(0)-612(C) to map physical units 610(0)-610(A) in the storage area 601. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0066] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it indicates that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it indicates that the data currently stored in the physical unit is invalid data.

[0067] The memory management circuit 51 may record management data describing the mapping relationship between logical units and physical units (also known as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 based on the information in the logical-to-physical mapping table.

[0068] In low-density parity-check codes, a parity check matrix (also called a parity check matrix) is used to define valid codewords. Hereinafter, the parity check matrix is ​​denoted as matrix M, and a codeword is denoted as V. According to the following equation (1), if the product of the parity check matrix M and the codeword V is a zero vector, the codeword V is a valid codeword. The operator × represents the matrix multiplication modulo 2 (mod2). In other words, the null space of the matrix M contains all valid codewords. However, the present invention does not limit the content of the codeword V. For example, the codeword V may also include an error correction code or an error checking code generated by any algorithm.

[0069] V×M T =0 (1)

[0070] Codeword V can include information bits and parity bits. That is, codeword V can be expressed as [UP]. Vector U is composed of information bits. Vector P is composed of parity bits. Vector U is also called write data (or data to be encoded). Vector P is also called parity data.

[0071] In a codeword, parity bits (i.e., parity data) are used to protect information bits (i.e., written data) and can be considered error-correcting or error-checking codes generated for the information bits. Furthermore, protecting information bits means, for example, maintaining the accuracy of the information bits. For example, when reading information bits from the rewritable non-volatile memory module 43, the parity bits corresponding to these information bits can be used to correct errors that may exist in the information bits.

[0072] When decoding a codeword V, a parity check operation is first performed on the codeword V, for example, by multiplying the matrix M by the codeword V to generate a vector (hereinafter labeled S, as shown in the following equation (2)). Each element in the vector S is also called a syndrome. The vector S is also called syndrome data. If the vector S is a zero vector (i.e., each element in the vector S is zero), the codeword V can be directly output. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it indicates that there is at least one error in the codeword V and the codeword V is not a valid codeword. If the codeword V is not a valid codeword, the error checking and correction circuit 54 can perform a decoding operation to attempt to correct the error in the codeword V.

[0073] V×H T =S (2)

[0074] In one exemplary embodiment, the ECC circuit 54 may include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 is used to encode data, and the decoding circuit 542 is used to decode data. In one exemplary embodiment, the encoding circuit 541 and the decoding circuit 542 may also be combined into a single encoding / decoding circuit.

[0075] The memory management circuit 51 may receive write data from the host system 11. The encoding circuit 541 may perform an encoding operation (also referred to as a first encoding operation) based on the write data and multiple sub-matrices in the matrix M (also referred to as a first sub-matrix and a second sub-matrix) to generate parity data (also referred to as first parity data). After generating the first parity data, the encoding circuit 541 may perform another encoding operation (also referred to as a second encoding operation) based on the write data, the first parity data, and multiple sub-matrices in the matrix M (also referred to as a third sub-matrix, a fourth sub-matrix, and a fifth sub-matrix) to generate parity data (also referred to as second parity data). The first parity data is different from the second parity data. Furthermore, the first parity data may be used alone or in combination with the second parity data to decode the write data.

[0076] After encoding the write data, the memory management circuit 51 may send a write command sequence (also referred to as a first write command sequence) to the rewritable non-volatile memory module 43. The first write command sequence may be used to instruct the rewritable non-volatile memory module 43 to store the write data, first parity data, and second parity data in the rewritable non-volatile memory module 43. Thereafter, when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read the first parity data (and the second parity data) from the rewritable non-volatile memory module 43. The decoding circuit 542 may decode the write data read from the rewritable non-volatile memory module 43 based on the first parity data (and the second parity data) to detect and correct errors in the write data.

[0077] Figure 7A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Figure 7A In an exemplary embodiment, the structure of matrix M (i.e., parity check matrix) is as shown in matrix 701. Matrix 701 includes sub-matrices A to E and X. Sub-matrix X is a zero matrix, and sub-matrices A to E are not zero matrices. Sub-matrix A can be an m×k matrix. Sub-matrix B can be an m×m matrix. Sub-matrix C can be an x×k matrix. Sub-matrix D can be an x×m matrix. Sub-matrix E can be an x×x matrix. Sub-matrix X can be an m×x matrix. k, m, and x are all positive integers, k can be greater than m, and m can be greater than x. The arrangement of sub-matrices A to E and X in matrix 701 is as follows: Figure 7A As shown, but not limited to.

[0078] In one exemplary embodiment, the first parity data can be generated according to the following equation (3). In equation (3), U represents the write data to be encoded, A and B represent sub-matrices A and B in matrix 701, respectively, and P(1) represents the first parity data. In addition, equation (3) can be further decomposed into the following equations (3.1) and (3.2). In equations (3.1) and (3.2), Q(1) represents the transient data (also referred to as the first transient data) used in the process of generating the first parity data.

[0079] P(1)=(B T ) -1 ×(A T ×U) (3)

[0080] Q(1)=A T ×U (3.1)

[0081] P(1)=(B T ) -1 ×Q(1) (3.2)

[0082] In an exemplary embodiment, the second parity data can be generated according to the following equation (4). In equation (4), C, D, and E represent sub-matrices C, D, and E in matrix 701, respectively, and P(2) represents the second parity data. In addition, equation (4) can be further decomposed into the following equations (4.1) to (4.5). In equations (4.1) and (4.2), Q(2) represents the transient data used in the process of generating the second parity data (also referred to as the second transient data). In equations (4.3) to (4.5), R(1) and R(2) represent the sub-transient data used in the process of generating the second transient data (also referred to as the first sub-transient data and the second sub-transient data), respectively.

[0083] P(2)=(E T ) -1 ×(C T ×U+D T ×P(1)) (4)

[0084] Q(2)=C T ×U+D T ×P(1) (4.1)

[0085] P(2)=(E T ) -1 ×Q(2) (4.2)

[0086] R(1)=C T ×U (4.3)

[0087] R(2)=D T ×P(1) (4.4)

[0088] Q(2)=R(1)+R(2) (4.5)

[0089] Figure 7B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention. Figure 7A and Figure 7B The encoding circuit 541 may include a channel switching circuit (also referred to as a first channel switching circuit) 71, an encoding circuit (also referred to as a first encoding circuit) 72, a channel switching circuit (also referred to as a second channel switching circuit) 73, and an encoding circuit (also referred to as a second encoding circuit) 74. Encoding circuit 72 is connected to channel switching circuits 71 and 73. Encoding circuit 74 is connected to channel switching circuits 71 and 73.

[0090] The encoding circuit 541 may perform a first encoding operation to generate parity data P(1). In the first encoding operation, the channel switching circuit 71 may provide the write data U to the encoding circuit 72. The encoding circuit 72 may perform an operation corresponding to equation (3.1) based on the write data U and the sub-matrix A to generate transient data Q(1). The channel switching circuit 73 may provide the transient data Q(1) to the encoding circuit 74. The encoding circuit 74 may perform an operation corresponding to equation (3.2) based on the transient data Q(1) and the sub-matrix B to generate parity data P(1).

[0091] After performing the first encoding operation, the encoding circuit 541 may perform a second encoding operation to generate parity data P(2). In the second encoding operation, the channel switching circuit 71 may provide the write data U to the encoding circuit 72 and feed back the parity data P(1) generated by the first encoding operation to the encoding circuit 72. The encoding circuit 72 may perform an operation corresponding to equation (4.1) based on the write data U, the parity data P(1), the sub-matrix C, and the sub-matrix D to generate transient data Q(2). The channel switching circuit 73 may provide the transient data Q(2) to the encoding circuit 74. The encoding circuit 74 may perform an operation corresponding to equation (4.2) based on the transient data Q(2) and the sub-matrix E to generate parity data P(2).

[0092] Both channel switching circuits 71 and 73 may include a multiplexer. Encoding circuit 72 may include a table circuit 721, a matrix operation circuit (also referred to as a first matrix operation circuit) 722, and an adder circuit 723. Matrix operation circuit 722 is connected to channel switching circuit 71, table circuit 721, and adder circuit 723. Table circuit 721 stores information about sub-matrices A, C, and D. Matrix operation circuit 722 may include at least one shifter, at least one exclusive OR (XOR) circuit, and at least one register to perform the required operation. Adder circuit 723 may include at least one exclusive OR circuit and at least one register to perform the required operation.

[0093] Encoding circuit 74 may include a table circuit 741 and a matrix operation circuit (also referred to as a second matrix operation circuit) 742. Matrix operation circuit 742 is connected to channel switching circuit 73, table circuit 741, and channel switching circuit 71. Table circuit 741 stores information about sub-matrices B and E. Matrix operation circuit 742 may include a circuit structure identical or similar to that of matrix operation circuit 722 to perform the required operations.

[0094] In the first encoding operation, the matrix operation circuit 722 can obtain information of the sub-matrix A from the table circuit 721 and receive the write data U via the channel switching circuit 71. The matrix operation circuit 722 can perform a matrix operation corresponding to the equation (3.1) based on the write data U and the sub-matrix A to generate the transient data Q(1). The matrix operation circuit 742 can obtain information of the sub-matrix B (e.g., information of the inverse matrix of the sub-matrix B) from the table circuit 741 and receive the transient data Q(1) via the channel switching circuit 73. The matrix operation circuit 742 can perform a matrix operation corresponding to the equation (3.2) based on the transient data Q(1) and the sub-matrix B (i.e., information of the inverse matrix of the sub-matrix B) to generate the parity data P(1).

[0095] In the second encoding operation, the matrix operation circuit 722 can receive information of the sub-matrices C and D from the table circuit 721 and receive the write data U and the parity data P(1) via the channel switching circuit 71. The matrix operation circuit 722 can perform an operation corresponding to equation (4.3) based on the write data U and the sub-matrix C to generate the sub-transient data R(1) and perform an operation corresponding to equation (4.4) based on the parity data P(1) and the sub-matrix D to generate the sub-transient data R(2). The addition circuit 723 can perform an operation corresponding to equation (4.5) based on the sub-transient data R(1) and R(2) to generate the transient data Q(2). The matrix operation circuit 742 can obtain information of the sub-matrix E (e.g., information of the inverse matrix of the sub-matrix E) from the table circuit 741 and receive the transient data Q(2) via the channel switching circuit 73. The matrix operation circuit 742 can perform a matrix operation corresponding to equation (4.2) according to the transient data Q(2) and the sub-matrix E (ie, the inverse matrix of the sub-matrix E) to generate the parity data P(2).

[0096] In other words, in Figure 7A and Figure 7B In the exemplary embodiment, the parity data P(1) and P(2) can be sequentially generated by the same encoding circuit 541. In this way, the utilization efficiency of the encoding circuit 541 can be effectively improved.

[0097] In one exemplary embodiment, the encoding circuit 541 may further perform another encoding operation (also referred to as a third encoding operation) based on the write data, the first parity data, the second parity data, and a plurality of sub-matrices (also referred to as the sixth sub-matrix, the seventh sub-matrix, and the eighth sub-matrix) in the matrix M to generate parity data (also referred to as third parity data). The first parity data, the second parity data, and the third parity data are each different. Furthermore, the first parity data may be used alone, in combination with the second parity data, or in combination with the second parity data and the third parity data to decode the write data.

[0098] After generating the third parity data, the memory management circuit 51 may further send a write command sequence (also referred to as a second write command sequence) to the rewritable non-volatile memory module 43. The second write command sequence may be used to instruct the rewritable non-volatile memory module 43 to store the third parity data in the rewritable non-volatile memory module 43. Thereafter, when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read the third parity data from the rewritable non-volatile memory module 43. The decoding circuit 542 may also decode the write data read from the rewritable non-volatile memory module 43 based on the first parity data, the second parity data, and the third parity data to detect and correct errors in the write data.

[0099] Figure 8A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Figure 8A In one exemplary embodiment, the structure of the matrix M (i.e., the parity check matrix) is shown in matrix 801. Matrix 801 includes Figure 7A Matrix 701, submatrices F to H and Y. Submatrix Y is a zero matrix, and submatrices F to H are not zero matrices. Submatrix F can be a y×k matrix. Submatrix G can be a y×(m+x) matrix. Submatrix H can be a y×y matrix. Submatrix Y can be a (m+x)×y matrix. k, m, x and y are all positive integers, k can be greater than m, and m can be greater than x and y. The arrangement of matrix 701 and submatrices F to H and Y in matrix 801 is as follows Figure 8A In other words, matrix 801 can be obtained by expanding matrix 701 (adding sub-matrices F to H and Y).

[0100] In an exemplary embodiment, the third parity data can be generated according to the following equation (5). In equation (5), F, G, and H represent sub-matrices F, G, and H in matrix 801, respectively, and P(3) represents the third parity data. In addition, equation (5) can be further decomposed into the following equations (5.1) to (5.5). In equations (5.1) and (5.2), Q(3) represents the transient data used in the process of generating the third parity data (also referred to as the third transient data). In equations (5.3) to (5.5), R(3) and R(4) represent the sub-transient data used in the process of generating the third transient data (also referred to as the third sub-transient data and the fourth sub-transient data), respectively.

[0101] P(3)=(H T ) -1 ×(F T ×U+G T ×{P(1),P(2)}) (5)

[0102] Q(3)=F T ×U+G T ×{P(1),P(2)} (5.1)

[0103] P(3)=(H T ) -1 ×Q(3) (5.2)

[0104] R(3)=F T ×U (5.3)

[0105] R(4)=G T ×{P(1),P(2)} (5.4)

[0106] Q(3)=R(3)+R(4) (5.5)

[0107] Figure 8B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention. Figure 8A and Figure 8B The encoding circuit 541 may include a channel switching circuit (i.e., a first channel switching circuit) 81, an encoding circuit (i.e., a first encoding circuit) 82, a channel switching circuit (i.e., a second channel switching circuit) 83, and an encoding circuit (i.e., a second encoding circuit) 84. Encoding circuit 82 is connected to channel switching circuits 81 and 83. Encoding circuit 84 is connected to channel switching circuits 81 and 83.

[0108] The encoding circuit 541 may perform a first encoding operation to generate parity data P(1). In the first encoding operation, the channel switching circuit 81 may provide the write data U to the encoding circuit 82. The encoding circuit 82 may perform an operation corresponding to equation (3.1) based on the write data U and the sub-matrix A to generate transient data Q(1). The channel switching circuit 83 may provide the transient data Q(1) to the encoding circuit 84. The encoding circuit 84 may perform an operation corresponding to equation (3.2) based on the transient data Q(1) and the sub-matrix B to generate parity data P(1).

[0109] After performing the first encoding operation, the encoding circuit 541 may perform a second encoding operation to generate parity data P(2). In the second encoding operation, the channel switching circuit 81 may provide the write data U to the encoding circuit 82 and feed back the parity data P(1) generated by the first encoding operation to the encoding circuit 82. The encoding circuit 82 may perform an operation corresponding to equation (4.1) based on the write data U, the parity data P(1), the sub-matrix C, and the sub-matrix D to generate transient data Q(2). The channel switching circuit 83 may provide the transient data Q(2) to the encoding circuit 84. The encoding circuit 84 may perform an operation corresponding to equation (4.2) based on the transient data Q(2) and the sub-matrix E to generate parity data P(2).

[0110] After performing the second encoding operation, the encoding circuit 541 may perform a third encoding operation to generate parity data P(3). In the third encoding operation, the channel switching circuit 81 may provide the write data U to the encoding circuit 82, feed back the parity data P(1) generated by the first encoding operation to the encoding circuit 82, and feed back the parity data P(2) generated by the second encoding operation to the encoding circuit 82. The encoding circuit 82 may perform an operation corresponding to equation (5.1) based on the write data U, the parity data P(1), the parity data P(2), the sub-matrix F, and the sub-matrix G to generate transient data Q(3). The channel switching circuit 83 may provide the transient data Q(3) to the encoding circuit 84. The encoding circuit 84 may perform an operation corresponding to equation (5.2) based on the transient data Q(3) and the sub-matrix H to generate parity data P(3).

[0111] Both channel switching circuits 81 and 83 may include multiplexers. It should be noted that encoding circuit 82 may include a table circuit 821, a matrix operation circuit (i.e., a first matrix operation circuit) 822, a channel switching circuit (also referred to as a third channel switching circuit) 823, and an adder circuit 824. Channel switching circuit 823 is connected between matrix operation circuit 822 and adder circuit 824. Channel switching circuit 823 may include a multiplexer. Table circuit 821 stores information about sub-matrices A, C, D, F, and G. Matrix operation circuit 822 may include at least one shifter, at least one exclusive-OR circuit, and at least one register to perform the required operation functions. Adder circuit 824 may include at least one exclusive-OR circuit and at least one register to perform the required operation functions.

[0112] The encoding circuit 84 may include a table circuit 841 and a matrix operation circuit (i.e., a second matrix operation circuit) 842. The table circuit 841 stores information about the sub-matrices B, E, and H. The matrix operation circuit 842 may include a circuit structure that is the same as or similar to the matrix operation circuit 822 to perform the required operation functions.

[0113] In the first encoding operation, the matrix operation circuit 822 can obtain information of the sub-matrix A from the table circuit 821 and receive the write data U via the channel switching circuit 81. The matrix operation circuit 822 can perform a matrix operation corresponding to the equation (3.1) based on the write data U and the sub-matrix A to generate the transient data Q(1). The matrix operation circuit 842 can obtain information of the sub-matrix B (e.g., information of the inverse matrix of the sub-matrix B) from the table circuit 841 and receive the transient data Q(1) via the channel switching circuit 83. The matrix operation circuit 842 can perform a matrix operation corresponding to the equation (3.2) based on the transient data Q(1) and the sub-matrix B (i.e., information of the inverse matrix of the sub-matrix B) to generate the parity data P(1).

[0114] In the second encoding operation, the matrix operation circuit 822 can receive information of the sub-matrices C and D from the table circuit 821 and receive the write data U and the parity data P(1) via the channel switching circuit 81. The matrix operation circuit 822 can perform an operation corresponding to equation (4.3) based on the write data U and the sub-matrix C to generate the sub-transient data R(1) and perform an operation corresponding to equation (4.4) based on the parity data P(1) and the sub-matrix D to generate the sub-transient data R(2). The channel switching circuit 823 can provide the sub-transient data R(1) and R(2) to the addition circuit 824. The addition circuit 824 can perform an operation corresponding to equation (4.5) based on the sub-transient data R(1) and R(2) to generate the transient data Q(2). The matrix operation circuit 842 can obtain information of the sub-matrix E (e.g., information of the inverse matrix of the sub-matrix E) from the table circuit 841 and receive the transient data Q(2) via the channel switching circuit 83. The matrix operation circuit 842 can perform a matrix operation corresponding to equation (4.2) according to the transient data Q(2) and the sub-matrix E (ie, the inverse matrix of the sub-matrix E) to generate the parity data P(2).

[0115] In the third encoding operation, the matrix operation circuit 822 can receive information of the sub-matrices F and G from the table circuit 821 and receive the write data U, the parity data P(1), and the parity data P(2) via the channel switching circuit 81. The matrix operation circuit 822 can perform an operation corresponding to equation (5.3) based on the write data U and the sub-matrix F to generate sub-transient data R(3) and perform an operation corresponding to equation (5.4) based on the parity data P(1), the parity data P(2), and the sub-matrix G to generate sub-transient data R(4). The channel switching circuit 823 can provide the sub-transient data R(3) and R(4) to the addition circuit 824. The addition circuit 824 can perform an operation corresponding to equation (5.5) based on the sub-transient data R(3) and R(4) to generate transient data Q(3). The matrix operation circuit 842 can obtain information of the sub-matrix H (e.g., information of the inverse matrix of the sub-matrix H) from the table circuit 841 and receive the transient data Q(3) via the channel switching circuit 83. The matrix operation circuit 842 can perform a matrix operation corresponding to equation (5.2) according to the transient data Q(3) and the sub-matrix H (ie, the inverse matrix of the sub-matrix H) to generate the parity data P(3).

[0116] In other words, in Figure 8A and Figure 8B In the exemplary embodiment, the parity data P(1), P(2) and P(3) can be sequentially generated by the same encoding circuit 541. In this way, the utilization efficiency of the encoding circuit 541 can be further improved.

[0117] Figure 9 is a schematic diagram of a decoding process according to an exemplary embodiment of the present invention. Figure 9 , assuming that the parity data P(1) to P(3) are all generated by encoding the write data 901 stored in the rewritable non-volatile memory module 43. The relevant operation details have been described above and will not be repeated here.

[0118] After the write data 901 is read from the rewritable non-volatile memory module 43, the parity data P(1) can also be read from the rewritable non-volatile memory module 43. The decoding circuit 542 can use the parity data P(1) to decode the write data 901. If the write data 901 can be successfully decoded based on the parity data P(1) (for example, all errors in the read write data 901 are corrected), the decoding of the write data 901 can be completed.

[0119] However, if the write data 901 cannot be successfully decoded based on the parity data P(1) (for example, all errors in the read write data 901 cannot be corrected), the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the parity data P(2). The decoding circuit 542 may use the parity data P(1) and P(2) to decode the write data 901. For example, the parity data P(1) and P(2) may be combined into parity data P(12) having a longer data length to decode the write data 901. In particular, the data length of the parity data P(12) is longer than the data length of the parity data P(1), so the error correction capability of the parity data P(12) may be higher than the error correction capability of the parity data P(1). Therefore, the decoding success rate of decoding the write data 901 using the parity data P(12) may be higher than the decoding success rate of decoding the write data 901 using the parity data P(1).

[0120] However, if the write data 901 still cannot be successfully decoded based on the parity data P(12), the memory management circuit 51 may further instruct the rewritable non-volatile memory module 43 to read the parity data P(3). The decoding circuit 542 may use the parity data P(1), P(2), and P(3) to decode the write data 901. For example, the parity data P(1), P(2), and P(3) may be combined into the parity data P(13) having a longer data length to decode the write data 901. In particular, the data length of the parity data P(13) is longer than the data length of the parity data P(12), so the error correction capability of the parity data P(13) may be higher than the error correction capability of the parity data P(12). Therefore, the decoding success rate of decoding the write data 901 using the parity data P(13) may be higher than the decoding success rate of decoding the write data 901 using the parity data P(12). In one exemplary embodiment, by gradually increasing the data length of the parity data during the decoding process, the decoding circuit 542 can gradually improve the error correction capability of the write data 901 .

[0121] exist Figure 9 In the exemplary embodiment, the parity data P(1), P(12), and P(13) can be used alone to decode the write data 901. However, the parity data P(2) and P(3) cannot be used alone to decode the write data 901.

[0122] In one exemplary embodiment, by expanding the matrix 801 (e.g., by adding more sub-matrices to the matrix 801), the encoding circuit 541 can also encode the same written data according to the expanded matrix 801 to generate more parity data P(4)-P(n). When the written data is subsequently decoded, in response to a decoding failure, the parity data P(4)-P(n) can be used in sequence to extend the data length of the initial parity data P(1). In this way, the decoding success rate of the written data can be effectively improved.

[0123] Figure 10 is a flow chart of an encoding control method according to an exemplary embodiment of the present invention. Figure 10 In step S1001, write data is received from a host system. In step S1002, an encoding circuit performs a first encoding operation based on the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate first parity data. In step S1003, the encoding circuit performs a second encoding operation based on the write data, the first parity data, a third sub-matrix in the parity check matrix, a fourth sub-matrix in the parity check matrix, and a fifth sub-matrix in the parity check matrix to generate second parity data. The first parity data is used alone or in combination with the second parity data to decode the write data. In step S1004, a first write command sequence is sent to instruct the write data, the first parity data, and the second parity data to be stored in the rewritable non-volatile memory module.

[0124] However, Figure 10 The steps have been described in detail above and will not be repeated here. Figure 10 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 10 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0125] In summary, exemplary embodiments of the present invention provide a method for encoding the same written data using different sub-matrices within the same parity-check matrix using a single encoding circuit to generate multiple parity data. These parity data can then be used individually or in combination, as needed, to decode the written data. This effectively improves the decoding efficiency of the written data and the flexibility of the encoding circuit.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A coding control method, characterized in that: For a rewritable non-volatile memory module, the encoding control method includes: receiving write data from the host system; performing, by an encoding circuit, a first encoding operation according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate first parity data; The encoding circuit performs a second encoding operation based on the write data, the first parity data, a third sub-matrix in the parity-check matrix, a fourth sub-matrix in the parity-check matrix, and a fifth sub-matrix in the parity-check matrix to generate second parity data, and the second parity data is used to increase the data length of the first parity data; Sending a first write command sequence to instruct to store the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module; performing, by the encoding circuit, a third encoding operation based on the write data, the first parity data, the second parity data, a sixth submatrix in the parity-check matrix, a seventh submatrix in the parity-check matrix, and an eighth submatrix in the parity-check matrix to generate third parity data; and A second write command sequence is sent to instruct to store the third parity data in the rewritable non-volatile memory module.

2. The encoding control method according to claim 1, wherein the first encoding operation comprises: The first channel switching circuit in the encoding circuit provides the write data to the first encoding circuit in the encoding circuit; The first encoding circuit generates first transient data according to the written data and the first sub-matrix; The second channel switching circuit in the encoding circuit provides the first transient data to the second encoding circuit in the encoding circuit; as well as The second encoding circuit generates the first parity data according to the first transient data and the second sub-matrix.

3. The encoding control method according to claim 1, wherein the second encoding operation comprises: The first channel switching circuit in the encoding circuit provides the write data to the first encoding circuit in the encoding circuit; Feeding back the first parity data to the first encoding circuit by the first channel switching circuit; generating second transient data by the first encoding circuit according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix; The second channel switching circuit in the encoding circuit provides the second transient data to the second encoding circuit in the encoding circuit; as well as The second encoding circuit generates the second parity data according to the second transient data and the fifth sub-matrix.

4. The encoding control method according to claim 3 , wherein the step of generating the second transient data by the first encoding circuit according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix comprises: generating, by a first matrix operation circuit in the first encoding circuit, first sub-transient data according to the written data and the third sub-matrix; generating second sub-transient data by the first matrix operation circuit according to the first parity data and the fourth sub-matrix; as well as The adding circuit in the first encoding circuit generates the second transient data according to the first sub-transient data and the second sub-transient data.

5. The encoding control method according to claim 1, wherein the third encoding operation comprises: The first channel switching circuit in the encoding circuit provides the write data to the first encoding circuit in the encoding circuit; Feeding back the first parity data and the second parity data to the first encoding circuit by the first channel switching circuit; generating, by the first encoding circuit, third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix; The second channel switching circuit in the encoding circuit provides the third transient data to the second encoding circuit in the encoding circuit; as well as The second encoding circuit generates the third parity data according to the third transient data and the eighth sub-matrix.

6. The encoding control method according to claim 5 , wherein the step of generating, by the first encoding circuit in the encoding circuit, the third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix comprises: generating third sub-transient data according to the written data and the sixth sub-matrix by a first matrix operation circuit in the first encoding circuit; generating fourth sub-transient data by the first matrix operation circuit according to the first parity data, the second parity data, and the seventh sub-matrix; as well as The adding circuit in the first encoding circuit generates the third transient data according to the third sub-transient data and the fourth sub-transient data.

7. The encoding control method according to claim 6 , wherein the step of generating, by the first encoding circuit in the encoding circuit, the third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix further comprises: The third channel switching circuit in the first encoding circuit provides the third sub-transient data and the fourth sub-transient data to the adding circuit.

8. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; The memory control circuit unit is used to: receiving write data from the host system; Sending a first write instruction sequence to instruct to store the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module, The memory control circuit unit includes an encoding circuit, and the encoding circuit is used to: performing a first encoding operation according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate the first parity data; performing a second encoding operation according to the write data, the first parity data, a third submatrix in the parity-check matrix, a fourth submatrix in the parity-check matrix, and a fifth submatrix in the parity-check matrix to generate second parity data, wherein the second parity data is used to increase a data length of the first parity data; performing a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix in the parity-check matrix, a seventh sub-matrix in the parity-check matrix, and an eighth sub-matrix in the parity-check matrix to generate third parity data; as well as The memory control circuit unit is further configured to send a second write command sequence to instruct to store the third parity data in the rewritable non-volatile memory module.

9. The memory storage device of claim 8, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the first encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit. The first encoding circuit is used to generate first transient data according to the written data and the first sub-matrix. The second channel switching circuit is used to provide the first transient data to the second encoding circuit, and The second encoding circuit is configured to generate the first parity data according to the first transient data and the second sub-matrix.

10. The memory storage device of claim 8, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the second encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit, The first channel switching circuit is further configured to feed back the first parity data to the first encoding circuit. The first encoding circuit is used to generate second transient data according to the write data, the first parity data, the third sub-matrix and the fourth sub-matrix. The second channel switching circuit is used to provide the second transient data to the second encoding circuit, and The second encoding circuit is configured to generate the second parity data according to the second transient data and the fifth sub-matrix.

11. The memory storage device of claim 10 , wherein the first encoding circuit comprises: a first matrix operation circuit connected to the first channel switching circuit; as well as an adding circuit connected to the first matrix operation circuit and the second channel switching circuit, In the second encoding operation, the first matrix operation circuit is used to generate first sub-transient data according to the written data and the third sub-matrix and to generate second sub-transient data according to the first parity data and the fourth sub-matrix, and The adding circuit is used for generating the second transient data according to the first sub-transient data and the second sub-transient data.

12. The memory storage device of claim 8, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the third encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit, The first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit. The first encoding circuit is used to generate third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix and the seventh sub-matrix. The second channel switching circuit is used to provide the third transient data to the second encoding circuit, and The second encoding circuit is configured to generate the third parity data according to the third transient data and the eighth sub-matrix.

13. The memory storage device of claim 12, wherein the first encoding circuit comprises: a first matrix operation circuit connected to the first channel switching circuit; as well as an adding circuit connected to the first matrix operation circuit and the second channel switching circuit, In the third encoding operation, the first matrix operation circuit is used to generate third sub-transient data according to the written data and the sixth sub-matrix and to generate fourth sub-transient data according to the first parity data, the second parity data and the seventh sub-matrix, and The adding circuit is used for generating the third transient data according to the third sub-transient data and the fourth sub-transient data.

14. The memory storage device of claim 13 , wherein the first encoding circuit further comprises: A third channel switching circuit is connected between the first matrix operation circuit and the adding circuit. In the third encoding operation, the third channel switching circuit is configured to provide the third sub-transient data and the fourth sub-transient data to the adding circuit.

15. A memory control circuit unit, characterized in that: For controlling a rewritable non-volatile memory module, the memory control circuit unit includes: A host interface for connecting to a host system; A memory interface, configured to connect to the rewritable non-volatile memory module; encoding circuit; and a memory management circuit connected to the host interface, the memory interface and the encoding circuit, The memory management circuit is used to: receiving write data from the host system; Sending a first write instruction sequence to instruct to store the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module, The encoding circuit is used to: performing a first encoding operation according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate the first parity data; performing a second encoding operation according to the write data, the first parity data, a third submatrix in the parity-check matrix, a fourth submatrix in the parity-check matrix, and a fifth submatrix in the parity-check matrix to generate second parity data, wherein the second parity data is used to increase a data length of the first parity data; performing a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix in the parity-check matrix, a seventh sub-matrix in the parity-check matrix, and an eighth sub-matrix in the parity-check matrix to generate third parity data; and The memory management circuit is further configured to send a second write command sequence to instruct to store the third parity data in the rewritable non-volatile memory module.

16. The memory control circuit unit according to claim 15, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the first encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit. The first encoding circuit is used to generate first transient data according to the written data and the first sub-matrix. The second channel switching circuit is used to provide the first transient data to the second encoding circuit, and The second encoding circuit is configured to generate the first parity data according to the first transient data and the second sub-matrix.

17. The memory control circuit unit according to claim 15, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the second encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit, The first channel switching circuit is further configured to feed back the first parity data to the first encoding circuit. The first encoding circuit is used to generate second transient data according to the write data, the first parity data, the third sub-matrix and the fourth sub-matrix. The second channel switching circuit is used to provide the second transient data to the second encoding circuit, and The second encoding circuit is configured to generate the second parity data according to the second transient data and the fifth sub-matrix.

18. The memory control circuit unit according to claim 17, wherein the first encoding circuit comprises: a first matrix operation circuit connected to the first channel switching circuit; as well as an adding circuit connected to the first matrix operation circuit and the second channel switching circuit, In the second encoding operation, the first matrix operation circuit is used to generate first sub-transient data according to the written data and the third sub-matrix and to generate second sub-transient data according to the first parity data and the fourth sub-matrix, and The adding circuit is used for generating the second transient data according to the first sub-transient data and the second sub-transient data.

19. The memory control circuit unit according to claim 15, wherein the encoding circuit comprises: a first channel switching circuit; a first encoding circuit connected to the first channel switching circuit; a second channel switching circuit connected to the first encoding circuit; as well as a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit, In the third encoding operation, the first channel switching circuit is used to provide the write data to the first encoding circuit, The first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit. The first encoding circuit is used to generate third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix and the seventh sub-matrix. The second channel switching circuit is used to provide the third transient data to the second encoding circuit, and The second encoding circuit is configured to generate the third parity data according to the third transient data and the eighth sub-matrix.

20. The memory control circuit unit according to claim 19, wherein the first encoding circuit comprises: a first matrix operation circuit connected to the first channel switching circuit; as well as an adding circuit connected to the first matrix operation circuit and the second channel switching circuit, In the third encoding operation, the first matrix operation circuit is used to generate third sub-transient data according to the written data and the sixth sub-matrix and to generate fourth sub-transient data according to the first parity data, the second parity data and the seventh sub-matrix, and The adding circuit is used for generating the third transient data according to the third sub-transient data and the fourth sub-transient data.

21. The memory control circuit unit according to claim 20, wherein the first encoding circuit further comprises: A third channel switching circuit is connected between the first matrix operation circuit and the adding circuit. In the third encoding operation, the third channel switching circuit is configured to provide the third sub-transient data and the fourth sub-transient data to the adding circuit.

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