Semiconductor packaging method

Abstract

The present application provides a semiconductor packaging method. The semiconductor packaging method includes: forming an encapsulation structure, the encapsulation structure includes an encapsulation layer and a chip, the encapsulation layer is provided with a cavity, the chip is located in the cavity, the chip has a front side, and the front side of the chip is provided with a pad; forming a rewiring structure electrically connected to the pad on the front side of the chip; arranging a first dielectric layer and a first auxiliary structure on a side of the encapsulation structure close to the front side of the chip; the first dielectric layer covers the first rewiring layer, and the surface of the rewiring structure away from the encapsulation structure exposes the first dielectric layer; the first auxiliary structure is arranged at the periphery of the first dielectric layer and is attached to the outer side wall of the first dielectric layer; forming a first seed layer covering the first dielectric layer on the front side of the chip; and forming a first rewiring layer based on the first seed layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: first, the front side of the chip is bonded to the carrier and hot-pressed and molded, the carrier is peeled off to obtain the encapsulation structure, and then a plurality of rewiring layers are formed on the encapsulation structure. The rewiring layers are used to lead out the internal circuits of the chip.

[0003] When forming the second rewiring layer on the first rewiring layer, a seed layer is first formed, and then the second rewiring layer is formed on the seed layer. The seed layer formed in the existing solution has poor thickness uniformity, resulting in poor thickness uniformity of the formed second rewiring layer, which may make it impossible for a part of the second rewiring layer to expose the dielectric layer used to protect the second rewiring layer, resulting in reduced product yield. Summary of the invention

[0004] The present application provides a semiconductor packaging method. The semiconductor packaging method includes:

[0005] Forming an encapsulation structure, the encapsulation structure comprising an encapsulation layer and a chip, the encapsulation layer being provided with an inwardly concave cavity, the chip being located in the cavity, the chip having a front surface, and a solder pad being provided on the front surface of the chip;

[0006] forming a rewiring structure electrically connected to a bonding pad of the chip on the front side of the chip;

[0007] A first dielectric layer and a first auxiliary structure are arranged on a side of the encapsulation structure close to the front side of the chip; the first dielectric layer is exposed on a surface of the rewiring structure away from the encapsulation structure; the first auxiliary structure is arranged on the periphery of the first dielectric layer and is attached to an outer side wall of the first dielectric layer;

[0008] forming a first seed layer on a side of the first dielectric layer facing away from the chip, wherein the first seed layer covers the first dielectric layer;

[0009] A first rewiring layer is formed based on the first seed layer.

[0010] In one embodiment, the first auxiliary structure is disposed around the first dielectric layer.

[0011] In one embodiment, forming a first redistribution layer based on the first seed layer includes:

[0012] Connecting the first seed layer to a power source and performing electroplating to form a first conductive layer on a side of the first seed layer away from the chip, thereby obtaining a first conductive structure including the first seed layer and the first conductive layer;

[0013] The first conductive structure is patterned to form a first redistribution layer.

[0014] In one embodiment, the material of the first auxiliary structure is a conductive material, and the first seed layer covers at least a portion of a surface of the first auxiliary structure away from the encapsulation structure; and connecting the first seed layer to a power source comprises:

[0015] The first auxiliary structure is connected to the power source, and the first seed layer is connected to the power source through the first auxiliary structure.

[0016] In one embodiment, the first dielectric layer and the first auxiliary structure are provided on a side of the encapsulation structure close to the front side of the chip, including:

[0017] Mounting a first auxiliary structure on the edge of the encapsulation structure;

[0018] A first dielectric layer is formed on the encapsulation structure and is located in the first auxiliary structure and covers the first redistribution layer.

[0019] In one embodiment, the distance from the surface of the first auxiliary structure mounted on the edge of the encapsulation structure away from the encapsulation structure to the encapsulation structure is greater than the distance from the surface of the rewiring structure away from the encapsulation structure to the encapsulation structure, and the distance from the surface of the first dielectric layer away from the encapsulation structure to the encapsulation structure is greater than the distance from the surface of the rewiring structure away from the encapsulation structure to the encapsulation structure; after forming the first dielectric layer located in the first auxiliary structure and covering the first rewiring layer on the encapsulation structure, the semiconductor packaging method further includes:

[0020] The first auxiliary structure and the first dielectric layer are thinned so that the surface of the rewiring structure away from the encapsulation structure exposes the first dielectric layer, and the surface of the first dielectric layer away from the encapsulation structure is flush with the surface of the first auxiliary structure away from the encapsulation structure.

[0021] In one embodiment, the orthographic projection of the first auxiliary structure on the encapsulation structure falls on the encapsulation structure.

[0022] In one embodiment, after forming the first redistribution layer based on the first seed layer, the semiconductor packaging method further comprises: looping and performing the following steps at least once:

[0023] forming a conductive column on a side of the exposed redistribution layer away from the encapsulation structure;

[0024] A second dielectric layer and a second auxiliary structure are provided; the second dielectric layer covers the exposed rewiring layer, and the conductive pillar is away from the surface of the encapsulation structure to expose the second dielectric layer; the second auxiliary structure is provided at the periphery of the second dielectric layer and is in contact with the outer side wall of the second dielectric layer;

[0025] forming a second seed layer on a side of the second dielectric layer facing away from the chip, wherein the second seed layer covers the second dielectric layer;

[0026] A second rewiring layer is formed based on the second seed layer being connected to a power source.

[0027] In one embodiment, the encapsulation structure further comprises a conductive structure, the surface of which exposes the encapsulation layer; the rewiring structure comprises a third rewiring layer electrically connected to the pad of the chip and a conductive protrusion located on a side of the third rewiring layer away from the chip;

[0028] The rewiring structure formed on the front side of the chip and electrically connected to the bonding pad of the chip comprises:

[0029] forming a third seed layer on a side of the encapsulation structure close to the front side of the chip, wherein the third seed layer is electrically connected to the conductive structure;

[0030] forming a third redistribution layer based on the third seed layer;

[0031] A conductive protrusion is formed on a side of the third redistribution layer away from the chip.

[0032] In one embodiment, the semiconductor packaging method further includes:

[0033] The first auxiliary structure is removed.

[0034] The main technical effects achieved by the embodiments of the present application are:

[0035] The semiconductor packaging method provided by the embodiment of the present application forms a first auxiliary structure on the encapsulation structure, and the first auxiliary structure is arranged on the periphery of the first dielectric layer and is in contact with the outer wall of the first dielectric layer. Therefore, no step structure is formed between the position on the outer wall of the first dielectric layer where the first auxiliary structure is arranged and the encapsulation structure. A first seed layer with uniform thickness can be formed on the surface of the first dielectric layer, which helps to improve the uniformity of the first redistribution layer. When a dielectric layer for protecting the first redistribution layer is subsequently formed, the problem that part of the structure of the first redistribution layer cannot be exposed from the dielectric layer can be avoided, which helps to improve the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

[0037] Figure 2 is a flow chart of forming an encapsulation structure provided by an exemplary embodiment of the present application;

[0038] Figure 3 is a structural schematic diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0039] Figure 4 is a structural schematic diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0040] Figure 5 is a schematic structural diagram of an encapsulation structure provided by an exemplary embodiment of the present application;

[0041] Figure 6 is a structural schematic diagram of a third intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0042] Figure 7 is a structural schematic diagram of a fourth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0043] Figure 8 is a top view of a first auxiliary structure provided by an exemplary embodiment of the present application;

[0044] Fig. 9 is a structural schematic diagram of a fifth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0045] Fig.10 is a structural schematic diagram of a sixth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0046] Fig.11 is a flow chart of forming a second redistribution layer based on a first seed layer provided by an exemplary embodiment of the present application;

[0047] Fig.12 is a structural schematic diagram of a seventh intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0048] Fig.13 is a structural schematic diagram of an eighth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0049] Fig.14 is a structural schematic diagram of a ninth intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0050] Fig.15 is a structural schematic diagram of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0051] Fig.16 It is a structural schematic diagram of a semiconductor packaging structure provided by another exemplary embodiment of the present application. Specific embodiments

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0054] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0055] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0056] The present application embodiment provides a semiconductor packaging method. Figure 1 The semiconductor packaging method includes the following steps 110 to 150.

[0057] In step 110, an encapsulation structure is formed, the encapsulation structure comprising an encapsulation layer and a chip, the encapsulation layer is provided with an inwardly concave cavity, the chip is located in the cavity, the chip has a front side, and a solder pad is provided on the front side of the chip.

[0058] In step 120, a rewiring structure electrically connected to a bonding pad of the chip is formed on the front side of the chip.

[0059] In step 130, a first dielectric layer and a first auxiliary structure are arranged on a side of the encapsulation structure close to the front side of the chip; the first dielectric layer covers the first rewiring layer, and the first dielectric layer is exposed on a surface of the rewiring structure facing away from the encapsulation structure; the first auxiliary structure is arranged on the periphery of the first dielectric layer and is bonded to the outer wall of the first dielectric layer.

[0060] In step 140 , a first seed layer is formed on a side of the first dielectric layer facing away from the chip, wherein the first seed layer covers the first dielectric layer.

[0061] In step 150 , a first redistribution layer is formed based on the first seed layer.

[0062] The semiconductor packaging method provided by the embodiment of the present application forms a first auxiliary structure on the encapsulation structure, and the first auxiliary structure is bonded to the outer wall of the first dielectric layer. Therefore, no step structure is formed between the outer wall of the first dielectric layer and the encapsulation structure, and a first seed layer with uniform thickness can be formed on the surface of the first dielectric layer, which helps to improve the uniformity of the first redistribution layer. When a dielectric layer is subsequently formed to protect the first redistribution layer, the problem that part of the structure of the first redistribution layer cannot be exposed from the dielectric layer can be avoided, which helps to improve the yield of the product.

[0063] The semiconductor packaging method provided in the embodiments of the present application will be described in detail below.

[0064] In step 110, an encapsulation structure is formed, the encapsulation structure comprising an encapsulation layer and a chip, the encapsulation layer is provided with an inwardly concave cavity, the chip is located in the cavity, the chip has a front side, and a solder pad is provided on the front side of the chip.

[0065] In one embodiment, the concave cavities on the encapsulation layer may correspond to the chips one by one, and the chips are located in the corresponding concave cavities.

[0066] In one embodiment, see Figure 2 The step 110 of forming the encapsulation structure includes the following steps 111 to 113.

[0067] In step 111 , the chip is mounted on a carrier board, with the front side of the chip facing the surface of the carrier board.

[0068] Through step 111, the following can be obtained: Figure 3 The first intermediate structure is shown. Figure 3 In the illustrated embodiment, a plurality of chips 20 are mounted on the carrier 10. In other embodiments, the number of the chip 20 mounted on the carrier 10 may be one.

[0069] In one embodiment, the carrier 10 includes a mounting area for mounting the chip 20. The shape of the mounting area is designed according to the layout of the chip 20 on the entire carrier 10, and the shape of the mounting area may include a circle, a rectangle or other shapes. The carrier may include multiple mounting areas.

[0070] In one embodiment, the chip 20 can be obtained by cutting a silicon wafer. The silicon wafer has an active surface, and the active surface of the silicon wafer is provided with a pad. The silicon wafer can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer, a grinding device can be used to grind the back side of the silicon wafer opposite to the active surface so that the thickness of the silicon wafer is a specified thickness.

[0071] The pads of the chip 20 are formed by the conductive electrodes that are led out from the internal circuit of the chip to the surface of the chip. A plurality of pads may be provided on the front of the chip 20. The pads are arranged on the conductive electrodes of the chip 20 to lead out the conductive electrodes of the chip 20.

[0072] In one embodiment, the carrier plate 10 may be circular, rectangular or other shapes. The material of the carrier plate 10 may be an iron-nickel fixed expansion alloy, or the material of the carrier plate 10 may also be stainless steel, polymer or the like.

[0073] In one embodiment, the chip 20 can be mounted on the carrier 10 via an adhesive layer, and the adhesive layer can be made of an easily peelable material so that the chip 20 can be peeled off from the carrier 10 later. For example, the adhesive layer can be made of a thermal separation material that can lose its viscosity by heating.

[0074] In one embodiment, before the step 111 of mounting the chip on a carrier, the semiconductor packaging method further includes: forming a protection layer on the front side of the chip.

[0075] In the subsequent step 112 of forming the encapsulation layer 30, since the encapsulation layer 30 needs to be formed under high pressure, the encapsulation material forming the encapsulation layer 30 in this process is easy to penetrate between the carrier 10 and the chip 20. By forming a protective layer on the front side of the chip 20, the protective layer can prevent the encapsulation material from penetrating into the surface of the chip 20, and even if the encapsulation material penetrates when the encapsulation layer 30 is formed, after the carrier 10 and the chip 20 are peeled off, the surface of the protective layer can be directly processed by chemical means or grinding means without directly contacting the front side of the chip 20, thereby avoiding damage to the pad on the front side of the chip 20.

[0076] In step 112, an encapsulation layer is formed, and the encapsulation layer covers the carrier to encapsulate the chip.

[0077] Through step 112, the following can be obtained: Figure 4 The second intermediate structure is shown.

[0078] See also Figure 4 The encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 to encapsulate the chip 20 to reconstruct a flat structure, so that after the carrier 10 is peeled off, rewiring and packaging can continue on the reconstructed flat structure.

[0079] In one embodiment, before forming the encapsulation layer 30, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 20 and the carrier 10, so that the encapsulation layer 30 can be more closely connected to the chip 20 and the carrier 10 without delamination or cracking.

[0080] In one embodiment, the encapsulation layer 30 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0081] In one embodiment, the step 120 of forming the encapsulation layer may include the following steps:

[0082] First, an encapsulation structure is formed, and the encapsulation structure covers the carrier board and encapsulates the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20, so that the encapsulation structure completely encapsulates the chip 20.

[0083] Then, the side of the encapsulation structure facing away from the carrier is thinned to obtain the encapsulation layer. In this step, the encapsulation structure can be thinned by a grinding process to thin the encapsulation structure to a specified thickness.

[0084] In step 113, the carrier is removed to obtain the encapsulation structure.

[0085] Through step 113, the following can be obtained: Figure 5 The encapsulation structure shown.

[0086] In one embodiment, the carrier 10 can be directly mechanically peeled off from the encapsulation layer 30 and the chip 20. In another embodiment, the chip 20 and the carrier 10 are bonded by an adhesive layer, and when the adhesive layer is made of a thermal separation material, the adhesive layer can be heated to reduce the viscosity of the adhesive layer after being heated, thereby peeling off the carrier 10. After the carrier 10 is peeled off, the front side of each chip 20 is exposed.

[0087] In one embodiment, when a protection layer is formed on the front surface of the at least one chip 20 , the protection layer is provided with openings for exposing the bonding pads on the front surface of each chip 20 .

[0088] In one embodiment, the encapsulation structure further includes a conductive structure 31, and the surface of the conductive structure 31 is exposed to the encapsulation layer 30. Figure 3 Before step 112, the forming of the encapsulation structure further includes: mounting the conductive structure 31 on the carrier. The conductive structure 31 can be arranged at the edge of the carrier 10. Figure 4 and Figure 5 The encapsulation layer 30 formed in step 112 covers the conductive structure 31 .

[0089] In step 120, a rewiring structure electrically connected to a bonding pad of the chip is formed on the front side of the chip.

[0090] Through step 120, the following can be obtained: Figure 6 The third intermediate structure shown. Figure 6 The rewiring structure includes a third rewiring layer 41 electrically connected to the bonding pad of the chip and a conductive protrusion 42 located on a side of the third rewiring layer 41 away from the chip.

[0091] In one embodiment, the third rewiring layer 41 may be formed first, and then the conductive protrusion 42 may be formed on the third rewiring layer 41. The third rewiring layer 41 is electrically connected to the pad on the front side of the chip 20, and the pad of the chip 20 is led out. The conductive protrusion 42 is electrically connected to the third rewiring layer 41, and the arrangement of the conductive protrusion 42 facilitates electrical connection with other structures.

[0092] In one embodiment, step 120 includes the following process:

[0093] First, a third seed layer is formed on a side of the encapsulation structure close to the front side of the chip, and the third seed layer is electrically connected to the conductive structure. The third seed layer can be formed on the front side of the chip by a sputtering process. The side of the encapsulation structure close to the front side of the chip refers to the side of the chip where the encapsulation structure is exposed.

[0094] Subsequently, a third rewiring layer is formed based on the third seed layer.

[0095] In one embodiment, the step of forming the third redistribution layer based on the third seed layer may be implemented by the following process:

[0096] The conductive structure is connected to a power source and electroplated to form a third conductive layer on the side of the third seed layer away from the chip, thereby obtaining a third conductive structure including the third seed layer and the third conductive layer; the third conductive structure is patterned to form a third rewiring layer.

[0097] In one embodiment, before the conductive structure is connected to a power source and electroplating is performed, step 120 further includes: providing a patterned photoresist layer on a side of the third seed layer away from the chip, and the third conductive layer is formed in an area of ​​the third seed layer that is not blocked by the photoresist layer. After the conductive structure is connected to a power source and electroplating is performed, step 120 further includes: removing the photoresist layer.

[0098] The step of patterning the third conductive structure includes: etching away the area of ​​the third seed layer that is not blocked by the third conductive layer, and the third seed layer and the third conductive layer that are not etched away serve as the third redistribution layer.

[0099] Subsequently, a conductive protrusion is formed on a side of the third redistribution layer away from the chip.

[0100] In step 130, a first dielectric layer and a first auxiliary structure are arranged on a side of the encapsulation structure close to the front side of the chip; the first dielectric layer covers the first rewiring layer, and the first dielectric layer is exposed on a surface of the rewiring structure facing away from the encapsulation structure; the first auxiliary structure is arranged on the periphery of the first dielectric layer and is bonded to the outer wall of the first dielectric layer.

[0101] Through step 130, the following can be obtained: Figure 7 The fourth intermediate structure shown in FIG. 1 : The first dielectric material layer can protect the third rewiring layer 41 and the conductive protrusion 42 , and can make the surface of the structure obtained after forming the third rewiring layer 41 smooth, so as to facilitate the formation of other structures in subsequent steps.

[0102] In one embodiment, the first auxiliary structure 50 is a closed annular structure, and the first auxiliary structure is arranged around the first dielectric layer 60, that is, the first auxiliary structure 50 completely surrounds the first dielectric layer 60. In this way, there is no step structure between each position of the side wall of the first dielectric layer 60 and the encapsulation structure, which is more conducive to improving the thickness uniformity of the first seed layer. Figure 8 , the first auxiliary structure 50 is a square frame. In other embodiments, the first auxiliary structure 50 may also be a circular ring.

[0103] Since the first auxiliary structure 50 is in contact with the outer wall of the first dielectric layer 60 , the first seed layer will not enter between the first auxiliary structure 50 and the first dielectric layer 60 when the first seed layer is subsequently formed, that is, the first seed layer will not be formed on the side wall of the first dielectric layer 60 .

[0104] In one embodiment, the step 130 of disposing a first dielectric layer and a first auxiliary structure on the encapsulation structure; and the step of covering the first redistribution layer with the first dielectric layer may include the following process:

[0105] First, a first auxiliary structure is mounted on the edge of the encapsulation structure;

[0106] Subsequently, a first dielectric layer is formed on the encapsulation structure, the first dielectric layer is located in the first auxiliary structure and covers the first redistribution layer.

[0107] In one embodiment, the surface of the mounted auxiliary structure and the initially formed first dielectric layer facing away from the encapsulation structure can be flush with the surface of the conductive protrusion facing away from the encapsulation structure. However, it is generally not easy to achieve the thickness of the first auxiliary structure and the thickness of the initial first dielectric layer so that the surface of the auxiliary structure facing away from the encapsulation structure is flush with the surface of the rewiring structure facing away from the encapsulation structure. Fig. 9 In the fifth intermediate structure shown, the distance from the surface of the encapsulation structure to the first auxiliary structure 50 mounted on the edge of the encapsulation structure is greater than the distance from the surface of the rewiring structure to the encapsulation structure (that is, the surface of the conductive protrusion 42 away from the encapsulation structure), and the distance from the surface of the encapsulation structure to the first dielectric layer 60 initially formed is greater than the distance from the surface of the rewiring structure to the encapsulation structure (that is, the surface of the conductive protrusion 42 away from the encapsulation structure) to the encapsulation structure.

[0108] In one embodiment, after the step of forming a first dielectric layer on the encapsulation structure that is located within the first auxiliary structure and covers the first redistribution layer, the semiconductor packaging method further includes:

[0109] The first auxiliary structure and the first dielectric layer are thinned so that the surface of the rewiring structure (that is, the surface of the conductive protrusion 42 facing away from the encapsulation structure) facing away from the encapsulation structure exposes the first dielectric layer, and the surface of the first dielectric layer facing away from the encapsulation structure is flush with the surface of the first auxiliary structure facing away from the encapsulation structure.

[0110] Since the thickness of the first auxiliary structure and the first dielectric layer mounted initially are relatively large, the surface of the first dielectric layer 60 away from the encapsulation structure, the surface of the first auxiliary structure 50 away from the encapsulation structure, and the surface of the rewiring structure away from the encapsulation structure are made flush by subsequent thinning, and the process is easier to implement. In some embodiments, the first dielectric layer and the first auxiliary structure can be thinned by grinding.

[0111] In one embodiment, the first auxiliary structure 50 can be mounted on the edge of the encapsulation structure through an adhesive layer. In this way, the position of the first auxiliary structure 50 mounted on the encapsulation structure can be fixed to prevent the first auxiliary structure 50 from moving. When the encapsulation structure includes multiple chips, the first auxiliary structure 50 encloses the conductive structures 40 on the multiple chips 20.

[0112] In one embodiment, the first dielectric layer 60 is one or more layers of insulating material, and the material of the first dielectric layer 60 can be a plastic film, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material or other materials with similar properties. In one embodiment, an organic or inorganic filler can also be added to the insulating film layer material. The first dielectric layer 60 can be formed by lamination, spin coating, printing, molding or other suitable methods.

[0113] In one embodiment, the orthographic projection of the first auxiliary structure 50 on the encapsulation structure falls on the encapsulation structure. The orthographic projection of the first auxiliary structure 50 on the encapsulation structure falls on the encapsulation structure, which means that the outer edge of the first auxiliary structure 50 is located inside the edge of the encapsulation structure, or the outer edge of the first auxiliary structure 50 is flush with the edge of the encapsulation structure. In this way, the setting of the first auxiliary structure 50 will not increase the size of the packaging structure, and there is no need to change the size of the processing equipment used in the subsequent steps due to the setting of the first auxiliary structure 50, which is more applicable.

[0114] In step 140 , a first seed layer is formed on a side of the first dielectric layer facing away from the chip, wherein the first seed layer covers the first dielectric layer.

[0115] Through step 140, the following can be obtained: Fig.10 The sixth intermediate structure shown.

[0116] In one embodiment, the first seed layer 70 may be formed by a sputtering process.

[0117] In one embodiment, the material of the first seed layer 70 includes one or more of copper, nickel, molybdenum, aluminum, titanium, etc. Copper, nickel, molybdenum, aluminum, and titanium have low resistivity, which can make the first seed layer 70 have good conductivity and low resistance, which is more conducive to increasing the current size and current density in the subsequent electroplating process. In other embodiments, the material of the first seed layer 70 can also be other materials with good conductivity.

[0118] In step 150 , a first redistribution layer is formed based on the first seed layer.

[0119] In one embodiment, see Fig.11 , step 150 may include the following steps 151 to 152.

[0120] In step 151, the first seed layer is connected to a power source and electroplated to form a first conductive layer on a side of the first seed layer facing away from the chip, thereby obtaining a first conductive structure including the first seed layer and the first conductive layer.

[0121] In one embodiment, the material of the first auxiliary structure 50 is a conductive material, and the first seed layer 70 at least covers a portion of the surface of the first auxiliary structure away from the encapsulation structure. Connecting the first seed layer to a power source includes:

[0122] The first auxiliary structure 50 is connected to the power source, and the first seed layer 70 is connected to the power source through the first auxiliary structure 50 .

[0123] In this way, the electrical connection between the first seed layer 70 and the power source can be achieved through the first auxiliary structure 50 without providing an electrode structure, which helps to simplify the semiconductor packaging process.

[0124] In some embodiments, a clamp may be disposed on the surface of the first auxiliary structure 50 , and the first auxiliary structure 50 may be connected to a power source through the clamp.

[0125] In other embodiments, the material of the first auxiliary structure 50 may be an insulating material, and the first seed layer 70 may be electrically connected to a power source through an electrode.

[0126] In one embodiment, before the step 151 of connecting the first seed layer to a power source for electroplating to form a first conductive layer on a side of the first seed layer facing away from the chip, the semiconductor packaging method further includes: providing a patterned photoresist layer on a side of the first seed layer facing away from the chip; the first conductive layer is formed in an area of ​​the first seed layer that is not blocked by the photoresist layer.

[0127] After forming the photoresist layer, the following can be obtained: Fig.12 The seventh intermediate structure shown in FIG. 7 shows that the photoresist layer 71 is a patterned film layer, and the photoresist layer 71 covers other areas on the first seed layer 70 except for the conductive layer to be formed later.

[0128] In one embodiment, the pre-prepared patterned photoresist layer 71 can be directly attached to the side of the first seed layer 70 away from the encapsulation structure. Since there is no step between the edge of the first dielectric layer and the encapsulation structure, when the photoresist layer 71 is attached, the edge of the photoresist layer 71 falls on the first auxiliary structure 50, which can avoid the problem that the photoresist layer 71 is broken during the lamination process of the photoresist layer 71 due to the presence of the step structure, thereby affecting the formation of the first conductive layer.

[0129] In other embodiments, a whole photoresist layer may be formed on the side of the first seed layer 70 away from the encapsulation structure, and then the photoresist layer may be patterned to obtain the photoresist layer 71. The material of the photoresist layer 71 may be positive photoresist or negative photoresist.

[0130] When electroplating is performed, the seventh intermediate structure is placed above the electroplating tank, the first auxiliary structure 50 is connected to the negative electrode of the power supply as a cathode, the anode arranged at the bottom of the electroplating tank is connected to the positive electrode of the power supply, and the electroplating tank contains an electrolyte. During the electroplating process, the metal atoms of the anode lose electrons and become metal cations that enter the electrolyte, and the metal cations in the electrolyte are reduced to metals and deposited on the surface of the first seed layer 70 that is not covered by the photoresist layer 71 to form a conductive layer.

[0131] In some embodiments, the electrolyte in the electroplating bath may be a cupric chloride solution or a copper sulfate solution, the material of the anode may be metallic copper, and the material of the formed conductive layer may be metallic copper.

[0132] By electroplating, the Fig.13 The eighth intermediate structure shown. Fig.13 The conductive layer 80 includes a plurality of conductive blocks 81 arranged at intervals, and the plurality of conductive blocks 81 are formed in the area of ​​the first seed layer 70 that is not covered by the photoresist layer 71. The provision of the photoresist layer 71 allows metal to be deposited only in the area where the conductive layer needs to be formed during electroplating. Compared with the solution of not providing the photoresist layer 71, forming a metal layer on the entire surface of the first seed layer 70 by electroplating, and then forming a conductive layer by etching, the provision of the photoresist layer 71 helps to shorten the time required for the electroplating process and save the process steps of etching the metal layer.

[0133] In one embodiment, after the first seed layer is connected to a power source and electroplated to form a first conductive layer on a side of the first seed layer away from the chip, the semiconductor packaging method further includes: removing the photoresist layer. In this step, the photoresist layer 71 can be removed by a film stripping process.

[0134] Through this step, we can obtain Fig.14 The ninth intermediate structure shown. Fig.14 The first conductive structure 91 includes a first seed layer 70 and a conductive layer 80. The shapes and positions of the plurality of conductive blocks 81 of the conductive layer 80 correspond to the shapes and positions of the second redistribution layer formed in subsequent steps.

[0135] In step 152, the first conductive structure is patterned to form a first redistribution layer.

[0136] Through this step, we can obtain Fig.15 The semiconductor package structure shown in FIG. Fig.15 , the first re-wiring layer 90 includes the remaining first seed layer 70 and the conductive blocks 81 .

[0137] In one embodiment, the step 152 of patterning the first conductive structure to form a first redistribution layer may include the following process:

[0138] The area of ​​the first seed layer 70 not blocked by the conductive layer 80 is etched away, and the first seed layer and the conductive layer 80 not etched away are the first redistribution layer 90. In this step, the area of ​​the first seed layer 70 not blocked by the conductive layer 80 can be etched by a wet etching process or a dry etching process.

[0139] In one embodiment, after forming the first redistribution layer based on the first seed layer, referring to Fig.16 , the semiconductor packaging method further comprises: performing the following steps at least once:

[0140] Forming a conductive pillar 92 on a side of the exposed redistribution layer away from the encapsulation structure;

[0141] A second dielectric layer 93 and a second auxiliary structure 94 are provided; the second dielectric layer 93 covers the exposed rewiring layer, and the conductive pillar 92 is away from the surface of the encapsulation structure to expose the second dielectric layer 93; the second auxiliary structure 94 is provided at the periphery of the second dielectric layer 93 and is in contact with the outer side wall of the second dielectric layer 93;

[0142] forming a second seed layer on a side of the second dielectric layer facing away from the chip, wherein the second seed layer covers the second dielectric layer 93;

[0143] A second rewiring layer 97 is formed based on the second seed layer. The second rewiring layer 97 may include a patterned second seed layer 95 and a second conductive layer 96.

[0144] The specific process of forming the second redistribution layer 97 based on the second seed layer can be found in the description of step 150 and will not be described in detail again.

[0145] At least one second rewiring layer can be formed through the above steps, so that the obtained semiconductor packaging structure includes multiple rewiring layers. In the above steps, by providing the second auxiliary structure, the second auxiliary structure is attached to the outer wall of the second dielectric layer, so that no step structure is formed between the outer wall of the second dielectric layer and the adjacent auxiliary structure, and the uniformity of the second rewiring layer can be improved.

[0146] Fig.16 The semiconductor package structure shown is a structure obtained by performing the above steps only once. In other embodiments, the above steps may be cyclically performed twice or more.

[0147] The process of the above steps is similar to the process of step 130 to step 150. For relevant details, please refer to the introduction of step 130 to step 150 and will not be repeated here.

[0148] In some embodiments, after the above steps are completed, a conductive column can be formed on the outermost second rewiring layer, and a dielectric layer covering the conductive column and the outermost second rewiring layer is formed, and the conductive column exposes the dielectric layer from the surface of the encapsulation structure.

[0149] In one embodiment, the semiconductor packaging method further includes: removing the first auxiliary structure and the second auxiliary structure. The first auxiliary structure and the second auxiliary structure may be removed by cutting the obtained semiconductor packaging structure.

[0150] In one embodiment, the semiconductor packaging method further includes: cutting the semiconductor packaging structure to obtain a plurality of sub-package structures, each sub-package structure including one or more chips.

[0151] It should be noted that the drawings provided in the embodiments of the present application are only for illustration and may differ from the actual structure. For example, the drawings do not illustrate the solder pads on the front side of the chip, but in reality the solder pads on the front side of the chip are electrically connected to the rewiring structure.

[0152] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0153] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0154] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor packaging method, characterized in that: include: Forming an encapsulation structure, the encapsulation structure comprising an encapsulation layer and a chip, the encapsulation layer being provided with an inwardly concave cavity, the chip being located in the cavity, the chip having a front surface, and a solder pad being provided on the front surface of the chip; forming a rewiring structure electrically connected to a bonding pad of the chip on the front side of the chip; A first dielectric layer and a first auxiliary structure are arranged on a side of the encapsulation structure close to the front side of the chip; the first dielectric layer is exposed on a surface of the rewiring structure away from the encapsulation structure; the first auxiliary structure is arranged on the periphery of the first dielectric layer and is attached to an outer side wall of the first dielectric layer; and no step structure is formed between the position where the first auxiliary structure is arranged on the outer side wall of the first dielectric layer and the encapsulation structure; forming a first seed layer on a side of the first dielectric layer facing away from the chip, wherein the first seed layer covers the first dielectric layer; A first rewiring layer is formed based on the first seed layer.

2. The semiconductor packaging method according to claim 1, wherein: The first auxiliary structure is disposed around the first dielectric layer.

3. The semiconductor packaging method according to claim 1, wherein: The forming of a first rewiring layer based on the first seed layer comprises: Connecting the first seed layer to a power source and performing electroplating to form a first conductive layer on a side of the first seed layer away from the chip, thereby obtaining a first conductive structure including the first seed layer and the first conductive layer; The first conductive structure is patterned to form a first redistribution layer.

4. The semiconductor packaging method according to claim 3, characterized in that: The material of the first auxiliary structure is a conductive material, and the first seed layer covers at least a portion of a surface of the first auxiliary structure away from the encapsulation structure; The step of connecting the first seed layer to a power source comprises: The first auxiliary structure is connected to the power source, and the first seed layer is connected to the power source through the first auxiliary structure.

5. The semiconductor packaging method according to claim 1, wherein: The first dielectric layer and the first auxiliary structure are arranged on a side of the encapsulation structure close to the front side of the chip, comprising: Mounting a first auxiliary structure on the edge of the encapsulation structure; A first dielectric layer is formed on the encapsulation structure and is located in the first auxiliary structure and covers the first redistribution layer.

6. The semiconductor packaging method according to claim 5, characterized in that: The distance from the surface of the first auxiliary structure mounted on the edge of the encapsulation structure away from the encapsulation structure to the encapsulation structure is greater than the distance from the surface of the rewiring structure away from the encapsulation structure to the encapsulation structure, and the distance from the surface of the first dielectric layer away from the encapsulation structure to the encapsulation structure is greater than the distance from the surface of the rewiring structure away from the encapsulation structure to the encapsulation structure; After forming a first dielectric layer on the encapsulation structure and located within the first auxiliary structure and covering the first redistribution layer, the semiconductor packaging method further includes: The first auxiliary structure and the first dielectric layer are thinned so that the surface of the rewiring structure away from the encapsulation structure exposes the first dielectric layer, and the surface of the first dielectric layer away from the encapsulation structure is flush with the surface of the first auxiliary structure away from the encapsulation structure.

7. The semiconductor packaging method according to claim 1, wherein: The orthographic projection of the first auxiliary structure on the encapsulation structure falls on the encapsulation structure.

8. The semiconductor packaging method according to claim 1, wherein: After forming the first redistribution layer based on the first seed layer, the semiconductor packaging method further comprises: looping and performing the following steps at least once: forming a conductive column on a side of the exposed redistribution layer away from the encapsulation structure; A second dielectric layer and a second auxiliary structure are provided; the second dielectric layer covers the exposed rewiring layer, and the conductive pillar is away from the surface of the encapsulation structure to expose the second dielectric layer; the second auxiliary structure is provided at the periphery of the second dielectric layer and is in contact with the outer side wall of the second dielectric layer; forming a second seed layer on a side of the second dielectric layer facing away from the chip, wherein the second seed layer covers the second dielectric layer; A second redistribution layer is formed based on the second seed layer being connected to a power source.

9. The semiconductor packaging method according to claim 1, wherein: The encapsulation structure further comprises a conductive structure, the surface of which exposes the encapsulation layer; the rewiring structure comprises a third rewiring layer electrically connected to the pad of the chip and a conductive protrusion located on a side of the third rewiring layer away from the chip; The rewiring structure formed on the front side of the chip and electrically connected to the bonding pad of the chip comprises: forming a third seed layer on a side of the encapsulation structure close to the front side of the chip, wherein the third seed layer is electrically connected to the conductive structure; forming a third redistribution layer based on the third seed layer; A conductive protrusion is formed on a side of the third redistribution layer away from the chip.

10. The semiconductor packaging method according to claim 1, wherein: The semiconductor packaging method further comprises: The first auxiliary structure is removed.

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