Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the structure comprising: a substrate, gate structures formed on the substrate, source / drain doped layers formed in the substrate on both sides of the gate structures, bottom source / drain plugs electrically connecting the source / drain doped layers formed between adjacent gate structures, a first interlayer dielectric layer formed on the substrate and covering the gate structures, an opening formed in the first interlayer dielectric layer and exposing a top of the bottom source / drain plug; a first etching stop layer formed on sidewalls of the opening; a second interlayer dielectric layer formed on the first interlayer dielectric layer, the first etching stop layer and the top of the bottom source / drain plug; a gate plug penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer between adjacent first etching stop layers; and a top source / drain plug penetrating through the second interlayer dielectric layer between adjacent first etching stop layers. The first etching stop layer on the sidewalls of the opening improves the alignment accuracy of the top source / drain plug and the bottom source / drain plug.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry.

[0004] Currently, to further reduce transistor area, the ContactOver Active Gate (COAG) process has been introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, on which a gate structure is formed, and in which source / drain doped layers are formed on both sides of the gate structure, and a bottom source / drain plug electrically connected to the source / drain doped layers is formed between adjacent gate structures; a first interlayer dielectric layer covering the gate structure is formed on the substrate, and an opening is formed in the first interlayer dielectric layer exposing the top of the bottom source / drain plug; a first etch stop layer located on the sidewall of the opening; a second interlayer dielectric layer located on top of the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug; a gate plug penetrating the second interlayer dielectric layer and the first interlayer dielectric layer between adjacent first etch stop layers, the bottom of the gate plug being connected to the gate structure; and a top source / drain plug penetrating the second interlayer dielectric layer between adjacent first etch stop layers, the bottom of the top source / drain plug being connected to the bottom source / drain plug.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, and a bottom source and drain plug electrically connected to the source and drain doped layers is formed between adjacent gate structures; a first interlayer dielectric layer covering the gate structure is formed on the substrate, and an opening is formed in the first interlayer dielectric layer exposing the top of the bottom source and drain plug; a first etch stop layer is formed on the sidewall of the opening; a second interlayer dielectric layer is formed covering the first interlayer dielectric layer, the first etch stop layer, and the bottom source and drain plug; the second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a gate contact hole exposing the gate structure between adjacent first etch stop layers, the gate contact hole being used to form a gate plug; and the second interlayer dielectric layer is etched to form a source and drain contact hole exposing the bottom source and drain plug between adjacent first etch stop layers, the source and drain contact hole being used to form a top source and drain plug.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure in which a bottom source / drain plug electrically connected to the source / drain doped layers is formed between adjacent gate structures. A first interlayer dielectric layer covering the gate structures is formed on a substrate. An opening is formed in the first interlayer dielectric layer exposing the top of the bottom source / drain plug. A first etch stop layer is located on the sidewall of the opening, at the top of the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug. The gate plug penetrates the second interlayer dielectric layer and the first interlayer dielectric layer between adjacent first etch stop layers. The bottom of the gate plug is connected to the gate structure. A top source / drain plug penetrates the second interlayer dielectric layer between adjacent first etch stop layers. The bottom of the top source / drain plug is connected to the bottom source / drain plug. In this embodiment of the invention, a first etch stop layer located on the sidewall of the opening enables self-alignment during the formation of the source / drain contact holes and the gate contact holes. This improves the positional accuracy of the gate contact holes and the source / drain contact holes, thereby simultaneously improving the alignment accuracy of the top source / drain plug with the corresponding bottom source / drain plug, as well as the alignment accuracy of the gate plug with the corresponding gate structure, and ultimately improving the performance of the semiconductor structure.

[0010] This invention provides a method for forming a semiconductor structure. A first interlayer dielectric layer covering the gate structure is formed on a substrate. An opening is formed in the first interlayer dielectric layer to expose the top of the bottom source / drain plug. A first etch stop layer is then formed on the sidewall of the opening. A second interlayer dielectric layer covering the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug is formed. The second interlayer dielectric layer and the first interlayer dielectric layer are then etched. A gate contact hole exposing the gate structure is formed between adjacent first etch stop layers. The gate contact hole is used to form the gate plug. The second interlayer dielectric layer is then etched. A source / drain contact hole exposing the bottom source / drain plug is formed between adjacent first etch stop layers. The source / drain contact hole is used to form the top source / drain plug. In this embodiment of the invention, by forming a first etch stop layer on the sidewall of the opening, during the formation of the source / drain contact hole and the gate contact hole, the etch rate of the first interlayer dielectric layer and the second interlayer dielectric layer is much greater than the etch rate of the first etch stop layer. Through the first etch stop layer, self-alignment can be achieved during the formation of the gate contact hole and the source / drain contact hole. This is beneficial to improving the positional accuracy of the gate contact hole and the source / drain contact hole, thereby simultaneously improving the alignment accuracy of the top source / drain plug with the corresponding bottom source / drain plug, as well as the alignment accuracy of the gate plug with the corresponding gate structure, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 6 This is a schematic diagram of the first embodiment of the semiconductor structure of the present invention;

[0013] Figure 7 This is a schematic diagram of the second embodiment of the semiconductor structure of the present invention;

[0014] Figure 8 This is a schematic diagram of the third embodiment of the semiconductor structure of the present invention;

[0015] Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;

[0016] Figures 19 to 21 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention;

[0017] Figures 22 to 23 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention;

[0018] Figures 24 to 26 This is a schematic diagram of the structure corresponding to each step in the fourth embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0019] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example.

[0020] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0021] refer to Figure 1 A substrate is provided, the substrate including a substrate 10 and fins 11 protruding from the substrate 10. A gate structure 14 is formed on the substrate. A source / drain doped layer 12 is formed in the fins 11 on both sides of the gate structure 14. A bottom source / drain plug 17 electrically connected to the source / drain doped layer 12 is formed between adjacent gate structures 14. A first interlayer dielectric layer 16 covering the gate structure 14 is formed on the substrate. An opening 18 is formed in the first interlayer dielectric layer 16 to expose the top of the bottom source / drain plug 17.

[0022] refer to Figure 2An etching barrier layer 19 is formed in the opening 18 that exposes the top of the bottom source / drain plug 17, and the top surface of the etching barrier layer 19 is flush with the top surface of the first interlayer dielectric layer 16.

[0023] refer to Figure 3 A second interlayer dielectric layer 22 is formed on top of the first interlayer dielectric layer 16 and the etch barrier layer 19.

[0024] refer to Figure 4 The second interlayer dielectric layer 22 and the first interlayer dielectric layer 16 are etched to form a gate contact hole (not shown) between adjacent etch barrier layers 19, exposing the gate structure 14; a gate plug 20 is formed in the gate contact hole, and the gate plug 20 is electrically connected to the gate structure 14.

[0025] refer to Figure 5 The second interlayer dielectric layer 22 and the etching barrier layer 19 are etched to form a source drain contact hole (not shown) that exposes the bottom source drain plug 17; a top source drain plug 21 is formed in the source drain contact hole, and the top source drain plug 21 is electrically connected to the bottom source drain plug 17.

[0026] Research has shown that as device feature sizes decrease, the spacing between adjacent fins 11 also decreases. Due to the etch barrier layer 19 formed on top of the bottom source / drain plug 17, self-alignment can be achieved during the formation of the gate plug 20. However, during the formation of the top source / drain plug 21, overlay shift significantly affects the positional accuracy of the source / drain contact holes, potentially leading to misalignment between the top source / drain plug 21 and the corresponding bottom source / drain plug 17 (e.g., ...). Figure 5 As shown in the dashed box, it is currently impossible to achieve self-alignment during the formation of both gate contact holes and source / drain contact holes, which can easily lead to a deterioration in the electrical performance of semiconductor structures.

[0027] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, and in which source / drain doped layers are formed within the substrate on both sides of the gate structure, and a bottom source / drain plug electrically connected to the source / drain doped layers is formed between adjacent gate structures; a first interlayer dielectric layer covering the gate structure is formed on the substrate, and an opening is formed in the first interlayer dielectric layer exposing the top of the bottom source / drain plug; a first etch stop layer is formed on the sidewall of the opening; a second interlayer dielectric layer is formed covering the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug; the second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a gate contact hole exposing the gate structure between adjacent first etch stop layers, the gate contact hole being used to form a gate plug; the second interlayer dielectric layer is etched to form a source / drain contact hole exposing the bottom source / drain plug between adjacent first etch stop layers, the source / drain contact hole being used to form a top source / drain plug.

[0028] In the embodiment of the present invention, a first interlayer dielectric layer covering the gate structure is formed on the substrate. An opening is formed in the first interlayer dielectric layer to expose the top of the bottom source / drain plug. Then, a first etch stop layer is formed on the sidewall of the opening. A second interlayer dielectric layer covering the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug is formed. Then, the second interlayer dielectric layer and the first interlayer dielectric layer are etched. A gate contact hole exposing the gate structure is formed between adjacent first etch stop layers. The gate contact hole is used to form the gate plug. The second interlayer dielectric layer is etched. A source / drain contact hole exposing the bottom source / drain plug is formed between adjacent first etch stop layers. The source / drain contact hole is used to form the top source / drain plug. In this embodiment of the invention, by forming a first etch stop layer on the sidewall of the opening, during the formation of the source / drain contact hole and the gate contact hole, the etch rate of the first interlayer dielectric layer and the second interlayer dielectric layer is much greater than the etch rate of the first etch stop layer. Through the first etch stop layer, self-alignment can be achieved during the formation of the gate contact hole and the source / drain contact hole. This is beneficial to improving the positional accuracy of the gate contact hole and the source / drain contact hole, thereby simultaneously improving the alignment accuracy of the top source / drain plug with the corresponding bottom source / drain plug, as well as the alignment accuracy of the gate plug with the corresponding gate structure, and thus improving the performance of the semiconductor structure.

[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 6 This is a schematic diagram of the first embodiment of the semiconductor structure of the present invention.

[0031] The semiconductor structure includes: a substrate on which a gate structure 503 is formed; source / drain doped layers 507 are formed in the substrate on both sides of the gate structure 503; bottom source / drain plugs 506 electrically connected to the source / drain doped layers 507 are formed between adjacent gate structures 503; a first interlayer dielectric layer 505 covering the gate structure 503 is formed on the substrate; an opening is formed in the first interlayer dielectric layer 505 exposing the top of the bottom source / drain plugs 506; a first etch stop layer 551 located on the sidewall of the opening; and a second interlayer dielectric layer. 510 is located at the top of the first interlayer dielectric layer 505, the first etch stop layer 551, and the bottom source / drain plug 506; the gate plug 518 penetrates the second interlayer dielectric layer 510 and the first interlayer dielectric layer 505 adjacent to the first etch stop layer 551, and the bottom of the gate plug 518 is connected to the gate structure 503; the top source / drain plug 519 penetrates the second interlayer dielectric layer 510 adjacent to the first etch stop layer 551, and the bottom of the top source / drain plug 519 is connected to the bottom source / drain plug 506.

[0032] In this embodiment of the invention, through the first etch stop layer 551 located on the sidewall of the opening, during the formation of the source / drain contact hole and the gate contact hole, the etching rate of the first interlayer dielectric layer 505 and the second interlayer dielectric layer 510 is much greater than the etching rate of the first etch stop layer 551. Through the first etch stop layer 551, self-alignment can be achieved during the formation of the gate contact hole and the source / drain contact hole. This is beneficial to improve the positional accuracy of the gate contact hole and the source / drain contact hole, thereby simultaneously improving the alignment accuracy of the top source / drain plug 519 with the corresponding bottom source / drain plug 506, and the alignment accuracy of the gate plug 518 with the corresponding gate structure 503, thereby improving the performance of the semiconductor structure.

[0033] In this embodiment, the semiconductor structure is a FinFET (Fin Field-Effect Transistor). The substrate includes a substrate 500 and fins 501 protruding from the substrate 500. In this embodiment, the substrate 500 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, and the substrate may also be other types of substrates such as silicon-on-insulator (SiI) substrate or germanium-on-insulator (CHI) substrate.

[0034] In this embodiment, the fin 501 is disposed on the substrate 500, and the material of the fin 501 is the same as that of the substrate 500, which is silicon.

[0035] When the device is in operation, the gate structure 503 is used to control the opening or closing of the conductive channel.

[0036] In this embodiment, the gate structure 503 is located on the substrate 500, and the gate structure 503 spans the fin 501 and covers part of the top and part of the sidewall of the fin 501.

[0037] In this embodiment, the gate structure 503 is a metal gate structure, which includes a high-k gate dielectric layer, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.

[0038] In this embodiment, the source / drain doped layer 507 is located in the fins 501 on both sides of the gate structure 503.

[0039] When the semiconductor device is an NMOS transistor, the source / drain doped layer 507 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When the semiconductor device is a PMOS transistor, the source / drain doped layer 507 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0040] In this embodiment, the semiconductor structure further includes a sidewall 502 located on the substrate exposed by the gate structure 503, and the sidewall 502 covers the sidewall of the gate structure 503.

[0041] Sidewall 502 defines the formation region of source / drain doped layer 507 and also protects the sidewalls of gate structure 503. Sidewall 502 can be a single-layer structure or a multilayer structure, and the material of sidewall 502 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, sidewall 502 is a single-layer structure, and the material of sidewall 502 is silicon nitride.

[0042] In this embodiment, the semiconductor structure further includes a third etch stop layer 504, located between the top of the exposed gate structure 503 of the gate plug 518 and the first interlayer dielectric layer 505.

[0043] The third etch stop layer 504 protects the gate structure 503.

[0044] The material of the third etch stop layer 504 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the third etch stop layer 504 is silicon nitride.

[0045] In this embodiment, the bottom source / drain plug 506 is located between adjacent gate structures 503.

[0046] The bottom source / drain plug 506 is in contact with the source / drain doped layer 507, and is used to make the source / drain doped layer 507 electrically connected to external circuits or other interconnection structures.

[0047] Among them, a top source / drain plug 519 is formed on the bottom source / drain plug 506 and contacts the bottom source / drain plug 506. The top source / drain plug 519 and the source / drain doped layer 507 are electrically connected through the bottom source / drain plug 506.

[0048] In this embodiment, the bottom source / drain plug 506 is made of tungsten. In other embodiments, the bottom source / drain plug may also be made of conductive materials such as ruthenium or cobalt.

[0049] In this embodiment, the first interlayer dielectric layer 505 is located on the substrate exposed by the gate structure 503, and the first interlayer dielectric layer 505 also covers the top of the gate structure 503.

[0050] The first interlayer dielectric layer 505 is used to achieve electrical isolation between the bottom source / drain plugs 506.

[0051] In this embodiment, the first interlayer dielectric layer 505 is an interlayer dielectric (ILD). The material of the first interlayer dielectric layer 505 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 505 is silicon oxide.

[0052] In this embodiment, an opening (not shown) is formed in the first interlayer dielectric layer 505 to expose the top of the bottom source / drain plug 506.

[0053] The opening provides space for the first etch stop layer 551.

[0054] In this embodiment, the sidewall of the opening protrudes relative to the sidewall of the bottom source drain plug 506.

[0055] The sidewall of the opening protrudes relative to the sidewall of the bottom source / drain plug 506. Therefore, after the first etch stop layer 551 is formed on the exposed sidewall of the opening of the bottom source / drain plug 506, the probability of the first etch stop layer 551 covering the top surface of the bottom source / drain plug 506 is reduced. In other words, the first etch stop layer 551 exposes more of the top surface of the bottom source / drain plug 506. Correspondingly, after the top source / drain plug 519 is formed on the top surface of the bottom source / drain plug 506, the contact area between the bottom source / drain plug 506 and the top source / drain plug 519 is larger, thereby improving the electrical connection effect between the bottom source / drain plug 506 and the top source / drain plug 519, which is beneficial to improving the performance of the semiconductor structure.

[0056] It should be noted that the protrusion of the sidewall of the opening relative to the sidewall of the bottom source / drain plug 506 should not be too large or too small. If the protrusion of the sidewall of the opening relative to the sidewall of the bottom source / drain plug 506 is too large, it will easily occupy too much of the top space of the gate structure 503, causing the formed gate plug 518 to fail to meet the process requirements, thereby affecting the structural performance of the semiconductor. If the protrusion of the sidewall of the opening relative to the sidewall of the bottom source / drain plug 506 is too small, since the first etch stop layer 551 has a certain lateral dimension, it will easily cause the first etch stop layer 551 to cover the top surface of the bottom source / drain plug 506, thereby affecting the electrical connection between the top source / drain plug 519 and the corresponding bottom source / drain plug 506. Therefore, in this embodiment, the protrusion of the sidewall of the opening relative to the sidewall of the bottom source / drain plug 506 is 2 nanometers to 10 nanometers.

[0057] In this embodiment, the bottom of the opening is higher than the top of the gate structure 503.

[0058] Specifically, the bottom of the opening is higher than the top of the gate structure 503, providing space for the second etch stop layer 552 located on top of the bottom source / drain plug 506.

[0059] It should be noted that the depth of the opening should not be too large or too small. If the opening depth is too large, it increases the difficulty of filling the first etch stop layer 551 on the sidewall of the opening; if the opening depth is too small, it may result in the first etch stop layer 551 being too shallow, affecting the alignment accuracy of the top source / drain plug 519 with the corresponding bottom source / drain plug 506, and the alignment accuracy of the gate plug 518 with the corresponding gate structure 503 during the formation of the gate plug 518 and the top source / drain plug 519, thereby affecting the performance of the semiconductor. Therefore, in this embodiment, the depth of the opening is 5 nanometers to 40 nanometers. For example, the depth of the opening is 10 nanometers, 20 nanometers, or 30 nanometers.

[0060] In this embodiment, the first etching stop layer 551 is located on the sidewall of the opening.

[0061] In this embodiment of the invention, through the first etch stop layer 551 located on the sidewall of the opening, during the formation of the source / drain contact hole and the gate contact hole, the etching rate of the first interlayer dielectric layer 505 and the second interlayer dielectric layer 510 is much greater than the etching rate of the first etch stop layer 551. Through the first etch stop layer 551, self-alignment can be achieved during the formation of the gate contact hole and the source / drain contact hole. This is beneficial to improve the positional accuracy of the gate contact hole and the source / drain contact hole, thereby simultaneously improving the alignment accuracy of the top source / drain plug 519 with the corresponding bottom source / drain plug 506, and the alignment accuracy of the gate plug 518 with the corresponding gate structure 503, thereby improving the performance of the semiconductor structure.

[0062] In this embodiment, the lateral direction is defined as the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 503, and the lateral dimension of the first etch stop layer 551 is 2 nanometers to 10 nanometers.

[0063] It should be noted that the lateral dimension of the first etch stop layer 551 should not be too large or too small. If the lateral dimension of the first etch stop layer 551 is too large, it will easily occupy too much space on the top of the gate structure 503, causing the formed gate plug 518 to fail to meet the process requirements, thereby affecting the structural performance of the semiconductor. If the lateral dimension of the first etch stop layer 551 is too small, it will increase the probability of damaging the first interlayer dielectric layer 505 in subsequent etching processes, reducing the alignment accuracy between the top source / drain plug 519 and the corresponding bottom source / drain plug 506. Therefore, in this embodiment, the lateral dimension of the first etch stop layer 551 is 2 nanometers to 10 nanometers, with the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 503 defined as the lateral direction. For example, the lateral dimension of the first etch stop layer 551 is 5 nanometers.

[0064] The material of the first etch stop layer 551 includes one or more of silicon nitride, silicon carbide, silicon carbide, or silicon nanocarbide. Silicon nitride, silicon carbide, silicon carbide, or silicon nanocarbide generally have high hardness, wear resistance, and etching resistance, enabling the first etch stop layer 551 to maintain a good morphology.

[0065] In this embodiment, the material of the first etch stop layer 551 is silicon nitride.

[0066] In this embodiment, the semiconductor structure further includes a groove (not shown) located between the opening and the bottom source / drain plug 506. The top of the groove is connected to the bottom of the opening, and the sidewall of the opening is flush with the sidewall of the bottom source / drain plug 506.

[0067] The groove provides space for the second etch stop layer 552.

[0068] It should be noted that the depth of the groove should not be too large or too small. If the groove depth is too large, the second etch stop layer 552 in the groove may become too large, increasing the difficulty of etching the second etch stop layer 552 in the process of forming the top source / drain plug 519. If the groove depth is too small, the second etch stop layer 552 may become too small, increasing the probability of over-etching in the process of forming the top source / drain plug 519, that is, increasing the probability of the bottom source / drain plug 506 being over-etched, and correspondingly increasing the probability of short-circuiting between the gate structure 503 and the top source / drain plug 519. Therefore, in this embodiment, the depth of the groove is 5 nanometers to 25 nanometers. For example, the depth of the groove is 10 nanometers, 15 nanometers, or 20 nanometers.

[0069] In this embodiment, the semiconductor structure further includes a second etch stop layer 552 located in the groove, wherein the second etch stop layer 552 is made of the same material as the first etch stop layer 551.

[0070] During the process of forming the top source drain plug 519 on the top of the bottom source drain plug 506, it is necessary to etch the second interlayer dielectric layer 510. The second etching stop layer 552 can play the role of etching stop, thereby protecting the bottom source drain plug 506.

[0071] In this embodiment, the second interlayer dielectric layer 510 is located on top of the first interlayer dielectric layer 505, the first etch stop layer 551, and the bottom source / drain plug 506.

[0072] The second interlayer dielectric layer 510 provides space for the gate plug 518 and the top source / drain plug 519, and also serves to achieve electrical isolation between the gate plug 518 and the top source / drain plug 519.

[0073] In this embodiment, the second interlayer dielectric layer 510 ensures that the heights of the gate plug 518 and the top source / drain plug 519 meet the process requirements.

[0074] The material of the second interlayer dielectric layer 510 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 510 is silicon oxide.

[0075] In this embodiment, the gate plug 518 penetrates the second interlayer dielectric layer 510 and the first interlayer dielectric layer 505 between adjacent first etch stop layers 551, and the bottom of the gate plug 518 is connected to the gate structure 503.

[0076] Gate plug 518 is used to realize the electrical connection between gate structure 503 and external circuitry or other interconnection structures.

[0077] In this embodiment, the top source / drain plug 519 penetrates the second interlayer dielectric layer 510 between adjacent first etch stop layers 551, and the bottom of the top source / drain plug 519 is connected to the bottom source / drain plug 506.

[0078] The top source / drain plug 519 and the bottom source / drain plug 506 constitute a source / drain plug, thereby enabling the electrical connection of the source / drain doped layer 507 with other interconnect structures or external circuits.

[0079] It should be noted that the top source drain plug 519 also penetrates the second etch stop layer 552.

[0080] Specifically, the top source / drain plug 519 also extends through the second etch stop layer 552, increasing the volume of the top source / drain plug 519 and achieving better electrical connection performance during electrical connections with other interconnect structures or external circuits.

[0081] It should be noted that in other embodiments, the semiconductor structure may not include the groove, that is, the top of the bottom source / drain plug 506 is flush with the bottom of the first etch stop layer 551, and correspondingly, the top of the bottom source / drain plug 506 does not include the second etch stop layer 552, that is, the bottom of the opening is flush with the top of the bottom source / drain plug 506.

[0082] Figure 7 This is a schematic diagram of the second embodiment of the semiconductor structure of the present invention.

[0083] The similarities between the semiconductor structure of this invention and the first embodiment will not be repeated here. The differences between the semiconductor structure of this invention and the first embodiment are as follows:

[0084] The semiconductor structure further includes: a bottom residual layer 652 located at the bottom of the opening and connected to the first etch stop layer 651; and a protective layer 609 located in the opening and covering the bottom residual layer 652, wherein the top of the protective layer 609 is flush with the top of the first etch stop layer 651.

[0085] During the formation of the first etch stop layer 651, the protective layer 609 protects the top of the first etch stop layer 651 and improves the flatness of the top surface of the first etch stop layer 651.

[0086] Specifically, during the formation of the first etch stop layer 651, after forming an etch stop material layer at the bottom and sidewalls of the opening and at the top of the first interlayer dielectric layer (not shown), a protective material layer covering the etch stop material layer is formed in the remaining opening. Subsequently, the protective material layer and the etch stop material layer are planarized until the top of the first interlayer dielectric layer is exposed. The remaining etch stop material layer on the sidewalls of the opening is retained as the first etch stop layer 651, and the remaining protective material layer in the opening is retained as the protective layer 609.

[0087] Correspondingly, the etching stop material layer at the bottom of the opening is covered by the protective layer 609 and thus retained as the bottom residual layer 652, which is an integral structure with the first etching stop layer 651.

[0088] Therefore, in this embodiment, the top surface of the first etching stop layer 651 is a flat surface.

[0089] The top surface of the first etch stop layer 651 is a flat surface, which makes the alignment accuracy of the top source drain plug and the corresponding bottom source drain plug 606, as well as the alignment accuracy of the gate plug and the corresponding gate structure 603, higher.

[0090] Furthermore, the bottom residual layer 652 correspondingly covers the second etch stop layer (not shown) located in the groove (not shown).

[0091] It should be noted that, for ease of illustration, Figure 7 The interface between the bottom residual layer 652 and the second etch stop layer is represented by a dashed line.

[0092] The protective layer 609 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the protective layer 609 is made of silicon oxide.

[0093] In this embodiment, the bottom of the top source / drain plug is connected to the bottom source / drain plug. Therefore, the top source / drain plug also penetrates the protective layer 609 and the bottom residual layer 652.

[0094] In this embodiment, the top of the bottom source / drain plug is flush with the top of the gate structure.

[0095] For a detailed description of the structure described in this embodiment, please refer to the relevant description in the first embodiment. This embodiment will not repeat the description here.

[0096] Figure 8 This is a schematic diagram of the third embodiment of the semiconductor structure of the present invention.

[0097] The similarities between the semiconductor structure of this invention and the first embodiment will not be repeated here. The differences between the semiconductor structure of this invention and the first embodiment are as follows:

[0098] The semiconductor structure further includes: a bottom residual layer 852 located at the bottom of the opening and connected to the first etch stop layer 851; and a protective layer 809 located in the opening and covering the bottom residual layer 852, wherein the top of the protective layer 809 is flush with the top of the first etch stop layer 851.

[0099] Furthermore, the semiconductor structure does not include a recess (not shown), meaning that the top of the bottom source / drain plug 806 is flush with the bottom of the first etch stop layer 851, and correspondingly, the bottom of the opening is flush with the top of the bottom source / drain plug 506.

[0100] During the formation of the first etch stop layer 851, the protective layer 809 protects the top of the first etch stop layer 851 and improves the flatness of the top surface of the first etch stop layer 851.

[0101] The protective layer 809 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the protective layer 809 is made of silicon oxide.

[0102] In this embodiment, the bottom of the top source / drain plug is connected to the bottom source / drain plug. Therefore, the top source / drain plug also penetrates the protective layer 809.

[0103] The top of the bottom source / drain plug 806 is higher than the top of the gate structure 803.

[0104] Specifically, the top of the bottom source / drain plug 806 is higher than the top of the gate structure 803, which increases the volume of the bottom source / drain plug 806 and achieves better electrical connection effect during the electrical connection with the top source / drain plug or external circuit.

[0105] For a detailed description of the structure described in this embodiment, please refer to the relevant descriptions of the first and second embodiments. This embodiment will not repeat the details here.

[0106] Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0107] refer to Figures 9 to 11 A substrate is provided, on which a gate structure 103 is formed. Source / drain doped layers 107 are formed within the substrate on both sides of the gate structure 103. Bottom source / drain plugs 106 electrically connecting the source / drain doped layers 107 are formed between adjacent gate structures 103. A first interlayer dielectric layer 105 is formed on the substrate covering the gate structure 103. An opening 109 is formed in the first interlayer dielectric layer 105 exposing the top of the bottom source / drain plug 106 (e.g., ...). Figure 11 (As shown).

[0108] The substrate is used to provide a process platform for subsequent process manufacturing.

[0109] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0110] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0111] When the device is in operation, the gate structure 103 is used to control the opening or closing of the conductive channel.

[0112] In this embodiment, the gate structure 103 is located on the substrate 100, and the gate structure 103 spans the fin 101 and covers part of the top and part of the sidewall of the fin 101.

[0113] In this embodiment, the gate structure 103 is a metal gate structure, which includes a high-k gate dielectric layer, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.

[0114] In this embodiment, the source / drain doped layer 107 is located in the fins 101 on both sides of the gate structure 103.

[0115] When forming an NMOS transistor, the source / drain doped layer 107 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer 107 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0116] It should be noted that, as Figure 9 As shown, in this embodiment, a sidewall 102 is also formed on the sidewall of the gate structure 103.

[0117] Sidewall 102 defines the formation region of source / drain doped layer 107 and also protects the sidewalls of gate structure 103. Sidewall 102 can be a single-layer structure or a multilayer structure, and the material of sidewall 102 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, sidewall 102 is a single-layer structure, and the material of sidewall 102 is silicon nitride.

[0118] In the step of providing the substrate, a third etch stop layer 104 is also formed between the top of the gate structure 103 and the first interlayer dielectric layer 105.

[0119] The third etch stop layer 104 is used as an etch stop layer during the subsequent formation of the gate contact hole that exposes the gate structure 103, thereby protecting the gate structure 103.

[0120] The material of the third etch stop layer 104 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the third etch stop layer 104 is silicon nitride.

[0121] In this embodiment, a bottom source / drain plug 106 electrically connected to the source / drain doped layer 107 is formed between adjacent gate structures 103.

[0122] The bottom source / drain plug 106 is in contact with the source / drain doped layer 107 to enable electrical connection between the source / drain doped layer 107 and external circuits or other interconnect structures.

[0123] Subsequently, a top source / drain plug is formed on the bottom source / drain plug 106, which is in contact with the bottom source / drain plug 106. The top source / drain plug and the source / drain doped layer 107 are electrically connected through the bottom source / drain plug 106.

[0124] In this embodiment, the bottom source / drain plug 106 is made of tungsten. In other embodiments, the bottom source / drain plug may also be made of conductive materials such as ruthenium or cobalt.

[0125] In this embodiment, during the step of providing the substrate, the top of the bottom source / drain plug 106 is higher than the top of the gate structure 103.

[0126] The top of the bottom source / drain plug 106 is higher than the top of the gate structure 103, providing space for the bottom source / drain plug 106 to form a recess in the subsequent etch portion.

[0127] The first interlayer dielectric layer 105 is used to achieve electrical isolation between the bottom source / drain plugs 106.

[0128] In this embodiment, the first interlayer dielectric layer 105 is an interlayer dielectric (ILD). The material of the first interlayer dielectric layer 105 is an insulating material, and the material of the first interlayer dielectric layer 105 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 105 is silicon oxide.

[0129] The opening 109 provides space for the subsequent formation of the first etch stop layer.

[0130] In this embodiment, as Figure 9 As shown, before the opening 109 is formed, the bottom source / drain plug 106 penetrates the first interlayer dielectric layer 105 between adjacent gate structures 103, that is, the top of the bottom source / drain plug 106 is flush with the top of the first interlayer dielectric layer 105.

[0131] The bottom source / drain plug 106 penetrates the first interlayer dielectric layer 105 between adjacent gate structures 103 to contact the source / drain doped layer 107, thereby enabling electrical connection between the source / drain doped layer 107 and external circuits or other interconnect structures.

[0132] Accordingly, the step of forming the opening 109 includes: as follows Figure 10 As shown, the bottom source / drain plug 106, with a portion of its thickness etched back, forms an initial opening 108 surrounded by the first interlayer dielectric layer 105 and the top of the bottom source / drain plug 106; as Figure 11 As shown, the sidewall of the initial opening 108 is etched laterally.

[0133] In this embodiment, during the step of forming the opening 109, the sidewall of the opening 109 protrudes relative to the sidewall of the bottom source drain plug 106.

[0134] The sidewall of the opening 109 protrudes relative to the sidewall of the bottom source / drain plug 106. Therefore, after the first etch stop layer is subsequently formed on the exposed sidewall of the opening 109 of the bottom source / drain plug 106, the probability of the first etch stop layer covering the top surface of the bottom source / drain plug 106 is reduced. In other words, the first etch stop layer exposes more of the top surface of the bottom source / drain plug 106. Correspondingly, after the top source / drain plug is subsequently formed on the top surface of the bottom source / drain plug 106, the contact area between the bottom source / drain plug 106 and the top source / drain plug is larger, thereby improving the electrical connection effect between the bottom source / drain plug 106 and the top source / drain plug, which is beneficial to improving the performance of the semiconductor structure.

[0135] In this embodiment, during the step of providing the substrate, the depth of the opening 109 is 5 nanometers to 40 nanometers.

[0136] It should be noted that the depth of the opening 109 should not be too large or too small. If the depth of the opening 109 is too large, it increases the difficulty of filling the first etch stop layer formed on the sidewall of the opening 109; if the depth of the opening 109 is too small, it can easily lead to the first etch stop layer being too shallow, affecting the alignment accuracy between the top source / drain plug and the corresponding bottom source / drain plug 106, as well as the alignment accuracy between the gate plug and the corresponding gate structure 103, during the subsequent formation of the gate plug and top source / drain plug, thereby affecting the semiconductor performance. Therefore, in this embodiment, the depth of the opening 109 is 5 nanometers to 40 nanometers. For example, the depth of the opening 109 is 10 nanometers, 20 nanometers, or 30 nanometers.

[0137] refer to Figures 12 to 14 A first etching stop layer 151 is formed on the sidewall of the opening 109 (e.g., Figure 14 (As shown).

[0138] Subsequent processes include: forming a second interlayer dielectric layer covering the first interlayer dielectric layer 105, the first etch stop layer 151, and the bottom source / drain plug 106; etching the second interlayer dielectric layer and the first interlayer dielectric layer 105 to form a gate contact hole between adjacent first etch stop layers 151, the gate contact hole being used to form a gate plug; etching the second interlayer dielectric layer to form a source / drain contact hole between adjacent first etch stop layers 151, the source / drain contact hole being used to form a top source / drain plug. By forming a first etch stop layer 151 on the sidewall of the opening 109, during the subsequent formation of the source / drain contact holes and the gate contact holes, the etching rate of the first interlayer dielectric layer 105 and the second interlayer dielectric layer is much greater than the etching rate of the first etch stop layer 151. Through the first etch stop layer 151, self-alignment can be achieved during the formation of the gate contact holes and the source / drain contact holes. This is beneficial to improving the positional accuracy of the gate contact holes and the source / drain contact holes, thereby simultaneously improving the alignment accuracy of the top source / drain plug and the corresponding bottom source / drain plug 106, as well as the alignment accuracy of the gate plug and the corresponding gate structure 103, thereby improving the performance of the semiconductor structure.

[0139] like Figure 12 As shown, after forming the opening 109 and before forming the first etch stop layer 151, the method further includes: etching back a portion of the thickness of the bottom source drain plug 106 at the bottom of the opening 109 to form a groove 161, the top of the groove 161 being connected to the bottom of the opening 109.

[0140] The groove 161 provides space for the subsequent formation of the second etch stop layer.

[0141] In this embodiment, during the step of etching back a portion of the thickness of the bottom source drain plug 106 at the bottom of the opening 109, the depth of the groove 161 is 5 nanometers to 25 nanometers.

[0142] It should be noted that the depth of the groove 161 should not be too large or too small. If the depth of the groove 161 is too large, the second etch stop layer 152 in the groove may become too large, increasing the difficulty of etching the second etch stop layer 152 in the subsequent process of forming the top source / drain plug. If the depth of the groove 161 is too small, the second etch stop layer 152 may become too small, increasing the probability of over-etching in the subsequent process of forming the top source / drain plug, that is, increasing the probability of the bottom source / drain plug being over-etched, and correspondingly increasing the probability of short-circuiting between the gate structure 103 and the top source / drain plug. Therefore, in this embodiment, the depth of the groove 161 is 5 nanometers to 25 nanometers. For example, the depth of the groove 161 is 10 nanometers, 15 nanometers, or 20 nanometers.

[0143] In this embodiment, the step of forming the first etching stop layer 151 on the sidewall of the opening 109 includes: as follows Figure 13 As shown, an etch stop material layer 131 is formed at the bottom and sidewalls of the opening 109, and at the top of the first interlayer dielectric layer 105; as Figure 14 As shown, the etching stop material layer 131 at the top of the first interlayer dielectric layer 105 and the bottom of the opening 109 is removed, and the remaining etching stop material layer 131 located on the sidewall of the opening 109 is retained as the first etching stop layer 151.

[0144] The etching stop material layer 131 provides the technological basis for forming the first etching stop layer 151.

[0145] In this embodiment, the etch stop material layer 131 is formed using atomic layer deposition (ALD). In other embodiments, the etch stop material layer may also be formed using chemical vapor deposition (CVD).

[0146] It should be noted that, in the step of forming the first etch stop layer 151, the etch stop material layer 131 is also filled in the groove 161 to form a second etch stop layer 152 located in the groove 161.

[0147] In this embodiment, during the step of forming an etch stop material layer 131 at the bottom and sidewalls of the opening 109 and at the top of the first interlayer dielectric layer 105, the etch stop material layer 131 also fills the groove 161. Specifically, the etch stop material layer 131 covers not only the bottom and sidewalls of the opening 109 but also the bottom and sidewalls of the groove 161, and the etch stop material layers 131 on opposite sidewalls of the groove 161 are in contact, thereby completely filling the groove 161. Consequently, this results in a relatively large thickness of the etch stop material layer 131 in the groove 161. Therefore, after removing the etch stop material layer 131 from the top of the first interlayer dielectric layer 105 and the bottom of the opening 109, the etch stop material layer 131 in the groove 161 can be retained.

[0148] The second etching stop layer 152 can act as an etching stop layer during the subsequent formation of source / drain contact holes, thereby protecting the top surface of the bottom source / drain plug 106.

[0149] In this embodiment, an anisotropic dry etching process (e.g., plasma dry etching process) is used to remove the etching stop material layer 131 at the top of the first interlayer dielectric layer 105 and the bottom of the opening 109, thereby allowing the etching stop material layer 131 in the sidewall of the opening 109 and the groove 161 to be retained.

[0150] It should be noted that in the process of removing the etch stop material layer 131 at the top of the first interlayer dielectric layer 105 and the bottom of the opening 109, the spin-coating photoresist and masking processes are omitted. That is, a maskless method is adopted, and the plasma dry etching process is used to directly react with the etch stop material layer 131 to remove the etch stop material layer 131 at the top of the first interlayer dielectric layer 105 and the bottom of the opening 109.

[0151] refer to Figure 15 A second interlayer dielectric layer 110 is formed covering the first interlayer dielectric layer 105, the first etch stop layer 151, and the bottom source / drain plug 106.

[0152] The second interlayer dielectric layer 110 provides space for forming gate contact holes and source / drain contact holes, and also serves to achieve electrical isolation between the subsequently formed gate plug and the top source / drain plug.

[0153] In this embodiment, the second interlayer dielectric layer 110 ensures that the heights of the gate plug and the top source / drain plug meet the process requirements.

[0154] The material of the second interlayer dielectric layer 110 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 110 is silicon oxide.

[0155] refer to Figures 16 to 17 The second interlayer dielectric layer 110 and the first interlayer dielectric layer 105 are etched to form a gate contact hole 160 between adjacent first etch stop layers 151, exposing the gate structure 103. The gate contact hole 160 is used to form a gate plug. The second interlayer dielectric layer 110 is etched to form a source drain contact hole 171 between adjacent first etch stop layers 151, exposing the bottom source drain plug 106. The source drain contact hole 171 is used to form a top source drain plug 119.

[0156] It should be noted that the reference Figure 16 After forming the second interlayer dielectric layer 110 and before forming the gate contact hole 160 and the top source / drain plug 119, the method further includes: forming a patterned hard mask layer 112, the opening 111 of which exposes the second interlayer dielectric layer 110 above the top of the gate structure 103 and the second interlayer dielectric layer 110 above the top of the bottom source / drain plug 106.

[0157] Specifically, in this embodiment, the hard mask layer 112 is used to form a gate contact hole 160 that exposes the gate structure 103 and a source / drain contact hole 171 that exposes the bottom source / drain plug 106.

[0158] In this embodiment, the material of the hard mask layer 112 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiOx), tantalum oxide, and tungsten-carbon composite materials.

[0159] It should be noted that the process of forming the gate contact hole 160 also includes etching the third etch stop layer 104 on the top of the gate structure 103.

[0160] In this embodiment, the step of forming the gate contact hole 160 includes: using the hard mask layer 112 as a mask, etching the interlayer dielectric layer 110 and the first interlayer dielectric layer 105 until an initial gate contact hole (not shown) is formed that exposes the third etch stop layer 104; etching away the third etch stop layer 104 exposed by the initial gate contact hole to form the gate contact hole 160.

[0161] It should be noted that in the step of forming the source / drain contact hole 171 exposing the bottom source / drain plug 106 between adjacent first etch stop layers 151, the second etch stop layer 152 is also etched after the second interlayer dielectric layer 110 is etched.

[0162] In this embodiment, the step of forming the source / drain contact hole 171 includes: using the hard mask layer 112 as a mask, etching the interlayer dielectric layer 110 until an initial source / drain contact hole (not shown) is formed that exposes the second etch stop layer 152; etching away the second etch stop layer 152 exposed by the initial source / drain contact hole, and forming a source / drain contact hole 171 that exposes the bottom source / drain plug 106 between adjacent first etch stop layers 151.

[0163] In this embodiment, a dry etching process is used to remove the second interlayer dielectric layer 110 and the first interlayer dielectric layer 105 on the top of the gate structure 103 to form a gate contact hole 160 exposing the gate structure 103; a dry etching process is also used to remove the second interlayer dielectric layer 110 on the top of the bottom source / drain plug 106 to form a source / drain contact hole 171 exposing the bottom source / drain plug 106.

[0164] The dry etching process has anisotropic etching characteristics, which is beneficial for precisely controlling the size and sidewall morphology of the gate contact hole 160 and the source / drain contact hole 171.

[0165] Specifically, in this embodiment, the gate contact hole 160 and the source / drain contact hole 171 are formed in the same step. During the formation of the gate contact hole 160, the third etch stop layer 104 on the top of the gate structure 103 is used as the etch stop position. During the formation of the source / drain contact hole 171, the second etch stop layer 152 on the top of the bottom source / drain plug 106 is used as the etch stop position.

[0166] It should be noted that after forming the gate contact hole 160 and the source / drain contact hole 171, the process also includes removing the hard mask layer 112.

[0167] It should also be noted that, in other embodiments, depending on process requirements, the gate contact hole and the source / drain contact hole may be formed in different steps respectively.

[0168] refer to Figure 18 The forming method further includes: forming a gate plug 118 in the gate contact hole 160 and forming a top source / drain plug 119 in the source / drain contact hole 171.

[0169] Gate plug 118 is used to realize the electrical connection between gate structure 103 and external circuitry or other interconnection structures.

[0170] The top source / drain plug 119 and the bottom source / drain plug 106 constitute a source / drain plug, thereby enabling the electrical connection of the source / drain doped layer 107 with other interconnect structures or external circuits.

[0171] Specifically, after filling the gate contact hole 160 and the source / drain contact hole 171 with conductive material, the conductive material is planarized, and the conductive material in the gate contact hole 160 is retained as the gate plug 118, and the conductive material in the source / drain contact hole 171 is retained as the top source / drain plug 119.

[0172] Figures 19 to 21 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention.

[0173] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0174] like Figure 20 As shown, during the formation of the first etch stop layer 251, after the formation of the etch stop material layer 231 and before the formation of the first etch stop layer 251, a protective layer 209 is also formed in the remaining opening (not shown).

[0175] Specifically, refer to Figure 21 The step of forming the first etch stop layer 251 includes: as follows Figure 20 An etch stop material layer 231 is formed at the bottom and sidewalls of the opening and at the top of the first interlayer medium 205; after forming the etch stop material layer 231, a protective layer 209 is formed in the remaining opening; as shown Figure 21 As shown, with the top of the first interlayer dielectric layer 205 as the stop position, the etching stop material layer 231 and the protective layer 209 are planarized, the etching stop material layer 231 and the protective layer 209 above the top of the first interlayer dielectric layer 205 are removed, and the remaining etching stop material layer 231 on the opening sidewall is retained as the first etching stop layer 251.

[0176] refer to Figures 19 to 20 The step of forming the protective layer 209 includes: forming a protective material layer 208 covering the etching stop material layer 231; taking the top of the etching stop material layer 231 as the stop position, performing planarization on the protective material layer 208, removing the protective material layer 208 above the top of the etching stop material layer 231, and retaining the remaining protective material layer 208 in the opening as the protective layer 209.

[0177] By first using the top of the etching stop material layer 231 as the stop position to planarize the protective material layer 208, it is beneficial to make the top surfaces of the protective layer 209 and the etching stop material layer 231 flush, so that the etching stop material layer 231 and the protective layer 209 can be planarized simultaneously in the future, thereby making the top surface of the first etching stop layer 251 a plane.

[0178] The protective layer 209 protects the top surface of the first etch stop layer during the subsequent formation of the first etch stop layer, thereby improving the flatness of the top surface of the first etch stop layer.

[0179] In this embodiment, the planarization process includes one or both of chemical mechanical polishing and dry etching.

[0180] As an example, the planarization process is a chemical mechanical polishing (CMP) process. The CMP process is characterized by high polishing efficiency and high surface smoothness, and can achieve a relatively smooth surface on the protective layer 209 while ensuring the removal of the protective material layer 208.

[0181] The protective layer 209 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the protective layer 209 is made of silicon oxide.

[0182] It should be noted that during the formation of the first etch stop layer 251, under the protection of the protective layer 209, the etch stop material layer 231 at the bottom of the opening is retained. Therefore, the etch stop material layer 231 remaining at the bottom of the opening serves as the bottom residual layer 252.

[0183] Accordingly, the bottom residual layer 252 covers the second etch stop layer (not shown) located in the groove (not shown).

[0184] For ease of illustration, Figure 21 The interface between the second etch stop layer and the bottom residual layer 252 is represented by a dashed line.

[0185] The bottom residual layer 252 will be removed during the subsequent formation of the source / drain contact hole.

[0186] Figures 22 to 23 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention.

[0187] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0188] refer to Figure 22 After the opening 309 is formed, the bottom source drain plug 306 at the bottom of the opening 309 is not etched back. Instead, an etch stop material layer 331 is formed directly on the bottom and sidewalls of the opening 309 and on the top of the first interlayer dielectric layer 305.

[0189] In this embodiment, the etching stop material layer 331 is formed using atomic layer deposition (ALD).

[0190] refer to Figure 23 A first etching stop layer 351 is formed on the sidewall of the opening 309.

[0191] In this embodiment, the etching stop material layer 331 is etched using a dry etching process to remove the etching stop material layer 331 located at the top of the first interlayer dielectric layer 305 and the bottom of the opening 309, thereby forming the first etching stop layer 351.

[0192] For a detailed description of the formation method described in this embodiment, please refer to the relevant description in the first embodiment. This embodiment will not repeat the description here.

[0193] Figures 24 to 26 This is a schematic diagram of the structure corresponding to each step in the fourth embodiment of the semiconductor structure formation method of the present invention.

[0194] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0195] This embodiment omits the step of forming the groove.

[0196] In addition, refer to Figures 25 to 26 The step of forming the first etch stop layer 451 includes: forming an etch stop material layer 431 at the bottom and sidewall of the opening (not shown) and at the top of the first interlayer dielectric layer 405; after forming the etch stop material layer 431, forming a protective layer 409 in the remaining opening; taking the top of the first interlayer dielectric layer 405 as the stop position, planarizing the etch stop material layer 431 and the protective layer 409, removing the etch stop material layer 431 and the protective layer 409 above the top of the first interlayer dielectric layer 405, and retaining the remaining etch stop material layer 431 on the sidewall of the opening as the first etch stop layer 451.

[0197] It should be noted that after planarization of the etching stop material layer 431 and the protective layer 409, the etching stop material layer 431 remaining at the bottom of the opening is used as the bottom residual layer 452.

[0198] The bottom residual layer 452 will be removed during the subsequent formation of the source / drain contact hole.

[0199] Furthermore, during the subsequent formation of source / drain contact holes, the bottom residual layer 452 can act as an etch stop layer. Since a third etch stop layer is formed on the top of the gate structure, the source / drain contact holes and the gate contact holes can be formed in the same step, thereby simplifying the process steps.

[0200] refer to Figures 24 to 25 The step of forming the protective layer 409 includes: forming a protective material layer 408 covering the etching stop material layer 431; taking the top of the etching stop material layer 431 as the stop position, performing planarization treatment on the protective material layer 408, removing the protective material layer 408 above the top of the etching stop material layer 431, and retaining the remaining protective material layer 408 in the opening as the protective layer 409.

[0201] By first using the top of the etching stop material layer 431 as the stop position to planarize the protective material layer 408, it is beneficial to make the top surfaces of the protective layer 409 and the etching stop material layer 431 flush, so that the etching stop material layer 431 and the protective layer 409 can be planarized simultaneously in the future, thereby making the top surface of the first etching stop layer 451 a plane.

[0202] During the formation of the first etch stop layer 451, the protective layer 409 protects the top surface of the first etch stop layer 451 and improves the flatness of the top surface of the first etch stop layer 451.

[0203] In this embodiment, the planarization process includes one or both of chemical mechanical polishing and dry etching.

[0204] As an example, the planarization process is a chemical mechanical polishing process, which has the advantages of high polishing efficiency and high surface flatness. It can make the surface of the protective layer 409 relatively flat while ensuring the removal of the protective material layer 408.

[0205] The protective layer 409 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the protective layer 409 is made of silicon oxide.

[0206] For a detailed description of the formation method described in this embodiment, please refer to the relevant description in the first embodiment. This embodiment will not repeat the description here.

[0207] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure. A bottom source / drain plug electrically connected to the source / drain doped layers is formed between adjacent gate structures. A first interlayer dielectric layer covering the gate structure is formed on the substrate. An opening is formed in the first interlayer dielectric layer that exposes the top of the bottom source / drain plug. The first etch stop layer is located on the sidewall of the opening; The second interlayer dielectric layer is located on top of the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug; A gate plug extends through the first interlayer dielectric layer between the second interlayer dielectric layer and the adjacent first etch stop layer, and the bottom of the gate plug is connected to the gate structure; A top source / drain plug extends through the second interlayer dielectric layer between adjacent first etch stop layers, and the bottom of the top source / drain plug is connected to the bottom source / drain plug.

2. The semiconductor structure as described in claim 1, characterized in that, The sidewall of the opening protrudes relative to the sidewall of the bottom source drain plug.

3. The semiconductor structure as described in claim 2, characterized in that, The bottom of the opening is higher than the top of the gate structure; The semiconductor structure further includes: a groove located between the opening and the bottom source / drain plug, the top of the groove being connected to the bottom of the opening, and the sidewalls of the groove being flush with the sidewalls of the bottom source / drain plug; and a second etch stop layer located in the groove, the second etch stop layer being made of the same material as the first etch stop layer. The top source drain plug also penetrates the second etch stop layer.

4. The semiconductor structure as described in claim 3, characterized in that, The bottom of the groove is lower than or flush with the top of the gate structure.

5. The semiconductor structure as described in claim 3, characterized in that, The depth of the groove is 5 nanometers to 25 nanometers.

6. The semiconductor structure as described in claim 3, characterized in that, The depth of the opening is 5 nanometers to 40 nanometers.

7. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a bottom residual layer located at the bottom of the opening and connected to the first etch stop layer; A protective layer is located in the opening and covers the bottom residual layer, and the top of the protective layer is flush with the top of the first etch stop layer; The top source drain plug also penetrates the protective layer and the bottom residual layer.

8. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a third etch stop layer located between the top of the exposed gate structure of the gate plug and the first interlayer dielectric layer.

9. The semiconductor structure as described in claim 2, characterized in that, The sidewall of the opening protrudes from the sidewall of the bottom source / drain plug by an amount of 2 to 10 nanometers.

10. The semiconductor structure as claimed in claim 1, characterized in that, With the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure as the lateral direction, the lateral dimension of the first etch stop layer is 2 nanometers to 10 nanometers.

11. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first etch stop layer includes one or more of silicon nitride, silicon carbide, silicon carbide, or silicon nanocarbide.

12. The semiconductor structure as claimed in claim 7, characterized in that, The material of the protective layer includes silicon oxide.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure. A bottom source / drain plug electrically connected to the source / drain doped layers is formed between adjacent gate structures. A first interlayer dielectric layer covering the gate structure is formed on the substrate, and an opening is formed in the first interlayer dielectric layer exposing the top of the bottom source / drain plug. A first etching stop layer is formed on the sidewall of the opening; A second interlayer dielectric layer is formed covering the first interlayer dielectric layer, the first etch stop layer, and the bottom source / drain plug; The second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a gate contact hole that exposes the gate structure between adjacent first etch stop layers. The gate contact hole is used to form a gate plug. The second interlayer dielectric layer is etched to form a source / drain contact hole between adjacent first etch stop layers, exposing the bottom source / drain plug. The source / drain contact hole is used to form the top source / drain plug.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the opening, the sidewall of the opening protrudes relative to the sidewall of the bottom source drain plug.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of providing the substrate, the top of the bottom source / drain plug is higher than the top of the gate structure; After forming the opening and before forming the first etch stop layer, the method further includes: etching back a portion of the thickness of the bottom source drain plug at the bottom of the opening to form a groove, the top of the groove being connected to the bottom of the opening; In the step of forming the first etch stop layer, the material of the first etch stop layer is also filled into the groove to form a second etch stop layer located in the groove; In the step of forming source / drain contact holes exposing the bottom source / drain plugs between adjacent first etch stop layers, the second etch stop layer is etched after the second interlayer dielectric layer is etched.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, In the step of etching back a portion of the thickness of the bottom source drain plug at the bottom of the opening, the depth of the groove is 5 nanometers to 25 nanometers.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, In the step of providing the substrate, the depth of the opening is 5 nanometers to 40 nanometers.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, Prior to forming the opening, the bottom source / drain plug penetrates the first interlayer dielectric layer between adjacent gate structures; The step of forming the opening includes: etching back a portion of the thickness of the bottom source / drain plug to form an initial opening surrounded by the first interlayer dielectric layer and the top of the bottom source / drain plug; Laterally etch the sidewalls of the initial opening.

19. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the first etch stop layer includes: forming an etch stop material layer at the bottom and sidewall of the opening and at the top of the first interlayer dielectric layer; removing the etch stop material layer at the top of the first interlayer dielectric layer and at the bottom of the opening, and retaining the remaining etch stop material layer at the sidewall of the opening as the first etch stop layer.

20. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the first etch stop layer includes: forming an etch stop material layer at the bottom and sidewalls of the opening and at the top of the first interlayer dielectric layer; after forming the etch stop material layer, forming a protective layer in the remaining opening; taking the top of the first interlayer dielectric layer as the stop position, planarizing the etch stop material layer and the protective layer, removing the etch stop material layer and the protective layer above the top of the first interlayer dielectric layer, and retaining the remaining etch stop material layer on the sidewalls of the opening as the first etch stop layer.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The step of forming the protective layer includes: forming a protective material layer covering the etch stop material layer; using the top of the etch stop material layer as the stop position, planarizing the protective material layer, removing the protective material layer above the top of the etch stop material layer, and retaining the remaining protective material layer in the opening as the protective layer.

22. The method for forming a semiconductor structure as described in claim 20 or 21, characterized in that, The planarization process includes one or both of chemical mechanical polishing and dry etching.

23. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, a third etch stop layer is also formed between the top of the gate structure and the first interlayer dielectric layer.

Images