Semiconductor device structure with manganese-containing conductive plugs and method of making the same

Abstract

The present disclosure provides a semiconductor device structure with manganese-containing conductive plugs and a method of fabricating the same. The semiconductor device structure has a first conductive layer disposed on a semiconductor substrate and a dielectric layer disposed on the first conductive layer. The semiconductor device structure also has a first conductive plug penetrating the dielectric layer and located in a pattern dense region and a liner layer covering the dielectric layer and the first conductive plug. The liner layer and the first conductive plug contain manganese. The semiconductor device structure further has a second conductive plug penetrating the liner layer and the dielectric layer and located in a pattern sparse region. The second conductive plug is separated from the dielectric layer by a portion of the liner layer. In addition, the semiconductor device structure has a second conductive layer covering the liner layer and the second conductive plug.

Description

[0001] CROSS-REFERENCE

[0002] The present disclosure claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 115,330, filed December 8, 2020, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device structure and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device structure having a manganese-containing conductive plug and a method of fabricating the same. BACKGROUND

[0004] Semiconductor devices are indispensable for many modern applications. As electronic technology advances, semiconductor devices become smaller in size while providing better functionality and including larger numbers of integrated circuits. Due to the miniaturization of semiconductor devices, different forms and sizes of semiconductor devices that implement different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed on the integration of semiconductor devices of various forms.

[0005] However, the fabrication and integration of semiconductor devices include many complex steps and operations. The integration in semiconductor devices becomes more complex. The increase in complexity of the fabrication and integration of semiconductor devices can cause defects, such as voids formed in conductive structures, which are caused by the difficulty in filling high aspect ratio openings. Accordingly, there is a continuing need to improve the fabrication process of semiconductor devices in order to address the defects and to enhance their performance.

[0006] The above description of background art is provided merely for purposes of background information and does not constitute an admission as prior art to the present disclosure. Any acknowledgement of the above background art does not constitute any admission as to whether or not any of the above background art is widely known. SUMMARY

[0007] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate, and a dielectric layer disposed on the first conductive layer. The semiconductor device structure also has a first conductive plug penetrating the dielectric layer and located in a pattern dense region, and a liner layer covering the liner layer and the first conductive layer. The liner layer and the first conductive plug include manganese. The semiconductor device structure further has a second conductive plug penetrating the liner layer and the dielectric layer and located in a pattern sparse region. The second conductive plug is separated from the dielectric layer by a portion of the liner layer. In addition, the semiconductor device structure has a second conductive layer covering the liner layer and the second conductive plug.

[0008] In some embodiments, the liner layer directly contacts the first conductive plug and includes a same material as the first conductive plug. In some embodiments, the liner layer and the first conductive plug include copper manganese (CuMn). In some embodiments, the first conductive plug and the second conductive plug include different materials. In some embodiments, the second conductive layer directly contacts the second conductive plug, and the second conductive layer and the second conductive plug include copper.

[0009] In some embodiments, the semiconductor device structure further includes an energy removable structure disposed in the pattern dense region and adjacent to the first conductive plug, wherein the energy removable structure is disposed between the liner layer and the first conductive layer. In some embodiments, the semiconductor device structure further includes an air gap surrounded by the energy removable structure.

[0010] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate, and a second conductive layer disposed on the first conductive layer. The semiconductor device structure also has a plurality of first conductive plugs disposed in a pattern dense region and between the first conductive layer and the second conductive layer, and a plurality of second conductive plugs disposed in a pattern sparse region and between the first conductive layer and the second conductive layer. The semiconductor device structure further has an energy removable structure disposed between the plurality of first conductive plugs. An air gap is surrounded by the energy removable structure. In addition, the semiconductor device structure has a liner layer disposed between the plurality of first conductive plugs and the second conductive layer. The liner layer and the plurality of first conductive plugs include manganese.

[0011] In some embodiments, the liner layer and the first plurality of conductive plugs comprise a first material, the second plurality of conductive plugs and the second conductive layer comprise a second material, and the first material is different from the second material. In some embodiments, the first material is copper manganese and the second material is copper. In some embodiments, the semiconductor device structure further comprises a dielectric layer disposed between the first conductive layer and the second conductive layer, wherein the second plurality of conductive plugs is surrounded by the dielectric layer, the liner layer extends between the dielectric layer and the second conductive layer, and each second conductive plug is separated from the dielectric layer by the liner layer.

[0012] In some embodiments, a first distance between adjacent pairs of the first plurality of conductive plugs is less than a second distance between adjacent pairs of the second plurality of conductive plugs. In some embodiments, the first plurality of conductive plugs and the second plurality of conductive plugs are electrically connected to the first conductive layer and the second conductive layer.

[0013] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method of fabricating includes forming a first conductive layer on a semiconductor substrate and forming a dielectric layer on the first conductive layer. The method of fabricating also includes replacing a portion of the dielectric layer with an energy-removable layer and performing an etching process to form a first opening in the energy-removable layer and a second opening in the dielectric layer. The first opening is located in a pattern-dense region and the second opening is located in a pattern-sparse region. The method of fabricating further includes depositing a liner layer on the energy-removable layer and the dielectric layer. The liner layer completely fills the first opening to form a first conductive plug and the liner layer partially fills the second opening. In addition, the method of fabricating includes forming a second conductive plug in a remaining portion of the second opening and forming a second conductive layer on the liner layer and the second conductive plug.

[0014] In some embodiments, a width of the first opening is less than a width of the second opening. In some embodiments, the etching process further includes forming a third opening in the pattern-dense region and adjacent to the first opening and forming a fourth opening in the pattern-sparse region and adjacent to the second opening, wherein a distance between the first opening and the third opening is less than a distance between the second opening and the fourth opening. In some embodiments, the first conductive plug comprises copper manganese and the second conductive plug comprises copper.

[0015] In some embodiments, the method further comprises partially removing the liner layer in the second via to expose the first conductive layer prior to forming the second conductive plug. In some embodiments, the second conductive plug is formed simultaneously with the second conductive layer in the same processing step. In some embodiments, the method further comprises performing a thermal treatment process to partially convert the energy-removable layer into an air gap after forming the second conductive layer.

[0016] Some embodiments of the present disclosure provide a semiconductor device structure and a method of fabricating the same. In some embodiments, the semiconductor device structure has a first conductive plug, a liner layer, and a second conductive plug; the first conductive plug penetrates through a dielectric layer and is located in a pattern-dense region; the liner layer covers the dielectric layer and the first conductive plug; the second conductive plug penetrates through the liner layer and the dielectric layer and is located in a pattern-sparse region. The liner layer and the first conductive plug contain manganese. The second conductive plug is separated from the dielectric layer by the liner layer. The manganese-containing conductive plug (e.g., the first conductive plug located in the pattern-dense region) and the liner layer can be monolithically formed, thereby reducing fabrication cost. Further, the liner layer can reduce or avoid the formation of voids in the subsequently formed conductive plug (e.g., the second conductive plug located in the pattern-sparse region), thereby reducing contact resistance. As a result, the operating speed of the semiconductor device structure can be improved, which significantly improves overall device performance.

[0017] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technical features and advantages of the present disclosure. Those skilled in the art will appreciate that the conception, upon which, the disclosure is based, can be readily utilized as the basis for the designing of other structures or processes, or in the carrying or a substantially similar industries. Those skilled in the art will realize that equivalent constructions do not depart from the spirit and scope of the present disclosure, set forth in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0018] The disclosed subject matter can be more fully understood with reference to the figures and

[0019] FIG. 1 A cross-sectional schematic view of a semiconductor device structure according to some embodiments of the present disclosure.

[0020] FIG. 2 A flowchart of a method of fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0021] FIG. 3A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a first conductive layer and a dielectric layer sequentially on a semiconductor substrate.

[0022] FIG. 4 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, etching the dielectric layer.

[0023] FIG. 5 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming an energy-removable layer.

[0024] FIG. 6 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, partially removing the energy-removable layer.

[0025] FIG. 7 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a patterned mask on the energy-removable layer and the dielectric layer.

[0026] FIG. 8 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, etching the energy-removable layer and the dielectric layer.

[0027] FIG. 9 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, removing the patterned mask.

[0028] FIG. 10 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, depositing a liner layer and forming a plurality of first conductive plugs.

[0029] FIG. 11 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a patterned mask on the liner layer.

[0030] FIG. 12 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, partially removing the liner layer to expose the first conductive layer.

[0031] FIG. 13A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, removing the patterned mask.

[0032] FIG. 14 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a second conductive layer.

[0033] FIG. 15 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a dielectric layer on the second conductive layer.

[0034] FIG. 16 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, etching the dielectric layer.

[0035] FIG. 17 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a liner layer.

[0036] FIG. 18 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a liner layer.

[0037] FIG. 19 A cross-sectional schematic view illustrating an intermediate stage of some embodiments of the disclosure, where the intermediate stage is during formation of the semiconductor element structure, forming a first conductive structure, a second conductive structure, and a third conductive structure.

[0038] FIG. 20 A partial structure schematic view of an example integrated circuit having an array of memory cells of some embodiments of the disclosure.

[0039] BRIEF DESCRIPTION OF DRAWINGS

[0040] 10: fabrication method

[0041] 50: memory cell

[0042] 51: field effect transistor

[0043] 53: capacitor

[0044] 55: drain

[0045] 57: source

[0046] 59: gate

[0047] 100: semiconductor element structure

[0048] 101: semiconductor substrate

[0049] 103: first conductive layer

[0050] 105: dielectric layer

[0051] 110: aperture

[0052] 113: energy-removable layer

[0053] 113': energy-removable structure

[0054] 115: patterned mask

[0055] 120a: aperture

[0056] 120b: aperture

[0057] 123: spacer layer

[0058] 123a: first conductive plug

[0059] 125: patterned mask

[0060] 127: second conductive plug

[0061] 129: second conductive layer

[0062] 131: dielectric layer

[0063] 140a: aperture

[0064] 140b: aperture

[0065] 143: spacer layer

[0066] 145: spacer layer

[0067] 147a: first conductive structure

[0068] 147b: second conductive structure

[0069] 149: third conductive layer

[0070] 160: air gap

[0071] 1000: memory element

[0072] A: pattern dense region

[0073] B: pattern sparse region

[0074] BL: bit line

[0075] D1: distance

[0076] D2: distance

[0077] D3: distance

[0078] D4: distance

[0079] D5: depth

[0080] D6: depth

[0081] H1: height

[0082] H2: height

[0083] S11: step

[0084] S13: step

[0085] S15: step

[0086] S17: step

[0087] S19: step

[0088] S21: step

[0089] S23: step

[0090] S25: step

[0091] S27: step

[0092] W1: width

[0093] W2: width

[0094] W3: width

[0095] W4: width

[0096] W5: width

[0097] W6: width

[0098] WL: word line DETAILED DESCRIPTION

[0099] The following description describes specific examples of components and configurations to simplify the present disclosure. These specific examples are merely intended to provide examples for discussion and are not intended to limit the scope of the present disclosure. For example, when a first component is described as being formed on a second component, the example can include embodiments where the first and second components are formed in direct contact with each other, or embodiments where one or more additional components are formed between the first and second components such that the first and second components do not directly contact each other. In addition, embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless specifically described in the context, it does not inherently represent a specific relationship between various embodiments and / or configurations discussed.

[0100] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0101] FIG. 1 A cross-sectional schematic diagram illustrating a semiconductor device structure 100 according to some embodiments of this disclosure is shown. FIG. 1 As shown, according to some embodiments, the semiconductor device structure 100 includes a first conductive layer 103 disposed on a semiconductor substrate 101; a dielectric layer 105 disposed on the first conductive layer 103; a second conductive layer 129 disposed on the dielectric layer 105; a dielectric layer 131 disposed on the second conductive layer 129; and a third conductive layer 149 disposed on the dielectric layer 131. Furthermore, the semiconductor device structure 100 has a pattern-dense region A and a pattern-loose region B. To make this disclosure clear, in... FIG. 1 The dashed line in the middle is used to represent the boundary between the dense pattern area A and the sparse pattern area B.

[0102] In some embodiments, the semiconductor device structure 100 has a plurality of first conductive plugs 123a that pass through the dielectric layer 105 and are located in the patterned dense region A. Furthermore, the semiconductor device structure 100 has a plurality of energy-removable structures 113' disposed in the dielectric layer 105 and in the patterned dense region A. In some embodiments, the plurality of first conductive plugs 123a are surrounded by energy-removable structures 113', and each energy-removable structure 113' has an air gap 160.

[0103] In some embodiments, the air gap 160 is surrounded by an energy-removable structure 113'. Although FIG. 1 The cross-sectional schematic shows four energy-removable structures 113', but in different cross-sectional schematics, the four energy-removable structures 113' are interconnected. Similar to the energy-removable structure 113', in... FIG. 1 The four air gaps 160 shown in the cross-sectional view can also be interconnected in different cross-sectional views. It should be understood that the number of energy-removable structures 113' and air gaps 160 can be adjusted according to the design requirements of the semiconductor device structure 100.

[0104] Reference is still made to FIG. 1 The semiconductor device structure 100 includes a liner layer 123 disposed between the dielectric layer 105 and the second conductive layer 129, and the energy-removable structure 113' and the first conductive plug 123a are covered by the liner layer 123. In some embodiments, the dashed lines representing the first conductive plug 123a and the liner layer 123 are used to clarify the present disclosure. There is no distinct interface between the first conductive plug 123a and the liner layer 123.

[0105] The semiconductor device structure 100 also includes a plurality of second conductive plugs 127 extending through the liner layer 123 and the dielectric layer 105 and located in the pattern-sparse region B. In some embodiments, in the pattern-sparse region B, the liner layer 123 extends between the dielectric layer 105 and the second conductive plugs 127. In some embodiments, the second conductive plugs 127 are separated from the dielectric layer 105 by the liner layer 123.

[0106] Further, the semiconductor device structure 100 has a liner layer 143, a liner layer 145, a first conductive structure 147a, and a second conductive structure 147b disposed between the second conductive layer 129 and a third conductive layer 149. In some embodiments, the first conductive structure 147a is located in the pattern-dense region A, and the second conductive structure 147b is located in the pattern-sparse region B. In some embodiments, a portion of the liner layers 143 and 145 is disposed between the dielectric layer 131 and the third conductive layer 149. In some embodiments, the liner layer 145 is disposed on the liner layer 143, and sidewalls and bottom surfaces of the first conductive structure 147a and the second conductive structure 147b are covered by the liner layer 145.

[0107] In some embodiments, the semiconductor device structure 100 is a dynamic random access memory (DRAM). In these examples, the plurality of conductive layers (e.g., the first conductive layer 103, the second conductive layer 129, and the third conductive layer 149) can function as bit lines (BLs), storage nodes, and / or wiring layers of the DRAM; and the plurality of conductive plugs (e.g., the first conductive plug 123a and the second conductive plugs 127) and the plurality of conductive structures (e.g., the first conductive structure 147a and the second conductive structure 147b) can function as bit line contact plugs, capacitor contact plugs, and / or interconnect structures of the DRAM.

[0108] In some embodiments, the first conductive plug 123a in the pattern dense region A is integrally formed with the liner layer 123. In some embodiments, the first conductive plug 123a and the liner layer 123 comprise the same material, and the first conductive plug 123a and the second conductive plug 127 comprise different materials. In some embodiments, the first conductive plug 123a and the liner layer 123 comprise a manganese-containing material.

[0109] For example, according to some embodiments, the liner layer 123 and the first conductive plug 123a both comprise copper manganese (CuMn), and the first conductive layer 103, the second conductive layer 129, and the second conductive plug 127 all comprise copper. In addition, in some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 all comprise copper, the liner layer 143 comprises manganese silicon (MnSi) or manganese-rich, and the liner layer 145 comprises copper manganese.

[0110] FIG. 2 A flowchart of a method 10 of fabricating a semiconductor device structure (e.g., the semiconductor device structure 100) according to some embodiments of the present disclosure is shown. The method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Steps S11 to S27 are described in detail in conjunction with the following figures.

[0111] FIGS. 3-19 Cross-sectional schematic views of various intermediate stages during the formation of the semiconductor device structure 100 according to some embodiments of the present disclosure are shown. As shown in FIG. 1A, a semiconductor substrate 101 is provided. The semiconductor substrate 101 can be a semiconductor wafer, such as a silicon wafer. FIG. 3

[0112] ​Additionally or alternatively, the semiconductor substrate 101 can include an elementary semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of the elementary semiconductor material can include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of the compound semiconductor material can include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of the alloy semiconductor material can include, but are not limited to, silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0113] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer over a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which can include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer. The semiconductor-on-insulator substrate can be, for example, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0114] Still referring to FIG. 3 , according to some embodiments, the first conductive layer 103 is formed over the semiconductor substrate 101, and the dielectric layer 105 is formed over the first conductive layer 103. The individual steps are shown in FIGS. 1A-1C, respectively. FIG. 2Step S11 in preparation method 10 shown.

[0115] In some embodiments, the first conductive layer 103 comprises copper, and the fabrication technique of the first conductive layer 103 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or other applicable processes. In some embodiments, the dielectric layer 105 comprises silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials, and the fabrication technique of the dielectric layer 105 includes a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes.

[0116] Next, as FIG. 4 As shown, according to some embodiments, an etching process is performed on dielectric layer 105 to form an opening 110, which exposes the first conductive layer 103. In some embodiments, the opening 110 is located in a patterned region A. The formation of the opening 110 may include forming a patterned mask (not shown) on dielectric layer 105; and etching dielectric layer 105 using the patterned mask as a mask. Furthermore, the etching process used to form the opening 110 may be a wet etching process, a dry etching process, or a combination thereof.

[0117] Next, as FIG. 5 As shown, according to some embodiments, an energy-removable layer 113 is conformally deposited on the dielectric layer 105. In some embodiments, an opening 110 (see reference) FIG. 4 The sidewalls and lower surface of the ) are covered by an energy-removable layer 113.

[0118] In some embodiments, the material of the energy-removable layer 113 comprises a base material and a biodegradable pore-forming material, which is substantially removed upon exposure to an energy source (i.e., a heat source). In some embodiments, the base material comprises hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous SiO2, while the biodegradable pore-forming material comprises a porogen organic compound that provides porosity to the space otherwise occupied by the energy-removable layer 113 in subsequent processes. Furthermore, the energy-removable layer 113 is deposited using a CVD, PVD, ALD, spin coating, or other suitable process.

[0119] Then, as FIG. 6 As shown, according to some embodiments, a planarization process is performed on the energy-removable layer 113 to remove a portion of the energy-removable layer 113. This planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, or other applicable processes. After the planarization process, the upper surface of the energy-removable layer 113 is substantially coplanar with the upper surface of the dielectric layer 105. In some embodiments, such as FIGS. 4-6 During the intermediate stage shown, a portion of dielectric layer 105 in the densely patterned region A is replaced by energy-removable layer 113, and its individual steps are shown in... FIG. 2 Step S15 in preparation method 10 shown.

[0120] Next, as FIG. 7 As shown, according to some embodiments, a patterned mask 115 is formed on the energy-removable layer 113 and the dielectric layer 105. In some embodiments, portions of the energy-removable layer 113 in the patterned dense region A and portions of the dielectric layer 105 in the patterned sparse region B are exposed by the patterned mask 115.

[0121] Next, as FIG. 8As shown, according to some embodiments, an energy-removable layer 113 and a dielectric layer 105 are etched using a patterned mask 115 as a mask, such that a plurality of openings 120a are formed in the energy-removable layer 113 and a plurality of openings 120b are formed in the dielectric layer 105. In some embodiments, openings 120a are located in a densely patterned region A, and openings 120b are located in a sparsely patterned region B. In some embodiments, the first conductive layer 103 is partially exposed through openings 120a and 120b. The etching process can be a wet etching process, a dry etching process, or a combination thereof. Individual steps are shown in... FIG. 2 Step S17 in preparation method 10 shown.

[0122] like FIG. 9 As shown, according to some embodiments, after the openings 120a and 120b are formed, the patterned mask 115 is removed. In some embodiments, each opening 120a has a width W1, each opening 120b has a width W2, and the width W2 is greater than the width W1. In some embodiments, the widths W1 and W2 are defined as the uppermost widths of the openings 120a and 120b. Furthermore, in some embodiments, each adjacent pair of openings 120a has a distance D1 between them, each adjacent pair of openings 120b has a distance D2 between them, and the distance D2 is greater than the distance D1.

[0123] Next, as FIG. 10 As shown, according to some embodiments, a pad layer 123 is deposited on the energy-removable layer 113 and the dielectric layer 105. It should be understood that the pad layer completely fills the opening 120a, and a portion of the pad layer 123 in the opening 120a forms a first conductive plug 123a. Simultaneously, the pad layer 123 partially fills each opening 120b, such that the remaining portion of the opening 120b is formed on the pad layer 123. Individual steps are shown in... FIG. 2 Step S19 in preparation method 10 shown.

[0124] In some embodiments, since the liner layer 123 and the first conductive plug 123a are integrally formed, the liner layer 123 and the first conductive plug 123a contain the same material, such as a manganese-containing material. In some embodiments, the liner layer 123 and the first conductive plug 123a contain copper-manganese. Furthermore, the fabrication technique of the liner layer may include a deposition process, such as a CVD process, a PVD process, an ALD process, or other applicable processes.

[0125] Next, as FIG. 11 As shown, according to some embodiments, a patterned mask 125 is formed on the padding layer 123. In some embodiments, a portion of the padding layer 123 at the bottom of the opening 120b is exposed by the patterned mask 125.

[0126] Then, as FIG. 12 As shown, according to some embodiments, the pad layer 123 is etched by using a patterned mask 125 as a mask, so that the first conductive layer 103 is partially exposed through the opening 120b. This etching process can be a wet etching process, a dry etching process, or a combination thereof. Individual steps are shown in... FIG. 2 Step S21 in preparation method 10 shown.

[0127] like FIG. 13 As shown, according to some embodiments, after the first conductive layer 103 is partially exposed through the opening 120b in the patterned sparse region B, the patterned mask 125 is removed.

[0128] Next, as FIG. 14 As shown, according to some embodiments, a second conductive plug 127 is formed in an opening 120b located in a pattern sparse region B (see reference). FIG. 13 In this process, a second conductive layer 129 is formed on the liner layer 123 and the second conductive plug 127. In some embodiments, the second conductive plug 127 and the second conductive layer 129 are integrally formed. Individual steps are shown in, for example... FIG. 2 Steps S23 and S25 in preparation method 10 shown.

[0129] In some embodiments, the second conductive plug 127 and the second conductive layer 129 are formed simultaneously in the same processing step, such as a deposition process and a subsequent planarization process. The deposition process may be a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, a plating process, or other applicable processes. The planarization process may include a CMP process, an etch-back process, or other applicable processes. Furthermore, in some embodiments, the second conductive plug 127 and the second conductive layer 129 comprise copper. Additionally, in some embodiments, each adjacent pair of first conductive plugs 123a in the densely patterned region A has a distance D3 between them, and each adjacent pair of second conductive plugs 127 in the sparsely patterned region B has a distance D4 between them, with distance D4 being greater than distance D3.

[0130] Next, as FIG. 15 As shown, according to some embodiments, dielectric layer 131 is formed on second conductive layer 129. Some materials and processes used to form dielectric layer 131 are similar to or the same as those used to form dielectric layer 105, and their detailed descriptions will not be repeated herein.

[0131] Then, as FIG. 16As shown, the dielectric layer 131 is etched to form an opening 140a in the densely patterned region A and an opening 140b in the sparsely patterned region B. In some embodiments, each opening 140a, 140b exposes a portion of the second conductive layer 129. The etching process used to form the openings 140a and 140b may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the opening 140a has a width W3, the opening 140b has a width W4, and the width W4 is greater than the width W3. In some embodiments, the widths W3 and W4 are defined as the uppermost widths of the openings 140a and 140b.

[0132] like FIG. 17 As shown, according to some embodiments, after the openings 140a and 140b are formed, a pad layer 143 is conformally formed on the dielectric layer 131 and covers the sidewalls and lower surfaces of the openings 140a and 140b. In some embodiments, the pad layer 143 comprises manganese silicon (MnSi) or manganese (Mn). The fabrication technique of the pad layer 143 includes a deposition process, such as CVD, PVD, ALD, MOCVD, sputtering, or plating.

[0133] Next, as FIG. 18 As shown, according to some embodiments, the liner layer 145 is conformally deposited on the liner layer 143. In some embodiments, the liner layer 145 comprises copper manganese. Some processes used to form the liner layer 145 are similar to or the same as those used to form the liner layer 143, and their detailed descriptions will not be repeated herein.

[0134] Next, as FIG. 19 As shown, according to some embodiments, a first conductive structure 147a is formed in the remaining portion of the opening 140a, a second conductive structure 147b is formed in the remaining portion of the opening 140b, and a third conductive layer 149 is formed on the pad layer 145, the first conductive structure 147a, and the second conductive structure 147b. In some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 are integrally formed.

[0135] In some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 are formed simultaneously in the same processing steps, such as a deposition process and a subsequent planarization process. The deposition process may be a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, a plating process, or other applicable processes. The planarization process may include a CMP process, an etch-back process, or other applicable processes. Furthermore, in some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 comprise copper.

[0136] In some embodiments, the opening 140b in the pattern sparse region B is wider than the opening 140a in the pattern dense region A (refer to FIG. 16 FIG. 2B). Thus, after the spacer layer 145 is formed, the remaining portion of the opening 140b has a width W6 that is greater than the width W5 of the remaining portion of the opening 140a, and the depth D6 of the remaining portion of the opening 140b is greater than the depth D5 of the remaining portion of the opening 140a. As a result, as shown in FIG. 19 FIG. 2B, according to some embodiments, the width W6 of the second conductive structure 147b is greater than the width W5 of the first conductive structure 147a, and the height H2 of the second conductive structure 147b is greater than the height H1 of the first conductive structure 147a.

[0137] Please refer back to FIG. 1 According to some embodiments, a thermal treatment process is performed to convert the energy-removable layer 113 into the air gap 160 and an energy-removable structure 113’, which surrounds the air gap 160. The energy-removable structure 113’ is the remaining portion of the energy-removable layer 113 after the thermal treatment process. In some embodiments, the air gap 160 is surrounded by the energy-removable structure 113’. The individual steps are shown in step S27 in the fabrication method 10 as shown in FIG. 2 FIG. 2B.

[0138] In some other embodiments, the thermal treatment process can be replaced by a light treatment process, an electron beam treatment process, a combination thereof, or other applicable energy treatment processes. After the air gap 160 is formed, the semiconductor device structure 100 is obtained.

[0139] FIG. 20 An exemplary partial structure diagram of an exemplary integrated circuit having an array of memory cells 50, such as a memory device 1000, is shown in FIG. 1. In some embodiments, the memory device 1000 is a dynamic random access memory (DRAM) device. In some embodiments, the memory device 1000 has a plurality of memory cells 50 arranged in a grid pattern and having a plurality of rows and columns. The number of memory cells 50 can vary depending on system requirements and fabrication technology.

[0140] In some embodiments, each memory cell 50 has an access element and a storage element. The access element is configured to provide control for accessing the storage element. In particular, according to some embodiments, the access element is a field effect transistor (FET) 51 and the storage element is a capacitor 53. In each memory cell 50, the field effect transistor 51 has a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the field effect transistor 51, and the other terminal of the capacitor 53 can be electrically connected to ground. Further, in each memory cell 50, the gate 59 of the field effect transistor 51 is electrically connected to a word line WL, and the drain 55 of the field effect transistor 51 is electrically connected to a bit line BL.

[0141] The above description refers to the field effect transistor 51 being electrically connected to the terminal of the capacitor 53 that is the source 57, and the field effect transistor 51 being electrically connected to the terminal of the bit line BL that is the drain 55. However, during read and write operations, the terminal of the field effect transistor 51 that is electrically connected to the capacitor 53 can be the drain, and the terminal of the field effect transistor 51 that is electrically connected to the bit line BL can be the source. That is, either terminal of the field effect transistor 51 can be a source or a drain, depending on the manner in which the field effect transistor 51 is controlled by the voltages applied to the source, drain, and gate.

[0142] By controlling the voltage at the gate 59 via the word line WL, a voltage potential can be generated across the field effect transistor 51 such that electrical charge can flow from the source 55 to the capacitor 53. Thus, the electrical charge stored in the capacitor 53 can represent a binary data in the memory cell 50. For example, a positive electrical charge stored in the capacitor 53 above a threshold voltage represents a binary "1." If the electrical charge in the capacitor 53 is below the threshold, a binary "0" can be said to be stored in the memory cell 50.

[0143] Bit lines BL are configured to read from or write data to memory cells 50, and to read or write data to memory cells 50. Word lines WL are configured to activate field effect transistors 51 to access a particular column of memory cells 50. Accordingly, memory element 1000 also has a peripheral circuit region, which can include an address buffer, a row decoder, and a column decoder. The row and column decoders selectively access memory cells 50 in response to a plurality of address signals, which are provided to the address buffer during read, write, and refresh operations. The address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

[0144] Referring back to FIG. 1 , a first conductive plug 123a (e.g., a manganese-containing conductive plug) is formed in a pattern dense region A, while a second conductive plug 127 (e.g., a copper-containing conductive plug) is formed in a pattern sparse region B. The pattern dense region A can be at any region of memory cells 50 in memory element 1000, and the pattern sparse region B can be at any region of the address buffer, row decoder, or column decoder in memory element 1000.

[0145] The present disclosure provides some embodiments of a semiconductor element structure 100 and a method of fabricating the same. In some embodiments, the semiconductor element structure 100 has a first conductive plug 123a, a liner layer 123, and a second conductive plug 127; the first conductive plug 123a penetrates through a dielectric layer 105 and is located in a pattern dense region A; the liner layer 123 covers the dielectric layer 105 and the first conductive plug 123a; and the second conductive plug 127 penetrates through the liner layer 123 and the dielectric layer 105 and is located in a pattern sparse region B. The liner layer 123 and the first conductive plug 123a contain manganese, and the second conductive plug 127 is separated from the dielectric layer 105 by the liner layer 123. The manganese-containing conductive plug (e.g., the first conductive plug 123a located in the pattern dense region A) and the liner layer 123 can be monolithically formed, thereby reducing fabrication cost. Further, the liner layer 123 can reduce or avoid the formation of holes in the subsequently formed conductive plug (e.g., the second conductive plug 127 located in the pattern sparse region B), thereby reducing contact resistance. As a result, the operating speed of the semiconductor element structure 100 can be improved, which significantly improves overall element performance.

[0146] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate, and a dielectric layer disposed on the first conductive layer. The semiconductor device structure also has a first conductive plug penetrating through the dielectric layer and located in a pattern dense region, and a liner layer covering the liner layer and the first conductive layer. The liner layer and the first conductive plug include manganese. The semiconductor device structure further has a second conductive plug penetrating through the liner layer and the dielectric layer and located in a pattern sparse region. The second conductive plug is separated from the dielectric layer by a portion of the liner layer. In addition, the semiconductor device structure has a second conductive layer covering the liner layer and the second conductive plug.

[0147] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate, and a second conductive layer disposed on the first conductive layer. The semiconductor device structure also has a plurality of first conductive plugs disposed in a pattern dense region and located between the first conductive layer and the second conductive layer, and a plurality of second conductive plugs disposed in a pattern sparse region and located between the first conductive layer and the second conductive layer. The semiconductor device structure further has an energy removable structure disposed between the plurality of first conductive plugs. An air gap is surrounded by the energy removable structure. In addition, the semiconductor device structure has a liner layer disposed between the plurality of first conductive plugs and the second conductive layer. The liner layer and the plurality of first conductive plugs include manganese.

[0148] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first conductive layer on a semiconductor substrate, and forming a dielectric layer on the first conductive layer. The method also includes replacing a portion of the dielectric layer with an energy removable layer, and performing an etching process to form a first opening in the energy removable layer and a second opening in the dielectric layer. The first opening is located in a pattern dense region, and the second opening is located in a pattern sparse region. The method further includes depositing a liner layer on the energy removable layer and the dielectric layer. The liner layer completely fills the first opening to form a first conductive plug, and the liner layer partially fills the second opening. In addition, the method includes forming a second conductive plug in a remaining portion of the second opening, and forming a second conductive layer on the liner layer and the second conductive plug.

[0149] Embodiments of the present disclosure have some advantageous features. By integrally forming the manganese-containing conductive plug in the pattern dense region and the manganese-containing liner layer, the fabrication cost can be reduced. In addition, the resistance of the conductive plug in the pattern sparse region and surrounded by the manganese-containing liner layer can be reduced. Therefore, the operating speed of the semiconductor device structure is improved, which significantly improves the overall device performance.

[0150] While the disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the techniques described can be performed with different hardware and software configurations, or in conjunction with each other in a manner not specifically described herein.

[0151] Further, the scope of the disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the appended claims are intended to cover all processes, machines, manufacture, compositions of matter, means, methods, or steps, substantially as set forth in the disclosure and their equivalents.

Claims

1. A semiconductor device structure, comprising: a first conductive layer disposed on a semiconductor substrate; a dielectric layer disposed on the first conductive layer; a first conductive plug penetrating the dielectric layer and located in a pattern dense region; a liner layer covering the dielectric layer and the first conductive layer, wherein the liner layer and the first conductive plug comprise manganese; a second conductive plug penetrating the liner layer and the dielectric layer and located in a pattern sparse region, wherein the second conductive plug is separated from the dielectric layer by a portion of the liner layer; and a second conductive layer covering the liner layer and the second conductive plug.

2. The semiconductor device structure of claim 1, wherein the liner layer directly contacts the first conductive plug and comprises a same material as the first conductive plug.

3. The semiconductor device structure of claim 2, wherein the liner layer and the first conductive plug comprise copper manganese.

4. The semiconductor device structure of claim 1, wherein the first conductive plug and the second conductive plug comprise different materials.

5. The semiconductor device structure of claim 1, wherein the second conductive layer directly contacts the second conductive plug and the second conductive layer and the second conductive plug comprise copper. The energy-removable structure is disposed between the liner layer and the first conductive layer.

7. The semiconductor device structure of claim 6, further comprising an air gap surrounded by the energy-removable structure.

8. A semiconductor device structure, comprising: a first conductive layer disposed on a semiconductor substrate; a second conductive layer disposed on the first conductive layer; a plurality of first conductive plugs disposed in a pattern dense region and located between the first conductive layer and the second conductive layer; a plurality of second conductive plugs disposed in a pattern sparse region and located between the first conductive layer and the second conductive layer; an energy-removable structure disposed between the plurality of first conductive plugs, wherein an air gap is surrounded by the energy-removable structure; and a liner layer disposed between the plurality of first conductive plugs and the second conductive layer, wherein the liner layer and the plurality of first conductive plugs comprise manganese.

9. The semiconductor device structure of claim 8, wherein the liner layer and the plurality of first conductive plugs comprise a first material, the plurality of second conductive plugs and the second conductive layer comprise a second material, and the first material is different from the second material.

10. The semiconductor device structure of claim 9, wherein the first material is copper manganese and the second material is copper. The plurality of second conductive plugs are surrounded by the dielectric layer, the liner layer extends between the dielectric layer and the second conductive layer, and each second conductive plug is separated from the dielectric layer by the liner layer.

6. The semiconductor device structure of claim 1, further comprising an energy-removable structure disposed in the pattern-dense region and adjacent to the first conductive plug, wherein, 12. The semiconductor device structure of claim 8, wherein a first distance between an adjacent pair of the plurality of first conductive plugs is less than a second distance between an adjacent pair of the plurality of second conductive plugs.

13. The semiconductor device structure of claim 8, wherein the plurality of first conductive plugs and the plurality of second conductive plugs are electrically connected to the first conductive layer and the second conductive layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ 11. The semiconductor device structure of claim 8, further comprising a dielectric layer disposed between the first conductive layer and the second conductive layer, wherein, ​ ​ ​ 14. A method for fabricating a semiconductor device, comprising: forming a first conductive layer on a semiconductor substrate; forming a dielectric layer on the first conductive layer; replacing a portion of the dielectric layer with an energy-removable layer; performing an etching process to form a first opening in the energy-removable layer and a second opening in the dielectric layer, wherein the first opening is located in a pattern dense region and the second opening is located in a pattern sparse region; depositing a liner layer on the energy-removable layer and the dielectric layer, wherein the liner layer completely fills the first opening to form a first conductive plug and the liner layer partially fills the second opening; forming a second conductive plug in a remaining portion of the second opening; and forming a second conductive layer on the liner layer and the second conductive plug.

15. The method for fabricating a semiconductor device of claim 14, wherein a width of the first opening is less than a width of the second opening.

16. The method of claim 14, wherein the etching process further comprises forming a third opening in the pattern dense region and adjacent to the first opening, and forming a fourth opening in the pattern sparse region and adjacent to the second opening, wherein, a distance between the first opening and the third opening is less than a distance between the second opening and the fourth opening.

17. The method for fabricating a semiconductor device of claim 14, wherein the first conductive plug comprises copper manganese and the second conductive plug comprises copper.

18. The method for fabricating a semiconductor device of claim 14, further comprising partially removing the liner layer in the second opening to expose the first conductive layer before forming the second conductive plug.

19. The method for fabricating a semiconductor device of claim 14, wherein the second conductive plug and the second conductive layer are formed simultaneously in a same processing step.

20. The method for fabricating a semiconductor device of claim 14, further comprising performing a thermal treatment process to partially convert the energy-removable layer into an air gap after forming the second conductive layer.

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