Semiconductor structure and method with in-device high-resistivity poly semiconductor elements

Abstract

This application relates to semiconductor structures and methods having high-resistivity poly semiconductor elements within a device, and discloses a structure including a semiconductor layer having a device region, and a single-crystalline portion within the device region and a poly-crystalline portion extending through the single-crystalline portion. The structure includes an active device including a device component located in the device region and including a poly-crystalline portion. For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or an RF switch) having at least one source / drain region located in the device region and including at least one poly-crystalline portion extending through the single-crystalline portion. The embodiments can vary depending on the type of structure (e.g., bulk or SOI), depending on the type of device therein, and also depending on the number, size, shape, location, orientation, etc. of the poly-crystalline portions. A method of forming the structure is also disclosed herein.

Description

TECHNICAL FIELD

[0001] Embodiments of semiconductor structures having one or more in-device high-resistivity poly semiconductor elements and methods of forming the same are disclosed. BACKGROUND

[0002] Integrated circuit (IC) designs for bulk semiconductor structures can include buried high-resistivity poly semiconductor elements that are buried within a bulk semiconductor substrate to align under active device regions. Such buried high-resistivity poly semiconductor elements can reduce parasitic losses and harmonics. In addition, integrated circuit (IC) designs for both bulk semiconductor structures and semiconductor-on-insulator structures can include high-resistivity poly semiconductor elements that are not buried (e.g., they are located in an upper portion of a bulk semiconductor substrate, or within a semiconductor layer on an insulator layer above a semiconductor substrate), and in particular, they are located outside of active device regions. The non-buried high-resistivity poly semiconductor elements provide isolation between adjacent active device regions, act as passive devices outside of active device regions, or act as semiconductor fill shapes outside of active device regions. SUMMARY

[0003] Embodiments of semiconductor structures having one or more in-device high-resistivity poly semiconductor elements are disclosed herein. The semiconductor structures can be bulk semiconductor structures or semiconductor-on-insulator structures (e.g., silicon-on-insulator (SOI) structures). In any case, the semiconductor structures can include a semiconductor layer having a first surface and a second surface opposite the first surface. The semiconductor layer can also have a device region adjacent the second surface, and a single-crystalline portion within the device region and one or more poly crystalline portions extending vertically from the second surface through the single-crystalline portion toward the first surface. The semiconductor structures can also include an active semiconductor device having, among other features, a device component located within the device region of the semiconductor layer and including at least one poly crystalline portion extending vertically through the single-crystalline portion. The embodiments of the semiconductor structures can vary depending on the type of structure (e.g., bulk or SOI), depending on the type of active semiconductor device therein, and depending on the number, size, shape, location, orientation, etc. of the one or more poly crystalline portions within the active semiconductor device.

[0004] Also disclosed herein are methods of forming the above-described semiconductor structures having one or more in-device high-resistivity poly crystalline semiconductor elements. In particular, the methods can include providing a semiconductor layer having a first surface and a second surface opposite the first surface, and the semiconductor layer initially has a single crystalline structure. The semiconductor layer can be a bulk semiconductor substrate for forming a bulk semiconductor structure, or a semiconductor layer on an insulator layer for forming a semiconductor-on-insulator structure (e.g., a silicon-on-insulator (SOI) structure). In any case, the methods can also include processing the semiconductor layer (e.g., with a patterned amorphization process followed by a recrystallization anneal process, as further described below in the DETAILED DESCRIPTION section) so that, within an active device region adjacent the second surface, the semiconductor layer has a single crystalline portion and one or more poly crystalline portions extending vertically from the second surface through the single crystalline portion toward the first surface. The methods can also include forming an active semiconductor device including, among other features, a device component located within the device region of the semiconductor layer and including at least one poly crystalline portion extending vertically through the single crystalline portion. Embodiments of the methods can vary depending on the type of structure being formed (e.g., bulk or SOI), depending on the type of active semiconductor device being formed, and depending on the number, size, shape, location, orientation, etc. of the one or more poly crystalline portions formed within the active semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present application will be better understood from the following detailed description taken in conjunction with the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0006] Figure 1 shows a top view of a semiconductor structure having one or more in-device high-resistivity poly crystalline semiconductor elements;

[0007] Figure 1A and 1B shows a cross-sectional view of the semiconductor structure of Figure 1 as a bulk semiconductor structure or a semiconductor-on-insulator structure, respectively;

[0008] Figure 2 shows a top view of a semiconductor structure having one or more in-device high-resistivity poly crystalline semiconductor elements;

[0009] Figure 2A and 2B shows a cross-sectional view of the semiconductor structure of Figure 2 as a bulk semiconductor structure or a semiconductor-on-insulator structure, respectively;

[0010] Figure 3 shows a top view of a semiconductor structure having one or more in-device high-resistivity poly crystalline semiconductor elements;

[0011] Figures 3A-1 to 3A-3 3B-1 to 3B-3 respectively show bulk semiconductor structures or semiconductor-on-insulator structures. Figure 3 A cross-sectional view of a semiconductor structure;

[0012] Figure 4 A top view showing a semiconductor structure having one or more high-resistivity polycrystalline semiconductor elements within the device;

[0013] Figures 4A-1 to 4A-2 4B-1 to 4B-2 respectively show bulk semiconductor structures or semiconductor-on-insulator structures. Figure 4 A cross-sectional view of a semiconductor structure;

[0014] Figure 5 A top view showing a semiconductor structure having one or more high-resistivity polycrystalline semiconductor elements within the device;

[0015] Figures 5A-1 to 5A-3 5B-1 to 5B-3 respectively show bulk semiconductor structures or semiconductor-on-insulator structures. Figure 5 A cross-sectional view of a semiconductor structure;

[0016] Figure 6 A flowchart showing an embodiment of a method for forming a bulk semiconductor structure having one or more high-resistivity polycrystalline semiconductor elements within a device;

[0017] Figures 7-14 Based on display Figure 6 A sectional view of the partially completed structure formed by the flowchart;

[0018] Figure 15 A flowchart illustrating an embodiment of a method for forming a semiconductor-on-insulator structure having one or more high-resistivity polycrystalline semiconductor elements within a device; and

[0019] Figures 16-20 Based on display Figure 15 The flowchart forms a partial sectional view of the completed structure. Detailed Implementation

[0020] As noted above, integrated circuit (IC) designs for bulk semiconductor structures can include embedded high-resistivity poly semiconductor elements that are embedded within a bulk semiconductor substrate to align below active device regions in an upper portion of the substrate. Such embedded high-resistivity poly semiconductor elements can reduce parasitic losses and harmonics. In addition, integrated circuit (IC) designs for both bulk semiconductor structures and semiconductor-on-insulator structures can include high-resistivity poly semiconductor elements that are not embedded (e.g., they are located in an upper portion of a bulk semiconductor substrate, or within a semiconductor layer on an insulator layer above a semiconductor substrate), and in particular, they are located outside of active device regions. The non-embedded high-resistivity poly semiconductor elements provide isolation between adjacent active device regions, act as passive devices outside of active device regions, or act as semiconductor fill shapes outside of active device regions. For purposes of this disclosure, an active device region is a semiconductor structure region that contains one or more active semiconductor devices (e.g., transistors or other active semiconductor devices, etc.). The inventors of the disclosed embodiments have found that performance advantages can also be obtained by selectively placing high-resistivity poly semiconductor elements within active semiconductor devices.

[0021] Accordingly, embodiments of semiconductor structures having one or more in-device high-resistivity poly semiconductor elements are disclosed herein. The semiconductor structures can be bulk semiconductor structures or semiconductor-on-insulator structures (e.g., silicon-on-insulator (SOI) structures). In any case, the semiconductor structures can include a semiconductor layer having a first surface and a second surface opposite the first surface. The semiconductor layer can also have a device region adjacent the second surface, and a single-crystalline portion and one or more poly crystalline portions within the device region, the one or more poly crystalline portions extending vertically through the single-crystalline portion from the second surface to the first surface. The semiconductor structures can also include an active semiconductor device. Among other features, the active semiconductor device can include a device component located within the device region of the semiconductor layer and including at least one poly crystalline portion extending vertically through the single-crystalline portion. The embodiments of the semiconductor structures can vary depending on the type of structure (e.g., bulk or SOI), depending on the type of active semiconductor device therein, and depending on the number, size, shape, location, orientation, etc. of the one or more poly crystalline portions within the active semiconductor device. Method embodiments for forming such semiconductor structures are also disclosed herein.

[0022] It should be noted that the active semiconductor device of the disclosed semiconductor structure embodiments can be any type of active semiconductor device that can benefit from inclusion of one or more in-device high-resistivity poly semiconductor elements within one or more of its components. For example, the active semiconductor device can be a field effect transistor (FET) having at least one source / drain region located in the device region of the semiconductor layer and including at least one poly portion extending through the single-crystal portion of the device region. The FET can be any type of FET ranging from a simple FET to a more complex FET such as a multi-finger FET of a low noise amplifier (LNA) or a radio frequency (RF) switch. The one or more poly portions in the source / drain region of the FET can be used, for example, to reduce body effect time constant (e.g., in the case of an LNA) or to reduce harmonics (e.g., in the case of an RF switch). For purposes of illustration, the disclosed semiconductor structure embodiments are described below and illustrated in the drawings with respect to a multi-finger FET. For purposes of this disclosure, a multi-finger FET refers to a complex FET that includes alternating source / drain regions and channel regions located within a semiconductor layer such that each channel region is laterally located between two source / drain regions, and gate structures having a plurality of parallel gate structures (referred to as fingers, gate fingers, etc.) that traverse the channel regions, and additional gate structures located above the isolation regions and perpendicular to and contacting one end of each of the parallel gate structures. It should be understood, however, that the active semiconductor device of the disclosed semiconductor structure can alternatively be any other type of active semiconductor device having at least one device component located in the device region of the semiconductor layer and including at least one poly portion extending through the single-crystal portion of the device region.

[0023] Figure 1 , 2 , 3, 4, and 5 are top views showing example embodiments of the disclosed semiconductor structures 100.1, 100.2, 100.3, 100.4, and 100.5, respectively, that include a semiconductor layer 101 (e.g., a silicon layer or some other suitable semiconductor material layer).

[0024] In some embodiments, the semiconductor structures 100.1-100.5 can be bulk semiconductor structures (see, e.g., the semiconductor structure 100.1A shown in the XX cross-sectional view of FIG. 1A; see, e.g., the semiconductor structure 100.2A shown in the XX cross-sectional view of FIG. 2A; and see, e.g., the semiconductor structures 100.3A, 100.4A, and 100.5A shown in the XX cross-sectional views of FIGS. 3A, 4A, and 5A, respectively). Figure 1A Figure 2A Figure 3A-1 3A-2 ​​​And the semiconductor structure 100.3A shown in the XX, WW and VV cross-sectional views of 3A-3; see respectively Figure 4A-1 and 4A-2 The semiconductor structure 100.4A shown in the cross-sectional views of XX and WW; and see respectively... Figure 5A-1 , 5A-2 The semiconductor structure 100.5A is shown in the XX, WW and VV cross-sectional views of 5A-3. In this case, the semiconductor layer 101 may be a bulk semiconductor substrate (e.g., a bulk silicon substrate) having a bottom surface 102 (referred to herein as the first surface) and a top surface 103 (referred to herein as the second surface) opposite and parallel to the bottom surface 102.

[0025] In other embodiments, the semiconductor structures 100.1-100.5 may be semiconductor-on-insulator structures, such as silicon-on-insulator (SOI) structures (see [link]). Figure 1B Semiconductor structure 100.1B shown in the XX cross-section; see also Figure 2B The semiconductor structure 100.2B shown in the XX cross-sectional view; see also [reference 1]. Figure 3B-1 , 3B-2 And the semiconductor structure 100.3B shown in the XX, WW and VV cross-sectional views of 3B-3; see respectively Figure 4B-1 and 4B-2 The semiconductor structure 100.4B shown in the cross-sectional views of XX and WW; and see respectively... Figure 5B-1 , 5B-2 The semiconductor structure 100.5B is shown in the XX, WW, and VV cross-sectional views of 5B-3. In this case, the semiconductor layer 101 may be, for example, a silicon layer having a bottom surface 102 (referred to herein as the first surface) and a top surface 103 (referred to herein as the second surface) opposite and parallel to the bottom surface 102. The bottom surface 102 of the semiconductor layer 101 may be located above and adjacent to the buried insulating layer 104 (e.g., a buried silicon dioxide layer, also referred to herein as a BOX layer). Moreover, the buried insulating layer 104 may be located above and adjacent to the top surface of the substrate 106 (e.g., a silicon substrate or some other suitable substrate).

[0026] Regardless of whether the semiconductor structures 100.1-100.5 are bulk semiconductor structures 100.1A-100.5A or semiconductor-on-insulator structures 100.1B-100.5B, they may include trench isolation regions 105. Trench isolation regions 105 may be, for example, shallow trench isolation (STI) regions. That is, trench isolation regions 105 may include trenches extending vertically from the top surface 103 into the semiconductor layer 101 and filled with one or more layers of isolation material (e.g., silicon dioxide or any other suitable isolation material). Trench isolation regions 105 may be formed (e.g., the trenches may be photolithographically patterned and etched, then filled with isolation material) to define the boundaries of active device regions 111 in the semiconductor layer 101. For example, active device regions 111 may extend laterally between trench isolation regions 105. Furthermore, trench isolation regions 105 may be formed to electrically isolate active device regions 111 from other regions of the semiconductor layer 101. In the case of bulk semiconductor structures of 100.1A-100.5A (e.g.) Figure 1A , Figure 2A , Figure 3A-1 , 3A-2 and 3A-3, Figure 4A-1 and 4A-2 ,as well as Figure 5A-1 , 5A-2 As shown in 5A-3), the trench isolation region 105 may extend from the top surface 103 a predetermined distance into the semiconductor substrate (e.g., through the upper part of the semiconductor substrate). In the case of semiconductor-on-insulator structures 100.1B-100.5B (e.g. Figure 1B , Figure 2B , Figure 3B-1 , 3B-2 and 3B-3, Figure 4B-1 and 4B-2 ,as well as Figure 5B-1 , 5B-2 As shown in 5B-3, the trench isolation region 105 can extend completely through the semiconductor layer 101 from the top surface 103 to the bottom surface 102 (that is, to the top surface of the insulating layer 104).

[0027] In any case, the semiconductor layer 101 may have a single-crystal portion 161 and one or more polycrystalline portions 162 (also referred to herein as in-device high resistivity polycrystalline semiconductor elements) within the active device region 111, the one or more polycrystalline portions extending vertically from the top surface 103 toward (or to) the bottom surface 102 through the single-crystal portion 161.

[0028] For example, in the case of a bulk semiconductor structure of 100.1A-100.5A (such as...) Figure 1A , Figure 2A ,Figure 3A-1 , 3A-2 and 3A-3, Figure 4A-1 and 4A-2 and Figure 5A-1 , 5A-2 and 5A-3), the single crystal portion 161 of the active device region 111 can extend laterally from one trench isolation region 105 to another trench isolation region, and one or more polycrystalline portions 162 can extend vertically through the single crystal portion 161. The semiconductor layer 101 (in this case, a semiconductor substrate) can also include an additional single crystal portion 165 (i.e., in the lower portion of the substrate) at the bottom surface 102 and a buried polycrystalline portion 163 (also referred to herein as a buried high resistivity polycrystalline semiconductor element) in the middle of the substrate between the additional single crystal portion 165 and the single crystal portion 161 of the active device region 111. The single crystal portion 161 of the active device region 111 can extend downward from the top surface 103 to the top of the buried polycrystalline portion 163. The one or more polycrystalline portions 162 can extend downward from the top surface 103 and can merge with the buried polycrystalline portion 163. It should be noted that the bottom of the buried polycrystalline portion 163 is shown as substantially planar in the figures. However, due to the formation techniques discussed in more detail below with respect to the method, the depth of the bottom of the buried polycrystalline portion 163 below the single crystal portion 161 can be greater than the depth of the bottom of the buried polycrystalline portion 163 below the one or more polycrystalline portions 162.

[0029] It should be noted that the buried polycrystalline portion 163 can also extend laterally between and in contact with the trench isolation regions 105 surrounding the active device region 111. It should be noted that the trench isolation regions 105 can extend a first depth into the semiconductor layer (i.e., the top surface 103 of the semiconductor layer 101 can be separated from the bottom surface of the trench isolation regions 105 by a first distance), and the single crystal portion 161 can extend a second depth into the semiconductor layer (i.e., the top surface 103 of the semiconductor layer 101 can be separated from the bottom surface of the single crystal portion 161 at the interface with the buried polycrystalline portion 163 by a second distance). In some embodiments, the first depth (i.e., the first distance) can be less than the second depth (i.e., the second distance), as shown in the figures. In this case, the buried polycrystalline portion can have a horizontal portion and vertical portions at the outer edges of the horizontal portion and extending upward to contact the trench isolation regions 105, thereby isolating the active device region 111. In other embodiments, the first depth (i.e., the first distance) can be equal to or greater than the second depth (i.e., the second distance) (not shown).

[0030] Similarly, in the case of the semiconductor-on-insulator structures 100.1B-100.5B (as shown in FIGS. 1B-1E, respectively), the single crystal portion 161 of the active device region 111 can extend laterally from one trench isolation region 105 to another trench isolation region, and one or more polycrystalline portions 162 can extend vertically through the single crystal portion 161. The semiconductor layer 101 (in this case, a semiconductor-on-insulator structure) can also include an additional single crystal portion 165 (i.e., in the lower portion of the substrate) at the bottom surface 102 and a buried polycrystalline portion 163 (also referred to herein as a buried high resistivity polycrystalline semiconductor element) in the middle of the substrate between the additional single crystal portion 165 and the single crystal portion 161 of the active device region 111. The single crystal portion 161 of the active device region 111 can extend downward from the top surface 103 to the top of the buried polycrystalline portion 163. The one or more polycrystalline portions 162 can extend downward from the top surface 103 and can merge with the buried polycrystalline portion 163. It should be noted that the bottom of the buried polycrystalline portion 163 is shown as substantially planar in the figures. However, due to the formation techniques discussed in more detail below with respect to the method, the depth of the bottom of the buried polycrystalline portion 163 below the single crystal portion 161 can be greater than the depth of the bottom of the buried polycrystalline portion 163 below the one or more polycrystalline portions 162. Figure 1B , Figure 2B , Figure 3B-13B-2 and 3B-3, Figure 4B-1 and 4B-2 and Figure 5B-1 5B-2 and 5B-3), the single crystal portion 161 of the active device region 111 can extend laterally from one trench isolation region 105 to another trench isolation region, and one or more polycrystalline portions 162 can extend vertically through the single crystal portion 161. In this case, both the single crystal portion 161 and the one or more polycrystalline portions 162 can extend from the top surface 103 to the bottom surface 102 of the semiconductor layer 101 (i.e., to the insulator layer 104).

[0031] The semiconductor structures 100.1-100.5 can also include at least one active semiconductor device 110, and this active semiconductor device 110 can include at least one device component located within the device region 111 such that the device component includes at least one polycrystalline portion 162 (i.e., at least one high resistivity polycrystalline element) extending therethrough. As noted above, the active semiconductor device 110 can be any type of active semiconductor device that can benefit by including one or more in-device high resistivity polycrystalline semiconductor elements within one or more components thereof. For purposes of illustration, however, each of the semiconductor structures 100.1-100.5 is shown in the figures and described below as including a multi-finger FET, and in particular a three-finger FET. It should be noted that the multi-finger FET can have any number of two-fingers or more, instead.

[0032] ​​Within the active device region 111 (which, as noted above, has one or more poly portions extending therethrough) laid out across the single crystal portion 161, the multi-finger FET can include alternating source / drain regions and channel regions, with each channel region of each FET segment laterally between two source / drain regions. It should be noted that for purposes of the present disclosure, each source / drain region laterally between channel regions of adjacent FET segments within a multi-finger FET is referred to herein as a "common source / drain region." Thus, as shown, in this three-finger FET, there are three FET segments 130, 140, 150, and the device region 111 includes the following components: a first body for the first FET segment 130, where the first body includes a first channel region 133 laterally between first source / drain regions 132; a second body for the second FET 140, where the second body includes a second channel region 143 laterally between second source / drain regions 142; and a third body for the third FET 150, where the third body includes a third channel region 153 laterally between third source / drain regions 152. Moreover, adjacent FET segments 130 and 140 have a common source / drain region 142 / 132 between their respective channel regions 133 and 143 (including one of the first source / drain regions 132 abutting one of the second source / drain regions 142), and adjacent FET segments 130 and 150 have a common source / drain region 132 / 152 between their respective first and third channel regions 133 and 153 (including the other of the first source / drain regions 132 abutting one of the third source / drain regions 152).

[0033] The multi-finger FETs can be, for example, N-type FETs (NFETs) or P-type FETs (PFETs). Those skilled in the art will appreciate that, for NFETs, the source / drain regions will typically be N+ source / drain regions (i.e., source / drain regions doped to have N-type conductivity at a higher conductivity level), and the channel regions will be P- channel regions (i.e., channel regions doped to have P-type conductivity at a lower conductivity level), or, alternatively, be un-doped (i.e., intrinsic channel regions). For PFETs, the source / drain regions will typically be P+ source / drain regions (i.e., source / drain regions doped to have P-type conductivity at a higher conductivity level), and the channel regions will be N- channel regions (i.e., channel regions doped to have N-type conductivity at a lower conductivity level), or, alternatively, be un-doped (i.e., intrinsic channel regions). In any case, the source / drain regions can be dopant implant regions having a well region, and the channel regions can be portions of the well region located between the source / drain regions. Optionally, each FET can have one or more additional components (e.g., source / drain extension regions, halos, etc.) within its respective body. Such components are well known in the art, and thus, details thereof are omitted from the present description to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0034] The multi-finger FETs can also have multi-finger gates, in which case the multi-finger gates include three parallel gate structures (also referred to as gate fingers) over their respective channel regions, and gate side-spacers laterally adjacent to opposite sidewalls of the gate structures. For example, the first FET segment 130 can have a first gate structure 131 over the first channel region 133, the second FET segment 140 can have a second gate structure 141 over the second channel region 143, and the third FET segment 150 can have a third gate structure 151 over the third channel region 153. The gate structures can be, for example, gate-first gate structures (e.g., poly-silicon gate structures) or replacement metal gates (RMGs). The three-finger gate can also include an additional gate structure 112 over the trench isolation region 105 at one side of the device region 111 and in contact with one end of each of the three parallel gate structures. Such a three-finger gate enables gate voltage to be applied simultaneously to the parallel gate structures. Gate structures as described above (including local interconnects or gate extensions electrically connecting them) are well known in the art, and thus, details thereof are omitted from the present description to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0035] In some embodiments, one or more polycrystalline portions (i.e., high-resistivity polycrystalline semiconductor elements) may be included in one or more source / drain regions of the FET. For example, in some embodiments, the multi-finger FET may be a low-noise amplifier (LNA). In an LNA, one or more polycrystalline portions (i.e., high-resistivity polycrystalline semiconductor elements) may be included within one or two of, for example, common source / drain regions (142 / 132, 132 / 152) to reduce the bulk effect time constant. In other embodiments, the multi-finger FET may be a radio frequency (RF) switch. In an RF switch, one or more polycrystalline portions (i.e., high-resistivity polycrystalline semiconductor elements) may be included within, for example, one or two common source / drain regions (142 / 132, 132 / 152) to reduce harmonics.

[0036] As described above, embodiments may vary depending on the type of structure (e.g., bulk or SOI) and the type of active semiconductor device contained in the structure. Embodiments may also vary depending on the number, size, shape, position, orientation, etc. of one or more polycrystalline portions 162 within the active semiconductor device.

[0037] For example, in Figure 1 In the semiconductor structure 100.1, and more specifically, in Figure 1A In the bulk semiconductor structure 100.1A, and in Figure 1B In the semiconductor-on-insulator structure 100.1B, the semiconductor layer 101 may have one or more polycrystalline portions 162 located within the active device region 111, including polycrystalline portions 162 extending vertically through single-crystal portions 161 in the common source / drain regions 142 / 132, and / or another polycrystalline portion 162 extending vertically through single-crystal portions 161 in the common source / drain regions 132 / 152. Each polycrystalline portion 162 may have a length measured in a direction perpendicular to the gate structure and the length is approximately equal to the distance between adjacent channel regions. Each polycrystalline portion 162 may also have a width measured in a direction parallel to the gate and the width is approximately equal to or greater than the width of the common source / drain region, such that the polycrystalline portion 162 traverses the entire length and width of the common source / drain region. Therefore, in this semiconductor structure 100.1, each polycrystalline portion 162 completely surrounds the corresponding common source / drain region.

[0038] For example, in Figure 2 In the semiconductor structure 100.2, and more specifically, in Figure 2A In the bulk semiconductor structure 100.2A, and in Figure 2BIn the semiconductor-on-insulator structure 100.2B, the semiconductor layer 101 may have one or more polycrystalline portions 162 located within the active device region 111, including a polycrystalline portion 162 extending vertically through a single-crystal portion 161 in the common source / drain regions 142 / 132, and / or another polycrystalline portion 162 extending vertically through a single-crystal portion 161 in the common source / drain regions 132 / 152. Each polycrystalline portion 162 may be parallel to the gate structure. Each polycrystalline portion 162 may have a length measured in a direction perpendicular to the gate structure and the length is less than the distance between adjacent channel regions. Each polycrystalline portion 162 may also have a width measured in a direction parallel to the gate, and optionally, the width is equal to or greater than the width of the common source / drain region, such that the polycrystalline portion 162 traverses the entire width of the common source / drain region. Each polycrystalline portion 162 may also be located in the central portion of the common source / drain region (e.g., approximately in the middle between the adjacent channel regions) so that it substantially bisects the common source / drain region.

[0039] For example, in Figure 3 In the semiconductor structure 100.3, and more specifically, in Figures 3A-1 to 3A-3 In the bulk semiconductor structure 100.3A, and in Figures 3B-1 to 3B-3 In the semiconductor-on-insulator structure 100.3B, the semiconductor layer 101 may have one or more polycrystalline portions 162 located within the active device region 111, including one or more polycrystalline portions 162 extending vertically through single-crystal portions 161 in the common source / drain regions 142 / 132, and / or one or more polycrystalline portions 162 extending vertically through single-crystal portions 161 in the common source / drain regions 132 / 152. Each polycrystalline portion 162 may have a length measured in a direction perpendicular to the gate structure and the length is approximately equal to the distance between adjacent channel regions. Each polycrystalline portion 162 may also have a width measured in a direction parallel to the gate and the width is less than the width of the common source / drain region, so that the polycrystalline portion 162 does not traverse the entire width of the common source / drain region. Optionally, a plurality of polycrystalline portions 162 may be located in each of the common source / drain regions 142 / 132 and 132 / 152. Optionally, within each of the common source / drain regions 142 / 132 and 132 / 152, a plurality of polycrystalline portions 162 may be physically separated (i.e., isolated). Optionally, when the polycrystalline portions 162 are located in two common source / drain regions, they may be staggered so that any two polycrystalline portions 162 located on opposite sides of the first gate structure 131 are misaligned.

[0040] For example, in Figure 4 In the semiconductor structure 100.4, and more specifically, in Figures 4A-1 to 4A-2 In the bulk semiconductor structure 100.4A, and inFigures 4B-1 to 4B-2 In semiconductor-on-insulator structure 100.4B, semiconductor layer 101 can have one or more poly portions 162 within active device region 111, including one or more poly portions 162 extending vertically through single crystal portion 161 in common source / drain region 142 / 132, and / or one or more poly portions 162 extending vertically through single crystal portion 161 in common source / drain region 132 / 152. Each poly portion 162 can have a length measured in a direction perpendicular to the gate structure and the length is approximately equal to the distance between the adjacent channel regions. Each poly portion 162 can also have a width measured in a direction parallel to the gate and the width is less than the width of the common source / drain region, such that poly portion 162 does not span the entire width of the common source / drain region. Alternatively, multiple poly portions 162 can be in each common source / drain region 142 / 132 and 132 / 152. Alternatively, multiple poly portions 162 can be physically separated (i.e., spaced apart) within each common source / drain region 142 / 132 and 132 / 152. Alternatively, when poly portions 162 are in both common source / drain regions, they can be aligned. That is, pairs of adjacent poly portions 162 on opposite sides of first gate structure 131 can be aligned.

[0041] For example, in semiconductor-on-insulator structure 100.5, and more specifically, in bulk semiconductor structure 100.45A of A-3, and in semiconductor-on-insulator structure 100.5B of A-4, Figure 5 For example, in semiconductor-on-insulator structure 100.5, and more specifically, in bulk semiconductor structure 100.45A of A-3, and in semiconductor-on-insulator structure 100.5B of A-4, Figures 5A-1 to 4 For example, in semiconductor-on-insulator structure 100.5, and more specifically, in bulk semiconductor structure 100.45A of A-3, and in semiconductor-on-insulator structure 100.5B of A-4, Figures 5B-1 to 5B-3 In semiconductor-on-insulator structure 100.5B, semiconductor layer 101 can have one or more poly portions 162 within active device region 111, including poly portions 162 extending vertically through single crystal portion 161 in common source / drain region 142 / 132, and / or poly portions 162 extending vertically through single crystal portion 161 in common source / drain region 132 / 152. Each poly portion 162 can include a plurality of vertical segments connected in a square meander pattern across the entire width of the common source / drain region. In particular, each poly portion 162 can have first segments (oriented in a first direction perpendicular to the gate structure and uniformly spaced across the width of the common source / drain region) and second segments (oriented in a second direction parallel to the gate structure and uniformly spaced across the width of the common source / drain region, but staggered), such that alternate second segments are on alternate sides of the common source / drain region (e.g., near one channel or the other) and extend between and contact adjacent first segments. Alternatively, both common source / drain regions 142 / 132 and 132 / 152 on opposite sides of first gate structure 131 can have poly portions 162 in such a pattern can be symmetrical (e.g., mirror image pattern).

[0042] It should be noted that in all embodiments where one or more polycrystalline portions 162 (i.e., high resistivity polycrystalline semiconductor elements within the device) extend vertically through a doped device component (e.g., a source / drain region of an FET), the one or more polycrystalline portions 162 can have the same doping (i.e., conductivity type and level) as the doped device component in which it is embedded. In bulk semiconductor structures 100.1A-100.5A, the buried polycrystalline portion 163 (located in the middle portion of the substrate aligned between the active device region 111 and the lower portion of the substrate) can be doped or undoped depending on the depth at which it is located within the semiconductor layer (e.g., depending on whether it is located within or below a well implant in the body of the FET, whether there is a buried well below the body of the FET, etc.).

[0043] Furthermore, it should be noted that the shapes denoted as polycrystalline portions 162 in the figures (e.g., in bulk semiconductor structures 100.1A-100.5A as well as in semiconductor-on-insulator structures 100.1B-100.5B) and the shapes denoted as buried polycrystalline portions 163 in the figures (e.g., in bulk semiconductor structures 100.1A-100.5A) can be completely polycrystalline in structure. Alternatively, the shapes denoted as polycrystalline portions 162 in the figures and the shapes denoted as buried polycrystalline portions 163 in the figures can be multilayer structures comprising a stack of thicker polycrystalline layers with thinner single crystalline layers sandwiched between the polycrystalline layers. The variation in the crystalline structure of the polycrystalline portions 162 or 163 depends on the formation technique used (see detailed discussion below regarding the method). It should also be noted that due to the formation technique used, bulk semiconductor structures 100.1A-100.5A can also (or can not) include a processing artifact, particularly another high resistivity polycrystalline portion 164 in the middle portion of the substrate aligned below the buried polycrystalline portion 163. This polycrystalline portion 164 can be thin and can vary in shape.

[0044] Optionally, the semiconductor structures 100.1-100.5 can also include one or more additional trench isolation regions 195 located in the semiconductor layer 101. The additional trench isolation regions 195 can also be, for example, STI regions, and can define the boundaries of one or more additional regions 191 within the semiconductor layer 101. Although only one additional region 191 is shown, it should be understood that the semiconductor structures 100.1-100.5 can have multiple additional regions 191, each of which is bounded by an STI region 195, and that these additional regions can have the same or different design functions. For example, the additional region 191 can include a passive device region, a dummy fill shape region, an additional active device region, etc. To avoid clutter in the drawings and to allow the reader to focus on the salient aspects of the disclosed semiconductor structure embodiments having in-die high-resistivity poly semiconductor elements 162, the drawings do not include any shapes that illustrate specific features in and / or on the additional region 191. Such shapes would vary depending on the design function of the additional region 191 and / or depending on whether the semiconductor structure is a bulk semiconductor structure or a semiconductor-on-insulator structure.

[0045] Additional features of the semiconductor structures 100.1-100.5 can include, but are not limited to: silicide layers located on top surfaces of the gate structures and / or the source / drain regions; one or more dielectric layers (e.g., conformal etch stop layers, blanket interlayer dielectric layers located on the conformal etch stop layers, etc.) over the devices located on the semiconductor layer; and middle of the line (MOL) contacts (e.g., gate contacts (not shown) and source / drain contacts 199 (shown only in top view) of the FETs) extending through the one or more dielectric layers to the devices. Such features are well known in the art, and thus, they are not shown in the drawings and details thereof are omitted from this description to allow the reader to focus on the salient aspects of the disclosed embodiments. It should be noted that, in some embodiments, it is preferable that one or more of the poly portions 162 and the source / drain contacts 199 are patterned and formed such that the contacts are aligned over the single-crystal semiconductor material within each source / drain region, without being located over the poly semiconductor material of any poly portions 162, as shown in the top view of the semiconductor structure 100.2-100.5 of FIG. 1C. Figures 2-5

[0046] Also disclosed herein are method embodiments for forming the above-described semiconductor structures including one or more in-die high-resistivity poly semiconductor elements (see, e.g., the example semiconductor structures 100.1-100.5 of FIGS. 1A-1E). Figures 1-5

[0047] ​​Generally, each of the method embodiments includes providing a semiconductor layer 101 having a bottom surface 102 (referred to herein as a first surface) and a top surface 103 (referred to herein as a second surface) opposite the bottom surface, and initially having a single crystalline structure. The semiconductor layer 101 can be a bulk semiconductor substrate (e.g., a bulk silicon substrate), and can be used to form a bulk semiconductor structure (see, e.g., FIGS. 1 OA, 1 OB, 1 OC, 1 OD, and 1 OE, respectively, of U.S. Patent No. 7,892,766, which is incorporated herein by reference). Figure 1A FIG. 1 OA, Figure 2A FIG. 10B, Figures 3A-1 to 3A-3 FIG. 10C, Figures 4A-1 to 4A-2 FIG. 10D, and Figures 5A-1 to 5A-3 FIG. 10E). Alternatively, the semiconductor layer 101 can be a semiconductor layer (e.g., a silicon layer) of a semiconductor-on-insulator wafer (e.g., a silicon-on-insulator (SOI) wafer), and can be used to form a semiconductor-on-insulator structure (see, e.g., FIGS. 1 OA, 1 OB, 1 OC, 1 OD, and 1 OE, respectively, of U.S. Patent No. 7,892,766, which is incorporated herein by reference). Figure 1B FIG. 1 OA, Figure 2B FIG. 10B, Figures 3B-1 to 3B-3 FIG. 10C, Figures 4B-1 to 4B-2 FIG. 10D, and Figures 5B-1 to 5B-3 FIG. 10E).

[0048] In any case, each of the method embodiments also includes processing the semiconductor layer 101 (e.g., using a patterned amorphization process followed by a recrystallization anneal process, as discussed in more detail below) so that, within the active device region 111, the semiconductor layer 101 has a single crystalline portion 161 at the top surface 103 and at least one polycrystalline portion 162 extending vertically through the single crystalline portion 161 from (or to) the top surface 103 to (or from) the bottom surface 102. Each of the method embodiments also includes forming an active semiconductor device 110 so that the active semiconductor device 110 includes at least one device component located within the device region 111 and including the at least one polycrystalline portion 162 (i.e., at least one device-internal high-resistivity polycrystalline semiconductor element).

[0049] It should be noted that the active semiconductor device formed in accordance with the disclosed method can be any type of active semiconductor device that can benefit from inclusion of one or more in-device high-resistivity poly crystalline semiconductor elements within one or more of its components. For example, the active semiconductor device can be a field effect transistor (FET) having at least one source / drain region located in the device region of the semiconductor layer and including at least one poly crystalline portion extending through the single crystalline portion of the device region. The FET can be any type of FET ranging from a simple FET to a more complex FET such as a multi-finger FET of a low noise amplifier (LNA) or a radio frequency (RF) switch. The one or more poly crystalline portions in the source / drain region of the FET can be used, for example, to reduce body effect time constant (e.g., in the case of an LNA) or to reduce harmonics (e.g., in the case of an RF switch). For illustrative purposes, the formation of a multi-finger FET is described in more detail below and the method embodiments are exemplified in the accompanying drawings with respect thereto. It should be understood, however, that the method can alternatively include forming any other type of active semiconductor device having at least one device component located in the device region of the semiconductor layer and including at least one poly crystalline portion extending through the single crystalline portion of the device portion.

[0050] Figure 6 The flow diagrams show method embodiments for forming Figure 1A a bulk semiconductor structure 100.1A, Figure 2A 100.2A, Figures 3A-1 to 3A-3 100.3A, Figures 4A-1 to 4A-2 100.4A, and Figures 5A-1 to 5A-3 100.5A, respectively, that include an active semiconductor device 110 and, in particular, a multi-finger FET having an in-device high-resistivity poly crystalline element 162. The method embodiments can include providing a semiconductor layer 101 and, in this case, a bulk semiconductor substrate (e.g., a bulk single crystalline silicon substrate) (see process step 602 and Figure 7 ).

[0051] A thin dielectric layer 180 composed of a first dielectric material can be formed on the top surface 103 of the semiconductor layer 101 (see process step 604 and Figure 7 ). For example, the first dielectric material can be a layer of silicon dioxide (SiO2) deposited on the top surface 103 (e.g., by thermal oxidation).

[0052] A first protective layer 181 (also referred to herein as a dopant implantation confinement layer) composed of a second dielectric material can be formed on the thin dielectric layer 180 (see process step 606 and Figure 7). The second dielectric material can be different from the first dielectric material. For example, the second dielectric material can be silicon nitride (SiN) deposited on top surface of dielectric layer 180 by, for example, chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). It should be noted that process steps 622-626 (to be discussed in more detail below) include a dopant implantation process and a rapid thermal anneal (RTA) process. Prior to the dopant implantation process, protective shapes having different thicknesses (i.e., having different total heights measured from the top surface of the semiconductor layer) are formed on the semiconductor layer. Thus, in some regions the inert dopant is prevented from being implanted into the semiconductor layer, and in other regions multi-level dopant implanted regions having modified crystal structures (especially amorphous crystal structures) are formed. During the RTA, recrystallization of the multi-level dopant implanted regions occurs, thereby forming one or more polycrystalline portions 162, a buried polycrystalline portion 163, and one or more single crystalline portions 161 (to be discussed in more detail below). First protective layer 181 will be used later for forming first protective shapes, and thus should be deposited to have a thickness sufficient to limit the implantation of the inert dopant into the semiconductor layer 101 during process step 622 to a certain predetermined depth. For example, first protective layer 181 can have a thickness varying in the range from 30-250 nanometers.

[0053] Next, trench isolation regions, such as shallow trench isolation (STI) regions, can be formed so that they extend through first protective layer 181 and dielectric layer 180 and into top surface 103 of semiconductor layer 101, and further so that they define boundaries of active device region 111 within semiconductor layer 101 (see process step 608 and Figure 7). Optionally, one or more additional trench isolation regions 195 can be formed at process step 608 to define boundaries of one or more additional design regions 191 (e.g., passive device regions, dummy fill shape regions, additional active device regions, etc.) within the same semiconductor layer 101. At process step 608, the above-described STI regions (e.g., STI 105, and, if applicable, STI 195) can be formed using conventional STI formation techniques. Specifically, trenches can be lithographically patterned and etched so that they extend substantially vertically through the first protective layer 181 and the dielectric layer 180, and into the top surface 103 of the semiconductor layer 101, the bottom of each trench being located a predetermined distance below the top surface 103. One or more isolation material layers can be deposited to fill the trenches. In one example embodiment, the isolation material can be a first dielectric material (e.g., SiO2). After the deposition of the isolation material, a chemical mechanical polishing (CMP) process can be performed to remove the isolation material from above the top surface of the first protective layer 181, thereby making the top surface of the STI region substantially coplanar with the top surface of the first protective layer 181.

[0054] Next, a mask layer 182 can be formed over the first protective layer 181 and the STI region (see process step 610 and Figure 7 ). The mask layer 182 can be made of, for example, the same first dielectric material (e.g., SiO2) used for the dielectric layer 180, and can be deposited, for example, by PECVD. Alternatively, the mask layer 182 can be made of any suitable dielectric material different from the second dielectric material used for the first protective layer 181. The mask layer 182 can also be patterned (e.g., using conventional photolithographic patterning and etching techniques) to form at least one mask shape 182b over a section of the active device region 111, and, optionally, one or more additional mask shapes 182a (e.g., covering the design region 191 entirely) (see process step 612 and Figure 8 ). The one or more mask shapes 182b can be patterned so that they correspond to the desired two-dimensional size, shape, location, orientation, etc. of one or more poly portions to be formed with the active device region 111 (e.g., within a designated common source / drain region of an adjacent FET). For illustrative purposes, the one or more mask shapes 182b are shown in the figures so that they correspond to the size, shape, location, orientation, etc. of one or more poly portions 162 that are to be formed completely around the active device region 111 as shown in Figure 1Atwo common source / drain regions of a multi-finger FET as shown in the bulk semiconductor structure 100.1A. However, it should be understood that the figures are not intended to be limiting, and instead, the mask shapes 182b can correspond to the dimensions, shapes, locations, orientations, etc. of one or more polysilicon portions 162 shown in any other bulk semiconductor structure described above.

[0055] The exposed portions of the first protective layer 181 (e.g., adjacent / around one or more mask shapes 182b) can be selectively removed (e.g., using a selective anisotropic etch process) (see process step 614 and Figure 9 ). If the dielectric layer 180, the STI regions 105, and the mask layer 182 are all made of the same first dielectric material (e.g., SiO2), and if the first protective layer 181 is made of a second dielectric material (e.g., SiN), then any suitable process can be employed at process step 614 to selectively etch the exposed SiN relative to the exposed SiO2. For example, a hot phosphoric acid etch process can be used. As shown, process step 614 effectively transfers the pattern of the mask shapes 182a and 182b to directly form the pattern of the first protective shapes 181a and 181b underneath. Next, the mask layer 182, particularly the remaining mask shapes 182a and 182b, can be selectively removed (see process step 616 and Figure 10 ). For example, if the mask layer 182 is made of the first dielectric material (e.g., SiO2), then it can be selectively removed by a selective oxide wet etch process (e.g., hydrofluoric acid (HF) etch) or by a reactive ion etch (RIE) process. It should be noted that if the dielectric layer 180 and the mask layer 182 are made of the same first dielectric material (e.g., SiO2), then process step 614 can also expose and etch away portions of the dielectric layer 180 within the opening 185 adjacent the first protective shape 181b, thereby exposing the top surface 103 of the semiconductor layer 101 adjacent the first protective shape 181b. Thus, prior to performing additional processing, the first dielectric material of the dielectric layer 180 should be re-deposited (e.g., re-grown) on the exposed semiconductor surface in this first section.

[0056] A second protective layer 184 (also referred to herein as a dopant implant stop layer) can be formed over the partially completed structure. The second protective layer can be, for example, a photoresist mask layer, a nitride mask layer, or any other suitable mask material layer. Next, this second protective layer 184 can be lithographically patterned and etched to expose the first protective shape 181b over the active device region 111, and portions of the dielectric layer 180 that are on the active device region and not covered by the first protective shape 181b (see process step 618 and Figure 11One or more remaining portions of the second protective layer 184 may cover the one or more first protective shapes 181a, and the stacked protective layers may form one or more second protective shapes that are thicker than (i.e., higher than) the one or more first protective shapes 181b and located above any region of the semiconductor layer in which the implantation of the inert dopant in process step 622 for the purpose of forming a modified crystal structure is undesirable. To prevent the implantation of the inert dopant, the second protective layer should be deposited to a sufficient thickness (in combination with the underlying first protective shape 181a and the dielectric layer 180, regardless of the material it is made of) to ensure that the inert dopant does not enter the semiconductor layer. For example, if the second protective layer is a photoresist layer, it should be at least 2 nanometers, preferably 4 nanometers or larger.

[0057] Next, the dopant implantation process can be performed to implant the inert dopant into the semiconductor layer 101 at the desired location, thereby forming a multilayer dopant implantation region 170 with a modified crystal structure (e.g., with an amorphous crystal structure) (see process step 622 and...). Figure 12 The resulting multi-layered doped implantation region 170 will have a first region 171 (extending a first depth into the semiconductor layer and aligned only below the dielectric material of the dielectric layer 180) and a second region 172 (extending to a second depth shallower than the first depth and aligned below the first protective shape 181b). It should be noted that when the inert dopant passes only through the dielectric layer 180, the crystal structure of the adjacent top surface 103 of the semiconductor layer 101 is not modified; therefore, the first region 171 is separated from the top surface 103 of the semiconductor layer 101 by a short distance (e.g., less than 5 nanometers). In other words, a thinner (e.g., less than 5 nanometers) single-crystal layer 173 will remain between the top surface 103 of the semiconductor layer 101 and the first region 171. However, when the inert dopant must pass through the first protective shape 181b and the dielectric layer 180, the crystal structure of the top surface of the semiconductor layer is modified; therefore, the second region 172 is adjacent to the top surface 103.

[0058] For the purposes of the present disclosure, an inert dopant refers to a dopant species that is not considered to be chemically reactive (i.e., neutral) at least with respect to the single crystalline semiconductor material (e.g., single crystalline silicon) that is implanted within at process step 622, such that the implantation of the dopant species at process step 622 is capable of altering the crystalline structure of the single crystalline semiconductor material, which does not prevent the recrystallization of the multi-level dopant implant region 170 during the RTA process of process step 626, as explained in greater detail below, and does not significantly affect the electrical properties of the resulting polycrystalline and / or single crystalline semiconductor region after recrystallization. Such inert dopants include, but are not limited to, inert gases (also referred to as noble gases) (e.g., argon, xenon, helium, neon, krypton, radon, etc.), silicon, or any other suitable inert dopant. Process step 622 can include a single dopant implant process to form the multi-level dopant implant region 170. Alternatively, process step 622 can include multiple sequential dopant implant processes, and each dopant implant process can implant dopant ions at different energies and / or at different doses to optimize the modified crystalline structure and potentially achieve a greater implant depth for both the first region 171 and the second region 172.

[0059] As mentioned above, any second protective shape located above the semiconductor layer 101 will prevent the implantation of the inert dopant and ensure that the region of the semiconductor layer located below (e.g., see design region 191) will retain its original single crystalline structure throughout process steps 622-626.

[0060] After process step 622, the second protective layer can be selectively removed (see process step 624). As mentioned above, the second protective layer can be, for example, a photoresist mask layer or a nitride mask layer. Techniques for selectively removing such materials are well known in the art.

[0061] Next, the RTA process can be performed to recrystallize the multi-level dopant implant region 170 (see process step 626 and Figure 13 ). That is, the partially completed structure can be heated at a higher temperature (e.g., greater than 900 °C) for a shorter period of time (e.g., 5-180 seconds) in a non-oxidizing environment. During this recrystallization process, the lower portion of the semiconductor layer 101 (located below the dopant implant region 170 and having an original single crystalline structure) and the thin single crystalline layer 173 (located between the top surface 103 of the semiconductor layer 101 and the first region 171) act as seed layers for recrystallization. Thus, in the first region 171, recrystallization occurs downward from the top adjacent the single crystalline layer 173 and upward from the bottom adjacent the lower portion of the semiconductor layer, but in the second region 172, recrystallization occurs upward from the bottom but not downward from the top.

[0062] Accordingly, after process step 626, the semiconductor layer 101 will have a single crystalline portion 161 located within the active device region 111 that extends laterally from one trench isolation region 105 to another trench isolation region, and one or more polycrystalline portions 162 that extend vertically through the single crystalline portion 161 and are aligned below the first protective shape 181b. The semiconductor layer 101 will also have a buried polycrystalline portion 163 (also referred to herein as a buried high resistivity polycrystalline semiconductor element) located below the active device region 111. The single crystalline portion 161 of the active device region 111 can extend downward from the top surface 103 to the top of the buried polycrystalline portion 163. The one or more polycrystalline portions 162 can extend downward from the top surface 103 and can merge with the buried polycrystalline portion 163. As described above with respect to the structural embodiments, the bottom of the buried polycrystalline portion 163 is shown in the figures as being substantially planar. However, it should be understood that the depth of the bottom of the buried polycrystalline portion 163 located below the single crystalline portion 161 can be greater than the depth of the bottom of the buried polycrystalline portion 163 located below the one or more polycrystalline portions 162.

[0063] For illustrative purposes, the method steps are shown in the figures to pattern the first protective shape 181b so that, after process steps 622-626, the resulting polycrystalline portions 162 will be the same as the portions shown in the bulk semiconductor structure 100.1A. However, it should be understood that by changing the pattern of the first protective shape 181b on the active device region (e.g., the number, size, shape, orientation, location, etc. of the second protective shape 181b), different patterns of polycrystalline portions 162 within the active device region 111 can be achieved to achieve different bulk semiconductor structures (e.g., bulk semiconductor structures 100.2A, 100.3A, 100.4A, or 100.5A, or any other similar bulk semiconductor structure that includes an active device region 111 located within single crystalline and polycrystalline portions 161-162 and has a buried polycrystalline portion 163 located below). Figure 1A

[0064] ​It should be noted that the configuration of the one or more poly portions 162 and the buried poly portion 163 (e.g., as a single layer or multiple layers) will vary depending on the type of dopant implantation process used in process step 622. That is, as described above, process step 622 can include a single dopant implantation process or multiple sequential dopant implantation processes. If a single dopant implantation process is used in process step 622, then process step 626 can result in a configuration in which the shapes labeled as poly portions 162 or buried poly portion 163 in the figures are structurally fully poly. Alternatively, if multiple sequential dopant implantation processes are used in process step 622, then process step 626 can result in a configuration in which the shapes labeled as poly portions 162 or buried poly portion 163 in the figures are a multiple layer structure including a stack of thicker poly layers with thinner single crystal layers sandwiched between the poly layers.

[0065] It should also be noted that other characteristics of the single crystal and poly portions will depend on the process recipe used in process steps 622-626. For example, the thickness of single crystal portion 161 can be controlled primarily by the energy of the implant (e.g., higher energy can result in a thicker single crystal portion 161) and secondarily by the RTA time (e.g., less RTA time can result in a thinner single crystal portion 161). Those skilled in the art will appreciate that the thickness of single crystal portion 161 (measured from the top surface 103 of the semiconductor layer to the top of the underlying buried poly portion 163) should be sufficient to allow at least one active semiconductor device 110 (see process step 632 below) to be formed thereon and to function properly.

[0066] After process step 626, the semiconductor layer 101 will remain single crystal below the buried poly portion 163 (i.e., will have an additional single crystal portion 165) and throughout the semiconductor layer 101 (i.e., from the top surface 103 to the bottom surface 102) in the areas protected by the second protective shape during the dopant implantation process. However, in some cases, process artifacts can also occur in the semiconductor layer 101 aligned below the buried poly portion 163, particularly the thinner buried poly portion 164. This thinner buried poly portion can be substantially planar, as shown, or have some other shape.

[0067] The first protective shapes 181a-181b can then be selectively removed (see process step 628 and Figure 14). For example, if the dielectric layer 180 and the STI region are made of the same first dielectric material (e.g., SiO2), and if the first protective layer 181 is made of a second dielectric material (e.g., SiN), then any suitable process can be employed to etch the exposed SiN selectively with respect to the exposed SiO2. Thus, a hot phosphoric acid etch process can be used. Alternatively, the height of the STI region can also be reduced (e.g., using a deglazing or wet etch process) to make the top of the STI region approximately flush with the top surface of the dielectric layer 180 (see process steps 630 and Figure 14 ). It should be noted that if process step 630 results in removal of the dielectric layer 180 and exposure of the underlying semiconductor surface, then the first dielectric material can be re-deposited (e.g., by thermal oxidation) to re-form the dielectric layer 180.

[0068] Figure 15 A flow diagram of a method embodiment for forming a semiconductor-on-insulator structure 100.1B of Figure 1B , 100.2B of Figure 2B , 100.3B of Figures 3B-1 to 3B-3 , 100.4B of Figures 4B-1 to 4B-2 , and Figures 5B-1 to 5B-3 100.5B is shown. Each of the embodiments has an active semiconductor device 110, in particular, a multi-finger FET having a high-resistivity poly element 162 within the device. The process steps are similar to those described above with respect to the formation of bulk semiconductor structures, but are less complex since the insulator layer is present below the semiconductor layer, so that there is no need to simultaneously form a buried poly portion below the active device region 111.

[0069] In particular, the method embodiments can include providing a semiconductor layer 101 (e.g., a single-crystalline silicon layer) having a bottom surface 102 (referred to herein as a first surface) and a top surface 103 (referred to herein as a second surface) opposite the bottom surface 102. The bottom surface 102 of the semiconductor layer 101 can be located above and in close proximity to a top surface of an insulator layer 104 (e.g., a buried silicon dioxide layer, also referred to herein as a BOX layer) that is located on a semiconductor substrate 106 (e.g., a silicon substrate) (see process step 1502 and Figure 16 ).

[0070] A thin dielectric layer 180 composed of a first dielectric material can be formed on the top surface 103 of the semiconductor layer 101 (see process step 1504 and Figure 16 ). For example, the first dielectric material can be a silicon dioxide (SiO2) layer deposited on the top surface 103. In addition, a first protective layer 181 (also referred to herein as a dopant implantation confinement layer) composed of a second dielectric material can be formed on the thin dielectric layer 180 (see process step 1506 andFigure 16 ) The second dielectric material can be different from the first dielectric material. For example, the second dielectric material can be silicon nitride (SiN).

[0071] Next, trench isolation regions, such as shallow trench isolation (STI) regions, can be formed so as to extend through the first protective layer 181 and the dielectric layer 180 and into the top surface 103 of the semiconductor layer 101, and further so as to define the boundaries of the active device region 111 within the semiconductor layer 101 (see process step 1508 and Figure 16 Optionally, one or more additional trench isolation regions 195 can be formed at the same time as process step 1508 to define the boundaries of one or more additional design regions 191 (e.g., passive device regions, dummy fill shape regions, additional active device regions, etc.) within the same semiconductor layer 101.

[0072] Next, a second protective layer 184 (also referred to herein as a dopant implant stop layer) can be formed over the partially completed structure. The second protective layer can be, for example, a photoresist mask layer, a nitride mask layer, or any other suitable mask material layer. This second protective layer can then be lithographically patterned and etched to have one or more openings 186 that expose one or more particular segments of the first protective layer (i.e., expose one or more first protective shapes 181e). The one or more first protective shapes 181e can be located over one or more corresponding segments of the active device region 111 in which polysilicon elements are to be formed (see process step 1510 and Figure 17 ) The one or more remaining portions of the second protective layer can cover other segments of the first protective layer, which are located over the active device region 111, and optionally, over one or more other design regions (e.g., over design regions 191) or segments thereof. The stack of protective layers can form one or more second protective shapes that are thicker (i.e., taller) than the one or more first protective shapes 181e, and are formed over any regions of the semiconductor layer in which polysilicon elements are not to be formed.

[0073] Subsequently, a dopant implant process can be performed to implant an inert dopant in one or more desired locations of the semiconductor layer 101 (i.e., in one or more segments of the semiconductor layer 101 that are within the active device region 111 and that are aligned under the one or more openings 186 of the second protective layer 184 and the one or more first protective shapes 181e). The implantation of the inert dopant results in the formation of one or more dopant implant regions 175 having a modified crystal structure (e.g., having an amorphous crystal structure) (see process step 1522 and Figure 18). Since the inert dopant must pass through the first protective shape 181e to the dielectric layer 180, the crystal structure next to the top surface 103 of the semiconductor layer 101 is altered, and thus, one or more dopant implant regions 175 are next to the top surface 103. As described above, if the one or more first protective shapes were not present during the dopant implant process, there would be a single crystalline semiconductor layer between the top surface of the semiconductor layer and the dopant implant regions 175. Furthermore, as described above, the presence of the second protective layer 184 will prevent the inert dopant from implanting into other regions, leaving those regions with their original single crystalline structure. After process step 1512, the second protective layer 184 can be selectively removed (see process step 1514).

[0074] Next, an RTA process can be performed to recrystallize the one or more dopant implant regions 175, thereby forming one or more polycrystalline portions 162 that extend vertically from the top surface 103 of the semiconductor layer 101 through the remaining single crystalline portion 161 of the semiconductor layer 101 within the active device region 111 (see process step 1516 and Figure 19 ).

[0075] For illustrative purposes, the method steps are shown in the figures as the first protective shapes 181e are patterned such that, after process steps 1512-1516, the resulting polycrystalline portions 162 will be the same as those shown in the semiconductor-on-insulator structure 100.2B. Figure 1B However, it should be understood that by varying the pattern of the one or more first protective shapes 181e on the active device region (e.g., the number, size, shape, orientation, position, etc. of the one or more first protective shapes 181e), different patterns of polycrystalline portions 162 within the active device region 111 can be achieved, thereby achieving different semiconductor-on-insulator structures (e.g., semiconductor-on-insulator structures 100.2B, 100.3B, 100.4B, or 100.5B or any other similar semiconductor-on-insulator structure that includes an active device region 111 within single crystalline and polycrystalline portions 161-162 and a underlying insulator layer).

[0076] Subsequently, the first protective layer 181 can be selectively removed (see process step 1518 and Figure 20 ). Optionally, the height of the STI region can also be reduced such that the top of the STI region is approximately flush with the top surface of the dielectric layer 180 (see process step 1520 and Figure 20 ). It should be noted that if process step 1520 results in the removal of the dielectric layer 180 and exposes the underlying semiconductor surface, the first dielectric material can be re-deposited to re-form this dielectric layer 180.

[0077] Referring to the flowchart and Figure 6 ).Figure 15 The flowchart illustrates that after forming a high-resistivity polycrystalline semiconductor element in semiconductor layer 101, additional processing can be performed to complete semiconductor structures 100.1-100.5 (see...). Figure 6 Process step 632 and Figure 1A , Figure 2A , Figures 3A-1 to 3A-3 , Figures 4A-1 to 4A-2 ,as well as Figures 5A-1 to 5A-3 The bulk semiconductor structures 100.1A-100.5A shown are also described. Figure 15 Process steps 1522 and Figure 1B , Figure 2B , Figures 3B-1 to 3B-3 , Figures 4B-1 to 4B-2 ,as well as Figures 5B-1 to 5B-3 The semiconductor-on-insulator structure shown is 100.1B-100.5B.

[0078] exist Figure 6 Process step 632 or Figure 15 The additional processing of process step 1522 may include active semiconductor device formation. Specifically, an active semiconductor device (e.g., a FET or other device) may be formed to have at least one device component located in device region 111 and including at least one previously formed polycrystalline portion 162. In some embodiments, in Figure 6 Process step 632 or Figure 15The active semiconductor device 110 formed by process step 1522 can be a multi- finger FET (e.g., for a low noise amplifier (LNA) or a radio frequency (RF) switch). Formation of such a multi-finger FET (e.g., gate patterning, source / drain formation, etc.) can be performed such that one or more polysilicon portions 162 previously formed fall on or optionally surround one or more source / drain regions (e.g., common source / drain regions 142 / 132 and / or 132 / 152 between adjacent FETs), as shown in the figures and as described in detail above with respect to various structural embodiments. Optionally, one or more additional semiconductor devices (not shown) can be formed simultaneously on the semiconductor layer 101 within one or more other design regions (e.g., within design region 191). Techniques for forming active semiconductor devices, including FETs (e.g., simple FETs, multi-finger FETs, etc.) as well as other types of active semiconductor devices, are well known techniques, and thus, details are omitted from the present description to allow the reader to focus on the salient aspects of the disclosed methods. This additional processing can also include, but is not limited to, dielectric layer deposition, middle of the line (MOL) contact formation (e.g., gate contact formation, source / drain contact 199 formation, etc.), etc. As described in detail above with respect to semiconductor structural embodiments, one factor to consider during patterning of one or more polysilicon portions 162 within a source / drain region of an FET and further during patterning of a source / drain contact 199 is that it is preferable for the source / drain contact to land on single-crystal semiconductor material, rather than polysilicon semiconductor material.

[0079] It should be appreciated that in the above-described methods and structures, the semiconductor material is a material whose electrical properties can be changed by doping with impurities. Example semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and gallium nitride-based semiconductor materials. A pure semiconductor material, particularly a semiconductor material that is not doped with impurities to increase electrical conductivity (i.e., an undoped semiconductor material), is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with impurities to increase electrical conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor, and will be more electrically conductive than an intrinsic semiconductor made of the same base material. That is, an extrinsic silicon will be more electrically conductive than an intrinsic silicon; an extrinsic silicon germanium will be more electrically conductive than an intrinsic silicon germanium, and so on. Moreover, it should be appreciated that different impurities (i.e., different dopants) can be used to obtain different conductivity types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor material used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with a Group III dopant such as boron (B) or indium (In) to obtain P-type conductivity, and typically doped with a Group V dopant such as arsenic (As), phosphorus (P) or antimony (Sb) to obtain N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to obtain P-type conductivity, or with silicon (Si) to obtain N-type conductivity. Those skilled in the art will also appreciate that different levels of conductivity will depend on the relative concentration levels of the dopants in a given semiconductor region.

[0080] It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, unless specifically stated otherwise, as used herein, the singular "a" and "the" include plural referents. Also, as used herein, the term "including" means including but not limited to, the meaning of the term "comprising" is inclusive (meaning that the compositions, methods, objects, etc. that are "comprised" need not be "comprised exclusively") and specifically indicate open-ended includes with or without the use of "comprising", "having" and "including" in this specification, the meaning of the term "consisting of is close-ended (meaning that the compositions, methods, objects, etc. "consisting of need to be only those particular compositions, methods, objects, etc. listed and no others), and specifically indicate that the listed composition, method, object, etc. are the only ones with which a device, article, composition, etc. can consist of. Moreover, as used herein, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "over", "under", "parallel", "perpendicular", and the like are intended to relate to the relative positions with respect to the orientation of the figures as they are shown in the drawings, unless otherwise indicated. Terms such as "touching", "directly touching", "adjacent", "directly adjacent", "immediately adjacent", and the like are intended to mean that at least one element is in physical contact with another element (without other elements intervening between the elements). As used herein, the term "laterally" is intended to relate to the relative positions of elements as they are shown in the drawings, and in particular means that one element is to the side of another element rather than above or below the other element. For example, one element laterally adjacent another element will be to the side of the other element, one element laterally immediately adjacent another element will be directly to the side of the other element, and one element laterally surrounding another element will be adjacent and encircling the outer sidewall of the other element. All means or step plus function elements in the claims that follow the

[0081] The description of various embodiments of the application has been made for the purpose of exemplification, and is not intended to be exhaustive or to limit the scope and spirit of the embodiments. Numerous modifications and variations will be apparent to those skilled in the art, without departing from the scope and spirit of the embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvements over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0082] Accordingly, embodiments of semiconductor structures having one or more in- device high-resistivity poly crystalline semiconductor elements are disclosed above. The semiconductor structures can be bulk semiconductor structures or semiconductor-on- insulator structures (e.g., silicon-on-insulator (SOI) structures). In any case, the semiconductor structures can include a semiconductor layer having a first surface and a second surface opposite the first surface. The semiconductor layer can also have a device region adjacent the second surface, and a single crystalline portion and one or more poly crystalline portions within the device region, the one or more poly crystalline portions extending vertically from the second surface through the single crystalline portion toward the first surface. The semiconductor structures can also include an active semiconductor device. Among other features, the active semiconductor device can include a device component located within the device region of the semiconductor layer and including at least one poly crystalline portion extending vertically through the single crystalline portion. The embodiments of the semiconductor structures can vary depending on the type of structure (e.g., bulk or SOI), depending on the type of active semiconductor device therein, and depending on the number, size, shape, location, orientation, etc. of the one or more poly crystalline portions within the active semiconductor device. Embodiments of methods of forming such semiconductor structures are also disclosed above.

Claims

1. A semiconductor structure, comprising: A semiconductor layer having a first surface and a second surface opposite to the first surface, wherein the semiconductor layer has a device region adjacent to the second surface, a single-crystal portion located within the device region, and at least one polycrystalline portion extending from the second surface toward the first surface through the single-crystal portion to a buried polycrystalline portion, wherein the buried polycrystalline portion comprises the same material as the single-crystal portion and the at least one polycrystalline portion; and An active semiconductor device, comprising the single-crystal portion and the at least one polycrystalline portion, Within this device region, the at least one polycrystalline portion includes a plurality of polycrystalline portions extending through the single-crystal portion. The active semiconductor device includes a field-effect transistor, which includes alternating channel regions and source / drain regions located within the device region. The source / drain regions located laterally between the two channel regions include at least one of the plurality of polycrystalline portions. Each of the two source / drain regions located on opposite sides of the channel region includes a single polycrystalline portion of the plurality of polycrystalline portions, and The single polycrystalline portion has multiple vertical segments connected in a square meandering pattern across the entire width of the source / drain region.

2. The semiconductor structure of claim 1, further comprising a trench isolation region located in the semiconductor layer at the second surface and extending to the buried polycrystalline portion. in, The device area extends laterally between the trench isolation areas. The semiconductor layer is a bulk semiconductor substrate, which further includes: An additional single-crystal portion is located at the first surface; and The embedded polycrystalline portion is located between the additional monocrystalline portion and the device area, and also extends laterally between and in contact with the trench isolation region.

3. A semiconductor structure, comprising: Substrate; An insulating layer is located on the substrate; A semiconductor layer having a first surface adjacent to the insulating layer and a second surface opposite to the first surface; A trench isolation region is located in the semiconductor layer extending from the second surface to the first surface, wherein the semiconductor layer has a device region extending laterally between the trench isolation regions, a single-crystal portion located within the device region, and at least one polycrystalline portion extending from the second surface through the single-crystal portion to the insulator layer located at the first surface; and An active semiconductor device, including the single-crystal portion and the at least one polycrystalline portion. Within this device region, the at least one polycrystalline portion includes a plurality of polycrystalline portions extending through the single-crystal portion. The active semiconductor device includes a field-effect transistor, which includes alternating channel regions and source / drain regions located within the device region. The source / drain regions located laterally between the two channel regions include at least one of the plurality of polycrystalline portions. Each of the two source / drain regions located on opposite sides of the channel region includes a single polycrystalline portion of the plurality of polycrystalline portions, and The single polycrystalline portion has multiple vertical segments connected in a square meandering pattern across the entire width of the source / drain region.

4. A method for forming a semiconductor structure, the method comprising: A semiconductor layer is provided having a first surface and a second surface opposite to the first surface, wherein the semiconductor layer initially has a single crystal structure; The semiconductor layer is processed such that, within the device region at the second surface, the semiconductor layer has a single-crystal portion and at least one polycrystalline portion extending from the second surface toward the first surface through the single-crystal portion to a buried polycrystalline portion, wherein the buried polycrystalline portion comprises the same material as the single-crystal portion and the at least one polycrystalline portion; and Forming an active semiconductor device including the single-crystal portion and the at least one polycrystalline portion. Within this device region, the at least one polycrystalline portion includes a plurality of polycrystalline portions extending through the single-crystal portion. The active semiconductor device includes a field-effect transistor, which includes alternating channel regions and source / drain regions located within the device region. The source / drain regions located laterally between the two channel regions include at least one of the plurality of polycrystalline portions. Each of the two source / drain regions located on opposite sides of the channel region includes a single polycrystalline portion of the plurality of polycrystalline portions, and The single polycrystalline portion has multiple vertical segments connected in a square meandering pattern across the entire width of the source / drain region.

5. The method as described in claim 4, in, The semiconductor layer is a bulk semiconductor substrate. The method further includes forming a trench isolation region in the semiconductor layer at the second surface to define the device region, and The process of performing the semiconductor layer is such that the buried polycrystalline portion is formed between the additional single-crystal portion on the first surface and the device region, and is also located between the trench isolation region, such that the first distance between the second surface and the bottom surface of the trench isolation region is less than the second distance between the second surface and the interface between the device region and the buried polycrystalline portion.

6. The method as described in claim 4, in, The processing of the semiconductor layer and the formation of the active semiconductor device are performed such that the at least one polycrystalline portion includes a single polycrystalline portion that extends vertically through the source / drain region within the device region and is any one of being parallel to an adjacent channel region within the device region, perpendicular to an adjacent channel region within the device region, or completely surrounding the source / drain region.

7. A method for forming a semiconductor structure, the method comprising: Provide substrate; An insulating layer is provided on the substrate; A semiconductor layer is provided having a first surface adjacent to the insulating layer and a second surface opposite to the first surface, wherein the semiconductor layer initially has a single crystal structure; The semiconductor layer is processed such that, within the device region at the second surface, the semiconductor layer has a single-crystal portion and at least one polycrystalline portion extending from the second surface toward the first surface through the single-crystal portion; A trench isolation region is formed in the semiconductor layer extending from the second surface to the first surface, wherein the semiconductor layer has a device region extending laterally between the trench isolation regions, a single-crystal portion located within the device region, and at least one polycrystalline portion extending from the second surface through the single-crystal portion to the insulator layer located at the first surface; and Forming an active semiconductor device including the single-crystal portion and the at least one polycrystalline portion; Within this device region, the at least one polycrystalline portion includes a plurality of polycrystalline portions extending through the single-crystal portion. The active semiconductor device includes a field-effect transistor, which includes alternating channel regions and source / drain regions located within the device region. The source / drain regions located laterally between the two channel regions include at least one of the plurality of polycrystalline portions. Each of the two source / drain regions located on opposite sides of the channel region includes a single polycrystalline portion of the plurality of polycrystalline portions, and The single polycrystalline portion has multiple vertical segments connected in a square meandering pattern across the entire width of the source / drain region.

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