An AOP RF antenna packaging structure and a method for fabricating the packaging structure.

Abstract

This application relates to the field of semiconductor packaging technology, providing an AOP (Aspect-Oriented Programmable) RF antenna packaging structure and its fabrication method. The AOP RF antenna packaging structure includes: a substrate with through-holes penetrating both sides of the substrate; interconnect conductor layers formed on both sides of the substrate, interconnected through the through-holes; an assembly conductor layer formed on the interconnect conductor layers, including a mounting end and an antenna end, the mounting end being used for connection to the motherboard; and an antenna post formed on the antenna end. This application utilizes semiconductor processes to fabricate the interconnect conductor layer, assembly conductor layer, and antenna post on a glass substrate, ultimately achieving vertical mounting. The substrate provides Z-axis support, resulting in high mechanical strength. The intermediate interconnect conductor layer circuit coupling is matched and the design is flexible. The top antenna metal feed post is suspended in the air, providing good bandwidth and loss characteristics. This application integrates a miniature dipole antenna onto an RF package, realizing a novel AOP RF antenna integration method.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging technology, and in particular relates to an AOP radio frequency antenna packaging structure and a method for preparing the packaging structure. Background Technology

[0002] With the development of microwave integrated circuits, RF modules containing complete functions such as amplification, coupling, filtering, switching, and frequency conversion can be integrated into a single package, realizing the device-level integration of microwave components. This significantly improves the size, power, and efficiency of these devices. Analyzing the overall microwave topology, antenna loss and bandwidth at the front end become bottlenecks for further improving the performance of transceiver modules (TRs). In millimeter-wave and even terahertz phased array radars, due to channel spacing limitations, antennas need to be integrated into microwave device packages. AOP (Antenna-on-Package) packaged RF antennas are currently a hot research topic.

[0003] AOP-packaged RF antennas are conventionally fabricated using Low Temperature Co-fired Ceramic (LTCC) and High Density Interconnect (HDI) processes. LTCC reduces losses by introducing low-dielectric, ultra-thin dielectric ceramics and low-resistance silver conductors; HDI improves performance by using low-dielectric cores such as Liquid Crystal Polymer (LCP) and glass. The multi-layered metal and dielectric patch structure limits the bandwidth and losses of these two types of packaged RF antennas, failing to meet the requirements of multi-frequency multiplexed antenna relays (TRs). Summary of the Invention

[0004] In view of this, embodiments of this application provide an AOP radio frequency antenna packaging structure and a method for preparing the packaging structure, so as to realize an antenna AOP integrated packaging method and meet the requirements of multi-frequency multiplexed TR for antennas.

[0005] This application is achieved through the following technical solution:

[0006] In a first aspect, embodiments of this application provide an AOP (Aspect-Oriented Programmable RF Antenna Packaging Structure, comprising: a substrate having through holes penetrating both sides of the substrate; interconnect conductor layers formed on both sides of the substrate, wherein the interconnect conductor layers on both sides of the substrate are interconnected through the through holes; an assembly conductor layer formed on the interconnect conductor layer, including a mounting end and an antenna end, wherein the mounting end is used to connect to the motherboard; and an antenna post formed on the antenna end.

[0007] In this embodiment, an interconnect conductor layer is fabricated on a glass substrate using semiconductor technology, and the conductor layer and antenna pillars are assembled, ultimately achieving a novel AOP (Aspect-Oriented Programming) RF antenna integration method. This integrated packaging method is suitable for low-loss broadband antennas with multi-frequency multiplexing, and its symmetrically arranged dipole antennas can cover most frequency bands within the millimeter-wave band, meeting the antenna requirements of the high-frequency, multi-beam, and highly integrated TR (Transmission and Replication) field.

[0008] Based on the first aspect, in some embodiments, the two sides of the substrate have the same structure, which are, in sequence, a substrate, an interconnect conductor layer, an assembly conductor layer, and an antenna column.

[0009] In this embodiment, the substrate has a symmetrical structure of air, metal, substrate, metal, and air on both sides. The interconnect conductor layers on both sides of the substrate can be used to fabricate low-loss microstrip coupling circuits as needed, which allows for flexible design and improves the integration of RF antenna packaging.

[0010] Based on the first aspect, in some embodiments, the via is filled with a first conductor, and the interconnecting conductor layers on both sides of the substrate are interconnected through the first conductor.

[0011] Based on the first aspect, in some embodiments, the mounting ends on both sides of the substrate are used to connect with the motherboard pads to realize a three-dimensional connection between the AOP RF antenna package structure and the motherboard.

[0012] In this embodiment, the mounting end serves as a solder pad, which is soldered to the motherboard solder pad using solder. The XYZ three-dimensional dimensions of both the mounting end and the motherboard solder pad can be adjusted based on stress simulation results, and an enhanced design can be adopted to improve shear strength.

[0013] Based on the first aspect, in some embodiments, the thickness of the interconnect conductor layer is less than the thickness of the assembly conductor layer.

[0014] Based on the first aspect, in some embodiments, the substrate is made of inorganic non-metallic material.

[0015] In some embodiments, using inorganic non-metallic materials as substrates avoids the problem of degradation of conventional PCB organic materials under cosmic rays and atomic oxygen irradiation, and can be used for a long time in cosmic particle radiation, thus improving the environmental reliability of the antenna.

[0016] Secondly, embodiments of this application provide a method for fabricating an AOP radio frequency antenna package structure, comprising: forming through holes penetrating both sides of a substrate on a substrate; forming interconnect conductor layers on both sides of the substrate after forming the through holes, and the interconnect conductor layers on both sides of the substrate are interconnected through the through holes; forming an assembly conductor layer on the interconnect conductor layer, the assembly conductor layer including a mounting end and an antenna end, the mounting end being used to connect to a motherboard; and forming an antenna post on the antenna end.

[0017] Based on the second aspect, in some embodiments, forming an interconnect conductor layer on both sides of the substrate after the via is formed includes: sputtering seed layers on both sides of the substrate after the via is formed; coating a photoresist layer on the seed layer and obtaining a first pattern by photolithography; depositing a first conductor on the first pattern by electroplating and simultaneously filling the via, so that the coupling circuits on both sides of the substrate are connected; and thinning and surface treating the first conductor layer deposited on the first pattern by planarization process to form an interconnect conductor layer.

[0018] Based on the second aspect, in some embodiments, forming an assembly conductor layer on an interconnect conductor layer includes: coating a photoresist layer on the interconnect conductor layer, obtaining a second pattern through a photolithography process, and depositing a second conductor on the second pattern through an electroplating and planarization process to form an assembly conductor layer.

[0019] Based on the second aspect, in some embodiments, after the antenna pillar is formed, the photoresist material is removed to expose the seed layer by a film removal process; the seed layer in areas other than the first pattern definition area is removed to expose the substrate by a chemical etching method; and the surface area defined by the first pattern is coated and protected by a coating process.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the AOP radio frequency antenna packaging structure provided in the embodiments of this application;

[0023] Figure 2 This is a flowchart of the AOP radio frequency antenna packaging structure fabrication method provided in the embodiments of this application;

[0024] Figure 3 This is an exploded view of the fabrication steps of the AOP radio frequency antenna packaging structure provided in the embodiments of this application. Detailed Implementation

[0025] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0026] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0027] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0029] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0031] As phased array radar technology continues to evolve, the same TR (transmit and receive) unit within the same array needs to operate alternately in X / S / Ku / Ka bands and even higher to perform different functions such as communication, detection, and electronic countermeasures. The entire RF module of the TR unit needs to integrate modules for each frequency band simultaneously. The antenna at the front end, using AOP or AIP modes, must meet the technical requirements of low differential loss and high efficiency within an ultra-wide bandwidth. Existing technologies such as LTCC, HDI, and fan-out packaging are difficult to meet these requirements.

[0032] This application provides a novel process approach for fabricating low-loss antennas suitable for multi-frequency multiplexing, particularly suitable for the high-frequency, multi-beam, highly integrated TR field. Based on the technical problems mentioned in the background, embodiments of this application provide an AOP (Aspect-Oriented Programming) RF antenna packaging structure. Metal is horizontally stacked and electroplated on a non-metallic substrate to prepare interconnect conductors, assembly conductors, and antenna pillars. Finally, the substrate is mounted perpendicular to the mother plate via assembly pads. The low-loss, wideband antenna is integrated onto the RF device package using an antenna feed line suspension method, achieving a novel AOP RF antenna integration packaging method. The symmetrically arranged miniature dipole antennas using this packaging method can cover most frequency bands within the millimeter-wave band.

[0033] like Figure 1 As shown in the figure, an AOP (Aspect-Oriented Programmable RF Antenna Packaging Structure provided in this application includes:

[0034] The substrate 100 has through holes that penetrate both sides of the substrate;

[0035] Interconnect conductor layers 110 are formed on both sides of the substrate, and the interconnect conductor layers on both sides of the substrate are interconnected through vias;

[0036] Assemble conductor layer 120, formed on interconnect conductor layer, including mounting end and antenna end, the mounting end for connection with motherboard;

[0037] Antenna post 130 is formed on the antenna end.

[0038] The two sides of the substrate have the same structure, consisting of the substrate, interconnect conductor layer, assembly conductor layer and antenna column in sequence.

[0039] The substrate uses low-loss dielectric materials such as quartz glass to support the antenna. The interconnect conductor layer, assembly conductor layer and antenna column are all made of metal. The through holes are filled with a first conductor. The interconnect conductor layers on both sides of the substrate are interconnected through the first conductor.

[0040] In some embodiments, the metal thickness of the interconnect conductor layer is generally less than 0.1 mm. The middle connection section of the entire antenna package structure forms a symmetrical sandwich structure of interconnect conductor layer-substrate-interconnect conductor layer, including five layers: air, metal, substrate, metal, and air. The metal on both sides of the substrate is symmetrically arranged, which can fabricate low-loss microstrip coupled circuits, realize flexible circuit design, and improve the integration of RF antenna.

[0041] In some embodiments, the metal thickness of the assembly conductor layer is typically 0.2-3 mm. The assembly conductor layer includes a mounting end and an antenna end; the end connected to the motherboard is the mounting end, and the end connected to the antenna post is the antenna end. Due to the size constraints of the integrated packaged RF module, and the fact that the antenna is at the very front where external reinforcement space is limited, the mechanical strength of the antenna itself is crucial to the overall impact resistance of the RF module. The packaging structure in this embodiment adopts a symmetrical design with a simple stress structure. The central support substrate is made of a high-strength inorganic non-metallic material, which is not easily deformed. The mounting end serves as a solder pad, soldered to the motherboard pad using solder. The XYZ three-dimensional dimensions of both the mounting end and the motherboard pad can be adjusted based on stress simulation results, and reinforcement designs can be adopted to improve shear strength. The antenna end is integrally electroplated and can be optimized using structures such as edge under-support to ensure impact resistance.

[0042] In some embodiments, the antenna uses low-dielectric inorganic non-metallic materials such as glass as the insulating layer, without organic polymer materials such as C / H, thus avoiding the problem of characteristic degradation of conventional PCB organic materials under cosmic rays and atomic oxygen irradiation. It can be used for a long time in cosmic particle radiation, and has higher environmental reliability.

[0043] like Figure 2 As shown in the embodiment of this application, a method for fabricating an AOP radio frequency antenna packaging structure includes steps 101 to 104.

[0044] Step 101: Create through holes on both sides of the substrate.

[0045] In some embodiments, such as Figure 3 As shown in (a), through-holes are formed in the substrate. The substrate, used as the antenna support material, can be a low-loss, high-strength inorganic dielectric material such as glass, quartz, or sapphire. In actual production, large-size substrates with multiple unit arrays are used to improve production efficiency. The schematic diagram only shows a single unit of a large-size substrate as a representative example. Picosecond cold laser processing is used to process the through-holes, with diameters ranging from 70-125 μm, based on the substrate thickness (0.15-2 mm). The ratio of substrate thickness to through-hole diameter is ensured to be less than 10:1, and a typical through-hole diameter is 100 μm. The laser-drilled hole process results in smooth hole walls, high perpendicularity, and a diameter difference of less than 5% between the upper and lower surfaces.

[0046] Step 102: An interconnect conductor layer is formed on both sides of the substrate after the via is formed, and the interconnect conductor layers on both sides of the substrate are interconnected through the via.

[0047] In some embodiments, the implementation process of step 102 may include steps 1021 to 1024.

[0048] Step 1021: Sputter seed layers on both sides of the substrate after the through-hole is made.

[0049] In some embodiments, such as Figure 3 As shown in (b), seed layers are sputtered on both sides of the substrate after the vias are created. First, the substrate after drilling is cleaned. Then, a metal layer is sputtered onto the clean substrate surface as a seed layer for subsequent electrochemical deposition. Typical metal types for the seed layer are Ti / Cu, with a total thickness of 50nm-5000nm. The structure and thickness of the seed layer can be adjusted according to different process requirements. The deposition method for the seed layer can be physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0050] Step 1022: Coat the seed layer with a photoresist layer and obtain the first pattern through photolithography.

[0051] Based on the current path requirements of the antenna, a first photolithographic pattern is designed. In some embodiments, the shapes on both sides of the substrate are not exactly the same, based on... Figure 3 (c) shows the interconnecting conductor layer formed by the first pattern. Current is input from the center of the mounting end on the top view side, and guided to the antenna end on the top view side, while also being guided through the through hole to the antenna end on the bottom view side.

[0052] In some embodiments, a photoresist layer is coated onto the substrate surface by spin coating or hot-pressing, and then a first pattern is obtained through standard photolithography processes such as exposure and development, which is used for subsequent fabrication of the interconnect conductor layer. The photoresist can be a high-viscosity photoresist, such as JSR's THB series negative photoresist, or a high-resolution photosensitive dry film, such as DuPont's ST series dry film. The photoresist layer thickness should be greater than 30 μm, the line resolution less than 10 μm, and the sidewalls steep.

[0053] Step 1022: Deposit the first conductor on the first pattern by electroplating, and fill the through holes to make the coupling circuits on both sides of the substrate connected.

[0054] like Figure 3 As shown in (d), after obtaining the first pattern through photolithography, the first conductor in the surface region defined by the first pattern is thickened to 30-200 μm using electrochemical deposition. The first conductor is made of the same metal material as the metal seed layer. At the same time, the vias with the metal underlay are filled to the surface protrusion, with no voids inside.

[0055] In some embodiments, copper is selected as the first conductor material, preferably a Cu electrolyte with deep hole filling, and a combination of pulse plating and DC plating is used during electroplating to maximize efficiency while ensuring that there are no voids in the copper deposition inside the through hole.

[0056] Step 1022: The thickness of the first conductor layer deposited on the first pattern is reduced and the surface is treated by a planarization process to form an interconnect conductor layer.

[0057] By using a planarization process to reduce the thickness of the plating layer and perform surface treatment, higher precision layer thickness and lower surface roughness can be obtained. After photolithography, electroplating and planarization, an interconnect conductor layer is formed on the substrate.

[0058] Step 103: Form an assembly conductor layer on the interconnect conductor layer. The assembly conductor layer includes a mounting end and an antenna end. The mounting end is used to connect to the motherboard.

[0059] like Figure 3 As shown in (e), a photoresist layer is coated on the interconnect conductor layer, a second pattern is obtained by photolithography, and a second conductor is deposited on the second pattern by electroplating and planarization processes to form an assembled conductor layer.

[0060] Step 104: Form an antenna post at the antenna end.

[0061] like Figure 3 As shown in (f), a photoresist layer is coated on the surface of the assembled conductor layer, a third pattern is obtained by photolithography, and a third conductor is deposited on the third pattern to form an antenna column by electroplating and planarization processes.

[0062] like Figure 3 As shown in (g), after the antenna pillar is formed, the photoresist material is removed through a stripping process to expose the seed layer. Photolithography is then performed again, and the seed layer in areas not defined by the first pattern is removed through chemical etching to expose the substrate. A coating process is then used to protect the surface metal pattern areas defined by the first pattern, improving environmental resistance.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0064] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0065] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0066] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0067] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An AOP (Aspect-Oriented Programmable RF Antenna Packaging Structure, characterized in that, include: The substrate has through holes extending through both sides of the substrate; Interconnect conductor layers are formed on both sides of the substrate, and the interconnect conductor layers on both sides of the substrate are interconnected through the vias; An assembly conductor layer is formed on the interconnect conductor layer, including a mounting end and an antenna end, the mounting end being used for connection to the motherboard; An antenna column is formed on the antenna end; The substrate has the same structure on both sides, which are, in sequence, the substrate, the interconnect conductor layer, the assembly conductor layer and the antenna column; The substrate is made of inorganic non-metallic material; The antenna uses inorganic non-metallic materials as the insulation layer.

2. The AOP RF antenna packaging structure as described in claim 1, characterized in that, The through-hole is filled with a first conductor, and the interconnecting conductor layers on both sides of the substrate are interconnected through the first conductor.

3. The AOP RF antenna packaging structure as described in claim 1, characterized in that, The mounting ends on both sides of the substrate are used to connect with the motherboard pads, realizing a three-dimensional connection between the AOP RF antenna package structure and the motherboard.

4. The AOP RF antenna packaging structure as described in claim 1, characterized in that, The thickness of the interconnect conductor layer is less than the thickness of the assembled conductor layer.

5. A method for fabricating an AOP (Aspect-Oriented Programmable RF Antenna Packaging Structure, characterized in that, The method for fabricating the AOP RF antenna package structure as described in any one of claims 1 to 4 comprises: Through holes are formed on the substrate, penetrating both sides of the substrate; Interconnect conductor layers are formed on both sides of the substrate after the via is formed, and the interconnect conductor layers on both sides of the substrate are interconnected through the via; An assembly conductor layer is formed on the interconnect conductor layer, the assembly conductor layer including a mounting end and an antenna end, the mounting end being used for connection to the motherboard; An antenna post is formed on the antenna end.

6. The method for fabricating the AOP RF antenna packaging structure as described in claim 5, characterized in that, The process of forming interconnect conductor layers on both sides of the substrate after the via is formed includes: Seed layers are sputtered on both sides of the substrate after the through-hole is opened; A photoresist layer is coated on the seed layer, and a first pattern is obtained by photolithography. A first conductor is deposited on the first pattern by electroplating, while the via is filled, so that the coupling circuits on both sides of the substrate are connected. The interconnect conductor layer is formed by thinning and surface treatment of the first conductor layer deposited on the first pattern through a planarization process.

7. The method for fabricating the AOP RF antenna packaging structure as described in claim 5, characterized in that, The process of forming an assembly conductor layer on the interconnect conductor layer includes: A photoresist layer is coated on the interconnect conductor layer, and a second pattern is obtained by photolithography. A second conductor is deposited on the second pattern through electroplating and planarization processes to form an assembled conductor layer.

8. The method for fabricating the AOP RF antenna packaging structure as described in claim 5, characterized in that, Also includes: After the antenna column is formed, the photoresist material is removed through a film removal process until the seed layer is exposed; The seed layer in areas not defined by the first pattern is removed by chemical etching to expose the substrate. The surface area defined by the first pattern is protected by a coating process.

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