amplification device

Abstract

The present application provides an amplifier device which is downsized. The amplifier device includes: an RF signal input terminal to which an RF signal is input; a buffer circuit having an input terminal connected to the RF signal input terminal, the RF signal being input to the input terminal; a linearizer; a power amplifier; and a control circuit. The linearizer includes a transistor provided at an input of the linearizer and having a control terminal. The control circuit outputs a first gate voltage which causes the transistor to operate in class B to the control terminal when a level of the RF signal input to the RF signal input terminal is a first level, and outputs a second gate voltage which causes the transistor to operate in class AB to the control terminal when the level of the RF signal is a second level higher than the first level. An output impedance of the buffer circuit viewed from an input side of the linearizer is set such that a reflection loss of the RF signal input from the buffer circuit to the linearizer becomes equal to or less than a predetermined level.

Description

Technical Field

[0001] This invention relates to an amplification device. Background Technology

[0002] Conventionally, there exists an MMIC (Monolithic Microwave Integrated Circuit) chipset that includes a transistor-implemented analog predistorter that performs Class C operation based on the input signal level to compensate for distortion of the output signal level of a power amplifier relative to the input signal level. The input signal of this MMIC chipset is in the E-band (see, for example, Non-Patent Document 1).

[0003] Existing technical documents

[0004] Non-patent literature

[0005] Non-patent literature 1: M. Gavell, G. C.Fager, SEGunnarsson, M.Ferndahl, H.Zirath, "An E-Band Analog Predistorter and Power Amplifier MMIC Chipset," IEEE Microwave and Wireless Components Letters, Vol.28, No.1, pp.31-33, Jan.2018.

[0006] Furthermore, analog predistorters performing Class C operations have low gain. Therefore, to increase the gain of the signal output from the power amplifier, the MMIC chip needs to include an additional amplifier besides the analog predistorter and the power amplifier. In this case, circuit devices such as MMIC chips become larger. Summary of the Invention

[0007] Therefore, the object of the present invention is to provide an amplification device that achieves miniaturization.

[0008] The amplification device disclosed herein includes: an RF (Radio Frequency) signal input terminal for receiving an RF signal; a buffer circuit having an input terminal connected to the RF signal input terminal for receiving the RF signal via the input terminal; a linearizer connected to the output side of the buffer circuit; a power amplifier connected to the output side of the linearizer; and a control circuit, wherein the linearizer includes a transistor disposed at the input portion of the linearizer and having a control terminal, the control circuit outputting a first gate voltage of the transistor performing Class B operation to the control terminal when the level of the RF signal input to the RF signal input terminal is a first level, and the control circuit outputting a second gate voltage of the transistor performing Class AB operation to the control terminal when the level of the RF signal is a second level higher than the first level, and the output impedance of the buffer circuit viewed from the input side of the linearizer is set such that the reflection loss of the RF signal input from the buffer circuit to the linearizer is below a predetermined level.

[0009] Invention Effects

[0010] The present invention provides a miniaturized amplification device. Attached Figure Description

[0011] Figure 1 This is a diagram showing a schematic configuration of the amplification device 100 and an example of the gain of each part.

[0012] Figure 2 This is a diagram illustrating an example of the pin-gain characteristics of the APD110.

[0013] Figure 3 This is a simplified diagram showing the internal structure of the APD110.

[0014] Figure 4 This is a diagram showing the configuration of the amplification device 100.

[0015] Figure 5 This is a diagram showing the equivalent circuit of the gate control circuit 112.

[0016] Figure 6 This is a diagram showing the equivalent circuit of buffer amplifier 110A and linearizer 111.

[0017] Figure 7 This is a diagram of an enlarged device 100M showing a modified example of the implementation method.

[0018] Explanation of reference numerals in the attached figures

[0019] 100, 100M: Amplification device

[0020] 101: RF signal input terminal

[0021] 102: RF signal output terminal

[0022] 50: Output stage amplifier

[0023] 51: DA

[0024] 52: PA (Power Amplifier)

[0025] 110: APD

[0026] 110A: Buffer Amplifier (Buffer Circuit)

[0027] 110A1: Input terminal

[0028] 202: FET (First FET)

[0029] 111: Linearizer

[0030] 212: FET (Second FET, Third FET)

[0031] 112: Gate control circuit (control circuit)

[0032] 112A: Coupling device (directional coupler)

[0033] 112B: Amplifier

[0034] 112B4: FET (Fourth FET)

[0035] 112C: Rectifier

[0036] 112C3: Capacitor

[0037] 112C4: Diode

[0038] 112C5: Capacitor (Smoothing Element)

[0039] 112D: Level Shifter

[0040] 112D5: FET (Fifth FET)

[0041] 120: Distributor

[0042] 130: Coupler. Detailed Implementation

[0043] The following describes the implementation method.

[0044] [Description of embodiments of this disclosure]

[0045] [1] An amplification device according to one aspect of the present disclosure includes: an RF signal input terminal for receiving an RF signal; a buffer circuit having an input terminal connected to the RF signal input terminal for receiving the RF signal via the input terminal; a linearizer connected to the output side of the buffer circuit; a power amplifier connected to the output side of the linearizer; and a control circuit, wherein the linearizer includes a transistor disposed at the input portion of the linearizer and having a control terminal, the control circuit outputs a first gate voltage of the transistor to the control terminal when the level of the RF signal input to the RF signal input terminal is a first level, and the control circuit outputs a second gate voltage of the transistor to the control terminal when the level of the RF signal is a second level higher than the first level, the control circuit outputs a second gate voltage of the transistor to the control terminal when the level of the RF signal is a second level higher than the first level, and the output impedance of the buffer circuit as seen from the input side of the linearizer is set such that the reflection loss of the RF signal input from the buffer circuit to the linearizer is below a predetermined level.

[0046] The output impedance of the buffer circuit, viewed from the input side of the linearizer, is set such that the reflection loss of the RF signal input from the buffer circuit to the linearizer is below a specified level. This suppresses the transmission of fluctuations in the input impedance of the linearizer during Class B and Class AB operations to the preceding stage of the buffer circuit. Furthermore, the control circuit outputs the first gate voltage to the control terminal when the RF signal level is the first level, and outputs the second gate voltage to the control terminal when the RF signal level is the second level. This increases the gain of the transistor when the RF signal level is the second level compared to the gain when the RF signal level is the first level. Consequently, the transistor performs a Class C operation, where the gain is increased in the high-level region of the RF signal. Moreover, this transistor operation is achieved by combining Class B and Class AB operations, thus obtaining a gain greater than that of Class C operation. Since a gain greater than that of Class C operation is obtained, no additional amplifier is required. Therefore, a miniaturized amplification device can be provided.

[0047] [2] In [1], the output impedance of the buffer circuit, viewed from the input side of the linearizer, may be set such that even if the input impedance of the linearizer, viewed from the output side of the buffer circuit, varies depending on whether the transistor performs a Class B operation, an operation between Class B and Class AB, or a Class AB operation, the reflection loss remains below a specified level. When the transistor of the linearizer performs each operation, the output impedance of the buffer circuit is set such that the reflection loss remains below a specified level. Therefore, regardless of which operation the transistor of the linearizer performs, the RF signal can be efficiently input from the buffer circuit to the linearizer.

[0048] [3] In [1] or [2], the RF signal may also be an E-band signal, and the specified level of the reflection loss represents the upper limit level value applicable to wireless communication in the E-band. Therefore, the E-band has low reflection loss, resulting in a good wireless communication environment.

[0049] [4] In any of [1] to [3], the buffer circuit may also include a first FET having a first gate terminal and a first drain terminal, the first gate terminal being connected to the input terminal of the buffer circuit, and the first drain terminal being connected to the output terminal of the buffer circuit. By using the first FET, the output impedance of the buffer circuit viewed from the input side of the linearizer can be more reliably set such that the reflection loss of the RF signal input from the buffer circuit to the linearizer is below a specified level, and by utilizing the high isolation of the first FET, the transmission of variations in the input impedance of the linearizer to the preceding stage of the buffer circuit can be more reliably suppressed.

[0050] [5] In any of [1] to [4], the transistor of the linearizer may also include: a second FET having a second gate terminal and a second drain terminal; and a third FET having a third gate terminal and a third drain terminal, the control terminal being connected to the input terminal of the linearizer, the second gate terminal and the third gate terminal being the control terminal, the second drain terminal and the third drain terminal being connected to the output terminal of the linearizer, and the portion between the second gate terminal and the second drain terminal of the second FET and the portion between the third gate terminal and the third drain terminal of the third FET being connected in parallel between the control terminal and the output terminal of the linearizer. The transistor of the linearizer includes the second FET and the third FET, thus enabling a greater gain. Therefore, a miniaturized amplification device can be more reliably achieved without the need for an additional amplifier.

[0051] [6] In any of [1] to [5], the control circuit may also include: a directional coupler having an input terminal connected to the RF signal input terminal, a first output terminal connected to the input terminal of the buffer circuit, and a second output terminal; an amplifier connected to the second output terminal; a rectifier connected to the output side of the amplifier; and a level converter connected to the output side of the rectifier, the level converter being connected to the control terminal and outputting the first gate voltage or the second gate voltage. The level converter outputs the first gate voltage or the second gate voltage based on the output of the second output terminal of the directional coupler. Therefore, by controlling the voltage of the control terminal of the linearizer according to the signal level of the RF signal input to the input terminal, the transistor can be made to operate in Class B when the level of the RF signal is the first level, and the transistor can be made to operate in Class AB when the level of the RF signal is the second level. Therefore, an amplifier device that can reliably compensate for the distortion of the input-output characteristics of the power amplifier and achieve miniaturization can be provided.

[0052] [7] In [6], the amplifier may also have a fourth FET having a fourth gate terminal connected to the second output terminal and a fourth drain terminal connected to the rectifier. This fourth FET amplifies the AC component of the signal input to the fourth gate terminal and outputs it from the fourth drain terminal. The AC component of the signal input from the second output terminal to the fourth gate terminal of the amplifier's fourth FET is a signal reflecting the signal level of the RF signal. Therefore, the fourth FET can amplify the AC component corresponding to the signal level of the RF signal and output it to the rectifier, reliably enabling the transistors of the linearizer to perform either Class B or Class AB operation based on the signal level of the RF signal.

[0053] [8] In [7], the rectifier may also include: a capacitor connected to the fourth drain terminal of the fourth FET of the amplifier; a rectifier element connected to the output side of the capacitor; and a smoothing element connected to the output side of the rectifier element. The rectifier rectifies and outputs the amplified AC component input from the fourth drain terminal to the level converter. Therefore, a DC voltage reflecting the amplified AC component input from the fourth drain terminal of the fourth FET can be output to the level converter, and the transistor of the linearizer can reliably perform the Class B operation or the Class AB operation according to the signal level of the RF signal.

[0054] [9] In [8], the rectifier element may also have a diode connected from a branch line connecting the capacitor and the smoothing element. This diode is cut off when the RF signal level is the first level and turned on when the RF signal level is the second level. Therefore, the level of the DC voltage output to the level converter can be reliably changed when the RF signal level is the first level and when the RF signal level is the second level, and the transistor of the linearizer can reliably perform either the Class B operation or the Class AB operation based on the signal level of the RF signal.

[0055]

[10] In [9], the level shifter may also have a fifth FET having a fifth gate terminal connected to the output side of the smoothing element and a source terminal connected to the control terminal of the linearizer and to which the first gate voltage is applied. The fifth FET is turned off when the RF signal level is the first level and turned on when the RF signal level is the second level. Therefore, the first gate voltage can be output from the source terminal when the RF signal level is the first level, and a second gate voltage higher than the first gate voltage can be output from the source terminal when the RF signal level is the second level. Therefore, the transistor of the linearizer can reliably perform the Class B operation when the RF signal level is the first level, and the transistor of the linearizer can reliably perform the Class AB operation when the RF signal level is the second level.

[0056]

[11] In any of [1] to

[10] , the amplification device may further include: a distributor; a coupler; and an RF signal output terminal. The amplification device includes multiple series circuits formed by connecting the buffer circuit, the linearizer, and the power amplifier in series. The distributor is connected between the RF signal input terminal and the input terminals of the multiple buffer circuits. The coupler is connected between the multiple power amplifiers and the RF signal output terminal. The multiple series circuits are connected in parallel between the distributor and the coupler. The control circuit outputs the first gate voltage or the second gate voltage to the control terminals of the transistors of the multiple linearizers. The multiple series circuits are connected in parallel between the distributor and the coupler, thereby increasing the gain of the RF signal input to the input terminal, providing an amplification device with high gain and miniaturization.

[0057] [Details of the embodiments of this disclosure]

[0058] The embodiments of this disclosure will now be described in detail, but these embodiments are not limited thereto. It should be noted that in this specification and accompanying drawings, sometimes repeated descriptions are omitted by using the same reference numerals to denote constituent elements having substantially the same functional configuration.

[0059] <Implementation Method>

[0060] [A rough outline of the amplification device 100]

[0061] Figure 1 This is a diagram illustrating a schematic configuration of the amplifier 100 and an example of the gain of each component. The amplifier 100 includes an RF signal input terminal 101, an RF signal output terminal 102, an APD (Analog Predistorter) 110, and an output stage amplifier 50. Figure 1 The diagram illustrates the configuration of the RF signal input terminal 101, the RF signal output terminal 102, the APD 110, and the output stage amplifier 50. The gain characteristics (Pin-gain characteristics) of each of the APD 110, the output stage amplifier 50, and the RF signal output terminal 102 relative to the power Pin of the input signal are shown below each of these components. The gain (dB) is the ratio of the power Pout (dBm) of the output signal in the amplifier, such as the output stage amplifier 50, to the power Pin (dBm) of the input signal.

[0062] As an example, the amplification device 100 is installed in a portable telephone base station to amplify radio waves (RF signals) used to transmit to terminals such as smartphones. In a portable telephone base station, for example, a high gain is required to amplify the RF signal using a single amplification device 100. Furthermore, since the portable telephone base station transmits RF signals across multiple frequency bands (multiple frequency bands), a wide frequency bandwidth (a broad frequency band) is required to amplify multiple frequency bands of RF signals using a single amplification device 100, for example. As an example, the amplification device 100 is used to amplify RF signals from frequency bands including the E-band (frequency bands of 5GHz from 71GHz to 76GHz and 5GHz from 81GHz to 86GHz). E-band RF signals are millimeter-wave RF signals (for example, a band of approximately 30GHz to approximately 300GHz). The E-band is a frequency band used in 5G (Fifth Generation). Furthermore, to improve the installability of the portable telephone base station, the amplification device 100 needs to be miniaturized.

[0063] It should be noted that, as an example, the transistors or FETs (Field Effect Transistors) described below are implemented using GaAs-HEMTs (High Electron Mobility Transistors) or GaN-HEMTs that perform well in the millimeter-wave band.

[0064] RF signal input terminal 101 is the terminal for inputting and transmitting RF signals. An APD 110 is connected to the RF signal input terminal 101. An output stage amplifier 50 is connected to the output side of the APD 110, and an RF signal output terminal 102 is connected to the output side of the output stage amplifier 50. As an example, the output stage amplifier 50 is a Class AB amplifier, and as shown below the output stage amplifier 50, its pin-gain characteristic has: a linear region where the gain is approximately constant relative to the power level of the input signal Pin; and a saturation region where the gain saturates as the power level of the input signal Pin increases to a certain extent. When the input signal is amplified with such a pin-gain characteristic, the difference between the saturated output power Psat and the 1dB gain compression point P1dB in the characteristic of the output signal power Pout of the output stage amplifier 50 relative to the power level of the input signal Pin increases. Here, as the power level of the input signal Pin continues to increase, the power level Pout of the amplifier's output signal converges (saturates) to a constant value. The output power Pout, after being amplified, is saturated with the power level of the output signal and is called the saturated output power Psat. Furthermore, the output power Pout, which decreases by 1 dB relative to the linear and ideal increase in power from the amplifier output as the input signal power Pin continues to increase, is called the 1dB gain compression point P1dB. A larger value for the 1dB gain compression point P1dB indicates better linearity of the amplifier.

[0065] As in Figure 1As shown below APD110, APD110 has a pin-gain characteristic that distorts the pin-gain characteristic of the output stage amplifier 50 in the opposite direction of the vertical axis representing gain relative to the horizontal axis representing the power pin of the input signal. When the gain characteristic of the RF signal input from the RF signal input terminal 101 is distorted by such APD110 and then input to the output stage amplifier 50, as shown below the RF signal output terminal 102, the pin-gain characteristic of the RF signal output from the output stage amplifier 50 to the RF signal output terminal 102 becomes a characteristic that provides approximately constant gain from the region where the power pin of the input signal is low to the region where the power pin of the input signal is high. That is, APD110 can reduce the difference between the saturated output power Psat of the output stage amplifier 50 and the 1dB gain compression point P1dB. A smaller difference between the saturated output power Psat and the 1dB gain compression point P1dB means that the value of the 1dB gain compression point P1dB increases. Furthermore, if the 1dB gain compression point P1dB increases, the value of OIP3 (Output Intercept Point 3rd) also becomes better. Here, OIP3 is the third-order cutoff point of the amplifier's output. Specifically, when two signals with similar frequency bands are simultaneously input to the amplifier, third-order intermodulation distortion (IM) occurs as a third-order distortion component. The third-order intermodulation distortion component appears near the frequency bands of the two signals, affecting the signal wave as an interference wave. The third-order intermodulation distortion component increases as the level of the input signal increases. Let OIP3 be the output level point at the intersection of the ideal linearity of the amplifier's output signal relative to the input signal when the amplifier is not saturated and the characteristic when the third-order intermodulation distortion component of the amplifier increases linearly. Therefore, the higher the OIP3, the smaller the difference between the saturated output power Psat and the 1dB gain compression point P1dB.

[0066] APD110 flattens the pin-gain characteristic of the output stage amplifier 50 by compensating for the pin-gain characteristic, where the pin-gain characteristic represents the relationship between the gain assigned to the RF signal output from the RF signal output terminal 102 and the power pin of the RF signal input to the RF signal input terminal 101. Therefore, by placing APD110 in the pre-stage (closer to the RF signal input terminal 101) of the output stage amplifier 50, the amplification device 100 can operate as a power amplifier with high linearity, linearly amplifying power from the region of low power pin level to the region of high power pin level of the input signal. It should be noted that... Figure 1The gain of the RF signal output from the RF signal output terminal 102 shown is approximately perfectly flat (linear) relative to the power pin of the RF signal input to the RF signal input terminal 101, which is an ideal characteristic.

[0067] [Pin-Gain Characteristics of APD110]

[0068] Figure 2 This is a graph illustrating an example of the pin-gain characteristics of the APD110. Figure 2 In the diagram, the pin-gain characteristics of the APD110 are shown in solid lines, while the pin-gain characteristics for Class C, Class B, and Class AB operations are shown in dashed lines. Due to the different operating points of the transistors, the gain obtained relative to the power pin of the input signal increases in this order for Class C, Class B, and Class AB operations. That is, the gain obtained through Class B operation is greater than the gain obtained through Class C operation, and the gain obtained through Class AB operation is greater than the gain obtained through Class B operation.

[0069] Here, as an example, the Pin-gain characteristic of the output stage amplifier 50 based on Class AB operation, which is distorted in the direction of the vertical axis representing the gain relative to the horizontal axis representing the power Pin of the input signal, can be as follows: like Class C operation, the gain is approximately constant from the region where the power Pin of the input signal is low until the power Pin of the input signal increases to a certain extent, and the gain increases sharply when the power Pin of the input signal increases further after it has increased to a certain extent.

[0070] Such a Pin-gain characteristic, which causes the output stage amplifier 50 to have a reverse distortion relative to the horizontal axis representing the power Pin of the input signal in the direction of the vertical axis representing the gain, can be achieved, for example, by combining a region in which the gain relative to the power Pin of the input signal is approximately constant in Class B operation with a region in which the gain relative to the power Pin of the input signal increases sharply in Class AB operation.

[0071] Therefore, the APD110 implements the Pin-Gain characteristic shown in solid lines using a transistor. This transistor operates in Class B mode in region (1), from a region where the input signal power Pin is low until the input signal power Pin increases to a certain extent. In region (2), where the input signal power Pin further increases compared to region (1), the gain increases sharply, approaching Class AB mode from Class B mode. In region (3), where the input signal power Pin further increases compared to region (2), Class AB mode is performed. Region (2) is a transitional region from Class B mode to Class AB mode, representing the region where Class B mode and Class AB mode occur. The gate voltage of the transistor included in the APD110 during Class B mode is an example of a first gate voltage, and the gate voltage during Class AB mode is an example of a second gate voltage.

[0072] The Pin-gain characteristic shown by the solid line is obtained by combining the region (1) where the gain is approximately constant through Class B operation, the region (2) where the gain increases in a manner approaching Class AB operation from Class B operation, and the region (3) where the gain increases sharply through Class AB operation. The Pin-gain characteristic shown by the solid line achieves a variation characteristic similar to the variation characteristic of the Pin-gain characteristic of Class C operation by combining the Pin-gain characteristics from region (1) to region (3). Furthermore, the Pin-gain characteristic shown by the solid line is achieved through Class B operation, the transition period operation between Class B and Class AB operation, and Class AB operation, thus achieving a higher gain than Class C operation. The Pin-gain characteristic shown by the solid line is an example of a Pin-gain characteristic of the output stage amplifier 50 based on Class AB operation that causes the horizontal axis representing the power Pin of the input signal to be distorted in the direction of the vertical axis representing the gain.

[0073] [A general overview of the APD110's structure and pin-gain characteristics]

[0074] Figure 3 This diagram provides a simplified representation of the internal structure of the APD110. Figure 3 In addition to showing the APD110, the output stage amplifier 50 and the pin-gain characteristics of each part are also shown. The APD110 has a linearizer (linearization circuit) 111 and a gate control circuit 112. The linearizer 111 includes a transistor with a gate terminal (control terminal) (in Figure 3 (Illustrations omitted). Figure 2 The pin-gain characteristic of the APD110, as explained in the text, refers to... Figure 3 The Pin-gain characteristic of linearizer 111 in the model.

[0075] The gate control circuit 112 has a coupler 112A that detects the signal level of the RF signal input from the RF signal input terminal 101, and controls the gate voltage Vg of the gate terminal of the transistor of the linearizer 111 based on the signal level of the RF signal detected by the coupler 112A. The coupler 112A is an example of a directional coupler.

[0076] exist Figure 3 In the dashed dialog box, the Pin-Vg characteristic of the gate voltage Vg output by the gate control circuit 112 relative to the power Pin of the input signal is shown. Furthermore, the Pin-gain characteristics of the linearizer 111, the output stage amplifier 50, and the RF signal output terminal 102 are shown below their respective pin-gain characteristics. Figure 3 In the Pin-Gain characteristics of the linearizer 111, output stage amplifier 50, and RF signal output terminal 102 shown, the gain of the transistor of the linearizer 111 is shown in solid line when the gate voltage of the transistor is controlled by the gate voltage Vg output by the gate control circuit 112.

[0077] Furthermore, for comparison, the gain in the pin-gain characteristic of linearizer 111 is shown by dashed lines when the transistor of linearizer 111 operates only in Class B mode. That is, the characteristic shown by dashed lines for comparison represents the gain when the gate voltage of the transistor of linearizer 111 is not controlled by the gate control circuit 112, and the transistor of linearizer 111 operates only in Class B mode.

[0078] Furthermore, in the pin-gain characteristic of the RF signal output terminal 102, a solid line shows the gain imparted to the RF signal output from the signal output terminal 102 when the gate voltage Vg of the transistor in the linearizer 111 is controlled by the gate voltage Vg output by the gate control circuit 112. For comparison, in the pin-gain characteristic of the RF signal output terminal 102, a dashed line shows the gain imparted to the RF signal output from the signal output terminal 102 when the gate voltage Vg is not controlled by the gate control circuit 112, and the transistor in the linearizer 111 only performs Class B operation.

[0079] The gate control circuit 112 controls the gate voltage Vg in regions (1), (2), and (3) as shown in the Pin-Vg characteristic in the dashed dialog box. The gate voltage Vg increases slowly with the increase of the power Pin of the input signal in region (1), increases sharply with the increase of the power Pin of the input signal in region (2) compared to region (1), and increases even more sharply with the increase of the power Pin of the input signal in region (3) compared to region (2).

[0080] The pin-gain characteristic of the linearizer 111, whose gate voltage Vg is controlled by such pin-Vg characteristics, is equal to the gain of the Class B operation shown by the dashed line in region (1), but the gain increases compared to the Class B operation in regions (2) and (3). Figure 2 The Class C operation shown also exhibits a sharp increase in gain in the region where the power pin of the input signal is high. This is achieved by controlling the gate voltage Vg through the gate control circuit 112, as described above. Figure 2 It is shown in solid lines and in Figure 3 The Pin-gain characteristic, shown in solid line below the linearizer 111, is implemented.

[0081] When the RF signal amplified by the Pin-gain characteristic of such linearizer 111 is input to the output stage amplifier 50, the RF signal will be affected by the distortion of the Pin-gain characteristic of the output stage amplifier 50. Therefore, as shown by the dashed line, the Pin-gain characteristic of the signal output terminal 102 when the gate voltage Vg is not controlled by the gate control circuit 112 becomes a characteristic that the gain drops sharply when entering region (2).

[0082] In contrast, as shown by solid lines, the pin-gain characteristic of the signal output terminal 102, when the gate voltage Vg is controlled by the gate control circuit 112, is approximately constant in gain, just like in region (1), even when entering region (2), and remains approximately constant until the gain saturates in region (3) where the power pin of the input signal is highest. By using APD 110 to compensate for the pin-gain characteristic of the output stage amplifier 50, the pin-gain characteristic, which represents the relationship between the gain given to the RF signal output from the RF signal output terminal 102 and the power pin of the RF signal input to the RF signal input terminal 101, can be flattened.

[0083] It should be noted that the transistor of the linearizer 111 of the APD110 is not operated in Class C mode, but rather in Class B mode, during the transition period between Class B and Class AB mode, and in Class AB mode, in order to obtain a higher gain than Class C mode. This achieves miniaturization of the amplifier 100 by obtaining a higher gain than Class C mode. Details will be described later.

[0084] [Composition of the amplification device 100]

[0085] Figure 4 This is a diagram showing the configuration of the amplification device 100. The amplification device 100 includes, in addition to... Figure 1 and Figure 3In addition to the RF signal input terminal 101, RF signal output terminal 102, APD 110, and output stage amplifier 50 shown, the system also includes a distributor 120 and a coupler 130. Furthermore, APD 110, besides having a linearizer 111 and a gate control circuit 112, also has a buffer amplifier 110A. Buffer amplifier 110A is an example of a buffer circuit and is located before the linearizer 111. Buffer amplifier 110A and linearizer 111 constitute linearization circuit 113.

[0086] exist Figure 4 In the diagram, three terminals are used to represent the RF signal input terminal 101 and the RF signal output terminal 102. These three terminals represent GSG (Ground-Signal-Ground). Numerous sections between the RF signal input terminal 101 and the RF signal output terminal 102 are connected by a transmission line with a characteristic impedance, similar to a microstrip line. As an example, the characteristic impedance is 50Ω.

[0087] exist Figure 4 In the amplification device 100 shown, APD 110 has two linearizers 111 and two buffer amplifiers 110A. The two linearizers 111 and the two buffer amplifiers 110A are connected in series. Furthermore, the amplification device 100 includes two output stage amplifiers 50. Each output stage amplifier 50 has a DA (Driver Amplifier) ​​51 and a PA (Power Amplifier) ​​52. PA52 is an example of a power amplifier. Inside each output stage amplifier 50, DA51 and PA52 are connected in series. Figure 4 In the amplification device 100 shown, two series circuits, consisting of a buffer amplifier 110A, a linearizer 111, a DA51, and a PA52 connected in series, are connected in parallel between the distributor 120 and the coupler 130. By connecting these two series circuits in parallel between the distributor 120 and the coupler 130, the RF signal input to the RF signal input terminal 101 can be amplified. It should be noted that while the method of connecting two series circuits in parallel between the distributor 120 and the coupler 130 has been described here, the number of series circuits connected in parallel can also be three or more.

[0088] [Configuration of RF signal input terminal 101 and coupling device 112A]

[0089] A coupling device 112A with a gate control circuit 112 connected to the RF signal input terminal 101 is used. The coupling device 112A is an example of a directional coupler, having an input terminal 112A1 and output terminals 112A2 and 112A3. Output terminal 112A2 is an example of a first output terminal, and output terminal 112A3 is an example of a second output terminal. Input terminal 112A1 is connected to the RF signal input terminal 101. The coupling device 112A outputs the RF signal input from the RF signal input terminal 101 to the input terminal 112A1 from the output terminal 112A2, and outputs a portion of the AC component of the RF signal input to the input terminal 112A1 from the output terminal 112A3.

[0090] [Composition of distributor 120]

[0091] The distributor 120 has an input terminal 121 and output terminals 122A and 122B. The input terminal 121 is connected to the output terminal 112A2 of the coupling device 112A. The output terminal 122A is connected to... Figure 4 The buffer amplifier 110A, shown in the upper series circuit, is connected to the input terminal 110A1, and the output terminal 122B is connected to the... Figure 4 The input terminals of the buffer amplifier 110A, shown in the series circuit below, are connected. The distributor 120 equally divides the power of the RF signal input from the coupling device 112A to the input terminal 121 into two parts and outputs them from the output terminals 122A and 122B.

[0092] [Construction of buffer amplifier 110A]

[0093] The buffer amplifier 110A has an input terminal 110A1 and an output terminal 110A2. Figure 4 The input terminal 110A1 of the buffer amplifier 110A in the upper series circuit is connected to the output terminal 122A of the distributor 120, and the output terminal 110A2 is connected to the input terminal 111A1 of the linearizer 111 in the upper circuit. Figure 4 The input terminal 110A1 of the buffer amplifier 110A in the lower series circuit is connected to the output terminal 122B of the distributor 120, and the output terminal 110A2 is connected to the input terminal 111A1 of the linearizer 111 in the lower circuit. The buffer amplifier 110A includes a FET, a gate voltage Vg1 is applied to the gate terminal of the FET, and a drain voltage Vd1 is applied to the drain terminal.

[0094] When the gate voltage Vg applied to the gate terminal of the transistor in linearizer 111 changes, causing the operation of the transistor in linearizer 111 to change from Class B operation through a transition state to Class AB operation, the input impedance of the transistor in linearizer 111 changes. Furthermore, when the operation of the transistor in linearizer 111 changes from Class AB operation through a transition state to Class B operation, the input impedance of the transistor in linearizer 111 changes.

[0095] The buffer amplifier 110A is configured such that even if the input impedance of the transistor in the linearizer 111 changes, the output impedance of the buffer amplifier 110A as viewed from the input side of the linearizer 111 is matched to a certain extent with the input impedance of the linearizer 111 as viewed from the output side of the buffer amplifier 110A.

[0096] For example, suppose the output impedance of the buffer amplifier 110A is matched with the input impedance of the linearizer 111 when the transistor of the linearizer 111 is operating in Class B mode. In this case, it is sufficient that even when the transistor of the linearizer 111 is operating in Class AB mode, the output impedance of the buffer amplifier 110A is matched with the input impedance of the linearizer 111 to a certain extent. This is also the case when the output impedance of the buffer amplifier 110A is matched with the input impedance of the linearizer 111 when the transistor of the linearizer 111 is operating in Class AB mode.

[0097] Furthermore, the output impedance of the buffer amplifier 110A can be matched with the input impedance of the linearizer 111 when the transistor of the linearizer 111 is operating between Class B and Class AB. In this case, regardless of whether the transistor of the linearizer 111 is operating in either Class B or Class AB mode, the output impedance of the buffer amplifier 110A is matched with the input impedance of the linearizer 111 to a certain extent.

[0098] Furthermore, more specifically, the buffer amplifier 110A is configured to ensure that even if the input impedance of the transistor in the linearizer 111 changes, the reflection loss of the RF signal input from the output terminal 110A2 of the buffer amplifier 110A to the input terminal 111A1 of the linearizer 111 remains below a specified value. This is because when the reflection loss is high, the RF signal will not be efficiently input from the buffer amplifier 110A to the linearizer 111, and the transmission efficiency of the RF signal will decrease. Here, reflection loss refers to the ratio of reflected power to input power in the high-frequency circuit receiving the input RF signal, expressed in decibels (dB).

[0099] For example, when the transistor of linearizer 111 is operating in Class B mode, the specified value of the reflection loss can be set to -10dB. If this is done, when the transistor of linearizer 111 is operating in Class AB mode or in a state between Class B and Class AB mode, the reflection loss will increase compared to -10dB, for example, to -7dB or -5dB. Thus, when the specified value of the reflection loss is already set when the transistor of linearizer 111 is operating in Class B mode, the reflection loss when the transistor of linearizer 111 is operating in Class AB mode or in a state between Class B and Class AB mode will be, for example, below the upper limit level (below the specified level) that allows the amplification device 100 to be applied to wireless communication in the E-band. This is also the case when the specified value of the reflection loss is already set when the transistor of linearizer 111 is operating in Class AB mode. When the transistors of linearizer 111 perform various operations, the output impedance of buffer amplifier 110A is set to be below a specified level for reflection loss. Therefore, regardless of which operation the transistors of linearizer 111 perform, the RF signal can be efficiently input from buffer amplifier 110A to linearizer 111.

[0100] Thus, as an example, the amplification device 100 can be used for wireless communication in the E-band at an upper limit level, such as -7dB or -5dB as mentioned above. It can also be set to a level that further reduces reflection loss, such as -10dB or -15dB, depending on the usage conditions of the wireless communication. If this is done, the reflection loss is low in the E-band, resulting in a good wireless communication environment.

[0101] Furthermore, the buffer amplifier 110A is provided to suppress the impact of changes in the input impedance of the linearizer 111 on the stage preceding the buffer amplifier 110A, even if such changes occur. The stage preceding the buffer amplifier 110A is impedance-matched between the stage preceding the stage of the linearizer 111. Therefore, when changes in the input impedance of the linearizer 111 affect the stage preceding the buffer amplifier 110A, the impedance matching between the stage preceding the stage of the linearizer 111 is affected, reducing the transmission efficiency of the RF signal. The buffer amplifier 110A is provided to prevent such changes in the input impedance of the linearizer 111 from affecting the stage preceding the buffer amplifier 110A. The buffer amplifier 110A includes a FET. The FET provides high isolation between the input and output sides. Utilizing the high isolation of the FET in the buffer amplifier 110A, a configuration is achieved that prevents changes in the input impedance of the linearizer 111 from affecting the stage preceding the buffer amplifier 110A.

[0102] [Construction of linearizer 111]

[0103] Linearizer 111 has an input terminal 111A1 and an output terminal 111A2. Input terminal 111A1 is connected to the output terminal 110A2 of buffer amplifier 110A, and output terminal 111A2 is connected to the input terminal 51A of DA51. The transistor in linearizer 111 is implemented by a FET. A gate voltage Vg is applied to the gate terminal of the FET from gate control circuit 112, and a drain voltage Vd is applied to the drain terminal. The FET in linearizer 111 operates in Class B, Class AB, or a transitional state between Class B and Class AB operations due to variations in the gate voltage Vg from gate control circuit 112 depending on the level of the RF signal. Because the operation of the FET in linearizer 111 varies in this way, the input impedance of linearizer 111 also varies.

[0104] [The composition of DA51]

[0105] DA51 has an input terminal 51A and an output terminal 51B. Input terminal 51A is connected to the output terminal 111A2 of linearizer 111, and output terminal 51B is connected to the input terminal 52A of PA52. As shown in the lower dialog box below DA51, DA51 has a configuration consisting of multiple amplifiers composed of multiple FETs connected in parallel. A gate voltage Vg6 is applied to the gate terminal of the FET in DA51, and a drain voltage Vd6 is applied to the drain terminal. DA51 has a lower amplification rate than PA52; relative to PA52, which is a high-output-power amplifier, DA51 is a medium-output-power amplifier. DA51 is used as the driver amplifier for PA52.

[0106] [The composition of PA52]

[0107] PA52 has an input terminal 52A and an output terminal 52B. Input terminal 52A is connected to output terminal 51B of DA51. Figure 4 The output terminal 52B of PA52 on the upper side is connected to the input terminal 131A of coupler 130. Figure 4 The output terminal 52B of PA52 on the lower side is connected to the input terminal 131B of coupler 130. As shown in the dialog box below PA52, PA52 has a configuration in which multiple amplifiers consisting of multiple FETs are connected in parallel. The multiple amplifiers of PA52 are connected in series with the multiple amplifiers of DA51, and the amplifiers of DA51 and PA52 connected in series are connected in parallel with each other. A gate voltage Vg7 is applied to the gate terminal of the FET of PA52, and a drain voltage Vd7 is applied to the drain terminal. PA52 has a higher amplification than DA51, and PA52 is a high output power amplifier.

[0108] [Configuration of Coupler 130]

[0109] Coupler 130 has input terminals 131A and 131B and an output terminal 132. Input terminal 131A is connected to... Figure 4 The output terminal 52B of PA52 in the series circuit shown above is connected, and the input terminal 131B is connected to the... Figure 4 The output terminal 52B of PA52, shown in the lower part of the series circuit, is connected. Output terminal 132 is connected to RF signal output terminal 102. Coupler 130 combines the RF signals input from the two PA52s to the two input terminals 131A and 131B and outputs them from output terminal 132.

[0110] [Construction of gate control circuit 112]

[0111] The gate control circuit 112 includes a coupling device 112A, an amplifier 112B, a rectifier 112C, and a level converter 112D. The coupling device 112A has already been described, so the amplifier 112B, the rectifier 112C, and the level converter 112D will be described here.

[0112] Amplifier 112B has an input terminal 112B1 and an output terminal 112B2. Input terminal 112B1 is connected to the output terminal 112A3 of coupling device 112A, and output terminal 112B2 is connected to the input terminal 112C1 of rectifier 112C. Amplifier 112B has a FET. The FET of amplifier 112B is an example of a fourth FET. A gate voltage Vg4 is applied to the gate terminal of the FET, and a drain voltage Vd4 is applied to the drain terminal. The gate voltage Vg4 and drain voltage Vd4 are fixed voltages. Amplifier 112B amplifies the AC component of the RF signal input from coupling device 112A with a specified gain and outputs it to rectifier 112C.

[0113] Rectifier 112C has an input terminal 112C1 and an output terminal 112C2. The output terminal 112C2 is connected to the input terminal 112D1 of level converter 112D. Rectifier 112C outputs the DC component obtained by rectifying the AC component amplified by amplifier 112B to level converter 112D.

[0114] Level shifter 112D has an input terminal 112D1 and an output terminal 112D2. Output terminal 112D2 is connected to the gate terminal of the FET in linearizer 111, outputting a gate voltage Vg. Level shifter 112D outputs a gate voltage Vg corresponding to the DC component input from rectifier 112C. When the signal level of the RF signal is... Figure 3When the level of region (1) in the Pin-Gain characteristic of linearizer 111 is reached, the gate voltage Vg output by level converter 112D becomes the voltage that causes the FET of linearizer 111 to operate in Class B mode. Furthermore, when the signal level of the RF signal is... Figure 3 When the level of region (2) in the Pin-Gain characteristic of linearizer 111 is reached, the gate voltage Vg output by level converter 112D becomes the voltage that causes the FET of linearizer 111 to operate between Class B and Class AB. Furthermore, when the signal level of the RF signal is... Figure 3 When the level of region (3) in the Pin-gain characteristic of linearizer 111 is reached, the gate voltage Vg output by level converter 112D becomes the voltage that causes the FET of linearizer 111 to perform Class AB operation.

[0115] [Equivalent circuit of gate control circuit 112]

[0116] Figure 5 This is a diagram showing the equivalent circuit of the gate control circuit 112. Here, the equivalent circuits of the coupling device 112A, amplifier 112B, rectifier 112C, and level converter 112D will be described.

[0117] In addition to the input terminal 112A1 and output terminals 112A2 and 112A3, the coupling device 112A also has two transmission lines 112A4 and 112A5. As an example, transmission lines 112A4 and 112A5 are constructed of microstrip lines. Transmission line 112A4 connects the input terminal 112A1 to the output terminal 112A2, and transmission line 112A5 connects the output terminal 112A3 to a grounded resistor. Transmission lines 112A4 and 112A5 extend parallel to each other in a near-parallel manner, performing capacitive coupling. When an RF signal is input from the input terminal 112A1 to the transmission line 112A4, the RF signal is output from the output terminal 112A2, and an AC component of the RF signal is generated in transmission line 112A5. The AC component of the RF signal generated in transmission line 112A5 is output from the output terminal 112A3.

[0118] Amplifier 112B, in addition to input terminal 112B1 and output terminal 112B2, also includes capacitor 112B3, FET 112B4, DC power supplies 112B5 and 112B6, and capacitor 112B7. FET 112B4 is an example of a fourth FET, its gate terminal is an example of a fourth gate terminal, and its drain terminal is an example of a fourth drain terminal. Capacitor 112B3 is connected in series between input terminal 112B1 and the gate terminal of FET 112B4, blocking the DC component of the signal input to input terminal 112B1.

[0119] FET112B4 has a gate terminal (G) connected to capacitor 112B3, a drain terminal (D) connected to capacitor 112B7, and a grounded source terminal (S). A DC power supply 112B5 with an output gate voltage Vg4 is connected to the gate terminal, and a DC power supply 112B6 with an output drain voltage Vd4 is connected to the drain terminal, thus FET112B4 is turned on. Therefore, FET112B4 can amplify the AC component of the RF signal input to the gate terminal and output it from the drain terminal via capacitor 112B7 to rectifier 112C. Capacitor 112B7 is connected in series between the drain terminal and the output terminal 112B2, blocking the DC component of the signal amplified by FET112B4. FET112B4 can amplify and output the AC component corresponding to the signal level of the RF signal to rectifier 112C, reliably enabling the transistor of linearizer 111 to operate in either Class B or Class AB mode depending on the signal level of the RF signal.

[0120] In addition to input terminal 112C1 and output terminal 112C2, rectifier 112C also includes capacitor 112C3, diode 112C4, capacitor 112C5, coil 112C6, and resistor 112C7. Capacitor 112C5 is an example of a smoothing element. Capacitor 112C3 is connected in series between input terminal 112C1 and the cathode of diode 112C4, blocking the DC component of the signal input to input terminal 112C1.

[0121] Diode 112C4 is an example of a rectifier element. The anode of diode 112C4 is grounded, and the cathode of diode 112C4 is connected to one of capacitors 112C3 and 112C5. Figure 5 The upper electrode (of the diode) is connected to coil 112C6. Diode 112C4 is branched off from the line connecting capacitors 112C3 and 112C5 and connected to ground. The threshold of diode 112C4 is set to the level of the RF signal input to RF signal input terminal 101. Figure 3 The amplitude of the AC component in region (1) shown.

[0122] Therefore, the level of the RF signal input to the RF signal input terminal 101 is Figure 3 When the signal level in region (1) is shown, diode 112C4 is cut off, and when the level of the RF signal input to RF signal input terminal 101 becomes... Figure 3 When the signal level in region (2) is shown, diode 112C4 becomes conductive. The RF signal level input to RF signal input terminal 101 is... Figure 3 When the signal level in region (2) or (3) is shown, diode 112C4 will rectify and output the AC component input via capacitor 112C3. Diode 112C4 performs half-wave rectification. It should be noted that the orientation of diode 112C4 for half-wave rectification can also be reversed. That is, the anode of diode 112C4 can be connected to capacitors 112C3, 112C5, and coil 112C6, while the cathode of diode 112C4 is grounded. Alternatively, four diodes can be connected in a bridge configuration to perform full-wave rectification instead of diode 112C4.

[0123] Capacitor 112C5 is a smoothing capacitor that smooths the signal generated by diode 112C4 through half-wave rectification. Coil 112C6 is connected in series with one electrode of capacitor 112C5. Figure 5 Between the upper electrode of the coil 112C6 and the output terminal 112C2, the AC component of the voltage smoothed by capacitor 112C5 is blocked, and only the DC component is output. Resistor 112C7 is spun out from between coil 112C6 and output terminal 112C2 and connected to ground. Resistor 112C7 is set to generate a DC voltage ΔVdc at output terminal 112C2 when diode 112C4 becomes conductive and the AC component is rectified.

[0124] The level of the RF signal input to the RF signal input terminal 101 is Figure 3 When the signal level in region (1) is shown, the DC voltage ΔVdc at the output terminal 112C2 of rectifier 112C is approximately zero, and the level of the RF signal input to the RF signal input terminal 101 is... Figure 3 When the signal level in region (2) or (3) is shown, the DC voltage ΔVdc at the output terminal 112C2 of rectifier 112C increases as the voltage value of the AC component rectified by diode 112C4 increases. When the level of the RF signal input to the RF signal input terminal 101 is... Figure 3When the signal level in region (1) is shown, the DC voltage ΔVdc becomes the voltage that turns off the FET 112D5, which has a gate terminal connected to the output terminal 112C2. Furthermore, when the level of the RF signal input to the RF signal input terminal 101 is... Figure 3 When the signal level of region (2) or (3) is shown, the DC voltage ΔVdc becomes the voltage that turns on the FET112D5 of the level converter 112D.

[0125] The rectifier 112C outputs a DC voltage reflecting the amplified AC component input from the drain terminal of FET 112B4 to the level shifter 112D, reliably enabling the transistor of linearizer 111 to operate in either Class B or Class AB mode depending on the signal level of the RF signal. Furthermore, diode 112C4 can operate at RF signal levels of... Figure 3 When the signal level of region (1) and the signal level of the RF signal are the same as those of region (2) or (3), the level of the DC voltage output to the level converter 112D can be reliably changed, and the transistor of the linearizer 111 can be reliably operated in Class B or Class AB mode according to the signal level of the RF signal.

[0126] In addition to input terminal 112D1 and output terminal 112D2, level shifter 112D also includes DC power supply 112D3, resistor 112D4, FET 112D5, diode 112D6, and capacitor 112D7. FET 112D5 is an example of a fifth FET, and the gate terminal of FET 112D5 is an example of a fifth gate terminal.

[0127] The DC power supply 112D3 outputs voltage Vc. The DC power supply 112D3 is connected to the source terminal of FET 112D5 via resistor 112D4. The DC power supply 112D3 and resistor 112D4 are connected in series between the output terminal 112D2 and ground. When FET 112D5 is off, the gate voltage Vg output from the output terminal 112D of the level shifter 112D becomes voltage Vc. Voltage Vc is the voltage that causes the FET of linearizer 111 to operate in Class B mode in region (1).

[0128] FET112D5 has a gate terminal connected to input terminal 112D1, a source terminal connected to resistor 112D4 and output terminal 112D2, and a drain terminal connected to the anode of diode 112D6. The level of the RF signal input to RF signal input terminal 101 is... Figure 3 When the signal level in region (1) is shown, FET112D5 is off, and the level of the RF signal input to RF signal input terminal 101 is... Figure 3When the signal level of region (2) or (3) is shown, FET112D5 becomes on.

[0129] Diode 112D6 has an anode connected to the drain terminal of FET 112D5 and a cathode grounded. Capacitor 112D7 is branched off from the junction of the source terminal of FET 112D5 and resistor 112D4 and connected to the output terminal 112D2 and grounded.

[0130] The level of the RF signal input to the RF signal input terminal 101 is Figure 3 When the signal level in region (1) is shown, FET 112D5 becomes off, and therefore the gate voltage Vg output by level shifter 112D becomes voltage Vc. Gate voltage Vg becoming voltage Vc is an example of gate voltage Vg being the first gate voltage. Therefore, the FET of linearizer 111 performs Class B operation.

[0131] Furthermore, the level of the RF signal input to the RF signal input terminal 101 is... Figure 3 When the signal level in region (2) or (3) is shown, FET112D5 becomes on. Here, if the voltage of the source terminal of FET112D5 relative to the gate terminal is set to Vgs, then when FET112D5 is on, current flows from the source terminal to the drain terminal, so the gate voltage Vg of the output terminal 112D2 becomes Vg = Vc - Vgs + ΔVdc. The gate voltage Vg being Vg = Vc - Vgs + ΔVdc is an example of the gate voltage Vg being the second gate voltage.

[0132] The level of the RF signal input to the RF signal input terminal 101 is Figure 3 When the signal level is in region (2) or (3), the DC voltage ΔVdc output from output terminal 112C2 increases with the increase of the voltage value of the AC component rectified by diode 112C4. Therefore, the gate voltage Vg of output terminal 112D2 increases with the increase of the voltage value of the AC component rectified by diode 112C4. Therefore, when the RF signal level is the signal level in region (1), the voltage Vc can be output from the source terminal, and when the RF signal level is the signal level in region (2) or (3), a voltage Vg = Vc - Vgs + ΔVdc higher than Vc can be output from the source terminal. Therefore, when the RF signal level is the signal level in region (1), the transistor of linearizer 111 can reliably operate in Class B mode, and when the RF signal level is the signal level in region (2) or (3), the transistor of linearizer 111 can reliably operate in Class AB mode. By using the gate control circuit 112 as described above, the distortion of the input-output characteristics of the output stage amplifier 50 can be reliably compensated.

[0133] [Equivalent circuit of buffer amplifier 110A and linearizer 111]

[0134] Figure 6 This diagram shows the equivalent circuitry of buffer amplifier 110A and linearizer 111. In addition to input terminal 110A1 and output terminal 110A2, buffer amplifier 110A also includes matching circuit 201, FET 202, matching circuit 203, and matching circuits 204 and 205. FET 202 is an example of a first FET. The gate terminal of FET 202 is an example of a first gate terminal, and the drain terminal of FET 202 is an example of a first drain terminal.

[0135] Matching circuit 201 is located between input terminal 110A1 and gate terminal of FET 202, and has input terminal 201A and output terminal 201B. Input terminal 201A is connected to input terminal 110A1, and output terminal 201B is connected to gate terminal of FET 202 and output terminal 204B of matching circuit 204. As an example, matching circuit 201 has two capacitors and a coil. Matching circuit 201 is provided to achieve impedance matching between distributor 120 and buffer amplifier 110A.

[0136] Matching circuit 203 is located between the drain terminal of FET 202 and output terminal 110A2, and has input terminal 203A and output terminal 203B. Input terminal 203A is connected to the drain terminal of FET 202 and output terminal 205B of matching circuit 205, and output terminal 203B is connected to output terminal 110A2. As an example, matching circuit 203 has a coil and a capacitor. Matching circuit 203 is provided to achieve impedance matching with linearizer 111 connected via coupling device 111C. Furthermore, the input impedance of linearizer 111 changes depending on whether the FET of linearizer 111 operates in Class B or Class AB mode. Therefore, the electrostatic capacitance of capacitor and the inductance of coil of matching circuit 203 are set such that even if the operating state of FET of linearizer 111 changes, the reflection loss of RF signal input from output terminal 110A2 to input terminal 111A1 of linearizer 111 is controlled below a specified value.

[0137] Matching circuit 204 has a power supply terminal 204A and an output terminal 204B. Power supply terminal 204A is connected to the DC power supply for the output DC voltage Vg1. Between power supply terminal 204A and output terminal 204B of matching circuit 204, to achieve impedance matching between the gate terminal of FET 202 and power supply terminal 204A, for example, two capacitors, a coil, and a resistor are provided. Output terminal 204B is connected to the gate terminal of FET 202 and the output terminal 201B of matching circuit 201. Matching circuit 204 outputs the gate voltage Vg1 to the gate terminal of FET 202. The gate voltage Vg1 is a fixed DC voltage.

[0138] Matching circuit 205 has a power supply terminal 205A and an output terminal 205B. Power supply terminal 205A is connected to the DC power supply for the output DC voltage Vd1. Between power supply terminal 205A and output terminal 205B of matching circuit 205, to achieve impedance matching between the drain terminal of FET 202 and power supply terminal 205A, for example, two capacitors, a coil, and a resistor are provided. Output terminal 205B is connected to the drain terminal of FET 202 and the input terminal 203A of matching circuit 203. Matching circuit 205 outputs the drain voltage Vd1 to the drain terminal of FET 202. The drain voltage Vd1 is a fixed DC voltage.

[0139] FET202 has a gate terminal connected to the output terminal 201B of matching circuit 201 and the output terminal 204B of matching circuit 204, a drain terminal connected to the input terminal 203A of matching circuit 203 and the output terminal 205B of matching circuit 205, and a grounded source terminal. A gate voltage Vg1 is applied to the gate terminal of FET202 and a drain voltage Vd1 is applied to the drain terminal of FET202, thereby turning FET202 on, amplifying and outputting the signal input to the gate terminal via matching circuit 201.

[0140] The buffer amplifier 110A achieves impedance matching with the distributor 120 through the matching circuit 201, and the output impedance of the buffer amplifier 110A is matched with the input impedance of the linearizer 111 through the matching circuit 203. In addition, the FET 202 provides high isolation between the input and output sides, thus preventing the effects of variations in the input impedance of the linearizer 111 from affecting the preceding stages of the buffer amplifier 110A.

[0141] The buffer amplifier 110A and linearizer 111 described above are AC connected via a coupling device 111C. The coupling device 111C has two transmission paths that are capacitively coupled. As an example, the two transmission paths are formed by microstrip lines, one of which is connected to the output terminal 110A2 of the buffer amplifier 110A, and the other is connected to the input terminal 111A1 of the linearizer 111.

[0142] In addition to input terminal 111A1 and output terminal 111A2, linearizer 111 also has matching circuit 211, two FETs 212, matching circuit 213, and matching circuits 214 and 215. The two FETs 212 are examples of transistors in linearizer 111, and the gate terminals of the two FETs 212 are examples of control terminals of transistors in linearizer 111.

[0143] One of the two FETs 212 is an example of a second FET, and the other is an example of a third FET. The gate and drain terminals of the FET 212 that is an example of a second FET are respectively an example of a second gate terminal and a second drain terminal. The gate and drain terminals of the FET 212 that is an example of a third FET are respectively an example of a third gate terminal and a third drain terminal.

[0144] Matching circuit 211 is located between input terminal 111A1 and the gate terminals of the two FETs 212, and has input terminal 211A, output terminals 211B1 and 211B2, and connection terminal 211C. Input terminal 211A is connected to input terminal 111A1, and output terminals 211B1 and 211B2 are respectively connected to the gate terminals of the two FETs 212. Connection terminal 211C is connected to the output terminal 214B of matching circuit 214. As an example, matching circuit 211 has a capacitor, two coils, and a resistor. Matching circuit 211 is provided to achieve impedance matching between buffer amplifier 110A and linearizer 111, and more specifically, to achieve input impedance matching of linearizer 111 to the output impedance of buffer amplifier 110A. The resistor of matching circuit 211 is connected between the gate terminals of the two FETs 212 and to connection terminal 211C. Connecting the resistor in matching circuit 211 between the gate terminals of the two FETs 212 improves the isolation between their gate terminals. The gate voltage Vg is input from the gate control circuit 112 to the connection terminal 211C via matching circuit 214. It should be noted that if isolation between the gate terminals of the two FETs 212 can be achieved even without connecting the resistor in matching circuit 211, then the resistor in matching circuit 211 may not be necessary.

[0145] Matching circuit 213 is located between the drain terminals of the two FETs 212 and the output terminal 111A2, and has input terminals 213A1 and 213A2, an output terminal 213B, and a connection terminal 213C. Input terminals 213A1 and 213A2 are connected to the drain terminals of the two FETs 212, respectively. Output terminal 213B is connected to output terminal 111A2. Connection terminal 213C is connected to the output terminal 215B of matching circuit 215. As an example, matching circuit 213 has two coils, four capacitors, and one resistor. Matching circuit 213 is provided to achieve impedance matching between linearizer 111 and output stage amplifier 50. Furthermore, the output impedance of linearizer 111 as seen from output stage amplifier 50 changes depending on whether the FET of linearizer 111 is operating in Class B or Class AB mode. Therefore, the electrostatic capacitance of the capacitor and the inductance of the coil in the matching circuit 213 are set such that even if the operating state of the FET of the linearizer 111 changes, the reflection loss of the RF signal input from the output terminal 111A2 to the output stage amplifier 50 is controlled below a specified value.

[0146] Matching circuit 214 has a power supply terminal 214A and an output terminal 214B. Power supply terminal 214A is connected to the output terminal 112D2 of the level shifter 112D of the gate control circuit 112 that outputs the DC voltage Vg (see reference). Figure 4 and Figure 5 The matching circuit 214 is connected to the power supply terminal 214A and the output terminal 214B. To achieve impedance matching between the gate terminals of the two FETs 212 and the power supply terminal 214A, a matching circuit with two capacitors and a coil is provided as an example. The output terminal 214B is connected to the gate terminals of the two FETs 212 via the connection terminal 211C and the output terminals 211B1 and 211B2 of the matching circuit 211. The matching circuit 214 outputs the gate voltage Vg to the gate terminals of the two FETs 212.

[0147] Matching circuit 215 has a power supply terminal 215A and an output terminal 215B. Power supply terminal 215A is connected to a DC power supply for the output DC voltage Vd. Between power supply terminal 215A and output terminal 215B of matching circuit 215, to achieve impedance matching between the drain terminals of the two FETs 212 and power supply terminal 215A, a matching circuit with two capacitors and a coil is provided as an example. Output terminal 215B is connected to the drain terminals of the two FETs 212 via the two coils of matching circuit 213. Matching circuit 215 outputs the drain voltage Vd to the drain terminals of the two FETs 212. The drain voltage Vd is a fixed DC voltage.

[0148] Two FETs 212 have gate terminals connected to the output terminals 211B1 and 211B2 of the matching circuit 211, drain terminals connected to the input terminals 213A1 and 213A2 of the matching circuit 213, and a grounded source terminal. The portion between the gate terminals and drain terminals of the two FETs 212 is connected in parallel between the input terminal 111A1 and the output terminal 111A2 of the linearizer 111. Inside the linearizer 111, the two FETs 212 are connected to the input terminal 111A1 via the matching circuit 211. Therefore, the two FETs 212 are located at the input portion of the linearizer 111. A gate voltage Vg is applied to the gate terminals of the two FETs 212, and a drain voltage Vd is applied to the drain terminals of the two FETs 212, thereby turning on the two FETs 212, amplifying and outputting the signal input to the gate terminals via the matching circuit 211.

[0149] The two FETs 212 perform Class B operation, operation between Class B and Class AB operation, and Class AB operation based on the gate voltage Vg. Thus, they achieve... Figure 3 The characteristics of the linearizer 111 are shown in solid line in the Pin-Gain characteristic. Furthermore, by connecting the portions between the gate terminals and drain terminals of the two FETs 212 in parallel, a greater gain can be more stably imparted to the RF signal input to the input terminal 111A1, thus enabling the output of a higher power RF signal.

[0150] [Operation of the amplification device 100]

[0151] like Figure 4 As shown, the RF signal input to the RF signal input terminal 101 passes through the coupling device 112A of the gate control circuit 112, is distributed by the distributor 120, amplified by the buffer amplifier 110A, and then passes through the linearizer 111 to amplify the pin-gain characteristic of the output stage amplifier 50, which is distorted in the direction of the vertical axis representing the gain relative to the horizontal axis representing the power pin of the input signal. This amplified pin-gain characteristic is then input to the output stage amplifier 50. In the output stage amplifier 50, the RF signal is amplified by DA51 and PA52. At this time, the RF signal distorted by the pin-gain characteristic of the linearizer 111 is distorted by the pin-gain characteristics of DA51 and PA52. Therefore, the pin-gain characteristic, which represents the relationship between the gain of the RF signal output from the RF signal output terminal 102 and the power pin of the RF signal input to DA51, becomes a characteristic that provides approximately constant gain from the region where the power pin of the input signal is low to the region where the power pin of the input signal is high. That is, it can reduce the difference between the saturated output power Psat of the output stage amplifier 50 and the 1dB gain compression point P1dB. In addition, if the value of the 1dB gain compression point P1dB increases, the value of OIP3 also becomes better.

[0152] As described above, by setting up buffer amplifier 110A, even if the input impedance of linearizer 111 changes, the output impedance of buffer amplifier 110A can be matched with the input impedance of linearizer 111 to a certain extent, thereby reducing the reflection loss between buffer amplifier 110A and linearizer 111.

[0153] Due to low reflection loss, the RF signal is efficiently input from buffer amplifier 110A to linearizer 111 with low loss. The RF signal input to linearizer 111 is amplified by PA52 after being amplified according to the inverse characteristic of the pin-gain characteristic of PA52. This flattens the pin-gain characteristic, which represents the relationship between the gain assigned to the RF signal output from RF signal output terminal 102 and the power pin of the RF signal input to RF signal input terminal 101. The gain assigned to the RF signal by linearizer 111 is based on Class B or Class AB operation, which is greater than the gain assigned by Class C operation. Therefore, for amplification device 100, the pin-gain characteristic is flattened, allowing the output of an RF signal amplified by a large gain even without the use of an additional amplifier.

[0154] Therefore, by controlling the reflection loss of the RF signal input from the buffer amplifier 110A to the linearizer 111 below a specified value, miniaturization of the amplifier device 100 can be achieved.

[0155] Furthermore, the input impedance of the linearizer 111 is determined to a certain value based on whether the transistor of the linearizer 111 operates in Class B, between Class B and Class AB, or in Class AB mode. Therefore, by adjusting the output impedance of the buffer amplifier 110A to match the input impedance of the linearizer 111, the reflection loss of the RF signal input from the buffer amplifier 110A to the linearizer 111 can be controlled below a specified value. That is, the reflection loss of the RF signal input from the buffer amplifier 110A to the linearizer 111 is at least determined by the set value of the output impedance of the buffer amplifier 110A.

[0156] [Enlarged device 100M of the modified embodiment]

[0157] The above is for example Figure 4 The diagram illustrates a series circuit in which two buffer amplifiers 110A, linearizer 111, DA51, and PA52 are connected in parallel between distributor 120 and coupler 130. However, a single series circuit is also possible.

[0158] Figure 7This diagram illustrates an amplification device 100M, a modified embodiment. The amplification device 100M includes a buffer amplifier 110A, a linearizer 111, a DA51, and a PA52 connected in series, and therefore excludes the distributor 120 and coupler 130. Thus, the output terminal 112A2 of the coupling device 112A of the gate control circuit 112 is connected to the input terminal 110A1 of the buffer amplifier 110A, and the output terminal 52B of the PA52 is connected to the RF signal output terminal 102. Impedance matching is performed between the coupling device 112A and the buffer amplifier 110A via microstrip lines or the like. Furthermore, impedance matching is performed between the PA52 and the RF signal output terminal 102 via microstrip lines or the like.

[0159] In amplification device 100M, similarly to amplification device 100, buffer amplifier 110A and linearizer 111 are configured to be impedance matched to a certain extent even if the input impedance of linearizer 111 changes. Furthermore, buffer amplifier 110A suppresses the impact of input impedance changes of linearizer 111 on coupling device 112A, which is located before buffer amplifier 110A. Buffer amplifier 110A includes FET 202 (see reference...). Figure 6 Therefore, high isolation can be achieved between the input and output sides of the buffer amplifier 110A. Utilizing the high isolation of the FETs in the buffer amplifier 110A, the effects of variations in the input impedance of the linearizer 111 can be prevented from affecting the configuration of the preceding stage of the buffer amplifier 110A.

[0160] Therefore, like amplifier 100, amplifier 100M has a flattened pin-gain characteristic, allowing it to output an RF signal amplified by a large gain even without the use of an additional amplifier. Thus, by controlling the reflection loss of the RF signal input from buffer amplifier 110A to linearizer 111 below a specified value, miniaturization of amplifier 100M is possible.

[0161] The above describes an amplification device according to an exemplary embodiment of the present invention. However, the present invention is not limited to the specific embodiments disclosed, and various modifications and alterations can be made without departing from the claims.

Claims

1. An amplification device, comprising: RF signal input terminal, through which RF signals are input; A buffer circuit having an input terminal connected to the RF signal input terminal, through which the RF signal is input; A linearizer is connected to the output side of the buffer circuit; A power amplifier is connected to the output side of the linearizer; as well as Control circuit, The linearizer includes a transistor located at the input of the linearizer and has a control terminal. When the level of the RF signal input to the RF signal input terminal is a first level, the control circuit will output a first gate voltage that causes the transistor to operate in Class B mode to the control terminal. When the RF signal level is a second level higher than the first level, the control circuit will output a second gate voltage to the control terminal, causing the transistor to operate in Class AB mode. The output impedance of the buffer circuit, viewed from the input side of the linearizer, is set such that the reflection loss of the RF signal input from the buffer circuit to the linearizer is below a specified level. The control circuit has: A directional coupler having: an input terminal connected to the RF signal input terminal; a first output terminal connected to the input terminal of the buffer circuit; and a second output terminal; The amplifier is connected to the second output terminal; A rectifier is connected to the output side of the amplifier; as well as A level converter is connected to the output side of the rectifier. The level converter is connected to the control terminal and outputs the first gate voltage or the second gate voltage.

2. The amplification device according to claim 1, wherein, The output impedance of the buffer circuit, viewed from the input side of the linearizer, is set such that even if the input impedance of the linearizer, viewed from the output side of the buffer circuit, changes according to the transistor performing the Class B operation, the operation between the Class B operation and the Class AB operation, or the Class AB operation, the reflection loss remains below a specified level.

3. The amplification device according to claim 1 or 2, wherein, The RF signal is an E-band signal. The specified level of the reflection loss represents the upper limit level value that can be applied to wireless communication in the E-band.

4. The amplification device according to claim 1 or 2, wherein, The buffer circuit includes a first FET having a first gate terminal and a first drain terminal. The first gate terminal is connected to the input terminal of the buffer circuit. The first drain terminal is connected to the output terminal of the buffer circuit.

5. The amplification device according to claim 1 or 2, wherein, The transistor of the linearizer includes: A second FET having a second gate terminal and a second drain terminal; and The third FET has a third gate terminal and a third drain terminal. The control terminal is connected to the input terminal of the linearizer. The second gate terminal and the third gate terminal are the control terminals. The second drain terminal and the third drain terminal are connected to the output terminal of the linearizer. The portion between the second gate terminal and the second drain terminal of the second FET and the portion between the third gate terminal and the third drain terminal of the third FET are connected in parallel between the control terminal and the output terminal of the linearizer.

6. The amplification device according to claim 1, wherein, The amplifier has a fourth FET having a fourth gate terminal connected to the second output terminal and a fourth drain terminal connected to the rectifier. The fourth FET amplifies the AC component of the signal input to the fourth gate terminal and outputs it from the fourth drain terminal.

7. The amplification device according to claim 6, wherein, The rectifier has: A capacitor is connected to the fourth drain terminal of the fourth FET of the amplifier; A rectifier element is connected to the output side of the capacitor; as well as A smoothing element is connected to the output side of the rectifier element. The rectifier rectifies the amplified AC component input from the fourth drain terminal and outputs it to the level converter.

8. The amplification device according to claim 7, wherein, The rectifier element has a diode that is connected from a branch line connecting the capacitor and the smoothing element. The diode is turned off when the RF signal level is the first level and turned on when the RF signal level is the second level.

9. The amplification device according to claim 8, wherein, The level shifter has a fifth FET, which has a fifth gate terminal connected to the output side of the smoothing element and a source terminal connected to the control terminal of the transistor and to which the first gate voltage is applied. The fifth FET is turned off when the RF signal level is the first level, and turned on when the RF signal level is the second level.

10. The amplification device according to any one of claims 1, 2, 6 to 9, further comprising: Distributor; Coupler; as well as RF signal output terminal, Furthermore, the amplification device includes multiple series circuits consisting of the buffer circuit, the linearizer, and the power amplifier connected in series. The distributor is connected between the RF signal input terminal and the input terminals of the plurality of buffer circuits. The coupler is connected between the plurality of power amplifiers and the RF signal output terminal. Multiple series circuits are connected in parallel between the distributor and the coupler. The control circuit outputs the first gate voltage or the second gate voltage to the control terminals of the transistors of the plurality of linearizers.

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