A pulse control circuit

Abstract

The present application relates to a pulse control circuit, including a first-level circuit, a second-level circuit, a third-level circuit and a pulse width monitoring circuit; the first-level circuit, the second-level circuit and the third-level circuit are connected in series in sequence; the first-level circuit is used to convert a rising edge signal with a preset slope into a first pulse signal and transmit it to the second-level circuit; the second-level circuit is used to narrow the second pulse signal at the output end of the third-level circuit by adjusting the pulse width of the first pulse signal; the pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal; the pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal. The pulse control circuit provided in the embodiment of the present application uses a three-level circuit to simultaneously achieve narrow pulse width output and pulse width monitoring.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a pulse control circuit. Background Art

[0002] With the development of lasers, ultra-narrow laser pulses are widely used in many fields such as master oscillator power amplifiers, electro-optic modulators, lidar, and Raman spectroscopy. Among them, the pulse drive circuit is an important device that affects the performance of laser pulses. As the core component of the pulse drive circuit, the picosecond pulse generator directly determines the key performance of the system. In modern engineering applications, the requirements for the diversification of high-speed pulse signal sources are getting higher and higher, which not only require high pulse frequency and fast speed, but also require adjustable pulse width and amplitude while meeting portability.

[0003] However, the pulse signal width generated by the picosecond pulse signal generating circuit in the existing pulse signal generator is generally around 1000 picoseconds, the pulse width is relatively wide, or the pulse control mechanism is relatively complex, which has certain limitations in the application of laser seed source control, radiation antenna signal source and signal detection. Therefore, developing a picosecond pulse generator with a simple structure, adjustable pulse width and monitorability is a technical problem that needs to be solved in the current field of pulse signal processing technology. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a pulse control circuit, including a first-level circuit, a second-level circuit, a third-level circuit and a pulse width monitoring circuit;

[0005] The first-stage circuit, the second-stage circuit and the third-stage circuit are connected in series in sequence;

[0006] The first-stage circuit is used to convert a rising edge signal with a preset slope into a first pulse signal and transmit it to the second-stage circuit; the second-stage circuit is used to narrow the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal;

[0007] The pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal;

[0008] The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal.

[0009] In some embodiments, the first stage circuit further includes a first capacitor, the second stage circuit further includes a second capacitor, and the third stage circuit further includes a third capacitor;

[0010] The first capacitor, the second capacitor and the third capacitor are connected in series in sequence;

[0011] The input end of the first capacitor is used to receive the rising edge signal, and the output end of the first capacitor is used to output a first pulse signal; the input end of the second capacitor is used to receive the first pulse signal; the output end of the third capacitor is used to output a second pulse signal;

[0012] The input end of the pulse width monitoring circuit is electrically connected to the output end of the first capacitor, and the output end of the pulse width monitoring circuit is electrically connected to the second capacitor; the pulse width monitoring circuit is used to provide a bias voltage to the second capacitor.

[0013] In some embodiments, the first stage circuit further includes a first resistor, the second stage circuit further includes a second resistor, and the third stage circuit further includes a third resistor and a fourth resistor;

[0014] The input end of the first resistor is electrically connected to the output end of the first capacitor, and the output end of the first resistor is grounded;

[0015] The input end of the second resistor is electrically connected to the output end of the second capacitor, and the output end of the second resistor is grounded;

[0016] The input end of the third resistor and the input end of the fourth resistor are both electrically connected to the output end of the third capacitor, the output end of the third resistor is grounded, and the output end of the fourth resistor is equivalently grounded.

[0017] In some embodiments, the pulse width monitoring circuit includes a comparator, an adjustable voltage source, and a first choke unit connected in series in sequence;

[0018] The input terminal of the comparator is electrically connected to the output terminal of the first capacitor;

[0019] The output end of the first choke unit is electrically connected to the input end of the second capacitor;

[0020] The comparator is used to monitor the pulse width of the first pulse signal;

[0021] The adjustable voltage source is used to provide the bias voltage to the second capacitor;

[0022] The first choke unit is used to block the AC signal through the DC signal.

[0023] In some embodiments, the pulse width monitoring circuit further includes a second choke unit;

[0024] The input end of the second choke unit is electrically connected to the output end of the adjustable voltage source; the output end of the second choke unit is electrically connected to the input end of the second resistor;

[0025] The second resistor is an adjustable resistor.

[0026] In some embodiments, an amplitude control circuit is further included, wherein the output end of the amplitude control circuit is electrically connected to the third-stage circuit; the input end of the amplitude control circuit is used to receive a TTL voltage switch signal;

[0027] The amplitude control circuit is used to adjust the amplitude of the second pulse signal.

[0028] In some embodiments, the amplitude control circuit includes a fifth resistor, a microstrip impedance converter, and a PIN diode switch connected in series in sequence;

[0029] The output end of the PIN diode switch is electrically connected to the output end of the third capacitor;

[0030] The TTL voltage switch signal is used to control the on or off of the PIN diode switch.

[0031] In some embodiments, further comprising an input buffer circuit;

[0032] The input buffer circuit is used to adjust the initial pulse trigger signal to the rising edge signal with a preset slope, and transmit the rising edge signal to the input end of the first stage circuit.

[0033] In some embodiments, the input buffer circuit includes a sixth resistor, a seventh resistor and a PNP transistor;

[0034] The input end of the sixth resistor is used to receive the initial pulse trigger signal;

[0035] The output end of the sixth resistor is electrically connected to the control end of the PNP transistor, and is used to control the PNP transistor to be turned on or off;

[0036] The output end of the PNP transistor is electrically connected to the seventh resistor; the seventh resistor outputs the rising edge signal;

[0037] The input buffer circuit is used to determine the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor;

[0038] Among them, the frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same.

[0039] In some embodiments, the input buffer circuit further includes an eighth resistor and an NPN transistor;

[0040] The input end of the eighth resistor is used to receive the initial pulse trigger signal;

[0041] The output end of the eighth resistor is electrically connected to the control end of the NPN transistor, and is used to control the on or off of the NPN transistor; the output end of the NPN transistor is used to output the rising edge signal;

[0042] The input buffer circuit is used to adjust the slope of the rising edge signal to the preset slope by changing the resistance value of the eighth resistor.

[0043] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:

[0044] The pulse control circuit provided in the embodiment of the present application uses a three-stage circuit to simultaneously realize narrow pulse width output and pulse width monitoring. It is capable of real-time monitoring the pulse width of the first pulse signal output by the first-stage circuit, and adopting the second-stage circuit to adjust the pulse width of the first pulse signal to achieve narrowing processing of the second pulse signal, thereby meeting the requirement of narrow pulse width of the pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 A schematic diagram of a structure of a pulse control circuit provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of another structure of the pulse control circuit provided in the embodiment of the present application;

[0049] Figure 3 A diagram showing a corresponding relationship between the pulse width of a second pulse signal output at point P2 and the pulse width of a first pulse signal output at point P1 provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of another structure of the pulse control circuit provided in the embodiment of the present application;

[0051] Figure 5 A schematic diagram of another structure of the pulse control circuit provided in the embodiment of the present application;

[0052] Figure 6 A schematic diagram of another structure of the pulse control circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0055] In the related technology, there is a high-speed pulse generator composed of avalanche transistors and pulse shaping transmission line technology, which uses the distributed parameter effect of the transmission line to select the frequency of the high-frequency signal and output it to generate a minimum pulse signal of 500ps. However, due to the use of avalanche transistors, although the minimum pulse output of 500ps is obtained, the amplitude is limited, and the output pulse amplitude is low.

[0056] There are also existing technical solutions that use digital circuit methods to synthesize pulse solutions with adjustable pulse width based on programmable logic devices FPGA and high-speed ECL devices, and achieve the goal of large-range, precise and continuous adjustable pulse width through the cooperation of FPGA internal counters and programmable delay chips. However, the method based on digital circuits generates pulse signals with large-range, precise and continuous adjustable pulse width, which can control the output pulse width. However, it cannot guarantee that the pulse width and output amplitude can be controlled at the same time, and the minimum pulse width based on this method can only reach a few nanoseconds, which cannot meet the actual narrow pulse width requirements.

[0057] In the existing technical solutions, there is also a solution that uses a mixture of digital and analog circuits to achieve the goal of simultaneously adjusting the pulse width and amplitude. The digital circuit generates an adjustable pulse width in the range of 1.95ns-800ns, and the pulse amplitude is controlled by adjusting the current of the current source. However, by mixing digital and analog circuits, the pulse width and amplitude can be independently adjusted. However, this solution requires the use of more integrated circuit modules, has a complex structure, and is costly. In addition, due to the limitation of the operating frequency of the digital circuit, the pulse width is in the nanosecond level, which also cannot meet the actual demand for narrow pulse width.

[0058] In actual engineering applications, many precision photoelectric detection systems have put forward higher requirements for ultra-wideband high-speed pulse signal sources. Therefore, how to accurately obtain narrow pulses and monitor the pulse width in real time, and regulate the pulses without increasing the complexity of the circuit to improve the system detection performance, is the main technical problem to be solved in this application.

[0059] To solve at least one of the above problems, the present application provides a pulse control circuit, such as Figure 1 As shown, Figure 1 A schematic diagram of a pulse control circuit provided in an embodiment of the present application, from Figure 1 It can be seen that the circuit includes: a first-stage circuit, a second-stage circuit, a third-stage circuit and a pulse width monitoring circuit, and the first-stage circuit, the second-stage circuit and the third-stage circuit are connected in series in sequence. The first-stage circuit is used to convert a rising edge signal with a preset slope into a first pulse signal and transmit it to the second-stage circuit. The second-stage circuit is used to narrow the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal. The pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal. The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal.

[0060] like Figure 1 As shown, the input terminal In1 of the first-stage circuit is used to receive the rising edge signal, and the output terminal Out1 of the first-stage circuit is used to output the first pulse signal. The input terminal In2 of the second-stage circuit is electrically connected to the output terminal Out1 of the first-stage circuit, and the output terminal Out2 of the second-stage circuit is electrically connected to the input terminal In3 of the third-stage circuit, and the output terminal Out3 of the third-stage circuit is used to output the second pulse signal. The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal. The second-stage circuit is used to narrow the second pulse signal by adjusting the pulse width of the first pulse signal.

[0061] The pulse control circuit provided in the embodiment of the present application uses a three-stage circuit to simultaneously realize narrow pulse width output and pulse width monitoring. It is capable of real-time monitoring the pulse width of the first pulse signal output by the first-stage circuit, and adopting the second-stage circuit to adjust the pulse width of the first pulse signal to achieve narrowing processing of the second pulse signal, thereby meeting the requirement of narrow pulse width of the pulse signal.

[0062] In some embodiments, the pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal and the pulse width of the pulse signal output by the second stage circuit, that is, the pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal and the pulse width of the pulse signal at the input end of the third stage circuit.

[0063] The technical solution provided by the embodiment of the present disclosure can effectively reduce the pulse width of the second pulse signal, and by adjusting the pulse width of the first pulse signal, there is no need to set an additional pulse width control circuit for the third-level circuit, so that the pulse width of the second pulse signal can be smaller than the pulse width of the pulse signal at the input end of the third-level circuit.

[0064] like Figure 1As shown, the output terminal Out1 of the first stage circuit, namely at point P1, is used to output the first pulse signal. The output terminal Out3 of the third stage circuit, namely at point P2, is used to output the second pulse signal. The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal at point P1. The second stage circuit is used to achieve narrowing processing of the second pulse signal at point P2 by adjusting the pulse width of the first pulse signal at point P1.

[0065] In some embodiments, Figure 1 As shown, for example, the input terminal In4 of the pulse width monitoring circuit is electrically connected to the output terminal Out1 of the first stage circuit, and the output terminal Out4 of the pulse width monitoring circuit is electrically connected to the output terminal Out2 of the second stage circuit. The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal.

[0066] The above is only one embodiment of the present application. The embodiments of the present application can also be as follows: Figure 2 As shown, Figure 2 Another structural diagram of the pulse control circuit provided in the embodiment of the present application is as follows: Figure 2 It can be seen that the first-stage circuit also includes a first capacitor C1, the second-stage circuit also includes a second capacitor C2, and the third-stage circuit also includes a third capacitor C3. The first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in series in sequence. The input terminal In1 of the first capacitor C1 is used to receive a rising edge signal, and the output terminal Out1 of the first capacitor C1 is used to output a first pulse signal. The input terminal In2 of the second capacitor C2 is electrically connected to the output terminal Out1 of the first capacitor C1, the input terminal In2 of the second capacitor C2 is used to receive the first pulse signal, the output terminal Out2 of the second capacitor C2 is electrically connected to the input terminal In3 of the third capacitor C3, and the output terminal Out3 of the third capacitor C3 is used to output a second pulse signal.

[0067] The input terminal In4 of the pulse width monitoring circuit is electrically connected to the output terminal Out1 of the first capacitor C1 , and the output terminal Out4 of the pulse width monitoring circuit is electrically connected to the second capacitor C2 . The pulse width monitoring circuit is used to provide a bias voltage to the second capacitor C2 .

[0068] In some embodiments, Figure 2 As shown, the output terminal Out4 of the pulse width monitoring circuit is electrically connected to the output terminal Out2 of the second capacitor C2.

[0069] In some embodiments, Figure 2As shown, the first-stage circuit also includes a first resistor R1, the second-stage circuit also includes a second resistor R2, and the third-stage circuit also includes a third resistor R3 and a fourth resistor R4. The input end of the first resistor R1 is electrically connected to the output end Out1 of the first capacitor C1, and the output end of the first resistor is grounded. The input end of the second resistor R2 is electrically connected to the output end Out2 of the second capacitor C2, and the output end of the second resistor is grounded. The input end of the third resistor R3 and the input end of the fourth resistor R4 are both electrically connected to the output end Out3 of the third capacitor C3, the output end of the third resistor R3 is grounded, and the output end of the fourth resistor R4 is equivalently grounded.

[0070] For example, from Figure 2 It can be seen that the rising edge signal has positive and negative ends which are respectively input into the first-stage circuit to form a complete circuit signal loop. Among them, the output end of the first resistor R1, the output end of the second resistor R2 and the output end of the third resistor R3 are all electrically connected to the negative signal line, and a negative voltage or a low-level voltage is provided to one end of the resistor in the circuit, which is equivalent to connecting one end of the resistor to the ground. The output end of the fourth resistor R4 outputs a pulse signal, and the output end of the fourth resistor R4 can be connected to a positive power supply DC voltage, for example, so that the output end of the fourth resistor R4 is equivalently grounded.

[0071] like Figure 2 As shown, the pulse width monitoring circuit is used to monitor the output terminal Out1 of the first capacitor C1, that is, the pulse width of the first pulse signal output at point P1. Since the pulse width of the second pulse signal output at point P2, that is, the output terminal Out3 of the third capacitor C3, has a direct corresponding relationship with the pulse width of the first pulse signal output at point P1, the pulse width of the second pulse signal at point P2 output by the third-level circuit can be indirectly obtained by monitoring the pulse width of the first pulse signal at point P1. And the corresponding relationship between the pulse width of the first pulse signal at point P1 and the pulse width of the second pulse signal at point P2 is as follows: Figure 3 As shown, Figure 3 The corresponding relationship diagram between the pulse width of the second pulse signal output at point P2 and the pulse width of the first pulse signal output at point P1 provided in the embodiment of the present application is shown in FIG. Figure 3It can be seen that the larger the pulse width of the first pulse signal at point P1, the smaller the pulse width of the second pulse signal at point P2. Conversely, when the pulse width of the first pulse signal at point P1 is smaller, the pulse width of the second pulse signal at point P2 is larger. Therefore, the pulse width of the second pulse signal at point P2 can be adjusted by adjusting the pulse width of the first pulse signal at point P1. And the pulse width of the first pulse signal at point P1 is larger than the pulse width of the second pulse signal at point P2. The first pulse signal is a nanosecond pulse signal, and the second pulse signal is a picosecond pulse signal. Therefore, compared with the pulse width of the picosecond pulse signal at point P2, the nanosecond pulse signal at point P1 adjusts the pulse width with a nanosecond control base, which is easier to implement and has high adjustment accuracy. Therefore, the second-stage circuit is used to narrow the second pulse signal at the output end of the third-stage circuit by increasing the pulse width of the first pulse signal.

[0072] For example, Figure 3 As shown, for example, when the pulse width of the first pulse signal at point P1 is adjusted, it can be adjusted from 1.4ns to 1.6ns. At this time, the pulse width of 1.6ns at point P1 corresponds to the pulse width of 400ps of the second pulse signal at point P2, and the pulse width of 1.4ns at point P1 corresponds to the pulse width of 700ps of the second pulse signal at point P2. That is, by adjusting the pulse width of the first pulse signal from 1.4ns to 1.6ns, the pulse width of the second pulse signal can be adjusted from 700ps to 400ps. Obviously, the pulse width at point P1 needs to be increased to achieve the effect of decreasing the pulse width at point P2, and increasing the pulse width is easier to achieve than decreasing it, and it is easier to operate. If the pulse width of point P2 is adjusted only at point P2, if a picosecond pulse width is to be achieved, the picosecond pulse width can only be reduced, for example, from 700ps directly to 400ps. This pulse width adjustment method must first be adjusted at the picosecond level, and the adjustment from a small pulse width to a smaller pulse width is difficult to control and difficult to achieve, and is not as accurate as the adjustment of the narrow pulse width from the larger pulse width at point P1 provided in the embodiment of the present application. The circuit provided in the embodiment of the present application can adjust the pulse width at the nanosecond level, and indirectly achieve the output effect of the picosecond pulse width.

[0073] Furthermore, by comparing the correspondence between the first pulse signal output at the second-level circuit input terminal P1 and the second pulse signal output at the third-level circuit output terminal P2, as well as the correspondence between the pulse signal at the third-level circuit input terminal and the second pulse signal at the third-level circuit output terminal P2, the correspondence between the first pulse signal output at the second-level circuit input terminal P1 and the second pulse signal output at the third-level circuit output terminal P2 is clearer and more obvious. Figure 3That is, it can be seen. Therefore, due to the special pulse width correspondence between the first pulse signal at point P1 and the second pulse signal at point P2, the embodiment of the present application uses the pulse width adjustment of the first pulse signal at point P1 to achieve the pulse width adjustment of the second pulse signal at point P2, and the effect of the pulse width adjustment of the second pulse signal at point P2 is better. In addition, the amplitude of the first pulse signal at point P1 is greater than the amplitude of the second pulse signal at point P2, and it is easier to be monitored by the pulse width monitoring circuit.

[0074] In some embodiments, the first stage circuit may include, for example, at least two first capacitors C1 connected in series, and / or the second stage circuit may include, for example, at least two second capacitors C2 connected in series, and / or the third stage circuit may include, for example, at least two third capacitors C3 connected in series. The technical solution provided by the embodiment of the present disclosure can make the RC time constant of the entire circuit smaller by setting a plurality of capacitors connected in series in each stage circuit, thereby making the pulse width of the second pulse signal narrower.

[0075] In some embodiments, Figure 4 As shown, Figure 4 Another structural diagram of the pulse control circuit provided in the embodiment of the present application is as follows: Figure 4 It can be seen that the pulse width monitoring circuit includes a comparator, an adjustable voltage source and a first choke unit connected in series in sequence. The input end of the comparator is electrically connected to the output end Out1 of the first capacitor C1, and the output end of the comparator is electrically connected to the input end of the adjustable voltage source. The output end of the adjustable voltage source is electrically connected to the input end of the first choke unit, and the output end of the first choke unit is electrically connected to the input end In2 of the second capacitor C2. The comparator is used to monitor the pulse width of the first pulse signal. The adjustable voltage source is used to provide a bias voltage to the second capacitor C2. The first choke unit is used to block the AC signal through a DC signal. That is, the first choke unit is used to pass the DC bias voltage and prevent the AC signal on the adjustable voltage source from leaking.

[0076] In some embodiments, the comparator is used to monitor the pulse width of the first pulse signal at the P1 point of the output terminal Out1 of the first capacitor C1. The comparator can be, for example, a high-speed comparator, and the high-speed comparator can be, for example, a comparator with a response speed of more than 1 GHz. The comparator can, for example, shape the first pulse signal into a square wave signal, and the comparator can monitor the pulse width of the first pulse signal in real time. The pulse width of the first pulse signal detected by the comparator is adjusted according to the corresponding relationship between the pulse width of the first pulse signal and the pulse width of the second pulse signal, and then the voltage value of the adjustable voltage source is adjusted through the adjustable voltage source to provide a suitable bias voltage to the second capacitor C2 in the second stage circuit. The bias voltage can be used to adjust the capacitance value of the second capacitor C2, and the pulse width of the first pulse signal can be adjusted by changing the capacitance value of the second capacitor C2, so that the pulse width of the second pulse signal can be adjusted.

[0077] In some embodiments, the pulse width monitoring circuit does not affect the operation of the first stage circuit, the second stage circuit, and the third stage circuit. And by cooperating with the pulse width monitoring circuit, the second stage capacitor C2 is a tuning capacitor, and the second capacitor C2 can include at least one of a varactor diode and an active capacitor, and the pulse width of the first pulse signal can be adjusted without changing the circuit structure. When the second capacitor C2 is a varactor diode, the bias voltage provided to the second capacitor C2 by the adjustable voltage source can change the capacitance of the varactor diode, and then the continuous and precise adjustment of the pulse width of the first pulse signal can be achieved. When the second capacitor C2 is an active capacitor, the bias voltage provided to the second capacitor C2 by the adjustable voltage source can change the capacitance of the second capacitor C2, and the active capacitor has extremely low resistive loss, thereby having a higher Q value.

[0078] Optionally, by adjusting any one of the capacitors (C) and resistors (R) in the first stage circuit, the second stage circuit, and the third stage circuit, for example, by changing the RC time constant, the pulse width of the rising edge signal can also be adjusted. Therefore, the RC time constant can be used as a consideration when designing a pulse control circuit.

[0079] In some embodiments, Figure 4 As shown, the pulse width monitoring circuit also includes a second choke unit. The input end of the second choke unit is electrically connected to the output end of the adjustable voltage source, and the output end of the second choke unit is electrically connected to the input end of the second resistor R2. Since the input end of the second resistor R2 is electrically connected to the output end Out2 of the second capacitor C2, the output end of the second choke unit is electrically connected to the output end Out2 of the second capacitor C2. The second resistor R2 is an adjustable resistor.

[0080] Optionally, the second resistor R2 may be, for example, an adjustable potentiometer, a sliding resistor, etc., and its resistance value may be adjusted by digital coding or manually.

[0081] Exemplarily, the second capacitor C2 can be a step recovery diode, for example. A certain forward bias voltage is provided to the second capacitor C2 through an adjustable voltage source. When a pulse signal comes, the step recovery diode is reverse biased and is equivalent to a charge storage capacitor. At this time, the pulse width of the first pulse signal can be adjusted by changing the resistance value of the second resistor R2, and the pulse width can be adjusted to be narrower.

[0082] Optionally, the second choke unit further includes a resistance adjuster, which is used to adjust the resistance value of the second resistor R2. The resistance adjuster may be, for example, an adjustable potentiometer, a sliding resistor, etc.

[0083] The pulse control circuit provided in the embodiment of the present application introduces a pulse width monitoring circuit in the second-stage circuit of the three-stage circuit. Without affecting the first-stage circuit and the second-stage circuit, the second capacitor can arbitrarily select a varactor diode, a step recovery diode or a two-port active capacitor as a tuning capacitor, thereby achieving a wider adjustable range of the pulse width of the second pulse signal, further narrowing the minimum pulse width of the second pulse signal, and achieving the effects of smaller circuit loss and higher Q value.

[0084] In some embodiments, the adjustable voltage source is a voltage source that can adjust the voltage, for example, it can be a potentiometer, a digital-to-analog conversion voltage source, etc.

[0085] In some embodiments, the first choke unit and the second choke unit may be, for example, the same structure or different structures. The first choke unit and the second choke unit may be, for example, high-frequency choke units, which may be, for example, choke inductors, coils, transmission line structures, or microstrip impedance transformers.

[0086] In some embodiments, reference Figure 4 In the circuit structure shown, the first choke unit and / or the second choke unit may be, for example, a microstrip impedance transformer. When viewed from point P1, the input impedance Z of the microstrip impedance transformer is in The following relationship is satisfied:

[0087]

[0088] Where Z0 is the characteristic impedance of the transmission line, which refers to Figure 4 The wire between the adjustable voltage source and point P1. L is the load impedance at the other end of the transmission line. The electrical length θ is related to the frequency, characteristic impedance, and physical length. For AC signals, when Z L =0, θ =π / 2, Z in →∞, which prevents high-frequency leakage. For DC signals, θ=0, Z in=Z L , plays the role of passing direct current. j is a constant.

[0089] In some embodiments, for example, by adopting a non-uniform transmission line structure, a wider suppression bandwidth can be achieved, extending the range of high-frequency chokes.

[0090] In the pulse control circuit provided in the embodiment of the present application, the first choke unit and / or the second choke unit in the pulse monitoring circuit can use a quarter-wavelength (λ / 4) microstrip impedance transformer to replace the traditional high-frequency choke inductor, which plays the role of passing DC bias and blocking AC leakage, avoiding the use of heavy inductors, and has a simple structure and high integration. Therefore, using a microstrip impedance transformer as a high-frequency choke unit can simplify the structure of the entire pulse control circuit, improve the circuit integration, and be compatible with the PCB process of circuit board wiring.

[0091] In some embodiments, Figure 4 As shown, the pulse monitoring circuit also includes, for example, a fourth capacitor C4, the input end of the fourth capacitor C4 is electrically connected to the output end Out1 of the first capacitor C1, and the input end of the fourth capacitor C4 is also electrically connected to the output end of the first choke unit. The output end of the fourth capacitor C4 is electrically connected to the input end of the comparator. At this time, the input end of the fourth capacitor C4 and the output end of the first choke unit are both connected to point P1. The fourth capacitor C4 is mainly used to prevent the voltage signal output by the adjustable voltage source from being transmitted to the comparator through the first choke unit, thereby causing a short circuit in the pulse monitoring circuit. As shown Figure 4 As shown, in the pulse width monitoring circuit, the output end of the first choke unit is electrically connected to the input end of the second capacitor C2, and the output end of the second choke unit is electrically connected to the output end of the second capacitor C2, so that the adjustable voltage source can provide a bias voltage to the second capacitor C2.

[0092] In some embodiments, Figure 5 As shown, Figure 5 Another structural diagram of the pulse control circuit provided in the embodiment of the present application is as follows: Figure 5 It can be seen that the pulse control circuit also includes an amplitude control circuit, the output end of the amplitude control circuit is electrically connected to the third-level circuit. The input end of the amplitude control circuit is used to receive the TTL voltage switch signal. The amplitude control circuit is used to adjust the amplitude of the second pulse signal.

[0093] Optionally, TTL (Transistor Transistor Logic) is transistor-transistor logic, and TTL voltage signals are generated by TTL devices.

[0094] Optionally, the amplitude of the second pulse signal may be, for example, greater than the amplitude of the rising edge signal and / or the amplitude of the first pulse signal. Or the amplitude of the second pulse signal is less than or equal to the amplitude of the rising edge signal and / or the amplitude of the first pulse signal. Specifically, the amplitude of the second pulse signal is set according to the actual amplitude requirement of the second pulse signal, which is not limited in the embodiments of the present disclosure.

[0095] The pulse control circuit provided in the embodiment of the present application can adjust the amplitude of the output second pulse signal through the amplitude control circuit. The amplitude control circuit has a simple structure, is easy to implement, and can well meet the precise requirements for the pulse amplitude range in practice.

[0096] In some embodiments, Figure 5 As shown, the amplitude control circuit includes a fifth resistor R5, a microstrip impedance converter and a PIN diode switch D1 connected in series in sequence. The output end of the PIN diode switch D1 is electrically connected to the output end Out3 of the third capacitor C3. The TTL voltage switch signal is used to control the conduction or shutdown of the PIN diode switch D1. Among them, the input end of the fifth resistor R5 is used to receive the TTL voltage switch signal, the output end of the fifth resistor R5 is electrically connected to the input end of the microstrip impedance converter, and the output end of the microstrip impedance converter is electrically connected to the control end of the PIN diode switch. When the TTL voltage switch signal is at a high level, the PIN diode switch D1 is reversely cut off. When the TTL voltage switch signal is at a low level, the TTL voltage switch signal controls D1 to be forward-conducted under the action of the bias voltage.

[0097] Ordinary diodes are composed of PN junctions. A thin layer of low-doped intrinsic semiconductor layer is added between P and N semiconductor materials to form a PIN diode. Optionally, the PIN diode switch is a photodiode switch.

[0098] In some embodiments, the pulse control circuit further includes an output drive circuit, the input end of the output drive circuit is electrically connected to the output end of the third stage circuit. Figure 5 As shown, the output drive circuit includes an NPN transistor Q1, a PNP transistor Q2, a ninth resistor R9, a tenth resistor R10, a Zener diode D2, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and a DC bias current source I b , the DC bias current source I b The ninth resistor R9, the NPN transistor Q1, and the DC bias current source I b The sixth capacitor C6 is connected in parallel to the DC bias current source Ib The tenth resistor R10 and the PNP transistor Q2 are connected in series. The ninth resistor R9, the NPN transistor Q1, and the DC bias current source I are connected in series. b The tenth resistor R10 and the PNP transistor Q2 connected in series are connected in parallel. The fifth capacitor C5 and the Zener diode D2 are connected in series, and the input end of the fifth capacitor C5 is electrically connected to the output end of the ninth resistor R9, and the output end of the Zener diode D2 is electrically connected to the control end of the PNP transistor Q2.

[0099] Among them, the PNP transistor is composed of two P-type semiconductors with one N-type semiconductor in the middle, so it is called a PNP transistor. The NPN transistor is a transistor composed of two N-type semiconductors with a P-type semiconductor in the middle, also known as a crystal transistor.

[0100] Specifically, Figure 5 As shown, the output end Out3 of the third capacitor C3 is electrically connected to the control end of the NPN transistor Q1, the input end of the ninth resistor R9 and the input end of the tenth resistor R10 are respectively used to receive the power supply voltage, the output end of the ninth resistor R9 is electrically connected to the input end of the NPN transistor Q1, and the output end of the NPN transistor Q1 is electrically connected to the DC bias current source I b Electrical connection, DC bias current source I b The output end of is electrically connected to the negative power line of the pulse control circuit. The sixth capacitor C6 is connected in parallel to the DC bias current source I b The input end of the fifth capacitor C5 is electrically connected to the output end of the ninth resistor, the output end of the fifth capacitor C5 is electrically connected to the input end of the Zener diode D2, the output end of the Zener diode D2 is electrically connected to the control end of the PNP transistor Q2, the output end of the PNP transistor Q2 is electrically connected to the output end of the tenth resistor R10 and the input end of the seventh capacitor C7, respectively, and the input end of the PNP transistor Q2 is electrically connected to the negative power line of the pulse control circuit. The output end of the seventh capacitor C7 is used to output a pulse signal indicating the end of control to the outside world.

[0101] In some embodiments, the input end of the ninth resistor R9 is used to receive a power supply voltage, and the power supply voltage is 5V, for example.

[0102] In some embodiments, the amplitude control circuit is used to adjust the amplitude Vo of the second pulse signal, wherein the amplitude Vo of the second pulse signal satisfies the following relationship:

[0103] Vo=Vcc-V p2 -I b *R9-V Q1_sat -V D2

[0104] Among them, VQ1_sat is the saturation voltage drop of NPN transistor Q1, Vcc is the supply voltage, V D2 It is the clamping voltage of Zener diode D2, which plays a clipping role. b is the DC bias current value provided by the DC bias voltage source to the output end of the NPN transistor Q1. When the TTL voltage switch signal is at a high level, the PIN diode switch D1 is reversely cut off, and the voltage of the DC static operating point of the output drive circuit is the voltage V at point P2. p2 , at this time V p2 The size of is determined by R3 and R4. When the TTL voltage switch signal is at a low level, D1 is forward-conducted under the action of the bias voltage, and V p2 Determined by R3, R4, and R5. Figure 5 When designing the circuit structure, Vcc, I b , R9, V Q1_sat 、V D2 All of them are fixed values. At this time, only by adjusting the voltage at point P2 can the amplitude Vo of the second pulse signal be adjusted according to the above formula.

[0105] Therefore, by setting different static operating points, the maximum output signal amplitude of the second pulse signal at point P2 can be controlled. The static operating point setting is achieved by switching the bias resistor value in combination with the PIN diode switch D1. When the TTL voltage switch signal is at a low level, D1 is forward-conducted under the action of the bias voltage, and V p2 Determined by R3, R4, and R5. When the TTL voltage switch signal is at a high level, the PIN diode switch D1 is reversely cut off, and the voltage at the DC static operating point of the output drive circuit is the voltage V at point P2. p2 , at this time V p2 The size is determined by R3 and R4.

[0106] In the pulse control circuit provided in the embodiment of the present application, Figure 5 As shown, the amplitude control circuit can provide a larger bias voltage to the static operating point of the output drive circuit, solving the problem that the amplitude of the second pulse signal output by the third-level circuit is too weak to drive the output drive circuit to transmit the second pulse signal outward, thereby realizing low-voltage drive of the output drive circuit. For example, a 5V power supply voltage is used to power the input end of the NPN transistor Q1, so that no matter how small the amplitude of the second pulse signal output from point P2 is, the output drive circuit can be guaranteed to work normally, realizing low-voltage drive of the output drive circuit.

[0107] In some embodiments, the input impedance Z of the microstrip impedance transformer in the amplitude control circuit is in The following relationship is satisfied:

[0108]

[0109] Where Z0 is the characteristic impedance of the transmission line, which refers to Figure 4 The wire between the adjustable voltage source in and point P1. For AC signals, when Z L =0, θ =π / 2, Z in →∞, which prevents high-frequency leakage. For DC signals, θ=0, Z in =Z L , Z L =R9, plays the role of passing direct current.

[0110] For example, Figure 5 As shown, by setting the TTL signal to a high level, under a 50Ω load, the amplitude of the second pulse signal is 1V. By setting the TTL signal to a low level, the amplitude of the second pulse signal is 2V.

[0111] In some embodiments, Figure 6 As shown, Figure 6 Another structural schematic diagram of a pulse control circuit provided in an embodiment of the present application, the pulse control circuit further includes an input buffer circuit. The input buffer circuit is used to adjust the initial pulse trigger signal to a rising edge signal with a preset slope, and transmit the rising edge signal to the input end of the first stage circuit.

[0112] The input buffer circuit is used to receive the initial pulse trigger signal and output a rising edge signal with a preset slope to the input end of the first stage circuit.

[0113] Among them, the input buffer circuit can adjust the slope of the rising edge signal to a preset slope, so as to adjust the amplitude of the first pulse signal. For example, the amplitude of the first pulse signal can be increased by adjusting the slope of the rising edge signal, and then the amplitude of the pulse signal is adjusted twice by the amplitude control circuit in the pulse control circuit, so that when the amplitude control circuit increases the amplitude of the pulse signal, it is easier to adjust and the accuracy of the amplitude adjustment can be improved.

[0114] The frequency, amplitude, pulse width and other parameters of the pulse signal in the pulse control circuit are independent of each other during adjustment and will not affect each other. And when adjusting the amplitude of the pulse signal, it will not affect the pulse width or frequency of the pulse signal that has been adjusted. That is, if the pulse width or amplitude of the pulse signal is adjusted after the frequency adjustment of the pulse signal is completed, it will not affect the frequency of the pulse signal. In the pulse control circuit provided in the embodiment of the present application, there is no order of priority for adjusting the three parameters of the frequency, pulse width and amplitude of the pulse signal, that is, the three parameters can be adjusted in any order according to the design of the actual circuit.

[0115] In some embodiments, Figure 6 As shown, the input buffer circuit is used to determine the frequency of the initial pulse trigger signal, and the input buffer circuit includes a sixth resistor R6, a seventh resistor R7 and a PNP transistor Q3. The input end of the sixth resistor R6 is used to receive the initial pulse trigger signal. The initial pulse trigger signal has a steep rising edge. The output end of the sixth resistor R6 is electrically connected to the control end of the PNP transistor Q3, and is used to control the PNP transistor to be turned on or off. The output end of the PNP transistor Q3 is electrically connected to the seventh resistor R7, and the seventh resistor R7 outputs a rising edge signal. As shown Figure 6 As shown, the seventh resistor R7 outputs a rising edge signal at point P0. The input buffer circuit is used to determine the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor R7. Among them, the frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same. The input end of the PNP transistor Q3 is grounded.

[0116] Exemplarily, a simulation experiment is conducted on an output waveform operating at a frequency of 30 MHz and an amplitude of 2 V, and by changing the resistance value of the seventh resistor R7, the waveform of the falling edge of the pulse becomes steeper, thereby obtaining a higher operating frequency.

[0117] In some embodiments, Figure 6 As shown, the input buffer circuit is used to adjust the slope of the rising edge signal to a preset slope. The input buffer circuit also includes an eighth resistor R8 and an NPN transistor Q4. The input end of the eighth resistor R8 is used to receive the initial pulse trigger signal. The output end of the eighth resistor R8 is electrically connected to the control end of the NPN transistor Q4, and is used to control the conduction or shutdown of the NPN transistor Q4. The output end of the NPN transistor Q4 is used to output the rising edge signal. Figure 6 As shown, the output end of the NPN transistor Q4 outputs a rising edge signal at point P0. The input buffer circuit is used to change the resistance value of the eighth resistor R8 to adjust the slope of the rising edge signal to a preset slope.

[0118] The input buffer circuit is used to change the resistance value of the eighth resistor R8 to adjust the slope of the rising edge signal to a preset slope. The amplitude of the first pulse signal can be adjusted. The input end of the NPN transistor Q4 is electrically connected to the power supply voltage end. The power supply voltage can be, for example, a 5V voltage.

[0119] Since the amplitude of the first pulse signal output by the third-stage circuit is positively correlated with the rising slope of the rising edge signal output at point P0, and adjusting the resistance value of the eighth resistor R8 can change the driving current of the NPN transistor Q4, and adjusting the driving current of the NPN transistor Q4 can change the rising slope of the rising edge signal output at point P0 within a certain range. Therefore, the input buffer circuit provided in the embodiment of the present application can also change the amplitude of the first pulse signal output by the third-stage circuit by changing the resistance value of the eighth resistor R8.

[0120] Since the amplitude of the first pulse signal will affect the amplitude adjustment of the second pulse signal, that is, the larger the amplitude of the first pulse signal, the easier it is to adjust the amplitude of the second pulse signal. For example, when the resistance value of the eighth resistor R8 is reduced, the voltage remains unchanged, and the current supplied to the NPN transistor Q4 per unit time will increase. After passing through the three-stage circuit, the response speed of the second pulse signal will be increased, and the rising edge slope of the second pulse signal will be higher, and then the amplitude of the second pulse signal output by the third-stage circuit will be larger, so it is easier to increase the amplitude adjustment of the second pulse signal.

[0121] In some embodiments, Figure 6 As shown, the input buffer circuit also includes a waveform shaping circuit module, which is also used to shape the original trigger signal trigger In signal, the trigger in signal is a common square wave signal with a falling edge, and outputs an initial pulse trigger signal with a steep rising edge to the eighth resistor and the sixth resistor. The waveform shaping circuit module includes an NPN transistor Q5, an eleventh resistor R11 and a twelfth resistor R12. Among them, the input end of the eleventh resistor R11 receives a power supply voltage, and the power supply voltage can be 5V, for example. The output end of the eleventh resistor R11 is electrically connected to the input end of the NPN transistor Q5. The input end of the twelfth resistor R12 is used to receive the trigger in signal, the output end of the twelfth resistor R12 is electrically connected to the control end of the NPN transistor Q5, and the output end of the NPN transistor Q5 is connected to the negative line of the entire circuit. The NPN transistor Q5, the eleventh resistor R11 and the twelfth resistor R12 can transform the trigger in signal with a slow falling edge into an initial pulse trigger signal with a steep rising edge. The eleventh resistor R11 outputs an initial pulse trigger signal with a steep rising edge.

[0122] The output end of the eleventh resistor R11 is electrically connected to the input end of the eighth resistor R8, providing the eighth resistor R8 with an initial pulse trigger signal with a steep rising edge. The input end of the NPN transistor Q4 is electrically connected to the power supply voltage end. The input end of the sixth resistor R6 is electrically connected to the output end of the eleventh resistor R11.

[0123] The pulse drive circuit provided in the embodiment of the present application further includes an input buffer circuit capable of shaping a common square wave signal, so that the drive circuit provided in the embodiment of the present application can be more widely applicable. When an initial pulse trigger signal with a steep rising edge can be directly provided to the eighth resistor and the sixth resistor, the waveform shaping circuit part in the input buffer circuit can be omitted.

[0124] Exemplarily, after the trigger in signal with a rising edge time of 5ns is shaped by the waveform shaping circuit module in the input buffer circuit, an initial pulse trigger signal with a rising edge time of 1ns can be output, so that the rising edge becomes steeper. And the output pulse width of the second pulse signal output by the 1ns initial pulse trigger signal through the three-stage circuit is 500ps and the amplitude is 1V. It shows that the three-stage circuit provided in the embodiment of the present application can well achieve the effect of narrow pulse width.

[0125] The above is a detailed introduction to a pulse control circuit provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0126] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0127] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse control circuit, characterized in that: It includes a first-level circuit, a second-level circuit, a third-level circuit and a pulse width monitoring circuit; The first-stage circuit, the second-stage circuit and the third-stage circuit are connected in series in sequence; The first-stage circuit is used to convert a rising edge signal with a preset slope into a first pulse signal and transmit it to the second-stage circuit; The second stage circuit is used for narrowing the second pulse signal at the output end of the third stage circuit by adjusting the pulse width of the first pulse signal; The pulse width of the second pulse signal is smaller than the pulse width of the first pulse signal; The pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal; The first stage circuit further includes a first capacitor, the second stage circuit further includes a second capacitor, and the third stage circuit further includes a third capacitor; The first capacitor, the second capacitor and the third capacitor are connected in series in sequence; The input end of the first capacitor is used to receive the rising edge signal, and the output end of the first capacitor is used to output a first pulse signal; the input end of the second capacitor is used to receive the first pulse signal; The output end of the third capacitor is used to output a second pulse signal; The input end of the pulse width monitoring circuit is electrically connected to the output end of the first capacitor, and the output end of the pulse width monitoring circuit is electrically connected to the second capacitor; the pulse width monitoring circuit is used to provide a bias voltage to the second capacitor; The first stage circuit further includes a first resistor, the second stage circuit further includes a second resistor, and the third stage circuit further includes a third resistor and a fourth resistor; The input end of the first resistor is electrically connected to the output end of the first capacitor, and the output end of the first resistor is grounded; The input end of the second resistor is electrically connected to the output end of the second capacitor, and the output end of the second resistor is grounded; The input end of the third resistor and the input end of the fourth resistor are both electrically connected to the output end of the third capacitor, the output end of the third resistor is grounded, and the output end of the fourth resistor is equivalently grounded; The pulse width monitoring circuit comprises a comparator, an adjustable voltage source and a first choke unit connected in series in sequence; The input terminal of the comparator is electrically connected to the output terminal of the first capacitor; The output end of the first choke unit is electrically connected to the input end of the second capacitor; The comparator is used to monitor the pulse width of the first pulse signal; The adjustable voltage source is used to provide the bias voltage to the second capacitor; The first choke unit is used to block the AC signal through the DC signal; The pulse width monitoring circuit also includes a second choke unit; The input end of the second choke unit is electrically connected to the output end of the adjustable voltage source; the output end of the second choke unit is electrically connected to the input end of the second resistor; The second resistor is an adjustable resistor.

2. The circuit according to claim 1, characterized in that It also includes an amplitude control circuit, the output end of the amplitude control circuit is electrically connected to the third-level circuit; the input end of the amplitude control circuit is used to receive a TTL voltage switch signal; The amplitude control circuit is used to adjust the amplitude of the second pulse signal.

3. The circuit according to claim 2, characterized in that The amplitude control circuit comprises a fifth resistor, a microstrip impedance converter and a PIN diode switch connected in series in sequence; The output end of the PIN diode switch is electrically connected to the output end of the third capacitor; The TTL voltage switch signal is used to control the on or off of the PIN diode switch.

4. The circuit according to claim 1, characterized in that Also included is an input buffer circuit; The input buffer circuit is used to adjust the initial pulse trigger signal to the rising edge signal with a preset slope, and transmit the rising edge signal to the input end of the first stage circuit.

5. The circuit according to claim 4, characterized in that The input buffer circuit includes a sixth resistor, a seventh resistor and a PNP transistor; The input end of the sixth resistor is used to receive the initial pulse trigger signal; The output end of the sixth resistor is electrically connected to the control end of the PNP transistor, and is used to control the PNP transistor to be turned on or off; The output end of the PNP transistor is electrically connected to the seventh resistor; the seventh resistor outputs the rising edge signal; The input buffer circuit is used to determine the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor; Among them, the frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same.

6. The circuit according to claim 4, characterized in that The input buffer circuit also includes an eighth resistor and an NPN transistor; The input end of the eighth resistor is used to receive the initial pulse trigger signal; The output end of the eighth resistor is electrically connected to the control end of the NPN transistor, and is used to control the on or off of the NPN transistor; the output end of the NPN transistor is used to output the rising edge signal; The input buffer circuit is used to adjust the slope of the rising edge signal to the preset slope by changing the resistance value of the eighth resistor.

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