Method and apparatus for vector sorting using vector permute logic

Abstract

A method for sorting a vector in a processor is provided that includes generating (5400), by the processor in response to a vector sort instruction, a control input vector for vector permute logic included in the processor based on values in a lane of the vector and a sort order of the vector indicated by the vector sort instruction; and storing (5402) the control input vector at a storage location.

Description

Background Technology

[0001] Digital signal processors (DSPs) are optimized for processing data streams that can be derived from a variety of input signals, such as sensor data, video streams, voice channels, radar signals, biomedical signals, etc. A DSP that operates on real-time data can receive an input data stream, perform filtering functions (such as encoding or decoding) on ​​the data stream, and output a transformed data stream. This system is called real-time because if the transformed data stream is unavailable for output at the scheduled time, the application fails. Video encoding may require predictable but discontinuous patterns of input data. The example application requires memory access to load data registers into a data register file and then feed data from the data registers to the functional units that perform data processing.

[0002] One or more DSP processing cores can be combined with various peripheral circuits, memory blocks, etc., on a single integrated circuit (IC) die to form a System-on-a-Chip (SoC). These systems can include multiple interconnected processors that share the use of on-chip and off-chip memory. Processors can include some combination of instruction cache (ICache) and data cache (DCache) to improve processing. Furthermore, multiple processors with shared memory can be merged into a single embedded system. Processors can physically share the same memory without accessing data or executing code located in the same memory location, or certain portions of the shared memory can be used as common shared memory. Summary of the Invention

[0003] Embodiments of this specification relate to methods and systems for sorting vectors using vector permutation control inputs. In one aspect, a method for sorting vectors in a processor is provided, the method comprising: generating control input vectors for vector permutation logic contained in the processor based on values ​​in a channel of the vectors and a sorting order of the vectors indicated by the vector sorting instructions, in response to vector sorting instructions; and storing the control input vectors in a storage location.

[0004] In one aspect, a processor is provided, comprising: comparator logic configured to compare values ​​in channels of a vector according to a sorting order indicated by a vector sorting instruction in response to a vector sorting instruction; vector permutation logic configured to generate a sorted vector using a control input vector indicated by a vector permutation instruction in response to a vector permutation instruction; and vector sorting logic configured to generate a control input vector based on the result of the comparison of values ​​performed by the comparator logic. Attached Figure Description

[0005] Figure 1This illustrates a dual scalar / vector data path processor;

[0006] Figure 2 illustrate Figure 1 The registers and functional units in the processor that provide paired scalar / vector data paths are described in the diagram;

[0007] Figure 3 Description of the global scalar register file;

[0008] Figure 4 This describes the local scalar register file shared by the algorithm functional units;

[0009] Figure 5 This describes the local scalar register file shared by the multiplication function unit;

[0010] Figure 6 This describes the local scalar register file shared by local / memory units;

[0011] Figure 7 Description of the global vector register file;

[0012] Figure 8 Explain the assertion register file;

[0013] Figure 9 This describes the local vector register file shared by the algorithm's functional units;

[0014] Figure 10 This describes the local vector register file shared by the multiplication function unit and related function units;

[0015] Figure 11 Explain the pipeline stages of the processing unit;

[0016] Figure 12 This describes the sixteen instructions for extracting a single package;

[0017] Figure 13 Examples illustrating instruction encoding;

[0018] Figure 14 Explain the bit encoding of condition code expansion slot 0;

[0019] Figure 15 Explain the bit encoding of the condition code extension gap 1;

[0020] Figure 16 This indicates the bit encoding 0 for the constant extension gap;

[0021] Figure 17 This is a partial block diagram illustrating the extension of constants;

[0022] Figure 18 Explain carry control used in SIMD operations;

[0023] Figure 19 Explain the conceptual view of the streaming engine;

[0024] Figure 20 This describes a series of formatting operations;

[0025] Figure 21 An example illustrating channel assignment in a vector;

[0026] Figure 22 An example illustrating channel assignment in a vector;

[0027] Figure 23 Explain the basic two-dimensional (2D) flow;

[0028] Figure 24 illustrate Figure 23 The order of elements in the example stream;

[0029] Figure 25 This means extracting a smaller rectangle from a larger rectangle;

[0030] Figure 26 This demonstrates how the example streaming engine extracts streams with a shift granularity of 4 bytes;

[0031] Figure 27 This demonstrates how the example streaming engine extracts streams with a shifting granularity of 8 bytes;

[0032] Figure 28 Explain the details of the example streaming engine;

[0033] Figure 29 Explain the example stream template register;

[0034] Figure 30 illustrate Figure 29 The example stream template register's subfield definition of the tag field;

[0035] Figure 31 An example illustrating a vector length mask / group repeating block;

[0036] Figure 32 This is a partial schematic diagram of an example of generating a valid or invalid stream engine indication;

[0037] Figure 33 This is a partial schematic diagram illustrating the stream engine address generator that generates loop addresses and loop counts;

[0038] Figure 34 The illustration shows a partial schematic of the streaming engine supplying data for this example;

[0039] Figure 35 The illustration shows a partial schematic of the stream engine supplying valid data to the assertion unit;

[0040] Figure 36 Explain the bitonic merge sort of sixteen elements;

[0041] Figure 37 This is an example of a 32-element bitonic merge sort;

[0042] Figure 38 This demonstrates how to implement a 32-element bitonic merge sort using two different sorting methods with sixteen 32-bit elements.

[0043] Figure 39 This demonstrates the use of paired sorting instructions to perform a bitonic merge sort on 32 elements;

[0044] Figure 40 and Figure 41 This describes a modified "brute-force" method for implementing comparisons in sorting instructions;

[0045] Figure 42 This describes the masking method used to place sorted vector elements in the output vector channel;

[0046] Figure 43 This describes the permutation method used to place sorted vector elements into the output vector channel;

[0047] Figure 44 Explain the block diagram of example unit C;

[0048] Figure 45 illustrate Figure 44 Example absolute difference summation (SAD) logic in example unit C;

[0049] Figure 46 illustrate Figure 45 An example implementation of the absolute difference elements of the SAD logic and the corresponding multiplier;

[0050] Figure 47 Instructions for Figure 45 The default input combination for the SAD logic.

[0051] Figure 48 Explanation of Figure 47 The input is modified to perform a comparison for pair sorting instructions;

[0052] Figure 49 Explanation of Figure 45 Modify the SAD logic to achieve Figure 48 Input;

[0053] Figure 50 Explanation when vector elements are 32-bit values Figure 45 The input of the absolute difference element array of the SAD logic;

[0054] Figure 51 illustrate Figure 44 A block diagram illustrating an implementation of one or more vector sorting instructions in the global processing unit of the C unit;

[0055] Figure 52 , Figure 53 and Figure 54 It is a method used for vector sorting; and

[0056] Figure 55 This is a block diagram of a multiprocessor system. Detailed Implementation

[0057] For consistency, similar elements in the various figures are indicated by similar reference numerals.

[0058] Digital signal processors (DSPs) are optimized for processing data streams that can be derived from a variety of input signals, such as sensor data, video streams, voice channels, radar signals, biomedical signals, etc. Memory bandwidth and scheduling are concerns for DSPs that operate on real-time data. This paper describes an example DSP processing core that includes a streaming engine to improve memory bandwidth and data scheduling.

[0059] One or more DSP processing cores can be combined with various peripheral circuits, memory blocks, etc., on a single integrated circuit (IC) die to form a system-on-a-chip (SoC). For example, see "66AK2Hx Multicore Keystone". TM DSP+ "System-on-Chips", 2013, which is incorporated herein by reference.

[0060] In the example DSP core described in this paper, an autonomous flow engine (SE) is coupled to the DSP. In this example, the flow engine comprises two tightly coupled flow engines that can manage two data streams simultaneously. In another example, the flow engine is capable of managing only a single stream, while in other examples, the flow engine can handle more than two streams. In each case, for each stream, the flow engine includes an address generation stage, a data formatting stage, and some storage for formatted data waiting to be consumed by the processor. In the example described in this paper, addresses are derived from an algorithm that may involve multi-dimensional loops, with each dimension maintaining an iteration count. In one example, the flow engine supports six levels of nested iterations. In other examples, more or fewer levels of iterations are supported.

[0061] References in this article Figures 1-18 The example DSP processor is described in detail. This article references... Figures 19-35 A sample streaming engine is described in detail, capable of managing two data streams using a six-dimensional nested loop.

[0062] Furthermore, the example DSP core described in this article provides instruction support for sorting vector elements. See here. Figures 36-54 Examples of instruction support for vector sorting are described.

[0063] Figure 1 The description includes an example processor 100 with paired scalar / vector data paths 115, 117. Processor 100 includes a streaming engine 125, which is described in more detail herein. Processor 100 includes separate Level 1 instruction cache (L1I) 121 and Level 1 data cache (L1D) 123. Processor 100 includes a Level 2 (L2) combined instruction / data cache 130 that holds both instructions and data. Figure 1 This describes the connection between the L1I register and the L2 combined instruction / data register 130, i.e., the 512-bit bus 142. Figure 1 This describes the connection between L1D cache 123 and L2 combined instruction / data cache 130, specifically the 512-bit bus 145. In the example processor 100, L2 combined instruction / data cache 130 stores instructions for backing up L1I cache 121 and data for backing up L1D cache 123. In this example, L2 combined instruction / data cache 130 uses instructions not in... Figure 1 The known or later-developed memory system technologies described herein are further connected to higher-level caches and / or main memory. As used herein, the term "higher-level" memory or cache refers to the next level in the memory hierarchy further away from the processor, while the term "lower-level" memory or cache refers to the level in the memory hierarchy closer to the processor. In various examples, L1I cache 121, L1D cache 123, and L2 cache 130 may be implemented in different sizes. In this example, L1I cache 121 and L1D cache 123 are each 32KB, and L2 cache 130 is 1024KB. In example processor 100, L1I cache 121, L1D cache 123, and L2 combined instruction / data cache 130 are formed on a single integrated circuit. This single integrated circuit may optionally include other circuitry.

[0064] Processing unit core 110 fetches instructions from L1I cache 121 under the control of instruction fetch unit 111. Instruction fetch unit 111 determines the next instruction to be executed and calls a set of such instructions of fetch packet size. The nature and size of the fetch packet are further detailed below. If these instructions are stored in L1I cache 121, the instructions are fetched directly from L1I cache 121 after a cache hit. After a cache miss when the specified instruction is not stored in L1I cache 121, the instruction is searched in L2 combined cache 130. In this example, the cache line size in L1I cache 121 is equal to the size of a 512-bit fetch packet. The memory location of these instructions is either hit or miss in L2 combined cache 130. A hit is serviced by L2 combined cache 130. A miss is serviced by a higher-level cache (not shown) or by main memory (not shown). In this example, the requested instructions are supplied to both the L1I cache 121 and the processing unit core 110 simultaneously to accelerate their use.

[0065] In this example, the processing unit core 110 includes multiple functional units to execute data processing tasks specified by instructions. The instruction dispatch unit 112 determines the target functional unit for each fetched instruction. In this example, the processing unit 110 operates as a Very Long Instruction Word (VLIW) processor, capable of processing multiple instructions within a corresponding functional unit simultaneously. The compiler organizes the instructions executed together in the execution package. The instruction dispatch unit 112 directs each instruction to its target functional unit. The functional unit assigned to an instruction is entirely specified by the instructions generated by the compiler. The hardware of the processing unit core 110 does not participate in functional unit allocation. In this example, the instruction dispatch unit 12 operates several instructions in parallel. The number of such parallel instructions is determined by the size of the execution package, as described further herein.

[0066] Part of the dispatching task of instruction dispatch unit 112 is to determine whether an instruction is executed on a functional unit in scalar data path A 115 or on vector data path B 116. An instruction bit, referred to as the s-bit, in each instruction determines which data path the instruction controls. This is described further herein.

[0067] Instruction decoding unit 113 decodes each instruction in the current execution package. Decoding includes identifying the functional unit executing the instruction, identifying the registers from a possible register file (RF) used to supply data for the corresponding data processing operation, and identifying the register destination of the result of the corresponding data processing operation. As further described below, an instruction may include a constant field replacing an operand field of a register number. The result of this decoding is signals used to control the target functional unit to perform the data processing operation specified by the corresponding instruction on the given data.

[0068] The processing unit core 110 includes a control register 114. The control register 114 stores information for controlling the functional units in the scalar data path side A 115 and the vector data path side B 116. This information may include mode information, etc.

[0069] Decoded instructions from instruction decoder 113 and information stored in control register 114 are supplied to scalar data path side A115 and vector data path side B116. As a result, functional units in scalar data path side A115 and vector data path side B116 execute instruction-specified data processing operations based on the instruction-specified data and store the results in one or more instruction-specified data registers. Each of scalar data path side A115 and vector data path side B116 includes multiple functional units operating in parallel. These combinations... Figure 2 Further description follows. A data path 117 that allows data exchange exists between scalar data path side A 115 and vector data path side B 116.

[0070] The processing unit core 110 further includes non-instruction-based modules. The emulation unit 118 allows the machine state of the processing unit core 110 to be determined in response to instructions. This capability can be used for algorithm development. The interrupt / exception unit 119 enables the processing unit core 110 to respond to external asynchronous events (interrupts) and to respond to attempts to perform inappropriate operations (exceptions).

[0071] Processor 110 includes a streaming engine 125. Streaming engine 125 supplies two data streams from predetermined addresses cached in L2 combined cache 130 to the register file of the vector data path side B of processing unit core 110. This provides controlled data movement directly from memory (such as cached in L2 combined cache 130) to the operand inputs of the functional units. This is further described herein.

[0072] Figure 1 This illustrates example data widths of the buses between the various sections. L1I buffer 121 supplies instructions to instruction fetch unit 111 via bus 141. In this example, bus 141 is a 512-bit bus. Bus 141 provides unidirectional access from L1I buffer 121 to processing unit 10. L2 combined buffer 130 supplies instructions to L1I buffer 121 via bus 142. In this example, bus 142 is a 512-bit bus. Bus 142 provides unidirectional access from L2 combined buffer 130 to L1I buffer 121.

[0073] L1D buffer 123 exchanges data with the register file in scalar data path A115 via bus 143. In this example, bus 143 is a 64-bit bus. L1D buffer 123 exchanges data with the register file in vector data path B116 via bus 144. In this example, bus 144 is a 512-bit bus. Buses 143 and 144 are illustrated as bidirectionally supporting both data reading and data writing to the processing unit core 110. L1D buffer 123 exchanges data with L2 combined buffer 130 via bus 145. In this example, bus 145 is a 512-bit bus. Bus 145 is illustrated as a caching service bidirectionally supporting both data reading and data writing to the processing unit core 110.

[0074] After a cache hit (if the requested data is stored in L1D cache 123), the processor data request is fetched directly from L1D cache 123. After a cache miss (if the specified data is not stored in L1D cache 123), the data is searched in L2 combined cache 130. The memory location of the requested data is either hit or miss in L2 combined cache 130. A hit is serviced by L2 combined cache 130. A miss is serviced by another level cache (not shown) or by main memory (not shown). The requested data can be simultaneously supplied to both L1D cache 123 and processing unit core 110 to accelerate usage.

[0075] L2 combined buffer 130 supplies data from a first data stream to streaming engine 125 via bus 146. In this example, bus 146 is a 512-bit bus. Streaming engine 125 supplies data from the first data stream to the functional unit of vector data path side B 116 via bus 147. In this example, bus 147 is a 512-bit bus. L2 combined buffer 130 supplies data from a second data stream to streaming engine 125 via bus 148. In this example, bus 148 is a 512-bit bus. Streaming engine 125 supplies data from this second data stream to the functional unit of vector data path side B 116 via bus 149. In this example, bus 149 is a 512-bit bus. In this example, buses 146, 147, 148, and 149 are illustrated as unidirectional connections from L2 combined buffer 130 to streaming engine 125 and to vector data path side B 116.

[0076] After a cache hit (if the requested data is stored in L2 combined cache 130), the streaming engine data request is fetched directly from L2 combined cache 130. After a cache miss (if the specified data is not stored in L2 combined cache 130), the data is searched for from another level cache (not illustrated) or from main memory (not illustrated). In some examples, it is technically feasible for L1D cache 123 to cache data not stored in L2 combined cache 130. If this operation is supported, L2 combined cache 130 listens to L1D cache 1233 for streaming engine data requests based on missed streaming engine data requests in L2 combined cache 130. If L1D cache 123 stores the data, the listener response includes the data subsequently served to service the streaming engine request. If the L1D cache 123 does not store data, the listener response indicates this result and the L2 combined cache 130 serves streaming engine requests from another cache level (not shown) or from main memory (not shown).

[0077] In this example, according to U.S. Patent No. 6,606,686 entitled “Unified Memory System Architecture Including Cache and Directly Addressable Static Random Access Memory”, both the L1D cache 123 and the L2 combined cache 130 can be configured as a selected number of caches or directly addressable memory, the aforementioned patent being incorporated herein by reference.

[0078] In this example, processor 100 is fabricated on an integrated chip (IC) mounted on a ball grid array (BGA) substrate. The BGA substrate and IC die may be referred to together as a "BGA package," "IC package," "integrated circuit," "IC," "chip," "microelectronic device," or similar terms. A BGA package may include encapsulation material to cover and protect the IC die from damage. In another example, other types of known or later-developed packaging technologies may be used with processor 100.

[0079] Figure 2Further details regarding the functional units and register files in scalar data path side A115 and vector data path side B116 are provided. Scalar data path side A115 includes L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226. Scalar data path side A115 also includes a global scalar register file (RF) 211, an L1 / S1 local register file 212, an M1 / N1 local register file 213, and a D1 / D2 local register file 214. Vector data path side B116 includes L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246. Vector data path side B116 includes a global vector register file 231, an L2 / S2 local register file 232, an M2 / N2 / C local register file 233, and an assertion register file 214. This article describes in more detail which functional unit can read from or write to which register file.

[0080] The scalar data path side A 115 includes L1 unit 221. L1 unit 221 typically accepts two 64-bit operands and produces a 64-bit result. Both operands are called from registers specified by instructions in the global scalar register file 211 or the L1 / S1 local register file 212. L1 unit 221 performs operations selected by the following instructions: 64-bit addition / subtraction; 32-bit minimum / maximum operations; 8-bit single-instruction multiple-data (SIMD) instructions (such as absolute summation, minimum and maximum value determination); loop minimum / maximum operations; and various move operations between register files. The result is written to the register specified by instructions in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0081] The scalar data path side A 115 includes S1 unit 222. S1 unit 222 typically accepts two 64-bit operands and produces a 64-bit result. Both operands are called from registers specified by instructions in the global scalar register file 211 or the L1 / S1 local register file 212. In this example, S1 unit 222 performs the same type of operation as L1 unit 211. In another example, there may be slight variations between the data processing operations supported by L1 unit 211 and S1 unit 222. The result is written to registers specified by instructions in the global scalar register file 211, L1 / S1 local register file 212, M1 / N1 local register file 213, or D1 / D2 local register file 214.

[0082] The scalar data path side A 115 includes M1 unit 223. M1 unit 223 typically accepts two 64-bit operands and produces a 64-bit result. Both operands are called from registers specified by instructions in the global scalar register file 211 or the M1 / N1 local register file 213. Examples of operations selected by instructions executed by M1 unit 223 include: 8-bit, 16-bit, and 32-bit multiplication operations; Galois field multiplication; complex multiplication with and without rounding; IEEE floating-point multiplication operations; complex dot product operations; 32-bit counting operations; complex conjugate multiplication operations; and bitwise logic operations, shifting, addition, and subtraction. The result is written to registers specified by instructions in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0083] The scalar data path side A 115 includes N1 unit 224. N1 unit 224 typically accepts two 64-bit operands and produces a 64-bit result. Both operands are called from registers specified by instructions in the global scalar register file 211 or the M1 / N1 local register file 213. In this example, N1 unit 224 performs the same type of operation as M1 unit 223. Dual operations (called dual-issue instructions) also exist, simultaneously using both M1 unit 223 and N1 unit 224. The result is written to the register specified by instructions in the global scalar register file 211, L1 / S1 local register file 212, M1 / N1 local register file 213, or D1 / D2 local register file 214.

[0084] The scalar data path side A 115 includes units D1 225 and D2 226. Units D1 225 and D2 226 typically accept two 64-bit operands and each produce a 64-bit result. Units D1 225 and D2 226 typically perform address calculations and corresponding load and store operations. Unit D1 225 is used for 64-bit scalar load and store. Unit D2 226 is used for 512-bit vector load and store. In this example, units D1 225 and D2 226 also perform: swapping, packing, and unpacking of load and store data; 64-bit SIMD algorithm operations; and 64-bit bitwise logic operations. The D1 / D2 local register file 214 stores the base address and offset address used for address calculations of the corresponding load and store operations. Both operands are called from registers specified by instructions in the global scalar register file 211 or the D1 / D2 local register file 214. The results of the calculations are written to the registers specified by the instructions in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0085] The vector data path side B 116 includes an L2 unit 241. The L2 unit 241 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are invoked from registers specified by instructions in the global vector register file 231, the L2 / S2 local register file 232, or the assertion register file 234. In this example, the L2 unit 241 executes instructions similar to those in the L1 unit 221, except for the wider 512-bit data. The result can be written to registers specified by instructions in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the assertion register file 214.

[0086] The vector data path side B 116 includes S2 unit 242. S2 unit 242 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are invoked from registers specified by instructions in the global vector register file 231, the L2 / S2 local register file 232, or the assertion register file 234. In this example, S2 unit 242 executes instructions similar to those in S1 unit 222. The result is written to the register specified by instructions in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the assertion register file 214.

[0087] The vector data path side B 116 includes M2 unit 243. M2 unit 243 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are called from registers specified by instructions in the global vector register file 231 or the M2 / N2 / C local register file 233. In this example, M2 unit 243 executes instructions similar to those in M1 unit 223, except for the wider 512-bit data. The result is written to the register specified by instructions in the global vector register file 231, the L2 / S2 local register file 232, or the M2 / N2 / C local register file 233.

[0088] The vector data path side B 116 includes N2 unit 244. N2 unit 244 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are called from registers specified by instructions in the global vector register file 231 or the M2 / N2 / C local register file 233. In this example, N2 unit 244 executes instructions of the same type as M2 unit 243. There are also dual operations that simultaneously utilize both M2 unit 243 and N2 unit 244 (referred to as dual-issue instructions). The result is written to the register specified by the instructions in the global vector register file 231, L2 / S2 local register file 232, or M2 / N2 / C local register file 233.

[0089] The vector data path side B 116 includes a related unit (C unit) 245. C unit 245 typically accepts two 512-bit operands and produces a 512-bit result. Both operands are called from registers specified by instructions in the global vector register file 231 or the M2 / N2 / C local register file 233. In this example, C unit 245 executes "search" and "search" instructions for WCDMA (Wideband Code Division Multiple Access) encoding / decoding. In this example, C unit 245 can execute up to 512 2-bit PN (pseudo-random numbers) and 8-bit I / Q (complex numbers) per clock cycle; 8-bit and 16-bit absolute difference summation (SAD) calculations, up to 512 SADs per clock cycle; horizontal addition and horizontal minimum / maximum instructions; and vector permutation instructions. C unit 245 also includes four vector control registers (CUCR0 to CUCR3) for controlling certain operations of C unit 245 instructions. Control registers CUCR0 to CUCR3 are used as operands for certain C unit 245 operations. In some examples, control registers CUCR0 through CUCR3 are used to control the Generalized Permutation Instruction (VPERM) and serve as masks for SIMD Multiple Point Product Operation (DOTPM) and SIMD Multiple Absolute Difference Summation (SAD) operations. In another example, control register CUCR0 is used to store the polynomial for the Galois field multiplication operation (GFMPY), and control register CUCR1 is used to store the Galois field polynomial generator function.

[0090] The vector data path side B 116 includes a P unit 246. The vector assertion (P) unit 246 performs basic logic operations on the registers of the local assertion register file 234. The P unit 246 has direct access to read from and write to the assertion register file 234. These logic operations include single register unary operations such as NEG (invert), which inverts each bit of a single register; BITCNT (bit count), which returns the count of the number of bits in a single register with a predetermined numeric state (1 or 0); RMBD (rightmost bit detection), which returns the number of bit positions from the least significant bit position (rightmost bit) to the first bit position with a predetermined numeric state (1 or 0); DECIMATE (downsampling), which selects the Nth (1, 2, 4, etc.) bit specified by each instruction for output; and EXPAND (expand), which copies each bit N (2, 4, etc.) times as specified by the instruction. These logical operations also include two-register binary operations, such as AND, which is a bitwise AND operation on the data of two registers; NAND, which is a bitwise AND operation on the data of two registers and then inverted; OR, which is a bitwise OR operation on the data of two registers; NOR, which is a bitwise OR operation on the data of two registers and then inverted; and XOR, which is a bitwise XOR operation on the data of two registers. These logical operations include transferring data from the assertion registers in assertion register file 234 to another specified assertion register or to a specified data register in global vector register file 231. One use of P unit 246 is to manipulate the results of SIMD vector comparisons used to control further SIMD vector operations. The BITCNT instruction can be used to count the number of 1s in the assertion registers to determine the number of valid data elements from the assertion registers.

[0091] Figure 3 The global scalar register file 211 is described. There are 16 independent 64-bit wide scalar registers, labeled A0-A15. Each register in the global scalar register file 211 can be read or written as 64-bit scalar data. All scalar data path side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read from or write to the global scalar register file 211. The global scalar register file 211 can be read as 32 bits or read as 64 bits and written as 64 bits. The execution of instructions determines the size of the data read. The vector data path side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read from the global scalar register file 211 via cross path 117 under the constraints described below.

[0092] Figure 4 Description of D1 / D2 local register file 214. There are sixteen independent 64-bit wide scalar registers, labeled D0-D16. Each register in D1 / D2 local register file 214 is read or written as 64-bit scalar data. All scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to global scalar register file 211. Only D1 unit 225 and D2 unit 226 can be read from D1 / D2 local register file 214. Data stored in D1 / D2 local register file 214 may include a base address and offset address used for address calculation.

[0093] Figure 5 The L1 / S1 local register file 212 is described. In this example, the L1 / S1 local register file 212 includes eight independent 64-bit wide scalar registers, labeled AL0-AL7. In this example, the instruction encoding allows the L1 / S1 local register file 212 to include up to 16 registers. In this example, eight registers are implemented to reduce circuit size and complexity. Each register in the L1 / S1 local register file 212 can be read or written as 64-bit scalar data. All scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the L1 / S1 local register file 212. L1 unit 221 and S1 unit 222 can read from the L1 / S1 local register file 212.

[0094] Figure 6 The M1 / N1 local register file 213 is described. In this example, eight independent 64-bit wide scalar registers are implemented, labeled AM0-AM7. In this example, the instruction encoding allows the M1 / N1 local register file 213 to include up to 16 registers. In this example, eight registers are implemented to reduce circuit size and complexity. Each register in the M1 / N1 local register file 213 can be read or written as 64-bit scalar data. All scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the M1 / N1 local register file 213. M1 unit 223 and N1 unit 224 can read from the M1 / N1 local register file 213.

[0095] Figure 7The global vector register file 231 is described. There are sixteen independent 512-bit wide vector registers. Each register in the global vector register file 231 can be read or written as 64-bit scalar data, labeled B0-B15. The instruction type determines the data size. All vector data path-side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read from or write to the global vector register file 231. Scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read from the global vector register file 231 via cross path 117 under the constraints described below.

[0096] Figure 8 The assertion (P) local register file 234 contains eight independent 64-bit wide registers, labeled P0-P7. Each register in the P local register file 234 can be read from or written as 64-bit scalar data. Functional units L2 241, S2 242, C 244, and P 246 on the vector data path side can write to the P local register file 234. L2 241, S2 242, and P 246 can read from the P local register file 234. One use of the P local register file 234 is to: write a single bit of SIMD vector comparison result from L2 241, S2 242, or C 244; manipulate the SIMD vector comparison result by P 246; and use the manipulated result to control further SIMD vector operations.

[0097] Figure 9 The L2 / S2 local register file 232 is described. In this example, eight independent 512-bit wide vector registers are implemented. In this example, the instruction encoding allows the L2 / S2 local register file 232 to include up to sixteen registers. In this example, eight registers are implemented to reduce circuit size and complexity. Each register in the L2 / S2 local vector register file 232 can be read or written as 64-bit scalar data, labeled BL0-BL7. Each register in the L2 / S2 local vector register file 232 can be read or written as 512-bit vector data, labeled VBL0-VBL7. The instruction type determines the data size. All vector data path-side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can write to the L2 / S2 local vector register file 232. L2 unit 241 and S2 unit 242 can read from the L2 / S2 local vector register file 232.

[0098] Figure 10 Description of M2 / N2 / C local register file 233. In this example, eight independent 512-bit wide vector registers are implemented. In this example, the instruction encoding allows M2 / N2 / C local register file 233 to include up to sixteen registers. In this example, eight registers are implemented to reduce circuit size and complexity. Each register in M2 / N2 / C local vector register file 233 can be read or written as 64-bit scalar data, labeled BM0-BM7. Each register in M2 / N2 / C local vector register file 233 can be read or written as 512-bit vector data, labeled VML0-VML7. All vector data path-side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can write to M2 / N2 / C local vector register file 233. Units M2 243, N2 244, and C 245 can be read from the M2 / N2 / C local vector register file 233.

[0099] The specification of global register files accessible by all functional areas on one side and local register files accessible by some functional units on one side is a design choice. In another example, different accessibility specifications can be made, such as using a class of register files corresponding to the global register files described herein.

[0100] Cross path 117 allows limited data exchange between scalar data path side A 115 and vector data path side B 116. During each operating cycle, a 64-bit data word can be called from global scalar register file A 211 as an operand for one or more function units on vector data path side B 116, and a 64-bit data word can be called from global vector register file 231 as an operand for one or more function units on scalar data path side A 115. Any scalar data path side A 115 function unit (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read a 64-bit operand from global vector register file 231. This 64-bit operand is the least significant bit of the 512-bit data in the register accessed by global vector register file 231. Multiple scalar data path side A 115 function units can use the same 64-bit cross path data as the operands during the same operating cycle. However, within a single operation cycle, a single 64-bit operand is transferred from the vector data path side B 116 to the scalar data path side A 115. Any vector data path side B 116 (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read the 64-bit operand from the global scalar register file 211. If the corresponding instruction is a scalar instruction, the cross-path operand data is treated as a 64-bit operand. If the corresponding instruction is a vector instruction, the high 448 bits of the operand are filled with zeros. Multiple vector data path side B 116 functional units can use the same 64-bit cross-path data as the operands during the same operation cycle. In one example, within a single operation cycle, a single 64-bit operand is transferred from the scalar data path side A 115 to the vector data path side B 116.

[0101] Streaming Engine 125 ( Figure 1Data is transmitted under certain constraints. Streaming engine 125 controls two data streams. Each stream consists of a sequence of elements of a specific type. Programs operating on these streams sequentially read the data and then operate on each element. Each stream has the following basic properties: the stream data has a well-defined start and end time; the stream data has a fixed element size and type throughout the stream; and the stream data has a fixed element sequence. Once a stream is opened, streaming engine 125 performs the following operations: calculates addresses; fetches the defined data type from L2 unified cache 130 (which may require caching services from higher-level memory, such as in the event of a cache miss in L2); performs data type manipulations such as zero extension, sign extension, data element sorting / transposition (such as matrix transpose); and transfers the data directly to the programmed data register file in processor core 110. Therefore, streaming engine 125 is beneficial for real-time digital filtering operations on well-behaved data. Streaming engine 125 frees up the corresponding processor from these memory tasks, thus enabling other processing functions.

[0102] The streaming engine 125 provides several benefits. For example, the streaming engine 125 allows for multidimensional memory access, increases the available bandwidth of functional units, minimizes the number of cache stalls due to the streaming buffer bypassing the L1D cache 123, and reduces the number of scalar operations required to maintain loops. The streaming engine 125 also manages address pointers and handles the release of address generation instruction slots for other computations, as well as address generation for D1 unit 225 and D2 unit 226.

[0103] Processor Core 110 ( Figure 1 The instruction pipeline is operated. Instructions are extracted from fixed-length instruction packets, as described further below. All instructions require the same number of pipeline stages for extraction and decoding, but different numbers of execution stages.

[0104] Figure 11 Describe the following pipeline stages: program fetch stage 1110, dispatch and decode stage 1120, and execution stage 1130. Program fetch stage 1110 comprises three levels for all instructions. Dispatch and decode stage 1120 comprises three levels for all instructions. Execution stage 1130 comprises one to four levels depending on the instruction.

[0105] The fetch phase 1110 includes a program address generation (PG) stage 1111, a program access (PA) stage 1112, and a program receive (PR) stage 1113. During the program address generation stage 1111, a program address is generated in the processor, and a read request is sent to the memory controller of the L1I register. During the program access stage 1112, the L1I register processes the request, accesses the data in its memory, and sends the fetch packet to the processor boundary. During the program receive stage 1113, the processor registers the fetch packet.

[0106] Extract instructions from an extraction packet containing 16 32-bit wide words. Figure 12 This illustrates sixteen instructions 1201-1216 in a single fetch packet. The fetch packet is aligned on 512-bit (16-word) boundaries. This example uses a fixed 32-bit instruction length, which makes it easy for the decoder to align. Properly aligned instruction fetches can load multiple instructions into a parallel instruction decoder. Predetermined instruction alignment achieves this proper alignment when it is stored in memory coupled to fixed instruction packet fetches by aligning the fetch packet on 512-bit boundaries. Conversely, variable-length instructions require initial steps to locate each instruction boundary before decoding. Fixed-length instruction sets generally allow for a more regular layout of instruction fields, which simplifies the structure of each decoder and is beneficial for wide-issue VLIW processors.

[0107] The execution of individual instructions is partially controlled by a p-bit in each instruction. In this example, the p-bit is a 32-bit gap of bit 0. The p-bit determines whether an instruction is executed in parallel with the next instruction. Instructions are scanned from lower to higher addresses. In this example, if the p-bit of an instruction is 1, the next following instruction (at a higher memory address) is executed in parallel with this instruction (within the same cycle). If the p-bit of an instruction is 0, the next following instruction is executed in the cycle following this instruction.

[0108] Processor Core 110 ( Figure 1 ) and L1I buffer 121 pipeline ( Figure 1 They are mutually decoupled. The fetched packets returned from the L1I cache can take a different number of clock cycles, depending on external conditions, such as whether a hit occurs in the L1I cache 121 or the L2 combined cache 130. Therefore, the program access level 1112 can take several clock cycles instead of one clock cycle as in other levels.

[0109] Instructions executed in parallel form execution packets. In this example, an execution packet may include up to sixteen 32-bit wide gaps for sixteen instructions. No two instructions in an execution packet can use the same functional unit. Gaps are one of five types: 1) self-contained instructions that execute on one of the functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) of processor core 110; 2) unitless instructions, such as NOP (no operation) instructions or multiple NOP instructions; 3) branch instructions; 4) constant field extensions; and 5) condition code extensions. Some of these gap types are described further in this document.

[0110] Dispatch and decoding phase 1120 ( Figure 11 This includes the instruction dispatch to the appropriate execution unit (DS) level 1121; the instruction pre-decoding (DC1) level 1122; and the instruction decoding and operand fetch (DC2) level 1123. During the instruction dispatch to the appropriate execution unit level 1121, the fetch packet is divided into execution packets and assigned to the appropriate functional unit. During the instruction pre-decoding level 1122, the source register, destination register, and associated path are decoded for use with instructions in the execution functional unit. During the instruction decoding and operand fetch level 1123, more detailed unit decoding is performed, and operands are read from the register file.

[0111] Execution phase 1130 includes execution (E1-E5) levels 1131-1135. Different types of instructions require different numbers of these levels to complete execution. The pipeline's execution levels play a crucial role in understanding the device state at the boundaries of the processor cycle.

[0112] During E1 level 1131, the conditions of the instruction are estimated and the operands are operated on. For example... Figure 11 As illustrated, E1 stage 1131 can receive operands from either stream buffer 1141 or register file (illustratively shown as 1142). For load and store instructions, address generation is performed and the address modifications are written to the register file. For branch instructions, the branch fetch packet in the PG stage is affected. Figure 11 The illustration shows load and store instructions accessing memory (illustrated here as memory 1151). For single-cycle instructions, the result is written to the destination register file when any condition of the instruction is estimated to be correct. If the condition is estimated to be incorrect, the instruction does not write any result or has any pipelined operation after E1 level 1131.

[0113] During E2 level 1132, the load instruction sends the address to memory. The store instruction sends the address and data to memory. If saturation occurs, a single-cycle instruction that saturates the result sets the SAT bit in the control status register (CSR). For two-cycle instructions, the result is written to the destination register file.

[0114] During E3 level 1133, a data memory access is performed. If saturation occurs, any multi-instruction that saturates the result sets the SAT bit in the Control Status Register (CSR). For 3-cycle instructions, the result is written to the destination register file.

[0115] During E4 stage 1134, load instructions bring data to the processor boundary. For 4-cycle instructions, the result is written to the destination register file.

[0116] During E5 level 1135, the load instruction writes data into a register, such as in... Figure 11 The diagram illustrates this using inputs from memory 1151 to E5 stage 1135.

[0117] Figure 13 This illustration shows an example of instruction encoding 1300 used by the processing unit core 110. The illustrated instruction format is a two-source arithmetic instruction. Other instruction encodings may also be used. Typically, the instruction consists of 32 bits and controls the operation of one of the various controllable functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246).

[0118] exist Figure 13 In the example, the dst field 1301 specifies a register in the corresponding register file as the destination of the instruction result. The src2 / cst field 1302 has several meanings, depending on the instruction opcode field 1304 and the unit field 1305. One meaning is to specify a register in the corresponding register file as the second operand. Another meaning is a direct constant. Depending on the instruction type, field 1302 is treated as an unsigned integer and zero extended to the specified data length, or as a signed integer and sign extended to the specified data length.

[0119] The src1 field 1303 specifies the register in the corresponding register file as the first source operand. The opcode field 1304 specifies the type of instruction. The unit field 1305, in conjunction with the side bit 1306, indicates which functional units are used to execute the instruction. A detailed explanation of the opcodes, except for the instruction options described below, is beyond the scope of this specification.

[0120] Bit s1306 specifies either scalar data path side A 115 or vector data path side B 116. If s = 0, scalar data path side A 115 is selected, which limits the functional unit to... Figure 2 The diagram illustrates L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, and their corresponding register files. Similarly, s=1 selects the vector data path side B 116, which restricts the functional units to... Figure 2 The diagram illustrates L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, P unit 246, and their corresponding register files.

[0121] Bit p (1307) marks the execution packet. Bit p determines whether the instruction is executed in parallel with subsequent instructions. Bit p is scanned from lower to higher addresses. If p = 1 for the current instruction, the next instruction is executed in parallel with the current instruction. If p = 0 for the current instruction, the next instruction is executed in the cycle following the current instruction. All instructions executed in parallel form an execution packet. An execution packet can contain up to sixteen instructions. Each instruction in an execution packet uses a different functional unit.

[0122] Most instructions in the processing unit core 110 do not include direct encoding for conditional execution. However, instructions can be made conditional. The behavior that makes an instruction conditional is called an assertion, and the register that stores the condition is called the assertion register. An execution packet may include two 32-bit condition code extension gaps that encode 4 bits of condition information for instructions in the same execution packet. The condition code gaps are called condition code extension gap 0 and condition code extension gap 1, and the 4 bits of condition information are referred to herein as the creg / z field.

[0123] Table 1 shows the encoding of the creg / z fields. The creg bit identifies the assertion register, and the z bit indicates whether the assertion is based on zero or non-zero in the assertion register. The execution of a conditional instruction depends on the value stored in the specified data register. If z = 1, the test is for equality against zero. If z = 0, the test is for non-zero. The cases of creg = 0 and z = 0 are considered "true" to allow the execution of unconditional instructions. Note that "z" in the z bit column refers to the zero / non-zero comparison selection mentioned above, and "x" indicates no state is considered.

[0124] Table 1

[0125]

[0126] Figure 14This describes the encoding used for condition code extension gap 0 1400. Field 1401 specifies the four creg / z bits allocated to instruction L1 unit 221, field 1402 specifies the four creg / z bits allocated to instruction L2 unit 241, field 1403 specifies the four creg / z bits allocated to instruction S1 unit 222, field 1404 specifies the four creg / z bits allocated to instruction S2 unit 242, field 1405 specifies the four creg / z bits allocated to instruction D1 unit 225, field 1406 specifies the four creg / z bits allocated to instruction D2 unit 245, field 1407 is unused / reserved, and field 1408 is encoded as a unique set of bits (CCEX0) that identify condition code extension gap 0. When a unique ID of condition code extension gap 0 is detected, the creg / z bit is used to control the conditional execution of any corresponding instructions in L1 unit 221, L2 unit 241, S1 unit 222, S2 unit 242, D1 unit 225, and D2 unit 226 within the same execution packet. Note that a properly encoded condition code extension gap 0 can make some instructions in the execution packet conditional and some instructions unconditional.

[0127] Figure 15 This describes the encoding used for condition code extension gap 1 1500. Field 1501 specifies the four creg / z bits allocated to the instruction in unit M1 223, field 1502 specifies the four creg / z bits allocated to the instruction in unit M2 243, field 1503 specifies the four creg / z bits allocated to the instruction in unit C 245, field 1504 specifies the four creg / z bits allocated to the instruction in unit N1 224, field 1505 specifies the four creg / z bits allocated to the instruction in unit N2 244, field 1506 is unused / reserved, and field 1507 is encoded as a unique set of bits (CCEX1) to identify condition code extension gap 1. When the unique ID of condition code extension gap 1 is detected, the corresponding creg / z bits are used to control the conditional execution of any instruction in unit M1 223, unit M2 243, unit C 245, unit N1 224, and unit N2 244 within the same execution packet.

[0128] Refer again Figure 13 In some instructions, the bits in opcode field 1304 referred to as constant extension bits can be encoded to indicate that the constant in src2 / CST field 1302 should be extended. The execution package can contain two 32-bit constant extension gaps, each of which can store 27 bits to be concatenated into higher-order bits with the 5-bit constant in field 1302 to form a 32-bit constant. Figure 16This describes the fields of constant extension gap 0 1600. Field 1601 stores the 27 most significant bits of the extended 32-bit constant. Field 1602 is encoded with a unique set of bits (CSTX0) to identify constant extension gap 0. In this example, constant extension gap 0 1600 can be used to extend the constant of one of the following instructions in the same execution package: L1 unit 221 instruction, D1 unit 225 instruction, S2 unit 242 instruction, D2 unit 226 instruction, M2 unit 243 instruction, N2 unit 244 instruction, branch instruction, or C unit 245 instruction. Constant extension gap 1 is similar to constant extension gap 0 except that this gap is encoded with a unique set of bits (CSTX1) to identify constant extension gap 1. In this example, the constant extension gap 1 can be used to extend the constant of one of the instructions in L2 unit 241, D2 unit 226, S1 unit 222, D1 unit 225, M1 unit 223, or N1 unit 224 within the same execution package.

[0129] Constant extension gap 0 and constant extension gap 1 are used as follows: Instruction decoder 113 determines the constant in field 1302 (referred to as the direct field) based on the instruction opcode bits, and determines whether the constant should be extended from the previously mentioned constant extension bit in opcode field 1304. If instruction decoder 113 detects constant extension gap 0 or constant extension gap 1, instruction decoder 113 checks the instructions within the execution packet for the instruction corresponding to the detected constant extension gap. Constant extension is performed when a corresponding instruction has a constant extension bit equal to 1.

[0130] Figure 17 This is a block diagram 1700 illustrating the extension of constants. Figure 17 Assuming instruction decoder 113 ( Figure 1The constant extension gap and the corresponding instruction within the same execution packet are detected. The instruction decoder 113 supplies twenty-seven extension bits from field 1601 of the constant extension gap and five constant bits from field 1302 of the corresponding instruction to serializer 1701. Serializer 1701 forms a single 32-bit word based on these two parts. In this example, the twenty-seven extension bits from field 1601 of the constant extension gap are the most significant bits and the five constant bits from field 1302 are the least significant bits. The combined 32-bit word is supplied to one input of multiplexer 1702. The five constant bits from field 1302 of the corresponding instruction supply a second input to multiplexer 1702. The selection of multiplexer 1702 is controlled by the state of the constant extension bits. If the constant extension bit is 1, multiplexer 1702 selects the serialized 32-bit input. If the constant extension bit is 0, the multiplexer 1702 selects five constant bits from the corresponding instruction field 1302. The output of the multiplexer 1702 supplies the input to the symbol extension unit 1703.

[0131] The symbol extension unit 1703 forms the final operational value based on the input from the multiplexer 1703. The symbol extension unit 1703 receives control inputs of scalar / vector and data size. The scalar / vector input indicates whether the corresponding instruction is a scalar instruction or a vector instruction. The functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) on the data path side A 115 execute scalar instructions. Any instruction pointing to one of these functional units is a scalar instruction. The functional units L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, and C unit 245 on the data path side B 116 can execute either scalar or vector instructions. The instruction decoder 113 determines whether the instruction is a scalar or vector instruction based on the opcode bit. The P unit 246 can execute scalar instructions. The data size can be eight bits (byte B), sixteen bits (half-word H), 32 bits (word W), or 64 bits (double word D).

[0132] Table 2 lists the operations of the symbol extension unit 1703 for various options.

[0133] Table 2

[0134]

[0135] As described above Figure 13As described, both constant extension gap 0 and constant extension gap 1 can include p bits to define the execution packet. In this example, as in the case of condition code extension gaps, constant extension gap 0 and constant extension gap 1 have bits 0 (p bits) encoded as 1. Therefore, neither constant extension gap 0 nor constant extension gap 1 can be in the last instruction gap of the execution packet.

[0136] An execution package may include a constant extension gap of 0 or 1 and more than one corresponding instruction marked as constant extension (e bit = 1). For such an event, for constant extension gap 0, more than one of the following instructions in the execution package—L1 unit 221, D1 unit 225, S2 unit 242, D2 unit 226, M2 unit 243, or N2 unit 244—may have an e bit of 1. For such an event, for constant extension gap 1, more than one of the following instructions in the execution package—L2 unit 241, D2 unit 226, S1 unit 222, D1 unit 225, M1 unit 223, or N1 unit 224—may have an e bit of 1. In one example, instruction decoder 113 determines that such an event is an invalid operation and is not supported. Alternatively, the combination may be supported by the extension bit of the constant extension gap applied to each corresponding functional unit instruction marked as constant extension.

[0137] Units L1 221, S1 222, L2 241, S2 242, and C 245 typically operate in Single Instruction Multiple Data (SIMD) mode. In this SIMD mode, the same instruction is applied to packed data from two operands. Each operand holds multiple data elements set in predetermined intervals. SIMD operation is enabled by carry control at data boundaries. This carry control enables operation on varying data widths.

[0138] Figure 18The carry control logic is explained. AND gate 1801 receives the carry output of bit N within an algorithmic logic unit of operand width (64 bits for function unit A 115 on the scalar data path side and 512 bits for function unit B 116 on the vector data path side). AND gate 1801 also receives a carry control signal, as described further below. The output of AND gate 1801 is supplied to the carry input of bit N+1 of the algorithmic logic unit of operand width. AND gates (such as AND gate 1801) are set between each pair of bits at possible data boundaries. For example, for 8-bit data, such AND gates would be between bits 7 and 8, bits 15 and 16, bits 23 and 24, etc. Each such AND gate receives a corresponding carry control signal. If the data size is the minimum size, each carry control signal is 0, effectively blocking carry transmission between adjacent bits. If the selected data size requires two algorithmic logic unit segments, the corresponding carry control signal is 1. Table 3 below shows example carry control signals for a 512-bit operand used by the B116 functional unit on the vector data path side. These can be divided into 8-bit, 16-bit, 62-bit, 64-bit, 128-bit, or 256-bit segments. In Table 3, the top 32 bits control the carry for the uppermost bits (bits 128 to 511), and the bottom 32 bits control the carry for the lowermost bits (bits 0 to 127). No control is needed for the carry output of the most significant bit; therefore, only 63 carry control signals are required.

[0139] Table 3

[0140]

[0141] powers of 2 (2) N It is common to operate on data sizes of 2. However, carry control techniques are not limited to powers of 2 and can be applied to other data sizes and operand widths.

[0142] In this example, at least L2 unit 241 and S2 unit 242 employ two types of SIMD instructions using registers in the assertion register file 234. In this example, the SIMD vector assertion instruction operates on a data size specified by the instruction. Data sizes include byte (8-bit) data, half-word (16-bit) data, word (32-bit) data, double-word (64-bit) data, quad-word (128-bit) data, and half-vector (256-bit) data. In the first type of these instructions, the functional unit (L2 unit 241 or S2 unit 242) performs a SIMD comparison on data packed in two general-purpose data registers and supplies the result to the assertion data register. This instruction specifies the data size, the two general-purpose data register operands, and the target assertion register. In this example, each assertion data register includes one bit corresponding to each minimum data size portion of the general-purpose data register. In the current example, the general-purpose data register is 512 bits (64 bytes), and the assertion data register is 64 bits (8 bytes). Each bit of the assertion data register corresponds to eight bits of the general-purpose data register. The comparison is performed on a specified data size (8, 16, 32, 64, 128, or 256 bits). If the comparison is true, the function unit supplies 1 to all assertion register bits corresponding to that data size portion. If the comparison is false, the function unit supplies zero to the assertion register bits corresponding to that data size portion. In this example, the enabled comparison operations include: less than, greater than, and equal to.

[0143] In the second type of instruction, the functional unit (L2 unit 241 or S2 unit 242) performs a first SIMD operation or a second SIMD operation on the data packed in the general-purpose data register based on the state of the data in the assertion data register. The instruction specifies the data size, one or two general-purpose data register operands, controls the assertion register, and the destination of the general-purpose data register. For example, for each data size portion of two vector operands, the functional unit can select either the first data element of the first operand or the second data element of the second operand to be stored in the destination register based on the 1 / 0 state of the corresponding bit in the assertion data register. In another example, depending on the data of the corresponding bit in the assertion register, a data element of a single vector operand may be saved to memory or not saved.

[0144] The operation of P unit 245 allows for multiple composite vector SIMD operations based on more than one vector comparison. For example, two comparisons can be used for range determination. In a SIMD operation, a candidate vector is compared with a vector reference that has the minimum value of the range, packed in a data register. The greater than result is scalar data, where the bit corresponding to the SIMD data width is set to 0 or 1 according to the SIMD comparison and is stored in the assertion data register. Another SIMD comparison is performed between the candidate vector and another reference vector that has the maximum value of the range, packed in a different data register, which produces another scalar, less than the result, stored in another assertion register. The P unit then performs an AND operation on the two assertion registers. The AND result indicates whether each SIMD data portion of the candidate vector is within or outside the range. The P unit BITCNT instruction for the AND result can produce a count of the data elements within the comparison range. The P unit NEG function can be used to: convert a less than comparison result to a greater than or equal to comparison result; convert a greater than comparison result to a less than or equal to comparison result; or convert an equal to comparison result to a not equal to comparison result.

[0145] Streaming engine

[0146] Figure 19 yes Figure 1 A conceptual view of the stream engine 125 of the example processor 100. Figure 19 This description describes the processing of a single stream representing two streams controlled by stream engine 125. Stream engine 1900 includes a stream address generator 1901. Stream address generator 1901 continuously generates addresses of stream elements and supplies these element addresses to system memory 1910. Memory 1910 retrieves data (data elements) stored at the element addresses and supplies these data elements to a data FIFO buffer 1902. Data FIFO buffer 1902 provides buffering between memory 1910 and processor 1920. Data formatter 1903 receives data elements from data FIFO memory 1902 and provides data formatting according to the stream definition. This process is described in more detail here. Stream engine 1900 supplies formatted data elements from data formatter 1903 to processor 1920. The program executing on processor 1920 consumes this data and generates output.

[0147] Stream elements can reside in system memory. Memory does not prescribe a specific structure for the stream. The program defines the stream and therefore specifies its structure by specifying stream attributes, such as the address of the first element of the stream; the size and type of the elements in the stream; the formatting of the data in the stream; and the address sequence associated with the stream.

[0148] The streaming engine defines the address sequence of stream elements based on pointers traversing the entire memory. Multiple levels of nested loops control the paths taken by the pointers. The iteration count of a loop level indicates the number of times the level repeats. Dimensions indicate the distance between pointer positions within loop levels.

[0149] In the basic forward flow, the innermost loop physically consumes consecutive elements from memory because the implicit dimension of the innermost loop is one element. The pointer moves element by element in a continuously increasing order. In each level outside the inner loop, the loop moves the pointer to a new position based on the size of the loop level's dimension. This form of addressing allows the program to specify a regular path through memory using a small number of parameters. Table 4 lists the addressing parameters for the basic flow. In this example, ELEM_BYTES ranges from 1 to 64 bytes, as shown in Table 5.

[0150] Table 4

[0151]

[0152] Table 5

[0153] ELEM_BYTES Stream element length 000 1 byte 001 2 bytes 010 4 bytes 011 8 bytes 100 16 bytes 101 32 bytes 110 64 bytes 111 reserve

[0154] The above definition maps consecutive elements of a stream to increasing addresses in memory, which is applicable to many algorithms. Some algorithms serve this better by reading elements at a lower memory address level, using reverse stream addressing. For example, discrete convolution computes the vector dot product, as illustrated in the following diagram:

[0155]

[0156] Here, f[] and g[] represent arrays in memory. For each output, the algorithm reads f[] in the forward direction and g[] in the reverse direction. The actual filter limits the exponent range of [x] and [tx] to a finite number of elements. To support this mode, the streaming engine supports reading elements in a reduced address order.

[0157] Matrix multiplication presents unique challenges for streaming engines. Each element in a matrix product is a vector dot product between a row from the first matrix and a column from the second matrix. Programs can store matrices in either row-major or column-major order. Row-major order stores all elements of a single row contiguously in memory. Column-major order stores all elements of a single column contiguously in memory. Matrices can be stored in the same order as the language's default array order. As a result, only one of the two matrices in matrix multiplication maps to the streaming engine's 2D stream definition. In the example, the first index progresses through the columns of one array and through the rows of the other. Streaming engines support implicit matrix transposition using transposed streams. Transposed streams avoid the cost of explicitly transforming data in memory. Instead of accessing data in strictly consecutive element order, the streaming engine efficiently swaps the two inner cyclic dimensions of the lateral order, extracting elements into consecutive vector channels along the second dimension.

[0158] This algorithm works, but its implementation is impractical for small element sizes. Some algorithms work with matrix concatenation where multiple columns and rows are together. Therefore, the streaming engine defines a separate transpose granularity. The hardware specifies the minimum granularity. The transpose granularity needs to be at least as large as the element size. The transpose granularity causes the streaming engine to extract one or more consecutive elements from dimension 0 before moving along dimension 1. When the granularity is equal to the element size, a single column is extracted from the row-major array. Otherwise, the granularity specifies extracting two, four, or more columns from the row-major array each time. This also applies to column-major layouts by swapping the rows and columns in this description. The GRANULE parameter indicates the transpose granularity in bytes.

[0159] Another common matrix multiplication technique swaps the innermost two loops of a matrix multiplication. When reading rows across another matrix, the resulting inner loop no longer reads columns down a matrix. For example, the algorithm could push an item out of the inner loop and replace it with a scalar value. The innermost loop can be implemented by performing a vector summation after multiplying a single scalar by a vector. Alternatively, it can traverse the length of the vector and repeat scalar values ​​using vector-to-vector multiplication. The streaming engine in this example directly supports the latter and related use cases with an element repetition mode. In this mode, the streaming engine reads a granule smaller than the full vector size and duplicates that granule to fill the next vector output.

[0160] The streaming engine treats each complex number as a single element with two sub-elements, which are given by the real and imaginary parts (Cartesian coordinates) or the magnitude and angle parts (polar coordinates). Not all programs or peripherals are consistent with the order in which these sub-elements should exist in memory. Therefore, the streaming engine provides the ability to swap two sub-elements of a complex number at no cost. This involves swapping half of an element without interpreting its contents and can be used to swap sub-element pairs of any type, not just complex numbers.

[0161] Algorithms typically prefer to operate at high precision, but high-precision values ​​require more storage and bandwidth than low-precision values. Generally, programs store data in memory at low precision, boost these values ​​to higher precision for computation, and then reduce them back to lower precision for storage. Streaming engines directly support this operation by allowing algorithms to specify a type boosting level. In this example, each child element can be boosted to a larger type size with either sign-extended or zero-extended integer types. In some examples, streaming engines support floating-point boosting, boosting 16-bit and 32-bit floating-point values ​​to 32-bit and 64-bit formats, respectively.

[0162] Although the streaming engine defines a stream as a discrete sequence of data elements, the processing unit core 110 consumes data elements that are continuously packed into vectors. Vectors are similar to streams because vectors contain multiple elements of the same type and some implicit sequence. Because the streaming engine reads streams, but the processing unit core 110 consumes vectors, the streaming engine maps streams to vectors in a consistent manner.

[0163] The vector is divided into lanes of equal size, each lane allocated to store sub-elements. The processing unit core 110 marks the rightmost lane of the vector as lane 0, regardless of the current endianness mode. Lane numbers increase from right to left. The actual number of lanes within a vector varies depending on the length of the vector and the size of the sub-elements. Furthermore, lanes may be referred to herein as channels, vector channels, or SIMD channels.

[0164] Figure 20 This describes the sequence of formatting operations of formatter 1903. Formatter 1903 includes three sections: input section 2010, formatting section 2020, and output section 2030. Input section 2010 receives data retrieved from system memory 1910, such as data accessed via stream address generator 1901. This data can be retrieved via linear fetch stream 2011 or transpose fetch stream 2012.

[0165] Formatting section 2020 includes various formatting blocks. The formatting performed by these blocks within formatter 1903 is further described below. Complex number swapping block 2021 optionally swaps two child elements that form a complex number element. Type promotion block 2022 optionally promotes each data element to a larger data size. Promotion includes zero extension for unsigned integers and sign extension for signed integers. Downsampling block 2023 optionally downsamples data elements. In this example, the downsampling can be 2:1 (reserving every other data element) or 4:1 (reserving every three data elements). Element repeating block 2024 optionally repeats individual data elements. In this example, data element repeating is a power of 2 (2^2 + 2^3 ...N (where N is an integer), including multipliers of 2, 4, 8, 16, 32, and 64. In this example, data repetition can be extended across multiple destination vectors. The Vector Length Mask / Group Repetition Block 2025 has two main functions. The independently specified vector length VECLEN controls the data elements supplied to each output data vector. When group repetition is off, redundant channels in the output data vector are zero-padded, and these channels are marked as invalid. When group repetition is on, input data elements of the specified vector length are repeated to fill the output data vector.

[0166] Output section 2030 holds data for output to the corresponding functional unit. The registers and buffers of processor 2031 store formatted data vectors for processing unit core 110 (…). Figure 1 The functional unit is used as an operand.

[0167] Figure 21 This is the first example illustrating channel assignment in a vector. Vector 2100 is divided into eight 64-bit channels (8 × 64 bits = 512 bits in vector length). Channel 0 includes bits 0 to 63; Channel 1 includes bits 64 to 127; Channel 2 includes bits 128 to 191; Channel 3 includes bits 192 to 255; Channel 4 includes bits 256 to 319; Channel 5 includes bits 320 to 383; Channel 6 includes bits 384 to 447; and Channel 7 includes bits 448 to 511.

[0168] Figure 22 Here is another example illustrating channel assignment in a vector. Vector 2210 is divided into sixteen 32-bit channels (16 × 32 bits = 512 bits of vector length). Channel 0 includes bits 0 to 31; Channel 1 includes bits 32 to 63; Channel 2 includes bits 64 to 95; Channel 3 includes bits 96 to 127; Channel 4 includes bits 128 to 159; Channel 5 includes bits 160 to 191; Channel 6 includes bits 192 to 223; Channel 7 includes bits 224 to 255; Channel 8 includes bits 256 to 287; Channel 9 includes bits 288 to 319; Channel 10 includes bits 320 to 351; Channel 11 includes bits 352 to 383; Channel 12 includes bits 384 to 415; Channel 13 includes bits 416 to 447; Channel 14 includes bits 448 to 479; and Channel 15 includes bits 480 to 511.

[0169] The streaming engine directly maps the innermost streaming dimension to vector channels. Within the innermost streaming dimension, the first elements are mapped to lower channel numbers, and the last elements to higher channel numbers, regardless of whether the stream proceeds in ascending or descending address order. Regardless of the stream's defined order, the streaming engine stores elements in the vector in ascending channel order. For non-composite data, the streaming engine places the first element in the core of the processing unit (…). Figure 1 In the extracted vector, the second element is placed in channel 1 within channel 0, and so on. For composite data, the streaming engine places the first element in channels 0 and 1, the second element in channels 2 and 3, and so on. Regardless of the streaming direction, the child elements within an element maintain the same relative order. For non-interleaved composite elements, the child element with the lower address in each pair is placed in the even-numbered channel, and the child element with the higher address in each pair is placed in the odd-numbered channel. For interleaved composite elements, the placement is reversed.

[0170] The streaming engine fills each vector extracted by processing unit core 110 with as many elements as possible from the innermost streaming dimension as the CPU can handle. If the innermost dimension is not a multiple of the vector length, the streaming engine zero-padding the dimension to make it a multiple of the vector length. As described below, the streaming engine also marks channels as invalid. Therefore, for higher-dimensional streams, the first element from each iteration of the outer dimension arrives at channel 0 of the vector. The streaming engine maps the innermost dimension to consecutive channels in the vector. For transposed streams, the innermost dimension comprises a group of child elements along dimension 1, not dimension 0, because the transpose swaps these two dimensions.

[0171] Two-dimensional (2D) streams exhibit greater variability compared to one-dimensional streams. A basic 2D stream extracts smaller rectangles from larger ones. A transposed 2D stream reads rectangles column-by-column rather than row-by-row. A cyclic stream with the second dimension overlapping the first performs finite impulse response (FIR) filtering, repeatedly looping through a sliding window of samples providing the input sample.

[0172] Figure 23 This describes the memory regions that can be accessed using a basic two-dimensional stream. The two internal dimensions, represented by ELEM_BYTES, ICNT0, DIM1, and ICNT1 (refer to Table 4), provide sufficient flexibility to describe the removal of a smaller rectangle 2320 with dimensions 2321 and 2322 from a larger rectangle 2310 with dimensions 2311 and 2312. In this example, rectangle 2320 is a 9×13 rectangle with 64-bit values, and rectangle 2310 is the larger 11×19 rectangle. The following stream parameters define this stream: ICNT0 = 9, ELEM_BYTES = 8, ICNT1 = 13, and DIM1 = 88 (11 multiplied by 8).

[0173] Therefore, the iteration count in dimension 0 (2321) is nine, and the iteration count in dimension 1 (2322) is thirteen. Note that ELEM_BYTES scales the innermost dimension. The first dimension has ICNT0 elements of size ELEM_BYTES. The stream address generator does not scale the outer dimensions. Therefore, DIM1 = 88, which has eleven elements, each scaled by eight bytes.

[0174] Figure 24 illustrate Figure 23 The example shows the order of elements within the stream. The stream engine extracts the elements of the stream in the order shown in the diagram (2400). The first nine elements come from the first row of matrix 2300, from left to right, hops 1 to 8. Elements 10 through 24 come from the second row, and so on. When the stream moves from the 9th element to the 10th element... Figure 24 In the jump (9), the streaming engine calculates the new position based on the pointer's position at the beginning of the inner loop, rather than at the end of the first dimension. Therefore, DIM1 is independent of ELEM_BYTES and ICNT0. DIM1 represents the distance between the first bytes of each consecutive line.

[0175] A transposed stream is accessed along dimension 1 before being accessed along dimension 0. The following example illustrates a transposed stream with varying transpose granularity. Figure 25 This describes how to extract a smaller rectangle 2520 (12×8) with dimensions 2521 and 2522 from a larger rectangle 2510 (14×13) with dimensions 2511 and 2515. Figure 25 ELEM_BYTES in the middle is equal to 2.

[0176] Figure 26 Explain how the streaming engine extracts... Figure 25 The example stream has a four-byte transpose granularity. Extraction mode 2600 extracts element pairs from each row (because a granularity of four is twice that of ELEM_BYTES with a value of two), but otherwise moves down the columns. Once the streaming engine reaches the bottom of a pair of columns, it repeats the mode with the next pair of columns.

[0177] Figure 27 Explain how the streaming engine extracts... Figure 25 The example stream has an eight-byte transpose granularity. The overall structure remains the same. As shown in extraction mode 2700, the stream engine extracts four elements from each row (because a granularity of eight is four times that of ELEM_BYTES with a value of two), and then moves to the next row on the column.

[0178] The stream examined so far reads each element from memory exactly once. A stream can read a given element from memory multiple times, effectively cycling through a portion of memory. FIR filters exhibit two common cyclical patterns: rereading the same filter tap for each output, and reading input samples from a sliding window. Two consecutive outputs require input from two overlapping windows.

[0179] Figure 28 illustrate Figure 1 Details of the streaming engine 125. The streaming engine 125 comprises three main segments: Stream 0 2810; Stream 1 2820; and a shared L2 interface 2830. Stream 0 2810 and Stream 1 2820 both contain the same hardware for parallel operation. Stream 0 2810 and Stream 1 2820 both share the L2 interface 2830. Each stream 2810 and 2820 feeds data to the processing unit core 110 at a rate of up to 512 bits / cycle. Figure 1 It provides data, which is enabled through a dedicated flow path and a shared dual L2 interface.

[0180] Each stream engine 125 includes a corresponding dedicated 6D stream address generator 2811 / 2821, each of which can generate a new misalignment request per cycle. As further described herein, the address generator 2811 / 2821 outputs a 512-bit aligned address that overlaps with elements in a sequence defined by the stream parameters.

[0181] Each address generator 2811 / 2811 is connected to a corresponding dedicated micro-workbench backup buffer (μTLB) 2812 / 2822. Each μTLB 2812 / 2822 translates a single 48-bit virtual address to a 44-bit physical address per cycle. Each μTLB 2812 / 2822 has eight entries, covering a minimum of 32KB with 4KB pages or a maximum of 16MB with 2MB pages. Each address generator 2811 / 2821 generates two addresses per cycle. Each μTLB 2812 / 2822 translates only one address per cycle. To maintain throughput, the streaming engine 125 operates under the assumption that most streaming benchmarks reside within the same 4KB page. Therefore, address translation does not modify bits 0 through 11 of the address. If aout0 and aout1 are located in the same 4KB page (aout0[47:12] is the same as aout1[47:12]), then μTLB 2812 / 2822 only translates aout0 and reuses the translation of the higher bit of the two addresses.

[0182] The translated addresses are arranged in the corresponding command queues 2813 / 2823. These addresses are aligned with information from the corresponding memory dispatch and trace blocks 2814 / 2824. The streaming engine 125 does not explicitly manage μTLBs 2812 / 2822. The system memory management unit (MMU) invalidates the μTLBs as needed during environment switching.

[0183] Storage allocation and tracking of the 2814 / 2824 block manages the internal storage device, exploring data reuse and tracking the lifetime of each data segment. Each block accepts two virtual addresses per cycle and, if the addresses are not already allocated to a gap, constrains them to gaps in the internal storage device. Data storage is organized as an array of gaps. The streaming engine maintains the following metadata to track the content and lifetime of the data in each gap: the 49-bit virtual address associated with the gap, a valid bit indicating whether the tag address is valid, an immediate bit indicating that data has arrived at the address, an active bit indicating whether there are any significant references to the data, and the last reference value indicating the most recent reference to that gap in the reference queue. Storage allocation and tracking are further described in this paper.

[0184] The corresponding reference queues 2815 / 2825 store sequences of references generated by the corresponding address generators 2811 / 2821. These reference sequences enable the data formatting network to present data to the processing unit core 110 in the correct order. Each entry in the corresponding reference queues 2815 / 2825 contains the necessary information for reading data from the data memory and aligning it for use with the processing unit core 110. The corresponding reference queues 2815 / 2825 maintain the information listed in Table 6 during each interval.

[0185] Table 6

[0186]

[0187] When address generators 2811 / 2821 generate a new address, memory dispatch and trace blocks 2814 / 2824 insert a reference into reference queues 2815 / 2825. When data becomes available and there is space in the stream holding register, memory dispatch and trace blocks 2814 / 2824 remove the reference from reference queues 2815 / 2825. When memory dispatch and trace blocks 2814 / 2824 remove gap references from reference queues 2815 / 2825 and format the data, they check the most recent reference for the corresponding gap. Memory dispatch and trace blocks 2814 / 2824 compares the last reference in reference queues 2815 / 2825 with the last reference of the record in the gap. If the pointer and the last reference of the record match, memory dispatch and trace blocks 2814 / 2824 mark the gap as inactive once the data is no longer needed.

[0188] The streaming engine 125 has corresponding data stores 2816 / 2826 for a selected number of elements. Deep buffering allows the streaming engine to fetch ahead of the stream, thus hiding memory system latency. Each data store 2816 / 2826 accommodates two simultaneous read operations and two simultaneous write operations per cycle, and is therefore referred to as a two-read-two-write (2r2w) data store. In other examples, the buffering amount may be different. In the current example, the streaming engine 125 contributes 32 gaps per stream, each gap being tagged by the metadata described previously. Each gap holds 64 bytes of data in eight octet groups.

[0189] Implementation Reference for Data Memory 2816 / 2826 and Corresponding Storage Allocation / Tracking Logic 2814 / 2824 and Reference Queue 2815 / 2825 Figure 19 The data described is FIFO 1902.

[0190] The corresponding butterfly network 2817 / 2827 includes a seven-level butterfly network, which implements formatter 1903. Figure 19 , Figure 20 The Butterfly Network 2817 / 2827 receives 128 bytes of input and produces 64 bytes of output. The first stage of this Butterfly Network is actually a half-stage, which collects bytes from the two gaps extracted by the misaligned matching and merges the collected bytes into a single rotated 64-byte array. The remaining six stages form the standard Butterfly Network. The corresponding Butterfly Network 2817 / 2827 performs the following operations: rotates the next element down to byte channel 0; promotes the data type by powers of two if requested; swaps the real and imaginary parts of the complex number if requested; and converts big-endian to little-endian if the processing unit core 110 is currently in big-endian mode. The user specifies the element size, type promotion, and real / imaginary swap as part of the stream parameters.

[0191] The streaming engine 125 attempts to extract and format the data before the processing unit core 110 demands it, in order to maintain sufficient throughput. The corresponding stream header registers 2818 / 2828 provide a small amount of buffering, allowing the processing to remain adequately pipelined. The corresponding stream header registers 2818 / 2828 are not directly visible in the architecture. Each stream also has a corresponding stream validity register 2819 / 2829. The validity registers 2819 / 2829 indicate which elements in the corresponding stream header registers 2818 / 2828 are valid.

[0192] The two streams 2810 / 2820 share a pair of independent L2 interfaces 2830: L2 interface A (IFA) 2833 and L2 interface B (IFB) 2834. For an aggregate bandwidth of 1024 bits / cycle, each L2 interface communicates directly with the L2 controller 130 via the corresponding bus 147 / 149. Figure 1 It provides a throughput of 512 bits per cycle. The L2 interface uses a credit-based Multicore Bus Architecture (MBA) protocol. The MBA protocol is described in more detail in U.S. Patent 9,904,645, "Multicore Bus Architecture with Non-Blocking HighPerformance Transaction Credit System," which is incorporated herein by reference. The L2 controller allocates a pool of command credits to each interface. As described in more detail herein, this pool has sufficient credits to allow each interface to send enough requests to obtain adequate read-return bandwidth when reading from L2 RAM, L2 cache, and the Multicore Shared Memory Controller (MSMC) memory.

[0193] To maximize performance, in this example, both flows can use both L2 interfaces, allowing a single flow to send peak command rates of two requests / cycles. Each interface preferentially uses one flow over the other, but this preference changes dynamically for each request. IFA 2833 and IFB 2834 consistently preferentialize opposite flows; when IFA 2833 preferentializes flow 0, IFB 2834 preferentializes flow 1, and vice versa.

[0194] The corresponding arbitrators 2831 / 2832 preceding each corresponding interface 2833 / 2834 apply the following basic protocol on each cycle with available credit. Arbitrator 2831 / 2832 checks if the preferred flow has a command ready to be sent. If so, arbitrator 2831 / 2832 selects that command. Arbitrator 2831 / 2832 then checks if the alternative flow has at least two requests or one command ready to be sent and has no credit. If so, arbitrator 2831 / 2832 pulls the command from the alternative flow. If either interface issues a command, the annotations of the preferred and alternative flows are swapped for the next request. Using this algorithm, the two interfaces can dispatch requests as quickly as possible while maintaining fairness between the two flows. The first rule ensures that each flow can send requests on each cycle with available credit. The second rule provides a mechanism for the first flow to borrow the interface of the other flow when the second interface is idle. The third rule expands the bandwidth requirements for each flow across the two interfaces, ensuring that neither interface becomes a bottleneck.

[0195] The corresponding coarse-grained rotators 2835 / 2836 enable the streaming engine 125 to support a transposed matrix addressing mode. In this mode, the streaming engine 125 swaps the two innermost dimensions of the multidimensional loop to access the array column-by-column rather than row-by-row. The corresponding rotators 2835 / 2836 are not architecturally visible.

[0196] Figure 29 This section describes the example stream template register 2900. The stream definition template provides the complete structure of a stream containing data. Iteration counts and dimensions provide most of this structure, while various identifiers provide the remaining details. In this example, a single stream template 2900 is defined for all streams containing data. All stream types supported by the stream engine are covered by template 2900. The stream engine supports six levels of nested loops for addressing elements in the stream. Most fields in stream template 2900 directly map to parameters in the algorithm. The numbers on the fields are bits within a 256-bit vector. Table 7 shows the stream field definitions for the stream template.

[0197] Table 7

[0198] field name Figure 29 Figure label describe Size / Number of digits ICNT0 2901 Iteration count of loop 0 32 ICNT1 2902 Iteration count of loop 1 32 ICNT2 2903 Iteration count of loop 2 32 ICNT3 2904 Iteration count of loop 3 32 ICNT4 2905 Iteration count of loop 4 32 ICNT5 2906 Iteration count of loop 5 32 DIM1 2911 Signed dimension of cycle 1 32 DIM2 2912 Signed dimension of loop 2 32 DIM3 2913 Signed dimensions of cycle 3 32 DIM4 2914 Signed dimensions of cycle 4 32 DIM5 2915 Signed dimensions of cycle 5 32 FLAGS 2921 Stream modifier identifier 64

[0199] Loop 0 is the innermost loop, and loop 5 is the outermost loop. In the current example, DIM0 is equal to ELEM_BYTES, which physically defines continuous data. Therefore, stream template register 2900 does not define DIM0. Stream engine 125 interprets iteration counts as unsigned integers and dimensions as unscaled signed integers. A zero iteration count at any level (ICNT0, ICNT1, ICNT2, ICNT3, ICNT4, or ICNT5) indicates an empty stream. Each iteration count must be at least 1 to define a valid stream. The templates described above specify the type of elements, the length of the stream, and the dimensions. Stream instructions specify the start address, for example, by specifying the scalar register in file 211 that stores the start address. Therefore, a program can open multiple streams using the same template but with different registers storing the start address.

[0200] Figure 30 illustrate Figure 29 The example shown is a subfield definition of identifier field 2921. Figure 30 As shown, the identifier field 2921 is 6 bytes or 48 bits. Figure 30 The table shows the number of bits in each field. Table 8 shows the definitions of these fields.

[0201] Table 8

[0202]

[0203] The ELTYPE field 3001 defines the data type of the elements in the stream. The four-bit encoding of this ELTYPE field 3001 is defined as shown in Table 9.

[0204] Table 9

[0205]

[0206]

[0207] The real / complex number type determines whether the streaming engine treats each element as either a real number or two parts of a complex number (real / imaginary part or magnitude / angle), and also specifies whether the two parts of a complex number are interchanged. Complex number types have a total element size that is twice the size of their child elements. Otherwise, the child element size is equal to the total element size.

[0208] The size of a child element is determined by type promotion and vector channel width. For example, when a stream request is type promoted, a 16-bit child element is promoted to a 32-bit or 64-bit child element. Since core 110 lists vectors in little-endian byte order, when processing unit core 110 ( Figure 1 When operating in big-endian byte order mode, the vector channel width is important.

[0209] The total element size specifies the smallest granularity of the stream, which determines the number of bytes the stream extracts in each iteration of the innermost loop. The stream reads elements in ascending or descending order. Therefore, the innermost dimension of the stream spans 0 x the total element size in bytes.

[0210] The TRANSPOSE field 3002 determines whether the streaming engine accesses the stream in a transposed order. Transposing the order swaps the two internal addressing levels. The TRANSPOSE field 3002 also indicates the granularity used to transpose the stream. The three bits of the TRANSPOSE field 3002 are encoded as shown in Table 10 for normal 2D operations.

[0211] Table 10

[0212]

[0213]

[0214] The streaming engine 128 can transpose data elements at a granularity different from the element size, thus allowing programs to extract multiple columns of elements from each row. The transpose granularity cannot be smaller than the element size. The TRANSPOSE field 3002 interacts with the DIMFMT field 3009 in a manner further described below.

[0215] The PROMOTE field 3003 controls whether the flow engine promotes child elements in the flow and the type of promotion. When enabled, the flow engine 125 promotes types in powers of 2. The three-bit encoding of the PROMOTE field 3003 is defined as shown in Table 11.

[0216] Table 11

[0217]

[0218] When PROMOTE is 000, it corresponds to 1x promotion; each child element remains unchanged and occupies a vector channel with a width equal to the size specified by ELTYPE. When PROMOTE is 001, it corresponds to 2x promotion and zero extension; each child element is treated as an unsigned integer and zero-extends to a vector channel twice the width specified by ELTYPE. 2x promotion is invalid for 64-bit initial child element sizes. When PROMOTE is 010, it corresponds to 4x promotion and zero extension; each child element is treated as an unsigned integer and zero-extends to a vector channel four times the width specified by ELTYPE. 4x promotion is invalid for 32-bit or 64-bit initial child element sizes.

[0219] When PROMOTE is 011, corresponding to 8x promotion and zero expansion, each child element is treated as an unsigned integer and zero-expanded to eight times the width of the vector channel specified by ELTYPE. 8x promotion is invalid for initial child element sizes of 16-bit, 32-bit, or 64-bit. When PROMOTE is 101, corresponding to 2x promotion and sign expansion, each child element is treated as a signed integer and sign-expanded to twice the width of the vector channel specified by ELTYPE. 2x promotion is invalid for initial child element sizes of 64-bit.

[0220] When PROMOTE is 110, corresponding to 4x promotion and sign extension, each child element is treated as a signed integer and sign-extended to a vector channel four times the width specified by ELTYPE. 4x promotion is invalid for initial child element sizes of 32-bit or 64-bit. When PROMOTE is 111, corresponding to 8x promotion and zero extension, each child element is treated as a signed integer and sign-extended to a vector channel eight times the width specified by ELTYPE. 8x promotion is invalid for initial child element sizes of 16-bit, 32-bit, or 64-bit.

[0221] The VECLEN field 3004 defines the stream vector length of the stream in bytes. The stream engine 125 breaks the stream down into groups of elements of length VECLEN bytes. The encoding of the three bits of the VECLEN field 3004 is defined as shown in Table 12. VECLEN cannot be less than the product of the element size in bytes and the repetition factor. As shown in Table 11, the maximum VECLEN of 64 bytes is equal to the preferred vector size of the vector data path side B 116. When the VECLEN is shorter than the native vector width of the processing unit core 110, the stream engine 125 fills in additional channels in the vector provided to the processing unit core 110. The GRDUP field 3006 determines the type of filling. The VECLEN field 3004 interacts with the ELDUP field 3005 and the GRDUP field 3006 in the manner detailed below.

[0222] Table 12

[0223] VECLEN Flow vector length 000 1 byte 001 2 bytes 010 4 bytes 011 8 bytes 100 16 bytes 101 32 bytes 110 64 bytes 111 reserve

[0224] The ELDUP field 3005 specifies the number of times each element is repeated. The element size multiplied by the number of element repetitions cannot exceed 64 bytes. The encoding of the three bits of the ELDUP field 3005 is defined as shown in Table 13. The ELDUP field 3005 interacts with the VECLEN field 3004 and the GRDUP field 3006 in the manner detailed below. The nature of the relationship between the allowed element size, the element repetition factor, and the destination vector length requires that, after the repetition is completed, the repeated elements overflowing the first destination register fill an integer number of destination registers. The data in the additional destination registers is ultimately supplied to the corresponding stream header registers 2818 / 2828. After the repetition of the first data element is completed, the next data element is rotated down to the least significant bit of the source register 3100, thus discarding the first data element. This process is then repeated for the new data element.

[0225] Table 13

[0226] ELDUP Repeat factor 000 No repetition 001 2 times 010 4 times 011 8 times 100 16 times 101 32 times 110 64 times 111 reserve

[0227] GRDUP bit 3006 determines whether group repeat is enabled. If GRDUP bit 3006 is 0, group repeat is disabled. If GRDUP bit 3006 is 1, group repeat is enabled. When enabled by GRDUP bit 3006, streaming engine 125 repeats a group of elements to fill the vector width. VECLEN field 3004 defines the length of the group to be copied. When VECLEN field 3004 is less than the vector length of processing unit core 110 and GRDUP bit 3006 enables group repeat, streaming engine 125 fills additional channels with additional copies of the streaming vector (see [link to relevant documentation]). Figure 21 and Figure 22Because the stream vector length and the vector length of the processing unit core 110 are integer powers of 2, group repetition produces an integer number of duplicate copies. Note that GRDUP and VECLEN do not specify the number of repetitions. The number of repetitions performed is based on the ratio of VECLEN to the native vector length (64 bytes / 512 bits in this example).

[0228] The GRDUP field 3006 specifies how the streaming engine 125 pads the streaming vector to the vector length of the processing unit core 110 for the bits following the VECLEN length. When the GRDUP bit 3006 is 0, the streaming engine 125 fills the extra channels with zeros and marks the extra vector channels as invalid. When the GRDUP bit 3006 is 1, the streaming engine 125 fills the extra channels with a copy of the element group in each streaming vector. Setting the GRDUP bit 3006 to 1 has no effect when VECLEN is set to the native vector width of the processing unit core 110. VECLEN must be at least as large as the product of ELEM_BYTES and the element repetition factor ELDUP. Therefore, VECLEN cannot be used to separate elements or the number of element repetition factors.

[0229] Group repeat operates on the destination vector size. When the product of the element size ELEM_BYTES and the element repeat factor ELDUP is equal to or greater than the destination vector width, group repeat does not change the supplied data. In this case, the state of GRDUP bit 3006 and VECLEN field 3004 has no effect on the supplied data.

[0230] The following set of examples illustrates the interaction between VECLEN and GRDUP. Each of the following examples shows how the streaming engine maps a stream to a vector of different sizes across different stream vector lengths and vector data path sides B116. The stream in this example consists of 29 elements (E0 to E28) of 64 bits / 8 bytes. This stream can be a linear stream of 29 elements or an inner loop of 29 elements. These tables illustrate, for example... Figure 21 The eight-byte channel is shown. Each specified vector is stored sequentially in the corresponding stream header register 2818 / 2828.

[0231] Table 14 illustrates how the example stream is mapped to bits within a 64-byte processor vector when VECLEN is 64 bytes. As shown in Table 14, the stream is extended across four vectors. As previously mentioned, channels extended outside the stream within vector 4 are zero-padded. When the size of VECLEN is equal to the native vector length, the value of GRDUP is irrelevant because repetition is impossible for such a VECLEN.

[0232] Table 14

[0233]

[0234] Except that VECLEN is 32 bytes, Table 15 shows the same parameters as those shown in Table 14.

[0235] Group repetition is disabled (GRDUP=0). The twenty-nine elements of the stream are distributed in eight vectors across channels 0 through 3. The additional channels 4 through 7 in vectors 1 through 7 are zero-filled. In vector 8, channel 1 has the stream element (E28), and the other channels are zero-filled.

[0236] Table 15

[0237]

[0238] Except that VECLEN is sixteen bytes, Table 16 shows the same parameters as shown in Table 14. Group repeat is disabled (GRDUP = 0). The twenty-nine elements of the stream are distributed in fifteen vectors across channels 0 and 1. The additional channels 2 through 7 in vectors 1-14 are zero-padded. In vector 15, channel 1 has the stream element (E28), and the other channels are zero-padded.

[0239] Table 16

[0240]

[0241]

[0242] Except that VECLEN is eight bytes, Table 17 shows the same parameters as shown in Table 14. Group repeat is disabled (GRDUP = 0). The twenty-nine elements of the stream appear as twenty-nine vectors in channel 0. The extra channels 1-7 in vectors 1-29 are zero-padded.

[0243] Table 17

[0244]

[0245]

[0246] Table 18 shows the same parameters as shown in Table 15, except that VECLEN is thirty-two bytes and group repeat is enabled (GRDUP=1). The twenty-nine elements of the stream are distributed in eight vectors across channels 0-7. Each vector 1-7 includes four repeated elements. The repeat factor (2) is a result of the fact that VECLEN (32 bytes) is half the native vector length of 64 bytes. In vector 8, channel 0 has the stream element (E28), and channels 1-3 are zero-padded. Channels 4-7 of vector 9 repeat this pattern.

[0247] Table 18

[0248]

[0249] Table 19 shows the same parameters as shown in Table 16, except that VECLEN is sixteen bytes. Group repetition is enabled (GRDUP = 1). The twenty-nine elements of the stream are distributed across channels 0-7 in fifteen vectors. Each vector 1-7 includes two elements repeated four times. The repetition factor (4) is a result of VECLEN (16 bytes), which is one-quarter of the native vector length of 64 bytes. In vector 15, channel 0 has the stream element (E28), and channel 1 is zero-padded. This pattern is repeated in channels 2 and 3, channels 4 and 5, and channels 6 and 7 of vector 15.

[0250] Table 19

[0251]

[0252]

[0253] Except that VECLEN is eight bytes, Table 20 shows the same parameters as shown in Table 17. Group repetition is enabled (GRDUP = 1). The twenty-nine elements of the stream appear as twenty-nine vectors on channels 0 through 7. Each vector includes one element repeated eight times. The repetition factor (8) is a result of VECLEN (8 bytes) being one-eighth of the native vector length of 64 bytes. Therefore, each channel is identical in vectors 1-29.

[0254] Table 20

[0255]

[0256]

[0257] Figure 31 The description is included Figure 19 Vector length mask / group repeat block 2025 within formatter block 1903 (see formatter block 1903) Figure 20 Example of input register 3100 receiving data from... Figure 20The vector input of element repeating block 2024 is shown. Input register 3100 comprises 64 bytes arranged in 64 one-byte blocks, namely bytes 0 to 63. Note that the length of bytes 0 to 63 is equal to the minimum value of ELEM_BYTES. A set of multiplexers 3101 to 3163 couples the input bytes from source register 3100 to output register 3170. Each corresponding multiplexer 3101 to 3163 supplies input to the corresponding byte 1 to byte 63 of output register 3170. Not all input bytes 0 to 63 of input register 3100 are coupled to each multiplexer 3101 to 3163. Note that no multiplexer supplies byte 0 of output register 3170. In this example, byte 0 of output register 3170 is supplied by byte 0 of input register 3100.

[0258] Multiplexers 3101 to 3163 are controlled by multiplexer-controlled encoder 3180. Multiplexer-controlled encoder 3180 receives the ELEM_BYTES, VECLEN, and GRDUP input signals and generates corresponding control signals for multiplexers 3101 to 3163. ELEM_BYTES and ELDUP are supplied to multiplexer-controlled encoder 3180 to check that VECLEN is at least as large as the product of ELEM_BYTES and ELDUP. In operation, multiplexer-controlled encoder 3180 controls multiplexers 3101 to 3163 to transfer the least significant bit equal to the number of VECLEN bits from input register 3100 to output register 3170. If GRDUP = 0, indicating that group repeat is disabled, multiplexer-controlled encoder 3180 controls the remaining multiplexers 3101 to 3163 to transfer zeros to all bits in the remaining most significant channel of output register 3170. If GRDUP = 1, indicating that group repeat is enabled, the multiplexer-controlled encoder 3180 controls the remaining multiplexers 3101 to 3163 to repeat the least significant bits of the number of VECLENs in the input register 3100 into the most significant channel of the output register 3170. This control is similar to the element repeat control described above and fills the output register 3170 with the first vector. For the next vector, the data in the input register 3100 is rotated down by VECLEN, discarding the previous least significant bits of VECLEN. Formatter 1903 ( Figure 19 The rate at which data moves within the processing unit core 110 is determined by the processing unit core 110. Figure 1 The rate at which data is consumed is set via the stream read and forward commands described below. Group repeat formatting will repeat as long as the stream contains additional data elements.

[0259] Element-wise repeat (ELDUP) and group-wise repeat (GRUDP) are independent. It should be noted that these features include independent specifications and parameter settings. Therefore, element-wise repeat and group-wise repeat can be used together or separately. Given how these are specified, element-wise repeat allows overflow to the next vector, while group-wise repeat does not.

[0260] Refer again Figure 30 The DECIM field 3007 controls the downsampling of data elements in the corresponding stream. The stream engine 125 removes data elements from the stream after storing them in the corresponding stream header registers 2818 / 2828 to present them to the requesting functional unit. Downsampling removes all data elements, not just sub-elements. The DECIM field 3007 is defined as listed in Table 21.

[0261] Table 21

[0262] DECIM Downsampling factor 00 No downsampling 01 2 times 10 4 times 11 reserve

[0263] If DECIM field 3007 equals 00, no downsampling occurs. Data elements are passed unchanged to the corresponding stream head registers 2818 / 2828. If DECIM field 3007 equals 01, 2:1 downsampling occurs. Stream engine 125 removes odd-numbered elements from the data stream after storing them in stream head registers 2818 / 2828. Constraints in the formatted network require 2:1 downsampling when the data is boosted at least 2x (PROMOTE cannot be 000), ICNT0 must be a multiple of 2, and the total vector length (VECLEN) must be large enough to preserve repeating elements in a single boost. For transposed streams (TRANSPOSE ≠ 0), the transpose granularity must be at least twice the size of the element before boosting (in bytes). If DECIM field 3007 equals 10, 4:1 downsampling occurs. The streaming engine 125 retains every three data elements, removing three elements from the data stream after storing them in the stream head registers 2818 / 2828. Constraints in the formatted network require a 4:1 downsampling (PROMOTE cannot be 000, 001, or 101) when the data is boosted at least 4x, ICNT0 must be a multiple of 4, and the total vector length (VECLEN) must be large enough to preserve repeating elements in a single boost. For transposed streams (TRANSPOSE ≠ 0), in one example, downsampling removes columns but not rows. Therefore, in these cases, for 2:1 downsampling, the transpose granularity must be at least twice the size of the element before boosting (in bytes) (GRANULE ≥ 2 × ELEM_BYTES), and for 4:1 downsampling, the transpose granularity must be at least four times the size of the element before boosting (in bytes) (GRANULE ≥ 4 × ELEM_BYTES).

[0264] The throttling field 3008 controls the level of activity the flow engine extracts before processing unit core 110. The two bits of this field are encoded as shown in Table 22.

[0265] Table 22

[0266]

[0267]

[0268] THROTTLE does not change the meaning of the stream and is only used as a hint. The streaming engine can ignore this field. For the correctness of the program, the program should not rely on specific throttling behavior, as the architecture does not specify precise throttling behavior. THROTTLE allows the programmer to provide hints to the hardware about the program's behavior. By default, the streaming engine attempts to hide as much latency as possible before processing unit core 110 (equivalent to THROTTLE=11) while providing full streaming throughput to processing unit core 110. While some applications require this throughput level, such throughput can lead to other undesirable system-level behaviors. For example, the streaming engine discards all fetched data across context switches. Therefore, in systems with a large number of context switches, aggressively fetching in advance can lead to wasted bandwidth.

[0269] The DIMFMT field 3009 defines which of the following loop count fields of the Stream Template Register 2900—ICNT0 2901, ICNT1 2902, ICNT2 2903, ICNT3 2904, ICNT4 2905, and ICNT5 2906—which of the loop dimension fields—DIM1 2911, DIM2 2912, DIM3 2913, DIM4 2914, and DIM5 2915—and which of the addressing mode fields—AM0 3013, AM1 3014, AM2 3015, AM3 3016, AM4 3017, and AM5 3018 (part of the FLAGS field 2921)—is active for a given stream. Table 23 lists the active loops for the various values ​​of the DIMFMT field 3009. Each active loop count must be at least 1, and the outer active loop count must be greater than 1.

[0270] Table 23

[0271]

[0272] DIR bit 3010 determines the fetch direction of the inner loop (loop 0). If DIR bit 3010 is 0, loop 0 fetches in the forward direction toward increasing address. If DIR bit 3010 is 1, loop 0 fetches in the backward direction toward decreasing address. The fetch direction of other loops is determined by the sign of the corresponding loop dimensions DIM1, DIM2, DIM3, DIM4, and DIM5.

[0273] The CBK0 field 3011 and CBK1 field 3012 control the loop block size after loop addressing is selected. This article describes how the loop block size is determined.

[0274] AM0 field 3013, AM1 field 3014, AM2 field 3015, AM3 field 3016, AM4 field 3017, and AM5 field 3018 control the addressing mode of the corresponding loop, thus allowing the addressing mode to be specified independently for each loop. Each of AM0 field 3013, AM1 field 3014, AM2 field 3015, AM3 field 3016, AM4 field 3017, and AM5 field 3018 is three bits and is decoded as listed in Table 24.

[0275] Table 24

[0276] AMx field meaning 00 Linear addressing 01 The size of the loop addressing block is set by CBK0. 10 The size of the loop addressing block is set by CBK0 + CBK1 + 1 11 reserve

[0277] In linear addressing, the address proceeds arithmetically, either forward or backward. In loop addressing, the address remains within a defined address block. After reaching the end of the loop address block, the address wraps around to the beginning limit of the block. Loop addressing blocks are limited to 2 bytes. N A number of addresses are given, where N is an integer. Loop address arithmetic can be operated on by cutting the carry chain between bits and disallowing a selected number of most significant bits from being changed. Therefore, arithmetic beyond the end of the loop block only changes the least significant bits. The block size is set as listed in Table 25.

[0278] Table 25

[0279]

[0280]

[0281] In this example, the loop block size is set by a number encoded with CBK0 (first loop address mode 01) or a number encoded with CBK0+CBK1+1 (second loop address mode 10). For example, in the first loop address mode, the loop address block size can range from 512 bytes to 16M bytes. For the second loop address mode, the loop address block size can range from 1K bytes to 64G bytes. Therefore, the encoded block size is 2(B+9) bytes, where B is the encoded block number, which is CBK0 for the first block size (AMx is 01) and CBK0+CBK1+1 for the second block size (AMx is 10).

[0282] Processing unit 110 ( Figure 1 ) Stream Engine 125 ( Figure 28 The stream is exposed to the program. The program uses SEOPEN and SECLOSE to start and end the stream. SEOPEN opens a new stream, and the stream remains open until it is explicitly terminated by SECLOSE or replaced by a new stream via SEOPEN. The SEOPEN instruction specifies the stream number that indicates stream 0 or stream 1 to be opened. The SEOPEN instruction specifies the data register that stores the starting address of the stream. The SEOPEN instruction also specifies the stream template register that stores the stream template as described above. The arguments of the SEOPEN instruction are listed in Table 26.

[0283] Table 26

[0284] Variable describe Stream start address register Scalar register at the start address of the storage stream Flow number Stream 0 or Stream 1 Stream Template Register Vector register storing stream template data

[0285] In this example, the stream start address register is a general-purpose scalar register file 211 ( Figure 2 The SEOPEN instruction can be encoded via example instruction 1300 (in the registers). Figure 13 )'src1 field 1303 ( Figure 13 The SEOPEN instruction specifies the stream start address register. The SEOPEN instruction specifies stream 0 or stream 1 in its opcode. In this example, the stream template register is a vector register in the general-purpose vector register file 221. The SEOPEN instruction can be executed via the src2 / cst field 1302 ( Figure 13 The SEOPEN instruction specifies the stream template register. If the specified stream is active, the SEOPEN instruction closes the previous stream and replaces it with the specified stream.

[0286] SECLOSE explicitly marks a stream as inactive, flushing out any incomplete activity. Any further reference to that stream triggers an exception. SECLOSE also allows a program to terminate one or both streams prematurely.

[0287] The SESAVE command saves the state of a specified stream by capturing enough state information to restart the stream in the future. The SERSTR command restores a previously saved stream. The SESAVE command saves stream metadata but does not save any stream data. The stream responds to the SERSTR command by retrieving its stream data.

[0288] Each stream can be in one of three states: inactive, active, or frozen after reset. Both streams begin in an inactive state. Opening a stream moves it to the active state. Closing a stream returns it to the inactive state. Streams typically do not undergo further state transitions in the absence of interruptions or exceptions. To handle interruptions, the streaming engine adds a third state: frozen. The frozen state represents an interrupted active stream.

[0289] In this example, four bits (two bits per stream) define the state of the two streams. One bit for each stream resides within the stream engine, while the other bit resides within processor core 110. The stream engine internally tracks whether each stream maintains the parameter set associated with the active stream. This bit distinguishes between inactive and non-inactive streams. Processor core 110 uses dedicated bits in the Task Status Register (TSR) for each stream to separately track the state of each stream: TSR.SE0 for stream 0 and TSR.SE1 for stream 1. These bits distinguish between active and inactive streams.

[0290] Opening a stream moves it to the active state. Closing a stream moves it to the inactive state. If a program opens a new stream on top of a frozen stream, the new stream replaces the old one, and the streaming engine discards the contents of the previous stream. The streaming engine supports opening new streams on the currently active stream. The streaming engine discards the contents of the previous stream, flushes the pipeline, and begins fetching data for the newly opened stream. Once the data has been returned, the data to the processor becomes valid. If a program closes a stream that has already been closed, nothing happens. If a program closes an open or frozen stream, the streaming engine discards all state associated with the stream, clears the internal stream activation bit, and clears counters, register flags, and addressing. Closing a stream serves two purposes. Closing an active stream allows a program to specifically declare the stream and no longer need the resources associated with it. Closing a frozen stream also allows context switching codes to clear the state of the frozen stream, making it invisible to other tasks.

[0291] As mentioned above, there are cases where some data within stream holding registers 2818 or 2828 is invalid. This can occur at the end of the inner loop when the number of stream elements is less than the size of the corresponding stream holding register 2818 / 2828, or when the number of remaining stream elements is less than the number of channels defined by VECLEN. For times not at the end of the inner loop, if VECLEN is less than the width of stream holding registers 2818 / 2828 and GRDUP is disabled, channels exceeding VECLEN in stream holding registers 2818 / 2828 are invalid.

[0292] Refer again Figure 28 In this example, the streaming engine 125 also includes valid registers 2819 and 2829. Valid register 2819 indicates a valid channel in the streaming head register 2818. Valid register 2829 indicates a valid channel in the streaming head register 2828. Each valid register 2819 / 2829 includes one bit for each minimum ELEM_BYTES channel within its corresponding streaming head register 2818 / 2828. In this example, the minimum ELEM_BYTES is 1 byte. The preferred data path width of the processor 100 and the data length of the streaming head registers 2818 / 2828 are 64 bytes (512 bits). Valid registers 2819 / 2829 accordingly have a 64-bit data width. Each bit in the valid registers 2819 / 2829 indicates whether the corresponding byte in the streaming head registers 2818 / 2828 is valid. In this example, 0 indicates that the corresponding byte in the streaming head register is invalid, and 1 indicates that the corresponding byte is valid.

[0293] In this example, after reading the corresponding one of the stream header registers 2818 / 2828 and transferring the data to the request function unit, invalid / valid data in the corresponding valid registers 2819 / 2829 is automatically transferred to the assertion register file 234 corresponding to the specific stream. Figure 2 The data registers within the assertion register. In this example, the valid data for stream 0 is stored in assertion register P0, and the valid data for stream 1 is stored in assertion register P1.

[0294] Valid data stored in assertion register file 234 can be used in various ways. The functional unit can combine vector stream data with another set of vectors and then use the valid data indicator as a mask to store the combined data in memory. This allows the same processing procedure to be used for the end of loop data as for the case where all channels are invalid, avoiding the storage of invalid data. The valid indicator stored in assertion register file 234 can be used as a mask or operand in other processing procedures. P unit 246 ( Figure 2It can have an instruction (BITCNT) that counts the number of 1s in the assertion register, which can be used to determine the count of valid data elements from the assertion register.

[0295] Figure 32 This description is used to generate the data stored in valid register 2819. Figure 28 Example hardware 3200 with valid / invalid indication in ) . Figure 32 This describes the hardware for stream 0; stream 1 includes its corresponding hardware. Each time, in stream header register 2818 (... Figure 28 When updating data in the decoder, hardware 3200 operates to generate a valid word. The first input ELTYPE is supplied to decoder 3201. Decoder 3201 produces an output TOTAL ELEMENT SIZE corresponding to the minimum data size based on the element size ELEM_BYTES and whether the element is real or complex. The meanings of the various encodings of ELTYPE are shown in Table 9. Table 27 shows example outputs (in bytes) of decoder 3201 for various ELTYPE encodings. Note that Table 9 lists bits, and Table 27 lists bytes. As shown in Table 27, if the element is real, the TOTAL ELEMENT SIZE is 1, 2, 4, or 8 bytes, and if the element is complex, the TOTAL ELEMENT SIZE is 2, 4, 8, or 16 bytes.

[0296] Table 27

[0297]

[0298] The second input, PROMOTE, is supplied to decoder 3202. Decoder 3202 produces an output boost factor corresponding to the PROMOTE input. The meanings of the various encodings of PROMOTE are shown in Table 28, which represents example outputs (in bytes) of decoder 3201 for various PROMOTE encodings. The difference in extension type (zero extension or sign extension) is irrelevant to decoder 3202.

[0299] Table 28

[0300] PROMOTE Enhancement Factor 000 1 001 2 010 4 011 8 100 reserve 101 2 110 4 111 8

[0301] The outputs of decoders 3201 and 3202 are supplied to multiplier 3203. The product produced by multiplier 3203 is the channel size corresponding to the total amount size and the boost factor. Because the boost factor is an integer power of 2 (2^3 + ... NTherefore, multiplication can be achieved by shifting the corresponding TOTAL ELEMENT SIZE. For example, no shift is needed for a boost factor of 1, shift one bit for a boost factor of 2, shift two bits for a boost factor of 4, and shift three bits for a boost factor of 8.

[0302] Channel numbering unit 3204 receives the vector length VECLEN and LANE SIZE and generates a channel number. Table 29 shows an example of decoding for channel numbering with a channel size in bytes and a vector length VECLEN.

[0303] Table 29

[0304]

[0305] As mentioned earlier, VECLEN must be greater than or equal to the product of the element size and the repeatability factor. As shown in Table 29, VECLEN must also be greater than or equal to the product of the element size and the promotion factor. This means that VECLEN must be large enough to ensure that an element cannot be associated with a type-promoted block 2022 (…). Figure 20 The resulting extended separation. Cells marked with "-" below the diagonal in Table 29 indicate unauthorized combinations of parameters.

[0306] The channel number output of unit 3204 is used as one input to the channel / remaining element control word unit 3211. The second input comes from multiplexer 3212. Multiplexer 3212 receives cycle 0 input and cycle 1 input. Cycle 0 input and cycle 1 input represent the number of remaining elements in the current iteration of the corresponding cycle.

[0307] Figure 33 illustrate Figure 28The diagram shows a partial schematic of the address generator 2811. The address generator 2811 forms the address used to extract the next element in the defined stream of the corresponding stream engine. The start address register 3301 stores the start address of the data stream. As described above, in this example, the start address register 3301 is a scalar register specified in the global scalar register file 211 by the SEOPEN instruction that opens the corresponding stream. The start address can be copied from the specified scalar register and stored locally at the corresponding address generator 2811 / 2821 via control logic contained within the address generator 2811. The first loop of the stream employs a loop 0 counter register 3311, an adder 3312, a multiplier 3313, and a comparator 3314. The loop 0 counter register 3311 stores a working copy of the iteration count of the first loop (loop 0). For each iteration of loop 0, the adder 3312 (e.g., triggered by the next address signal) increments the loop count by 1, and the loop count is stored back in the loop 0 counter register 3311. Multiplier 3313 multiplies the current loop count by the quantity ELEM_BYTES. ELEM_BYTES is the size (in bytes) of each data element in loop 0. Loop 0 traverses physically contiguous data elements in memory with an iteration step of ELEM_BYTES.

[0308] Comparator 3314 compares the count stored in loop 0 counter register 3311 (after being incremented by adder 3313) with the count from the corresponding stream template register 2900. Figure 29 ICNT0 2901 ( Figure 29 The values ​​of the adder 3312 and the comparator 3314 are compared. When the output of the adder 3312 equals the value of ICNT0 2901 in the stream template register 2900, the iteration of loop 0 is complete. The comparator 3314 generates an activation loop 0 end signal. The loop 0 counter register 3311 is reset to 0 and triggers the iteration of the next higher loop (in this case, loop 1).

[0309] Loops used for higher cycles (cycle 1, cycle 2, cycle 3, cycle 4, and cycle 5) are similar to Figure 33 As shown in the diagram. Each loop includes a corresponding working loop counter register, an adder, a multiplier, and a comparator. The adder for each loop is triggered by the loop end signal of the previous loop. The second input of each multiplier is the corresponding dimensions DIM1, DIM2, DIM3, DIM4, and DIM5 from the corresponding stream template. The comparator for each loop compares the working loop register count with the corresponding iteration values ​​ICNT1, ICNT2, ICNT3, ICNT4, and ICNT5 of the corresponding stream template register 2900. The loop end signal generates the iteration for the next higher loop. The loop end signal from loop 5 terminates the stream.

[0310] Figure 33 The generation of the loop 0 count is also explained. The loop 0 count is equal to the updated data stored in the corresponding working count register 3311. The loop 0 count is updated with each change to the working loop 0 count register 3311. The loop counts for higher loops (loop 1, loop 2, loop 3, loop 4, and loop 5) are generated similarly.

[0311] Figure 33 The generation of the loop 0 address is also explained. The loop 0 address is equal to the data output by multiplier 3313. The loop 0 address is updated each time the working loop 0 counter register 3311 changes. Similar loops for loop 1, loop 2, loop 3, loop 4, and loop 5 generate their corresponding loop addresses. In this example, the loop 0 counter register 3311 and other loop counter registers are implemented as up-count registers. In another example, the initialization and compare operations are implemented as down-count circuits.

[0312] Refer again Figure 32 The value of the loop down count (such as loop 0 / ) is given by Loopx / = ICNTx - Loopx(loop x). Therefore, the loop down count is the initial iteration count specified in the stream template register and the value of the loop down count. Figure 33 The difference between the resulting cyclic upward counts is shown.

[0313] Channel / Remaining Element Control Word Unit 3211 ( Figure 32 The control word 3213 is generated based on the channel number from channel numbering unit 3204 and the cyclic down-counting selected by multiplexer 3212. The control input to multiplexer 3212 is from... Figure 30 The TRANSPOSE signal in field 3002. If TRANSPOSE is disabled (“000”), multiplexer 3212 selects cycle 0 down to count cycle 0 / . For all other valid values ​​of TRANSPOSE (“001”, “010”, “011”, “100”, “101”, and “110”), multiplexer 3212 selects cycle 1 down to count cycle 1 / . The streaming engine maps the innermost dimension to consecutive channels in the vector. For normal streaming, this is cycle 0. For transposed streaming, this is cycle 1 because transposition swaps the two dimensions.

[0314] Channel / Remaining Element Control Word Unit 3211 generates control word 3213 as described below. Control word 3213 has a number of bits equal to the channel number from unit 3204. If the remaining element count of the selected cycle is greater than or equal to the channel number, all channels are valid. In this case, control word 3213 is all 1s, indicating that all channels within the vector length VECLEN are valid. If the remaining element count of the selected cycle is non-zero and less than the channel number, some channels are valid and some channels are invalid. Based on the above... Figure 21 and Figure 22 The described channel allocation assigns stream elements to channels starting with the least significant channel. In these cases, control word 3213 includes a number of least significant bits set to one, equal to the number of bits counted down the selected cycle. All other bits of control word 3213 are set to zero. Figure 32 In the example shown, the channel number is eight and there are five significant (1) least significant bits followed by three invalid (0) most significant bits, which corresponds to a cycle of five elements remaining in the last iteration.

[0315] Control word extension unit 3214 extends control word 3213 based on the value of the channel size (LANE SIZE). The extended control word includes one bit for each minimum-sized channel. In this example, the minimum stream element size, and therefore the minimum channel size, is one byte (8 bits). In this example, the size of holding registers 2818 / 2828 is equal to a vector size of 64 bytes (512 bits). Therefore, the extended control word has 64 bits, with one bit for each byte of the stream holding registers 2818 / 2828. This extended control word fills the corresponding valid registers 2819 and 2829 (…). Figure 28 The least significant bit of ).

[0316] For the case where VECLEN equals the vector length, the description is complete. The extended control word includes some bits for all positions within the corresponding valid registers 2819 / 2829. When VECLEN is not equal to the vector length, some additional considerations apply. When VECLEN is not equal to the vector length, the extended control word does not have enough bits to fill the corresponding valid registers 2819 / 2829. For example... Figure 32 As shown, the extended control word fills the least significant bit of the corresponding valid registers 2819 / 2829, thus providing valid / invalid bits for channels within the VECLEN width. An alternative mechanism is provided for channels exceeding the VECLEN width up to the data width of the stream header register 2818.

[0317] Still referencing Figure 32Multiplexer 3215 and group repeat unit 3216 are illustrated to provide the required additional valid / invalid bits. Referring to the description of VECLEN, if group repeat is not enabled (GRDUP = 0), the redundant channels are invalid. The first input of multiplexer 3215 is the INVALID0 signal, which includes a number of bits equal to VECLEN. When GRDUP = 0, multiplexer 3215 selects this input. Group repeat unit 3216 repeats this input to all redundant channels of stream head register 2818. Therefore, the most significant bit of valid register 2819 is set to zero, indicating that the corresponding byte in stream head register 2818 is invalid. This occurs in vectors 1-8 of the example shown in Table 15, vectors 1-15 of the example shown in Table 16, and vectors 1-29 of the example shown in Table 17.

[0318] In another example, multiplexer 3215 and group repeat block 3216 are replaced with something similar to Figure 31 The group repeat logic 2025 shown is the group repeat logic.

[0319] As mentioned earlier, if group repeat is enabled (GRDUP=1), then the flow header register 2818 ( Figure 28 The redundant channels are filled with copies of the least significant bits. The second input of multiplexer 3215 is an extended control word from control word extension unit 3214. Multiplexer 3215 selects this input when GRDUP = 1. Group repeat unit 3216 repeats this input to all redundant channels of stream head register 2818.

[0320] There are two possible outcomes. In one outcome, in most cases, all channels within the VECLEN are valid, and the bits from the control word extension unit 3214 are all 1. This occurs in vectors 1-7 of the group repeat example shown in Table 18 and vectors 1-14 of the group repeat example shown in Table 19. Under these conditions, all bits of the extended control word from the control word extension unit 3214 are 1, and all channels of the stream head register 2818 are valid. The group repeat unit 3216 therefore fills all redundant channels with 1. In another outcome, the number of remaining stream data elements is less than the channel number within the VECLEN. This occurs in vector 8 of the group repeat example shown in Table 18 and vector 15 of the group repeat example shown in Table 19. Under these conditions, some channels within the VECLEN are valid, and some are invalid. The group repeat unit 3216 fills the redundant channels with bits that have the same pattern as the extended control word bits. In either case, the redundant channels corresponding to the extended control bits are filled.

[0321] Still referencing Figure 32The diagram illustrates the boundary 3217 between the least significant bit and the most significant bit. The position of this boundary is set by the size of VECLEN relative to the size of the stream head register 2818.

[0322] Figure 34 This is a partial schematic diagram 3400 illustrating the encoding of the above-mentioned stream input operands. Figure 34 Instruction decoder 113 (see...) Figure 1 As part of the instruction control function unit 3420, the src1 field 1303 of an instruction is decoded to control the corresponding src1 input of the function unit 3420. These same or similar circuits are repeated for the src2 / cst field 1302 of the instruction control function unit 3420. Furthermore, these circuits are repeated for each instruction within an execution packet capable of using streaming data as operands for simultaneous scheduling.

[0323] The instruction decoder 113 receives the src1 field 1303 of the instruction. The opcode field 1304 and the unit field 1305 specify the corresponding functional unit 3420 and the function to be performed. In this example, the functional unit 3420 can be L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, or C unit 245. Figure 34 The relevant part of the instruction decoder 113 illustrated in the diagram decodes the src1 field 1303. Sub-decoder 3411 determines whether the src1 field 1303 is in the range 00000 to 01111. If so, sub-decoder 3411 supplies the corresponding register number to the global vector register file 231. In this example, the register number is the four least significant bits of the src1 field 1303. The global vector register file 231 retrieves the data stored in the register corresponding to the register number and supplies the data to the src1 input of functional unit 3420.

[0324] Sub-decoder 3412 determines whether the srcl field 1303 is within the range of 10000 to 10111. If so, sub-decoder 3412 supplies the corresponding register number to the corresponding local vector register file. If the instruction points to L2 unit 241 or S2 unit 242, the corresponding local vector register file is local vector register file 232. If the instruction points to M2 unit 243, N2 unit 244, or C unit 245, the corresponding local vector register file is local vector register file 233. In this example, the register number is the three least significant bits of the src1 field 1303. The corresponding local vector register files 232 / 233 retrieve the data stored in the register corresponding to the register number and supply the data to the src1 input of function unit 3420.

[0325] Sub-decoder 3413 determines whether srcl field 1303 is 11100. If so, sub-decoder 3413 supplies the stream 0 read signal to stream engine 125. Stream engine 125 then supplies the stream 0 data stored in holding register 2818 to the src1 input of function unit 3420.

[0326] Sub-decoder 3414 determines whether srcl field 1303 is 11101. If so, sub-decoder 3414 supplies a stream 0 read signal to stream engine 125. Stream engine 125 then supplies the stream 0 data stored in holding register 2818 to the src1 input of function unit 3420. Sub-decoder 3414 also supplies a forward signal to stream 0. As previously described, stream engine 125 forwards to store the next sequence vector of data elements of stream 0 in holding register 2818.

[0327] A stream 0 read signal supplied to the streaming engine 125 by sub-decoder 3413 or sub-decoder 3414 will trigger another data move. Based on such a stream 0 read signal, the streaming engine 125 supplies data stored in the valid register 2819 to the assertion register file 234 for storage. In this example, this is a predetermined data register within the assertion register file 234. In this example, data register P0 corresponds to stream 0.

[0328] Sub-decoder 3415 determines whether srcl field 1303 is 11110. If so, sub-decoder 3415 supplies the stream 1 read signal to stream engine 125. Stream engine 125 then supplies the stream 1 data stored in holding register 2828 to the src1 input of function unit 3420.

[0329] Sub-decoder 3416 determines whether the srcl field 1303 is 11111. If so, sub-decoder 3416 supplies a stream 1 read signal to stream engine 125. Stream engine 125 then supplies the stream 1 data stored in holding register 2828 to the src1 input of function unit 3420. Sub-decoder 3414 also supplies a forward signal to stream 1. As previously described, stream engine 125 forwards to store the next sequence vector of the data elements of stream 1 in holding register 2828.

[0330] A stream 1 read signal supplied to the streaming engine 125 by sub-decoder 3415 or sub-decoder 3416 will trigger another data move. Based on such a stream 1 read signal, the streaming engine 125 supplies data stored in the valid register 2829 to the assertion register file 234 for storage. In this example, this is a predetermined data register within the assertion register file 234. In this example, data register P1 corresponds to stream 1.

[0331] Similar circuitry is used to select the data supplied to the src2 input of functional unit 3402 in response to the bit encoding of src2 / cst field 1302. A constant input can be supplied to the src2 input of functional unit 3420 in the manner described above. If instruction decoder 113 generates a read signal for stream 0 from src1 field 1303 or src2 / cst field 1302, stream engine 125 supplies the data stored in valid register 2819 to assert register P0 of assert register file 234 for storage. If instruction decoder 113 generates a read signal for stream 1 from src1 field 1303 or src2 / cst field 1302, stream engine 125 supplies the data stored in valid register 2829 to assert register P1 of assert register file 234 for storage.

[0332] The exact number of instruction bits dedicated to operand specification, as well as the number of data registers and streams, are design choices. In particular, specification of a single global vector register file and omission of local vector register files are feasible. This example uses bit encoding of the input operand selection field to indicate stream reads and another bit encoding to indicate stream reads and to advance the stream.

[0333] Each time stream data is read, Figure 34 The processing illustrated in the diagram automatically transfers valid data to assertion register file 234. Unit P 246 can then use the transferred valid data to further compute metadata. The transferred valid data can also be used as a mask or operand for other operations performed by one or more of the B116 functional units on the vector data path side (including L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, and C unit 245). Many feasible complex logic operations exist that utilize this stream of valid data.

[0334] Figure 35 This is a partial schematic diagram 3500 illustrating another example configuration for selecting the operand source. In this example, the corresponding stream valid registers 2819 / 2829 do not need to be automatically loaded into the predetermined registers in the assertion register file 234. Instead, explicit instructions using P unit 246 are used to move the data. Figure 35 Explanation of a portion of instruction decoder 113 (see...) Figure 1 This decodes the src1 field 1303 of an instruction to control the corresponding src1 input of P unit 246. These same or similar circuits can be reused to control the src2 / cst field 1302 of P unit 246. Figure 13 ).

[0335] The instruction decoder 113 receives the instruction's SRCL field 1303. The opcode field 1304 and the unit field 1305 specify the P unit 246 and the function to be performed. Figure 35 The relevant part of the instruction decoder 113 illustrated in the diagram decodes the src1 field 1303. The sub-decoder 3511 determines whether the src1 field 1303 is in the range 00000 to 01111. If so, the sub-decoder 3511 supplies the corresponding register number to the global vector register file 231. In this example, this register number is the four least significant bits of the src1 field 1303. The global vector register file 231 retrieves the data stored in the register corresponding to the register number and supplies that data to the src1 input of the P unit 246.

[0336] Sub-decoder 3512 determines whether the srcl field 1303 is within the range of 10000 to 10111. If so, sub-decoder 3512 supplies the decoded register number to the assertion register file 234. In this example, the register number is the three least significant bits of the src1 field 1303. The assertion register file 234 retrieves the data stored in the register corresponding to the register number and supplies that data to the src1 input of the assertion unit 246.

[0337] Sub-decoder 3513 determines whether srcl field 1303 is 11100. If so, sub-decoder 3513 supplies a stream 0 valid read signal to stream engine 125. Stream engine 125 then supplies the valid data stored in valid register 2819 to src1 input of P unit 246.

[0338] Sub-decoder 3514 determines whether srcl field 1303 is 11101. If so, sub-decoder 3514 supplies a stream 1 valid read signal to stream engine 125. Stream engine 125 then supplies the stream 1 valid data stored in valid register 2829 to the src1 input of P unit 246.

[0339] The P-unit 246 instruction that uses stream valid registers 2819 / 2829 as operands can be any P-unit instruction previously described, such as NEG, BITCNT, RMBD, DECIMATE, EXPAND, AND, NAND, OR, NOR, and XOR.

[0340] The specific instructions mentioned above can be limited to unit P242. Therefore, Figure 34 and Figure 35The operations outlined in the document can be used together. If the functional unit specified by the instruction is L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, or C unit 245, then the src1 field 1303 is interpreted as a reference. Figure 34 As outlined. If the functional unit specified by the instruction is unit P246, then the src1 field 1303 is as described in the reference. Figure 35 As outlined, it is interpreted accordingly. Alternatively, the stream valid register is automatically saved to... Figure 34 The predefined assertion register illustrated in the diagram may be implemented in one example and not in another.

[0341] In some examples of the processing unit core 110, instructions for sorting vector elements are provided. Some of these instructions sort vector elements as fixed-point elements and / or some of these instructions sort vector elements as floating-point elements. Variations of the sorting instructions may include sorting in descending order of element pairs, sorting elements in ascending order, and / or sorting half of a vector in either ascending or descending order and the other half in either ascending or descending order. Other variations may include sorting instructions that output control input to VPERM instructions, which perform the sorting of vector elements based on the control input.

[0342] Support for sorting vector elements is provided at least partially, as sorting is a common operation in fields such as signal processing and computer vision. There are many reasons to sort datasets. For example, median filters are used to remove certain types of noise. One way to find the median of a set of numbers is to sort the numbers and then take the middle number as the median.

[0343] In another example of processing in a communication system, the start of a data frame is detected based on a known preamble. The preamble may arrive at the receiver at any time and needs to be located to establish a connection. For this, the incoming data is sampled and compared with the expected known preamble at many different time offsets. Each of these comparisons results in a score, which will be the highest when the preamble has actually been found for the assumed time offset of a particular comparison. One way to find the maximum score is to sort the scores at the various time offsets.

[0344] In another example, in a multi-antenna and multipath system, some processing can be performed to identify N maximum peaks. Multipath refers to a signal bouncing off obstacles in the environment and thus arriving at the receiver at different times and angles. One way to find the N maximum peaks is to sort the peak signal values.

[0345] In another example, in a machine learning system, a score is calculated for each possible analysis of an image to determine what object the image might come from among a variety of objects the system has been trained to recognize, such as a bird, a fish, a cat, etc. One way to find the highest score is to rank the analysis scores.

[0346] Some of the sorting instructions provided are designed to accelerate the bitonic merge sort algorithm, as this is a parallel algorithm for sorting that can be efficiently executed on SIMD architectures such as the SIMD architecture of the processing unit core 110. This paper briefly describes the algorithm. Additional descriptions can be found, for example, in "BitonicSorter," Wikipedia (available at https: / / en.wikipedia.org / wiki / Bitonic_sorter) and KEBatcher, "Sorting Networks and Their Applications," Proceedings of AFIPS Spring Joint Computer Conference, 1968, Vol. 32, pp. 307-314.

[0347] The bitonic merge sort algorithm takes a dataset as input and produces an increasing number of groups of elements with the "bitonic" property. A bitonic sequence of numbers is a sequence in which the values ​​of the numbers begin to increase or decrease and then at some point change from increasing to decreasing or from decreasing to increasing.

[0348] Figure 36 This example, taken from the aforementioned Wikipedia entry, illustrates a bitonic merge sort of sixteen elements. Starting from the left, the sixteen numbers "slide along a horizontal line" and exit on the right in sorted order. The network shown is designed to sort the numbers in ascending order, meaning the largest number appears on the bottom horizontal line. Each arrow is a comparator. When two numbers reach the end of the arrow, they are compared. If the arrow points to the larger number, no change is made. Otherwise, the two numbers are swapped so that the arrow points to the larger number.

[0349] In boxes with arrows (e.g., boxes 3600, 3602, 3604), all arrows point either upwards or downwards, and each input in the upper half of the box is compared with the corresponding input in the lower half. If the input numbers in the boxes form a bitonic sequence (a single non-decreasing sequence followed by a single non-increasing sequence) and vice versa, the output is two bitonic sequences. Both the upper and lower halves of the output are bitonic; for boxes with downward-pointing arrows, each element in the upper half is less than or equal to each element in the lower half, and vice versa for boxes with upward-pointing arrows.

[0350] Boxes with arrows are combined to form larger boxes, such as boxes 3606 and 3608, where the arrows in the smaller boxes all point up or all point down. Each larger box has the same structure: the initial arrow box is applied to the entire input sequence, then two smaller arrow boxes are applied to each half of the result of the initial box, then two smaller arrow boxes are applied to each half of the result of the two boxes, and so on, until the last group of boxes each accepts only two inputs. This structure is called a butterfly network. If the input of a larger box is bitone, then for those boxes where the arrows in the smaller boxes all point down, the output of the box is completely sorted in ascending order, or for those boxes where the arrows in the smaller boxes all point up, the output of the box is completely sorted in descending order. When a number enters a larger box, the first smaller box sorts it to exactly half of the list. Then the number passes through a smaller box, which sorts it to exactly one-quarter of the list within that half. This continues until the number is sorted exactly in its correct position. Therefore, the output of the larger boxes is completely sorted.

[0351] Larger boxes are combined to form the entire sorting network, which can correctly sort any arbitrary input sequence, with the largest at the bottom. The output of each larger box will be a sorted sequence, so the output of each pair of adjacent outputs will be bitonic. Each column of a larger box takes N sorted sequences and concatenates these sequences in pairs to form N / 2 bitonic sequences, which are then sorted by the boxes in that column to form N / 2 sorted sequences. This process starts with each input as a sorted list considered as a single element and continues through all columns of the boxes until the last column merges the inputs into a single sorted list. Note that the sorting order can be reversed by reversing the direction of the arrows in the smaller boxes.

[0352] The processing unit core 110 implements instructions that can be used to sort groups of sixteen elements. These sixteen-element sorts can be used to implement a bitonic merge sort on a larger set of elements. Figure 37This is an example of a 32-element bitone merge sort. Note that at the intermediate temporary level 3700, there exists a set of sixteen elements sorted in ascending order and another set of sixteen elements sorted in descending order. In the next level 3702, there is an "interchange" between the two sets of sixteen elements. Following the "interchange" level 3702 is the sorting level, which sorts each set of sixteen elements generated by level 3702 in ascending order.

[0353] like Figure 38 As illustrated in the diagram, Figure 37 The equivalent of the 32-element bitone merge sort can be implemented using a 16-element sort that sorts elements in ascending order and a 16-element sort that sorts elements in descending order. In the accompanying figure, VSORTI16W sorts sixteen 32-bit elements in ascending order and VSORTI16W sorts sixteen 32-bit elements in descending order. The equivalent of the "swap" stage 3702 is implemented by executing the vector minimum instruction VMINW and the vector maximum instruction VMAXW in parallel. VMAXW takes two operands as input, compares the values ​​in the corresponding SIMD channels, and outputs the larger value for each channel. VMINW operates in a similar manner, outputting the smaller value for each channel. Table 30 shows the implementation. Figure 38 Example pseudocode for the operation. In this pseudocode, || indicates that the instruction is executed in parallel with the previous instruction.

[0354] Table 30

[0355]

[0356] In some examples, the processing unit core 110 provides sorting instructions for sorting a vector of sixteen 32-bit floating-point numbers. The `VSORTD16SP src,dst` instruction sorts the vector of floating-point numbers in descending order into the SIMD channels of the destination register, with the largest number placed in the lowest SIMD channel and the smallest number in the highest SIMD channel. The `VSORTD16SP src,dst` instruction sorts the vector of floating-point numbers in ascending order into the SIMD channels of the destination register, with the smallest number placed in the lowest SIMD channel and the largest number in the highest SIMD channel. As part of implementing a bitonetic sorting algorithm, these instructions can be combined to sort the vectors in ascending and descending order.

[0357] In some examples, the processing unit core 110 provides the instruction VSORTDIRSP dir,src,dst, which sorts a vector of sixteen floating-point numbers in ascending or descending order based on the value of the operand “dir”. In some examples, the processing unit core 110 provides sorting instructions for sorting a vector of sixteen 32-bit signed and / or unsigned fixed-point or integer numbers. The instructions VSORTDIRS16W, VSORTDIRS16W, VSORTDIRS16W, and VSORTDIRS16W operate as described above for floating-point sorting instructions, where “I” and “D” in the instruction mnemonic indicate the sorting direction, and “u” indicates unsigned.

[0358] In some examples, the processing unit core 110 provides one or more paired sorting instructions that sort thirty-two 16-bit data elements in a vector. Additionally, sorting of two sets of 16-bit data elements in the vector is provided. These instructions are VDSORTxy[U]16H instructions, where x is D or I and y is D or I, H indicates a half-word or 16-bit data element size, and U (if present) indicates unsigned data. x indicates whether the next sixteen elements in the input vector are sorted in descending or ascending order, and y indicates whether the next sixteen elements in the input vector are sorted in descending or ascending order. Elements can be fixed-point, half-precision floating-point, or integer. When sorting is performed, the corresponding sorted next sixteen elements of the input vector are placed in the next sixteen channels of the output, and the corresponding sorted next sixteen elements of the input vector are placed in the next sixteen channels of the output.

[0359] like Figure 39 As illustrated in the diagram, the VDSORTxy[U]16H instruction can be used to implement a 32-element bitonic sorting algorithm. This example illustrates sorting 32 16-bit elements in ascending order using sort level 3900 with VDSORTID16H, followed by an "interchange" level 3902, and then another sort level 3904 using VDSORTII16H. Using VDSORTDI16H followed by VDSORTDD16H will produce a descending sort.

[0360] The equivalent of the "interchange" level 3902 can be implemented by executing the vector minimum instruction VMINW and the vector maximum instruction VMAXW, as well as the VxyMV instruction, where x and y can be H and L, respectively, where H indicates the high half of the vector and L indicates the low half of the vector. The VLHMV instruction moves the low half of the vector specified by the first operand of the instruction to the high half of the output vector, and moves the high half of the vector specified by the second operand to the low half of the output vector. The VHLMV instruction moves the high half of the vector specified by the first operand of the instruction to the high half of the output vector, and moves the low half of the vector specified by the second operand to the low half of the output vector. Table 31 illustrates the implementation. Figure 39 Example pseudocode for the operation.

[0361] Table 31

[0362]

[0363] In some examples, the processing unit core 110 implements sorting instructions in a "brute-force" manner, where more hardware comparisons are used than are required using a "smarter" sorting method. Generally, this "brute-force" method includes the following steps: 1) comparing each element in the vector of elements with every other element in the vector; 2) based on the comparisons, counting the number of elements in the vector smaller than that element for each element; 3) using the count for each element to determine the channel of that element in the output vector.

[0364] For example, suppose the input elements are 3, 8, 2, and 5, and these elements are to be sorted in ascending order. Performing comparisons and counting how many elements are less than each element produces the following result: only one element (element 2) is less than element 3, three elements (elements 3, 2, and 5) are less than element 8, no element is less than element 2, and two elements (3 and 2) are less than element 5. Therefore, in the output vector, element 2 is placed in channel 0, element 3 in channel 1, element 5 in channel 3, and element 8 is placed in channel 4.

[0365] It should be noted that the above method does not work when an element value appears more than once in the element vector. For example, if the input elements are 3, 8, 3, 5, both elements with a value of 3 will be placed in channel 0, and no element will be placed in channel 1. This can be remedied by making the element comparison "less than or equal to" instead of "less than" when the channel number of an element in the input vector is greater than the channel number of the element it is being compared with. With this modification, the channel number of the second 3 in the input vector is greater than the channel number of the first 3, and therefore the count of the second 3 will be one instead of zero.

[0366] Figure 40Describe the comparison made for this modification method. Table 4000 generally shows which elements are compared using "less than" and which elements are compared using "less than or equal to". Table 4002 shows the results of substituting the numbers from the example into Table 4000. Table 4004 shows the counts obtained from the comparisons in Table 4002. It should be noted that when the comparison in Table 4002 is true, a one is placed in the corresponding position in Table 4004; otherwise, a zero is placed in the corresponding position. The values in each column of Table 4004 are added together to determine the count for each input element.

[0367] The "brute force" method can be further simplified to reduce the number of comparisons. As can be seen from Figure 40 Table 4000, all the comparisons on the diagonal are rn < rn, that is, the elements are being compared with themselves. These comparisons will never be true and can be eliminated. In addition, each pair of numbers is compared twice. For example, in Table 4000, there is both the comparison "r1 < r0" and the comparison "r0 ≤ r1". Changing the second comparison to "r1 ≥ r0" is equivalent to saying that r1 is not less than r0, that is, "r1 ≥ r0" is equivalent to!(r1 < r0). Therefore, as Figure 41 shown in Table 4100, for four input elements, only six actual comparisons are needed. Generally, for N input elements, the total number of comparisons required is (N 2 – N) / 2.

[0368] Once the channels are determined, the last step of sorting is to move the input elements into the identified channels in the output vector. In some examples, a masking method is used to place the elements in the output channels. This method is illustrated in Figure 42 the example. For each element in the input vector, the element is repeated across all the vector channels in the vector, and a mask based on the channel positions in the output vector is applied to the vector of repeated elements to generate an intermediate vector in which the element is in the desired channel position and zeros are in all other channel positions. Then the intermediate vectors are "OR"ed together to generate the output vector of the sorted elements.

[0369] Vector permutation logic (e.g., a permutation network) (if available) can also be used to move input elements into recognized channels of the output vector. In some examples, processing unit core 116 includes vector permutation logic that can be configured to perform any arbitrary rearrangement of any byte from any byte vector channel of the specified vector to any byte vector channel of the specified output vector in response to a control input specifying the permutation to be performed. The control input may also be referred to herein as the control input vector. Each byte of the vector to be permuted is controlled by the corresponding byte of the control input. In each byte of the control input, six bits, called byte selection bits, are used to indicate which byte of the input vector should be routed to the SIMD channel corresponding to the control byte, and two additional bits, called option control bits, are used to indicate other options. Additional descriptions of examples of such vector permutation logic can be found in co-owned U.S. Patent Application No. 16 / 551,587, filed August 26, 2019, entitled “Method and Apparatus for Vector Permutation,” which is incorporated herein by reference in its entirety.

[0370] To generate sorted vectors using vector permutation logic, the control inputs to the permutation network are generated based on the output channels identified for each element of the input vector. It should be noted that the identified output channels provide a mapping from each input channel to the output channel, while the control inputs to the permutation network require the opposite information: a mapping from each output channel to the input channel. Figure 43 As illustrated in the example, one solution is to create a matrix 4300 that maps each input channel to an identified output channel, and then transpose matrix 4300 (as shown by the vertical ellipse) to generate the mapping from each output channel to the input channel. To generate matrix 4300, the output channel identified for each input channel is transformed from an integer into a hot bit vector. Each vertical ellipse is re-encoded as an integer indicating the corresponding output channel-to-input channel mapping. The control inputs for the permutation network are then created based on these integers.

[0371] It should be noted that the example vector permutation logic operates on byte channels. Therefore, if the input and output vector channels are large, multiple consecutive byte channels in the control input are encoded for each large vector channel. For example, if the input and output vector channels are 32 bits, four consecutive byte channels of the control input are encoded for each channel of the output vector. Figure 43 Table 4302 shows the result of the permutation network controlling the input when the input elements are 32 bits.

[0372] It should be noted that the ascending order can be changed to a descending order by taking the two's complement of the "count" of each input element, i.e., by reversing each bit of the two's complement number. For the example of generating a sorted output vector using a permutation network, the least significant bit describing the byte position is not reversed because the relative byte position of each byte in the word is constant.

[0373] In some examples, processing unit core 110 provides sorting instructions that take a vector of 32-bit elements as input, compare the elements in the vector to determine their relationship to each other (e.g., greater than or less than), and then output a control word derived based on the comparison result. The control word produces the desired sorted output when supplied as control input to vector permutation instructions (e.g., VPERM instructions as described in U.S. Patent Application No. 16 / 551,587). In some examples, VPERM instructions can be configured to perform any arbitrary rearrangement of any byte from any byte vector channel on the input to any byte vector channel on the output, based on the control input.

[0374] The sorting instructions for the output control word are called VSORTPxxx instructions, where xxx is the previously mentioned combination set (Ivs D, 16SP vs 16W vs U16W). This control word is generated as described earlier and stored at the output location specified by the instruction. The execution of VSORTPxxx input,tmp followed by VPERMtmp,input,output is the same as the execution of VSORTxxx input,output. Such instructions are useful, for example, when the input vector is associated with some other pointer / attribute / data. Consider the example in Table 32. Suppose that “input” is a vector containing all scores of preamble detection for each time offset, and suppose that “related_data” contains the time offset from which the preamble begins, or a “guess.” To find the best candidate for the preamble, the sequence of instructions shown can be executed, resulting in “sorted_related_data” containing the N closest time offsets from that vector.

[0375] Table 32

[0376]

[0377] The vector sorting instruction is in unit C245 ( Figure 2 Executed on ), C unit 245 includes sorting logic for executing one or more of the above-described instruction variants and permutation network logic that can be used to perform vector permutations based on control inputs. Figure 44This is a block diagram of example C unit 245. Example processing unit core 110 includes a 512-bit vector processing architecture divided into eight 64-bit vector slices. Each slice contains the same processing logic and takes a corresponding 64 bits of the 512-bit vector as input. C unit 245 includes eight slice processing units 4402-4408, which are configured to perform operations on the corresponding 64-bit slices of the input vector. Multiplexing logic (not shown) routes each slice of the src1 and src2 input vectors to the corresponding slice processing unit 4002-4008. Each slice processing unit 4402-4408 includes logic for performing arithmetic operations, floating-point operations, etc., on the corresponding 64 bits of the input vector.

[0378] Each slice processing unit 4402-4408 also includes logic for passing the corresponding 64 bits of the src1 and src2 input vectors to the global processing unit 4400 for use in certain instructions such as vector sorting instructions. Units in the global processing unit 4400 operate on complete 512-bit vectors instead of 64-bit quantities. The global processing unit 4400 includes vector control registers CUCR0-CUCR3 4414, a correlation unit 4412, and a permutation unit 4410.

[0379] The permutation unit 4410 is configured to execute vector permutation instructions and any variations thereof. As described in more detail in previously cited U.S. Patent Application No. 16 / 551,587, the permutation unit 4410 includes vector permutation logic. This vector permutation logic can be used to generate a sorted output vector based on control inputs generated as previously described herein.

[0380] Related component 4412 is configured to perform operations such as sum of absolute differences (SAD), rake, and search, as well as vector sorting instructions. Related component 4412 includes logic that implements a class of instructions supporting SAD calculations. A detailed description of examples of such logic for 8-bit and 32-bit elements is provided in commonly owned U.S. Patent No. 9,788,011, published October 10, 2017, which is incorporated herein by reference in its entirety.

[0381] In some examples, a portion of the SAD logic contained in the relevant component 4412 is used to perform "brute-force" comparisons of various sorting instructions. Figure 45An example SAD logic for operating on 16-bit elements is described. This SAD logic comprises an array of absolute difference elements (e.g., elements 4501, 4511, 4531). Each absolute difference element performs a subtraction operation between element pairs of two input vectors c and r, and then takes the absolute value of the result of the subtraction operation. For example, absolute difference element 4501 takes vector elements c[0] and r[0] as input, subtracts c[0] from r[0], and outputs the absolute value of the result. Furthermore, as can be seen from the "columns" of the absolute difference elements, input element c[0] is also subtracted from elements r[1] to r

[15] , input element c[1] is subtracted from elements r[1] to r

[16] , input element c[2] is subtracted from elements r[2] to r

[17] , and so on. In this example, the SAD logic array has sixteen rows of absolute difference elements, for example, rows 4500, 4510, 4530, and each row has sixteen absolute difference elements.

[0382] Figure 46 illustrate Figure 45 An example implementation of the absolute difference elements and corresponding multipliers. The inversion unit 4601 forms an arithmetic inversion of the input elements from vector c, for example, by inverting the numbers and adding one. Adding one is performed by asserting the carry input (not shown) to the least significant bit of adder 4602. If the difference between the two inputs is negative, adder 4602 adds the output of inversion unit 4601 to the input elements from vector r and generates a valid carry output 4603. If the input element from vector c is greater than the input element from vector r, the difference will be negative. If adder 4602 generates a valid carry output 4603, inversion unit 4604 forms an arithmetic inversion of the output of adder 4602; otherwise, inversion unit 4604 does nothing with the input. The multiplier corresponding to the absolute difference elements is implemented by AND gate 4605 because the mask input is a single bit. If the mask is one, the absolute value remains unchanged. If the mask value is zero, the absolute value is set to all zeros. The output of AND gate 4605 is supplied to... Figure 45 The input to the summer of the corresponding rows in the table.

[0383] For sorting operations, an array of absolute difference elements (e.g., elements 4501, 4511, 4531) is used for the required comparisons. To perform comparisons between elements of the vectors to be sorted, vectors c and r are set to elements of the same vector. Carry output 4603 is used to determine if one vector element input is less than another vector element input. The logic in 4604 may differ depending on whether the data is signed or unsigned, and the sign of the input may also be considered.

[0384] Figure 47 Instructions for Figure 45 The default combination of inputs to the SAD logic. Figure 47Row 0 in the grid represents Figure 45 Row 4500, row 1 in the grid represents row 4510, and so on, ending with row 15 representing row 4530. The top row of the grid depicts the r-vector element input for each column of the SAD array, and the entries in the grid are the corresponding c-vector element input for each row of the SAD array to be subtracted from the r-vector elements. For example, consider row 6. This row indicates that the first subtraction in this row is c0 subtracted from r6, the next subtraction in this row is between c1 and r7, and so on.

[0385] As previously mentioned, the VDSORTxy[U]16H instruction sorts one half of the input vector according to the "x" label and the other half according to the "y" label. To achieve the desired comparison for these instructions, the input to the absolute difference element array is modified, as follows: Figure 48 The diagram illustrates this. Because there is only one input operand, in this diagram, the vector "c" to be sorted is replaced with "r". The comparisons in columns r0 to r15 are comparisons between all unique pairs of elements r0 to r15, and the comparisons in columns r16 to r30 are comparisons between all unique pairs of elements r17 to r31.

[0386] like Figure 49 As illustrated, a single multiplexer 4900 on the internal "Cx" operand is used for selection on the internal bus within the absolute difference element array. The output of multiplexer 4900 is broadcast to downstream absolute difference elements (comparators). The single multiplexer 4900 multiplexes elements r1 through r15 and elements r17 through r31 to select the input of each absolute difference element. Figure 49 In the figure, a single multiplexer 4900 is represented by several smaller multiplexers, which are labeled with the same reference numerals to indicate their connectivity with the absolute difference element.

[0387] As mentioned earlier, sorting instructions other than the VDSORTxy[U]16H instruction operate on 32-bit elements. Figure 50 This describes the input to the array of absolute difference elements when the elements are 32-bit quantities. Two adjacent 16-bit comparisons are used to construct the 32-bit comparisons. For example, comparing a pair of half-words (r0, r1) with (r2, r3) provides the information needed to compare I0 and I1, where I0 and I1 are 32-bit quantities given by the half-word set. Adjacent comparisons in “odd” rows are not useful; for example, comparing (r0, r1) with (r1, r2) is meaningless because (r1, r2) has the high half of I0 in r1 and the low half of I1 in r2. Odd rows are removed and replaced with other necessary comparisons. The 32-bit elements corresponding to each marked row are shown in the unmarked row immediately below each marked row.

[0388] Figure 51 This is a block diagram illustrating an example implementation of one or more sorting instructions in the global processing unit 4400. Sixteen comparator rows 5102, 5104, 5106 (e.g., comparator logic) are configured to receive vector elements to be compared via corresponding multiplexers. Each comparator row 5102, 5104, 5106 is... Figure 49 The absolute difference element rows in the SAD logic are used for comparison row 0 (5102) to row 4500, comparison row 1 (4510), and so on. The multiplexer is configured to target 16-bit elements according to... Figure 48 Select the vector elements of the corresponding comparator rows 5102, 5104, and 5106, and for the 32-bit elements, according to... Figure 50 The vector elements of the corresponding comparator rows 5102, 5104, and 5106 are selected. The results of the comparisons performed by the comparator rows 5102, 5104, and 5106 are provided to the vector sorting logic, which includes a counter calculation unit 5107, a permutation control generation unit 5108, and a permutation unit 4410.

[0389] The counter calculation unit 5107 is configured to receive the results of comparisons performed by comparator rows 5102, 5104, and 5106 and use these results to determine the count of each vector element. The determination of the count of each vector element given the comparison results from comparator rows 5102, 5104, and 5106 is previously referenced herein. Figure 40 and Figure 41 This has been described. As previously stated in this document, the count of the input vector elements is the channel number of the vector elements in the output vector.

[0390] The permutation control generation unit 5108 is configured to generate control inputs for the permutation network based on the output channel number identified for each input vector element. The generation of control inputs given channel numbers is previously referenced herein. Figure 43 The permutation control generation unit 5108 is further configured to output the control input as the output vector if the sorting instruction being executed is a VSORTPxxx instruction. The permutation control generation unit 5108 is also configured to provide the control input and the input vector to the permutation unit 4410 for use in other sorting instructions. The permutation unit 4410 is configured to generate a sorted output vector based on the control input.

[0391] Figure 52This is a flowchart of a method for sorting vectors, which can be executed by a processor (e.g., processing unit core 110). In this method, a vector sorting instruction is executed by the processor 5200 to generate a sorted vector from a vector, wherein the values ​​in the channels of the vector are sorted according to the order indicated by the vector sorting instruction. The sorted vector is then stored 5202 at the location specified by the vector sorting instruction. An example of such a vector sorting instruction has been described earlier in this document.

[0392] Figure 53 This is a flowchart of a method for sorting vectors, which can be executed by a processor (e.g., processing unit core 110). In this method, vector sorting instructions are executed by the processor 5300 to generate a sorted vector from a vector, wherein the values ​​in a portion of the channels of the vector are sorted according to the order indicated by the vector sorting instructions, and the values ​​in another portion of the channels of the vector are sorted according to the order indicated by the vector sorting instructions. The sorted vector is then stored 5302 at the location specified by the vector sorting instructions. An example of such vector sorting instructions has been described earlier in this document.

[0393] Figure 54 This is a flowchart of a method for sorting vectors, which can be executed by a processor (e.g., processing unit core 110). In this method, a vector sorting instruction is executed by the processor 5400 to generate a control input vector for vector permutation logic based on the values ​​in the vector channels and the sorting order of the vectors indicated by the vector sorting instruction. The control input vector is then stored 5402 in the location specified by the vector sorting instruction. An example of such a vector sorting instruction has been described earlier in this document.

[0394] Figure 55 This example illustrates a multiprocessor system. In this example, the SoC 5500 includes processor 100 ( Figure 1 (Referring to "Processor A") and it is combined with a second processor 5511 (referring to "Processor B"). Each processor is coupled to a shared Level 3 (L3) memory 5550 via bus 5551. Processor B includes an unshared Level 2 memory 5512. A Direct Memory Access (DMA) engine 5560 can be programmed to transfer blocks of data / instructions from L3 memory to L2 memory 130 or L2 memory 5512 using known or later-developed DMA technologies. Various types of peripheral devices 5562 are also coupled to memory bus 5551, such as wireless and / or wired communication controllers, etc.

[0395] In this example, processor A, processor B, and L3 memory 5550 are all included in SoC 5500, which can be encapsulated using known or later-developed packaging technologies to form a package that can be mounted on a substrate, such as a printed circuit board (PCB). For example, SoC 5500 can be encapsulated in a ball grid array (BGA) package. In this example, external memory interface (EMI) 5552 allows processor A and / or processor B to access additional external mass memory 5554.

[0396] In this example, processor B is capable of being used for scalar processing and control functions. Processors. In other examples, various types of known or later-developed processors can be combined with DSP 100. While two processors are illustrated in this example, in another example, multiple copies of DSP 100 and / or multiple copies of processor B can be included within the SoC, wherein the copies of DSP 100 include support for one or more vector sorting instructions described herein.

[0397] Other embodiments

[0398] Although this specification includes a limited number of embodiments, other embodiments may be designed without departing from the scope of this specification.

[0399] For example, this paper has described an instruction for independently sorting the two halves of a vector, such as VDSORTxy[U]16H. In other examples, the independently sorted regions in a vector can be of different sizes and / or there can be more than two independently sorted regions.

[0400] In another example, this paper assumes a 512-bit vector and 16-bit or 32-bit elements / channels to describe an example of a sorting instruction. In other examples, the vector can be smaller or larger and / or the element size can be larger or smaller.

[0401] Therefore, the appended claims cover any such modifications to embodiments that fall within the true scope of this specification.

Claims

1. A method for sorting vectors in a processor, the method comprising: The processor generates a control input vector for vector permutation logic contained in the processor based on the values ​​in the channels of the vector in response to a vector sorting instruction. Store the control input vector in the storage location; and The vector permutation logic, in response to a vector permutation instruction, generates a sorted vector using the vector and the control input vector. The control input vector includes a first selection value, which indicates which value of the vector is routed to the first destination channel of the sorted vectors. The control input vector further includes a second selection value, which indicates which value of the vector is routed to the second destination channel of the sorted vector.

2. The method of claim 1, wherein generating the control input vector further comprises comparing values ​​in the channels of the input vector according to a sorting order for the vectors indicated by the vector sorting instruction, wherein the control input vector is generated based on the result of the comparison.

3. The method of claim 1, wherein the value is selected from one of a single-precision floating-point number, a fixed-point number, and an integer.

4. The method of claim 1, wherein the value is a 32-bit value.

5. The method of claim 1, wherein the storage location is indicated by the vector sorting instruction.

6. The method of claim 2, wherein the comparison of the values ​​is performed using comparator logic included in the processor.

7. The method of claim 6, wherein the comparison of values ​​is performed in parallel on the comparator logic.

8. The method of claim 2, wherein generating the control input vector further comprises: Determine the count for each value based on the results; as well as Each count is converted into a channel number in the control input vector for the corresponding value.

9. The method of claim 8, wherein generating the control input vector further comprises converting the channel number into control input for the vector permutation logic: Based on the count of the channels for the vector, a matrix is ​​created that maps each channel of the vector to the corresponding destination channel of the sorted vector; and The control input vector is generated based on the transpose of the matrix.

10. The method of claim 6, wherein the comparator logic comprises an array of absolute difference elements.

11. The method of claim 10, wherein the absolute difference element is configured for summation of absolute difference calculations and for making the comparison of values.

12. A processor comprising: Comparator logic, which is configured to compare values ​​in the channels of a vector in response to a vector sorting instruction; Vector permutation logic is configured to generate sorted vectors in response to a vector permutation instruction using the vector and a control input vector indicated by the vector permutation instruction; as well as The vector sorting logic is configured to generate the control input vector based on the result of comparisons of the values ​​performed by the comparator logic. The control input vector includes a first selection value, which indicates which value of the vector is routed to the first destination channel of the sorted vectors. The control input vector further includes a second selection value, which indicates which value of the vector is routed to the second destination channel of the sorted vector.

13. The processor of claim 12, wherein the value is selected from single-precision floating-point numbers, fixed-point numbers, and integers.

14. The processor of claim 12, wherein the value is a 32-bit value.

15. The processor of claim 12, wherein the comparator logic is further configured to compare the values ​​in parallel.

16. The processor of claim 12, wherein the vector sorting logic is further configured to determine a count for each value based on the result, and to convert each count into a channel number in the control input vector for the corresponding value.

17. The processor of claim 16, wherein the vector sorting logic is further configured to convert the channel number into a control input vector for the vector permutation logic by at least the following operations: Based on the count of the channels for the vector, a matrix is ​​created that maps each channel of the vector to the corresponding destination channel of the sorted vector; and The control input vector is generated based on the transpose of the matrix.

18. The processor of claim 12, wherein the comparator logic comprises an array of absolute difference elements.

19. The processor of claim 18, wherein the absolute difference element is configured for summation of absolute difference calculations and for comparison of values.

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