Efficient Encoding of Binary Symmetric Invariant Product Codes Using a Half-Size Data Array

Abstract

The encoder encodes input data using a binary symmetric invariant product code. The encoder includes a circuit device including a half-size data array including D rows, each row having storage for H data bits (D=2×H+1). The encoder is configured to access the bits of each row of the product code by reading a first H-bit data word from one of the D rows and reading a second H-bit data word across H different rows of the half-size data array. The encoder also includes: a register configured to receive the bits of each row of the product code and rotate the bits to obtain the rows of the product code; and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate column parity for parity bits for all rows of the product code based on the row parity.

Description

Background Art

[0001] The present invention relates to data processing, and more particularly, to efficient encoding and decoding of data utilizing binary symmetric invariant product codes (e.g., half-product codes), such as in data storage systems or data communication systems.

[0002] Error correction coding is used in data storage systems and data communication systems to improve the accuracy of data that can be recovered from data channels. By encoding the data according to an error correction code (ECC) before providing it to the channel, errors at the channel output can be identified and corrected to a degree that depends on the properties of the ECC. Many such ECC schemes are known. One well-known class of ECC schemes is based on product codes. Product codes use two component ECC codes to encode the rows and columns of a conceptual two-dimensional array of input data.

[0003] The basic structure of conventional product codes is Figure 1 The input data symbols (which may typically be q-ary symbols with q possible symbol values, where q ≥ 2) are assigned to corresponding symbol positions in a conceptual array having n2 rows and n1 columns of symbol positions. In this example, k2×k1 data symbols are assigned to corresponding positions in a k2 by k1 subarray at the intersection of the first k2 rows and the first k1 columns of the n2 by n1 array. The resulting array of input data symbols is encoded by encoding the rows and columns of the array separately. The first ECC code C1 is used to convert the k symbols in each row of the array to i The symbol data word is encoded as a C1 codeword of length -n1. This example uses systematic encoding, whereby the input data is retained in the codeword. Specifically, the n1 code symbols of the C1 codeword are obtained by adding (n1-k1) parity symbols after the k1 symbol data words in a given row. Then, a second ECC code C2 is used to encode the k2 symbols in each column of the array into a C2 codeword of length -n2, here by adding (n2-k2) parity symbols at the end of each column. The resulting n2×n1 code symbols in the array form the output codeword of the product code. In an extension of this basic idea, the interleaved product code applies the C2 code on s>1 evenly spaced columns of the array, producing n1 / s C2 codewords.

[0004] Product codes can provide practical encoder / decoder implementations, whose decoders are based on hard decisions and therefore avoid the different complexity and latency issues associated with soft decision decoding. Some decoders for interleaved product codes use iterative decoding techniques based on a graph defined by the basic code structure. Briefly, a bipartite graph can be defined with n2 right nodes, each corresponding to a C1 codeword, and n1 / s left nodes corresponding to the corresponding C2 codeword. Each right node is connected to each left node by s edges. The s edges connecting a pair of nodes represent the s common symbols at the intersection of the C1 and C2 codewords of those nodes in the above conceptual array. Based on this graph, iterative decoding is performed by decoding the C1 codewords one by one, and then decoding the C2 codewords one by one. Each time a codeword is successfully decoded, the edge leaving the appropriate node is corrected. This process is iterated until decoding is complete, that is, the decoder no longer detects errors or has reached a predetermined maximum number of iterations. When the predetermined maximum number of iterations is reached, the decoder can declare decoding failure.

[0005] Another ECC scheme based on product codes was proposed in the context of Optical Transport Networks (OTN) in J. Justesen, “Error correction coding for OTN,” IEEE Communications Magazine, September 2010, and J. Justesen, “Performance of Product Codes and Related Structures with Iterative Decoding,” IEEE Transactions on Communications, 2011. These codes, called half-product codes (HPC), are product codes that use the same code for both the row code C1 and the column code C2. If each component code C1 and C2 is a rate k / n code with code length n (i.e., the number of symbols in a codeword) and dimension k (i.e., the number of data symbols encoded into each codeword), then the resulting product code C has length N=n. 2 , dimension K = k 2 Sum rate (k / n) 2 The codewords of C can be defined by a matrix X of (n by n) symbols corresponding to the above conceptual array, where each row and column of X is a codeword of a row / column code. Then by C H ={XX T : X∈C} defines the corresponding half-product code C H , where X T is the transposed matrix of X.

[0006] Note that if X is a codeword, then X T This is also true, because the row code and column code are the same. By construction, C HEach codeword Y H has a zero main diagonal (although any main diagonal can be a zero main diagonal, a zero main diagonal is defined herein as spanning the (n by n) symbol matrix Y H A row of symbols extending diagonally from the upper right symbol to the lower left symbol). That is, all symbols on the zero main diagonal have the value zero. Since according to C H Definition of Y H =Y H T , so the set of n(n-1) / 2 symbols in the triangular subarray on each side of the zero main diagonal is the same. Therefore, these n(n-1) / 2 symbols define the codeword Y H , so that the half-product code has N H = effective length of n(n-1) / 2. For HPC, encoding and iterative decoding are performed conventionally in the same way as for product codes, but the input data is restricted to triangular subarrays on one side of the zero main diagonal, giving K for HPC H =k(k-1) / 2 dimension.

[0007] exist Figure 2 An exemplary prior art HPC 200 is shown in FIG. In the prior art, to form the HPC 200, original input data 204 is packed into a square array below a main diagonal of zeros 202. Once all original input data 204 is filled, symmetrical replicated data 206 is formed by replicating the original input data 204, performing a bit-by-bit transposition of the original input data 204, and placing the resulting data above the main diagonal of zeros 202. Parity data 208 is then calculated separately for each row and column (e.g., using a Bose-Chadhouli-Hocking (BCH) error correction function). After encoding, due to data symmetry, only the portion of the array above or below the main diagonal of zeros 202 needs to be stored and / or transmitted.

[0008] When data is retrieved from memory or received via data transfer, the HPC 200 can be reconstructed by copying and transposing the retrieved / received data to fill the array. Therefore, any errors that occur during storage, retention, retrieval, and / or transmission of data will also be symmetric about the zero main diagonal of the reconstructed array, as shown in FIG. Figure 3 During conventional decoding (ie, an error correction process that iteratively processes rows and columns to correct row and column errors), data in the array is first accessed in row format and then in column format.

[0009] To achieve high performance, a hardware implementation of the HPC encoder and decoder would be preferred. However, a straightforward hardware implementation of a hardware encoder would form the complete HPC array (including the repeated data 206) in memory, and then iteratively encode each row row by row, and then iteratively encode each column column by column. While this approach can provide much higher performance than conventional software implementations, the present disclosure recognizes, in accordance with preferred embodiments, that integrated circuit devices that enable data to be accessed in a row and column format are very expensive in terms of die area. The present disclosure also understands, in accordance with preferred embodiments, that such a hardware implementation would require row and column data to be encoded independently, meaning that no benefit would be gained from array symmetry. Summary of the Invention

[0010] In at least one embodiment, the encoder performs iterative encoding of codewords in hardware using a binary symmetric invariant product code, such as a half product code (HPC).

[0011] In at least one embodiment, an encoder includes a half-size data array including D rows each having storage for H bits, wherein a binary symmetric invariant product code has row and column data dimensions of D, which is equal to 2×H+1. The encoder is configured to access the bits of each row of the product code by reading a first H-bit data word from one of the D rows and reading a second H-bit data word across H different rows of the half-size data array. The encoder also includes: a register configured to receive the bits of each row of the product code and rotate the bits to obtain the rows of the product code; and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate column parity for parity bits for all rows of the product code based on the row parity.

[0012] In at least one embodiment, the binary symmetric invariant product code is a half product code (HPC).

[0013] In at least one embodiment, a half-size data array is implemented using multiple shift register latches.

[0014] In at least one embodiment, the encoder is configured to shift bits between rows of the half-sized data array and recycle the first H-bit data word read from the half-sized data array back into the half-sized data array.

[0015] In at least one embodiment, the encoder forms all rows of the binary symmetric invariant product code by reading the same set of bit storage locations within the half-sized data array.

[0016] In at least one embodiment, the encoder is configured to pack the half-size data array with H bits of input data at a time.

[0017] In at least one embodiment, a method for encoding a binary symmetric invariant product code comprising D data bits and P parity bits in each dimension includes: packing input data into a half-sized data array comprising D rows, each row having storage for H bits of the input data, where D equals 2×H+1. The method additionally includes iteratively accessing the bits of each row of the binary symmetric invariant product code by reading a first H-bit data word from a row selected from the D rows of the half-sized data array and reading a second H-bit data word across H different rows of the half-sized data array. Rotating the bits of each row of the binary symmetric invariant product code as needed to obtain rows of the binary symmetric invariant product code. Generating row parity for each row of the binary symmetric invariant product code. Based on the row parity generated by a row parity generator, also generating column parity for the P parity bits of all rows of the binary symmetric invariant product code. Outputting the first H-bit data word, the row parity, and the column parity.

[0018] According to one aspect, there is provided an encoder for encoding input data using a binary symmetric invariant product code comprising D data bits and P parity bits in each dimension, the encoder comprising circuitry comprising: a half-sized data array comprising D rows of memory each having H bits for the input data, wherein D is an integer equal to 2×H+1, and wherein the encoder is configured to encode input data by reading a first H-bit data word from a row selected from the D rows of the half-sized data array and reading a second H-bit data word across H different rows of the half-sized data array. a data word to access the bits of each row of the binary symmetric invariant product code; a register configured to receive the bits of each row of the binary symmetric invariant product code and rotate the bits as needed to obtain the row of the binary symmetric invariant product code; a row parity generator coupled to the register and configured to generate a row parity for each row of the binary symmetric invariant product code; and a column parity generator configured to generate column parity for P parity bits for all rows of the binary symmetric invariant product code based on the row parity generated by the row parity generator.

[0019] According to another aspect, a data storage system is provided, comprising: a non-volatile memory system; and a controller coupled to the non-volatile memory system, wherein the controller comprises the encoder as described in Paragraph 18 .

[0020] According to another aspect, a data communication system is provided, comprising: an encoder as described in paragraph 18; and a modulator configured to receive encoded data from the encoder, modulate the encoded data, and output the modulated encoded data on a communication channel.

[0021] According to another aspect, a method for encoding a binary symmetric invariant product code comprising D data bits and P parity bits in each dimension is provided, the method comprising: packing input data in a half-size data array comprising D rows, each D row having storage for H bits of input data, where D is an integer equal to 2×H+1; iteratively accessing the bits of each row of the binary symmetric invariant product code by reading a first H-bit data word from a selected row of the D rows of the half-size data array and reading a second H-bit data word across H different rows of the half-size data array; rotating the bits of each row of the binary symmetric invariant product code as needed to obtain a row of the binary symmetric invariant product code; generating row parity for each row of the binary symmetric invariant product code, and generating column parity for P parity bits for all rows of the binary symmetric invariant product code based on the row parity generated by a row parity generator; and outputting the first H-bit data word, the row parity, and the column parity.

[0022] According to another aspect, there is provided a computer program comprising program code means adapted to perform the method described in the preceding paragraphs when said program is run on a computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0024] Figure 1 A prior art product code is shown;

[0025] Figure 2 A prior art Half Product Code (HPC) is shown;

[0026] Figure 3 Characterize the state-of-the-art HPC containing symmetric data errors;

[0027] Figure 4 is a high-level block diagram of a data storage system according to one embodiment;

[0028] Figure 5 is a high-level block diagram of a data communication system according to one embodiment;

[0029] Figure 6-7 Pictured Figure 4 An exemplary implementation of a data storage system;

[0030] Figure 8 depicts a conceptual HPC array according to one embodiment;

[0031] Figure 9 illustrates the data fields of conventional HPC, where input data and replicated data are separated on different sides of a zero main diagonal;

[0032] Figure 10 depicts a data field for HPC according to one embodiment, wherein input data is reorganized and replicated to obtain an equal number of input data bits in each row;

[0033] Figure 11 illustrates a half-sized data array sized to accommodate an equal number of input data bits per row for an HPC according to one embodiment;

[0034] Figure 12-14 According to one embodiment, the correspondence between the processing of HPC in a half-size data array and a conventional HPC array is depicted;

[0035] Figure 15 A hardware-based encoder for encoding input data using HPC is shown according to one embodiment; and

[0036] Figure 16 According to one embodiment Figure 15 A high-level logic flow chart of an exemplary process for encoding input data using HPC. DETAILED DESCRIPTION

[0037] In at least one embodiment, the present application is directed to an encoder that performs iterative encoding of data in hardware circuitry using a binary symmetric invariant product code, such as a half product code (HPC). The present application further relates to related methods.

[0038] While the solutions described herein are applicable to conventional HPC as discussed above, it will be appreciated that, in accordance with preferred embodiments, the invention disclosed herein is also applicable to symmetry-invariant product codes formed from more than one type of component code per row and more than one type of component code per column. Similarly, further extensions of HPC can be achieved by using more than one type of component code in the code construction. For example, two types of component codes with the same length n but different error correction capabilities t1 and t2 can be used. In the case of HPC, it can be required that the first half of a row / column be a codeword from the t1 error-correcting component code, and the second half of a row / column be a codeword from the t2 error-correcting component code.

[0039] See again the drawings and in particular Figure 4 , there is a high-level block diagram of an exemplary embodiment of a data storage system 400 for reading and writing ECC-encoded data on a data storage device. The data storage system 400 includes a recording channel 402 that includes a memory 404 (e.g., flash memory or other non-volatile random access memory (NVRAM)) and a read / write device 406 for reading and writing data in the memory 404. Although Figure 4 4. Although shown as a single block in FIG. 4, memory 404 may include any desired configuration of data storage cells ranging from, for example, a single chip or die to multiple banks (each bank including multiple memory chips packaged together). Read / write devices 406 perform read and write operations in a known manner by applying appropriate voltages to word and bit line arrays in memory 404 to address the memory cells for read and write purposes.

[0040] The data storage system 400 further includes an encoder 410 and a decoder 412. The encoder 410 encodes input (user) data into code symbols according to a binary symmetric invariant product code (e.g., HPC) and outputs the code symbols to the recording channel 402. The decoder 412 processes the readback symbols obtained by the read / write device 406 from the memory 404 to decode the symmetric invariant product code, thereby recovering and outputting the original input data.

[0041] like Figure 5 As further shown in FIG, symmetry-invariant product codes such as HPC are also used in data communication systems such as data communication system 500. The transmitter of data communication system 500 includes the above-mentioned Figure 4 5. The data communication system of FIG. 5 shows an encoder 510, a modulator 508, and a transmission device (TX) 506. The code symbols output by the encoder 510 are supplied to the transmission device 506 via the modulator 508, which generates a signal for transmitting the code symbols on the communication link 504. The communication link 504 may include a physical (wired or wireless) link or a logical link on one or more physical links. The receiver of the data communication system includes a receiving device (RX) 516 for receiving the signal transmitted via the link 504, a demodulator 518 for demodulating the received signal, and a decoder 512 for decoding the resulting code symbols received from the demodulator 518 as described above.

[0042] In a preferred embodiment, the functions of the encoders 410, 510 and decoders 412, 512 are implemented in hardware circuit devices (i.e., integrated circuit devices) to achieve high performance. However, in other embodiments, the functions of the encoders 410, 510 and decoders 412, 512 can be implemented in hardware that executes program instructions of software and / or firmware. For example, encoding and decoding can be performed in whole or in part by executing software that configures one or more processors as encoders and / or decoders to perform encoding and decoding.

[0043] Now see Figure 6-7 , depicting Figure 4 Data storage system 400 is a more detailed block diagram of an exemplary implementation of a data storage system. Figure 6A data processing environment 600 is shown that includes one or more hosts, such as a processor system 602 having one or more processors 604 that process instructions and data. The processor system 602 may also include a local storage device 606 (e.g., dynamic random access memory (DRAM) or a disk) that can store program code, operands, and / or results of the processing performed by the processor 604. In various embodiments, the processor system 602 may be, for example, a mobile computing device (such as a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (such as one of the POWER series servers available from International Business Machines Corporation), or a mainframe computer system. The processor system 602 may also be an embedded processor system using various processors (e.g., ARM, POWER, Intel X86), or any other processor in combination with any of a memory cache, a memory controller, local storage, an I / O bus hub, and the like.

[0044] Each processor system 602 also includes an input / output (I / O) adapter 608 coupled to a data storage system 620 via an I / O channel 610, either directly (i.e., without any intermediary device) or indirectly (i.e., through at least one intermediary device). In various embodiments, the I / O channel 610 may employ any one or a combination of known or future developed communication protocols, including, for example, Fibre Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transmission Control Protocol / Internet Protocol (TCP / IP), Peripheral Component Interconnect Express (PCIe), etc. I / O requests transmitted via the I / O channel 610 include read requests by which the processor system 602 requests data from the data storage system 620 and write requests by which the processor system 602 requests data to be stored in the data storage system 620.

[0045] Although not required, in the illustrated embodiment, the data storage system 620 includes a plurality of interface cards 622 through which the data storage system 620 receives and responds to I / O requests from the host via the I / O channel 610. Each interface card 622 is coupled to each of a plurality of redundant array of inexpensive disks (RAID) controllers 624 to facilitate fault tolerance and load balancing. Each of the RAID controllers 624 is in turn coupled (e.g., via a PCIe bus) to a non-volatile storage medium, which in the illustrated example includes a plurality of flash memory cards 626 carrying NAND flash memory. In other embodiments, alternative and / or additional non-volatile storage devices may be employed.

[0046] In the depicted embodiment, operation of data storage system 620 is managed by a redundant system management controller (SMC) 623 coupled to interface card 622 and RAID controller 624. In various embodiments, system management controller 623 may be implemented using hardware or hardware executing firmware and / or software.

[0047] Figure 7 Depicts Figure 6 6. A more detailed block diagram of an exemplary embodiment of a flash memory card 626 of a data storage system 620 is provided. The flash memory card 626 includes a gateway 730 that acts as an interface between the flash memory card 626 and the RAID controller 624. The gateway 730 is coupled to a general purpose processor (GPP) 732, which can be configured (e.g., via program code) to perform pre-processing of I / O requests received by the gateway 730 and / or schedule servicing of the I / O requests by the flash memory card 626. The GPP 732 is coupled to a GPP memory 734 (e.g., dynamic random access memory (DRAM)), which can conveniently buffer data created, referenced, and / or modified by the GPP 732 during its processing or data flowing through the gateway 730 that is destined for one or more of the flash memory controllers 740.

[0048] The gateway 730 is also coupled to a plurality of flash controllers 740, each of which controls a respective NAND flash memory system 750. The flash controllers 740 can be implemented, for example, by an application-specific integrated circuit (ASIC) and / or a field-programmable gate array (FPGA) and / or a microprocessor, and each has associated flash controller memory 742 (e.g., DRAM). In embodiments where the flash controllers 740 are implemented using FPGAs, the GPP 732 can program and configure the flash controllers 740 during startup of the data storage system 620. After startup, the flash controllers 740 generally receive read and write requests from the gateway 730 requesting to read data stored in the NAND flash memory system 750 and / or to store data in the NAND flash memory system 750. The flash controllers 740 service these requests, for example, by accessing the NAND flash memory system 750 to read or write the requested data from or to the NAND flash memory system 750, or by accessing a memory cache (not shown) associated with the NAND flash memory system 750.

[0049] Flash controller 740 implements a flash translation layer (FTL), which provides logical-to-physical address translation to facilitate access to specific memory locations within NAND flash memory system 750. Typically, an I / O request received by flash controller 740 from a host device (such as processor system 602) includes a logical block address (LBA) of the data to be accessed (read or written), and in the case of a write request, includes write data to be stored in data storage system 620. The I / O request may also specify the amount (or size) of data to be accessed. Other information may also be transmitted, depending on the protocols and features supported by data storage system 620. The flash translation layer converts the LBA received from RAID controller 624 into a physical address assigned to the corresponding physical location in NAND flash memory system 750. Flash controller 740 may perform the address translation and / or store the mapping between logical and physical addresses in a logical-to-physical translation data structure, such as a logical-to-physical translation table (LPT), which may be conveniently stored in flash controller memory 742.

[0050] In various embodiments, the NAND flash memory system 750 can take many forms. Figure 7 In the illustrated embodiment, each NAND flash memory system 750 includes a plurality (e.g., 32) of individually addressable NAND flash memory devices 752. In the illustrated example, the flash memory devices 752 take the form of on-board flash memory modules, such as single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) NAND flash memory modules. Preferably, the fidelity of data read from the flash memory devices 752 is enhanced by implementing ECC encoding, for example, by the flash controller 740 and / or a higher-level controller such as the GPP 732 or the RAID controller 624. In the illustrated embodiment, ECC encoding and decoding are implemented at least in the flash controller 740 by an encoder 744 and a decoder 746.

[0051] Now see Figure 8 , shows a conceptual HPC array that will be used to describe the encoding and decoding performed by encoders 410, 510, and 744 and decoders 412, 512, and 746. Figure 2As explained, HPC array 800 is a square array with an equal number of rows and columns. HPC array 800 additionally includes a zero main diagonal, for example, zero main diagonal 802. As previously described, input data 804 is packed into HPC array 800 below zero main diagonal 802, and symmetrically repeated data 806 is placed above zero main diagonal 802. Parity data 808 for each row and column is appended to the end of the relevant row or column. Parity data 808 includes a square cross-parity subarray 810 containing parity checks for the parity-only rows and columns.

[0052] In this conceptual HPC array 800, all rows and columns have a common dimension of F bits, including D bits of data and P bits of parity. Figure 8 As further indicated in , the D data bits in each row and column include a 0 data bit in the zero main diagonal 802 and 2×H other bits, meaning that D is an odd integer. These dimensions can be represented by the following relationship:

[0053] F=D+P

[0054] D=2×H+1

[0055] Among them, F, D, P, and H are all positive integers.

[0056] In the prior art, a typical implementation would fill the triangular array below the main diagonal 802 with bits of the input data 804 until all data bits have been filled, and then transpose the bits of the input data 804 one at a time to create the duplicate data 806. The parity fields would then be calculated separately for each row and column. Because it is difficult to process the triangular (non-rectangular) array of input data 804 in hardware, this process is typically performed in software, where each row includes a different number of data bits and calculating its transposition (to form the duplicate data 806) requires unique and specific row and column access for each element.

[0057] The present disclosure accordingly presents an innovative technique for encoding input data in hardware using binary symmetric invariant product codes (such as HPC). In order to perform this encoding in hardware using compact logic, the present disclosure implements a data packing technique that is significantly different from that employed in the prior art. To explain this technique, first see Figure 9 , which shows only the data field 900 of an exemplary conventional HPC array (i.e., omitting parity data). In this example, the data field 900 includes 15 rows numbered 0 to 14 and 15 columns numbered 0 to 14. Thus, in this example, D is 15, H is 7, and the data field 900 includes 225 bits, including 105 input bits, 105 repeating bits, and 15 '0' bits within the zero main diagonal. Figure 9In the example, each storage location is labeled with a pair consisting of a row number and a column number. These pairs range from (0, 0) in the lower right corner to (14, 14) in the upper left corner. In conventional HPC, input data is separated below the zero main diagonal 902 in the input data field 904, while duplicate data is separated above the zero main diagonal 902 in the duplicate data field 906. As described above, the number of storage locations for input data in each row is different, ranging from 14 bits in row 0 to 0 bits in row 14.

[0058] To facilitate more efficient data packing, it is preferred that all rows of the HPC contain the same number of input data bits. Figure 10 As shown, the data bits of the data field 1000 of the HPC can be reallocated to different storage locations so as to achieve an equal number of input data bits in all rows. In this example, the input data bits are not all packed below the zero main diagonal 1002. Instead, the input data is packed into a first input data field 1004a below the zero main diagonal 1002 and a second input data field 1004b above the zero main diagonal 1002. Similarly, the copy data is packed into a first copy data field 1006a above the zero main diagonal 1002 and a second copy data field 1006b below the zero main diagonal 1002. As a result of this arrangement, each row of the data field 1000 includes H=7 bits of input data, where each bit is marked to indicate Figure 9 0. Thus, for example, storage locations (0, 7) and (7, 0) are labeled D0.0 to indicate that these storage locations hold input data bits to be stored in storage location (0, 0) of data field 900.

[0059] Given the ability to pack data fields of input data with rows of equal length, it is possible to form Figure 11 The half-size data array shown is sized to accommodate an equal number of input data bits per row of HPC. In this example, the half-size data array 1100 includes 15 rows numbered 0 to 14 (i.e., D rows) and 7 columns numbered 0 to 6 (i.e., H columns). It should be noted that the half-size data array 1100 only includes input data fields 1104 and does not include repeated data fields. The half-size data array 1100 may also omit the storage of explicit zero main diagonals, but alternatively includes implicit zero main diagonals 1102, including implicit '0' bits for each row.

[0060] Given data bits packed into the input data field 1104 of the half-size array 1100, the Figure 10The conceptual HPC array 1000 depicted in FIG. 1 processes the same data bits to calculate parity for each row and column of the HPC array. For example, Figure 12 It is shown that the parity of row 0 1010 (and replicated transposed column 14) of the HPC array 1000 can be calculated by applying a selected parity algorithm (e.g., BCH) to the 15 bits within row 0. These same data bits (i.e., the data bits found in row 0 of the notional HPC array 1000) can be accessed from the half-size data array 1100 by accessing the corresponding 14 bits from diagonal data word 1200b (which includes data bits D14.6, D13.5, D12.4, D11.3, D10.2, D9.1, and D8.0) and horizontal data word 1200a (which includes data bits D0.0 through D0.6 (the '0' from the zero main diagonal 1002 is implicit)).

[0061] like Figure 13 As further illustrated in FIG, the parity of row 1 1012 (and replicated transposed column 13) of the HPC array 1000 may be calculated by applying a selected parity algorithm (e.g., BCH) to the 15 bits within row 1. While the parity can be calculated by changing the access location in the half-size data array 1100 from Figure 12 14. In the preferred embodiment, the input data in half-size data array 1100 is shifted to access the same data bits, but in the preferred embodiment, the input data in half-size data array 1100 is instead shifted so that the accessed locations in half-size data array 1100 remain the same to process all rows of the conceptual HPC array. Thus, in the preferred embodiment, after forming all 15 bits of row 0 of the conceptual HPC array, the input data located in row 0 of half-size data array 1100 is "recycled" back to the "top" (i.e., row 14) of the half-size data array 1100, and the remaining input data in half-size array 1100 is shifted down one row. Thus, for example, after data D0.[6-0] is loaded back to the top of the SRL array, all other input data is shifted "down" one row, and D1.[6-0] forming horizontal array 1202 a is now stored in row 0 of half-size array 1100. Within the input data rotated in this manner, row 1 of the conceptual HPC array 1000 can be formed by again accessing diagonal data word 1202b, which includes data bits D0.6, D14.5, D13.4, D12.3, D11.2, D10.1, and D9.0, and horizontal data word 1202a, which includes data bits D1.0 through D1.6 (the '0's from the zero main diagonal 1002 are again implicit).

[0062] like Figure 14As depicted in FIG, this process of accessing input data from the half-size array 1100, forming rows of HPC to calculate parity, and recycling the input data in the half-size array 1100 continues until the input data bits corresponding to the top row 1014 (e.g., row 14) of the conceptual HPC matrix 1000 are reached. Input data corresponding to the top row 1014 of the conceptual HPC array 1000 can be formed by again accessing diagonal data word 1204b, which includes data bits D13.6, D12.5, D11.4, D10.3, D9.2, D8.1, and D7.0, and horizontal data word 1204a, which includes data bits D14.0 through D14.6 (the '0' from the zero main diagonal 1002 is again implicit). Again, throughout this process, the position of the input data accessed from the half-size array 1100 does not change.

[0063] Now see Figure 15 , shows a hardware-based encoder for encoding input data using HPC according to one embodiment. The encoder 1500 can be used to implement any of the encoders 410, 510, or 744 described above.

[0064] As illustrated, encoder 1500 includes a half-size array 1502 of D rows for storing H bits of input data, where the corresponding data field of the conceptual HPC array is 2×H+1 (i.e., D) bits in each dimension, and each row and column contains P bits of parity. In a preferred embodiment, half-size data array 1502 includes H columns formed by an equal number of equal-sized, serially connected shift registers, which can be implemented, for example, using shift register latches (SRLs) 1504. Each such column includes serialized storage for 2×H+1 (i.e., D) bits. In this embodiment, each column of half-size array 1502 can be independently addressed across the column and even within the column, where each individual SRL 1504 receives a single "address" and outputs at most one data bit.

[0065] Data is received by encoder 1500 at input multiplexer 1508, which has a first input coupled to an H-bit input bus 1506 and a second input coupled to an H-bit recycling bus 1510 that recirculates horizontal data words read out of half-size array 1502. During a packing phase, during which the input data is initially packed into half-size array 1502, encoder 1500 controls input multiplexer 1508 to select data present at the first input for insertion into the next unoccupied row of half-size array 1502; during an encoding phase, encoder 1500 controls input multiplexer 1508 to select selected data present at the second input for insertion into the top row of half-size array 1502.

[0066] During the encoding phase, an HPC row register 1512 of size D = 2×H + 1 is loaded by simultaneously reading two words of length H from the half-sized array 1502. It should be noted that no single SRL 1504 within the half-sized array 1502 supplies more than a single data bit to the HPC row register 1512. In the illustrated embodiment, the leftmost bit of the HPC row register is a '0' bit representing a bit provided by the zero main diagonal of the notional HPC array, the next H bits are a horizontal data word 1514 provided from a predetermined horizontal row (e.g., bottom row 1518) of the half-sized array 1502, and the subsequent H bits are duplicate data bits 1516 provided by diagonal data words 1520.

[0067] As shown at reference numeral 1522, after the HPC row register 1512 is loaded with the HPC row data, the HPC row data is then rotated as needed in the HPC row register 1512 or another register. In the illustrated embodiment, the HPC row data is rotated right by N bits, where N is the corresponding integer row number of the conceptual HPC array. Thus, for row 0, no rotation is performed, and for row 14, the HPC row data is rotated right by 14 bits. As a result of the rotation, if performed, the '0' bits from the zero main diagonal are appropriately repositioned within the HPC row data, and one or more bits of the input data bits 1514 or the copied data bits 1520 are wrapped.

[0068] Once the HPC row data is properly formatted (if any) by rotation, a row parity generator 1524 generates P parity bits for the Nth row of the notional HPC array according to the selected parity algorithm (e.g., BCH). These P row parity bits are fed to a column parity generator 1526, which computes a P×P "cross parity" subarray 810 of the notional HPC array. It is important to note that the encoder 1500 outputs each of the D rows of data and parity (each having D+P bits) for storage and / or transmission, but preferably does not store or transmit (but rather discards) the repeated data bits 1516 provided by the diagonal data words 1520 after row parity generation. Similarly, in the cross parity subarray 810 generated by the column parity generator 1526, the encoder 1500 preferably outputs only the P×(P-1) / 2 bits below the zero main diagonal 802.

[0069] Now see Figure 16 , depicts a high-level logical flow diagram of an exemplary process by which, according to one embodiment, Figure 15 The encoder utilizes HPC data arrays to encode input data.

[0070] In response to encoder 1500 receiving input data to be encoded, the process begins at block 1600. The process then proceeds to block 1602, which illustrates the packing phase. During the packing phase, encoder 1500 controls input multiplexer 1508 to select incoming data from input bus 1506 and provides the necessary addressing signals to fill half-size array 1502 by packing H-bit words of input data into all D rows of half-size array 1502. After half-size array 1502 is packed, encoder 1500 enters the encoding phase, which is represented by a processing loop including blocks 1604-1612.

[0071] At block 1604, the encoder 1500 determines whether all D rows of the half-size array 1502 have been processed. If so, the process proceeds to block 1620, described below. If not, the encoder 1500 obtains the HPC row data for the next row of the conceptual HPC array by concatenating the horizontal H-bit word 1518 of the input data with the diagonal H-bit word 1520 of the replica data (block 1606). The encoder 1500 then barrel-rotates the HPC row data N positions to the right, where N is an integer between 0 and D-1, indicating which row of the half-size array 1502 is being processed (block 1608). The encoder 1500 then generates P parity bits for the row codeword using the row parity generator 1524 (block 1610). The encoder 1500 additionally recycles the horizontal H-bit word of the input data 1514 read out of the half-size array 1502 back to the top row of the half-size array 1502 and shifts the other rows of input data within the half-size array 1502 down one row (block 1612). This process iterates until the encoder 1500 determines at block 1604 that all D rows of the half-size array 1502 have been processed. In response to the encoder 1500 determining at block 1604 that all D rows of the half-size array 1502 have been processed, the encoder 1500 utilizes the column parity generator 1526 to generate and output P×(P-1) / 2 cross parity bits below the zero main diagonal of the HPC data array (block 1620). Thereafter, Figure 16 The process ends at box 1622.

[0072] It should be understood by those skilled in the art that Figure 16 1502 . Specifically, decoder 412, 512, or 746 packs the half-size array 1502 as described above. During iterative processing of the HPC row data, the parity output by row parity generator 1524 is compared with the stored or transmitted parity, and if one or more parity errors are detected, conventional error correction circuitry corrects the indicated error(s) if possible. The decoded data may then be stored, transmitted, or otherwise processed.

[0073] As described above, in at least one embodiment, the encoder encodes input data using a binary symmetric invariant product code. The encoder includes a circuit comprising a half-size data array comprising a data field having D rows, each D row having storage for H bits. The encoder is configured to access the bits of each row of the product code by reading a first H-bit data word from one of the D rows (e.g., the first row) and reading a second H-bit data word across H different rows of the half-size data array. The encoder also includes: a register configured to receive the bits of each row of the product code and rotate the bits to obtain the rows of the product code; and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate column parity for parity bits for all rows of the product code based on the row parity.

[0074] The disclosed encoder performs encoding with significantly less logic than conventional techniques. The reduction in required logic can be attributed in part to eliminating the need to select input data from any arbitrary array position within the array storing the input data to be encoded. The disclosed encoder also eliminates the need to form a full-size data array including both input data and replicated data in order to calculate row and column parity. The disclosed encoder is capable of high performance and enables reading a full HPC row of data from a half-size array in a single cycle.

[0075] The present invention may be a system, method, and / or computer program product.The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.

[0076] Computer readable storage medium can be a tangible device that can retain and store the instructions used by the instruction execution device.Computer readable storage medium can be, for example but not limited to, electronic storage device, magnetic storage device, optical storage device, electromagnetic storage device, semiconductor storage device or any suitable combination of the above.The non-exhaustive list of more specific examples of computer readable storage medium includes the following items: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, such as punch card or the like or with the mechanical encoding device of the protruding structure in the groove of the instruction recorded thereon and any suitable combination of the above.Computer readable storage medium as used herein should not be interpreted as transient signal itself, such as radio wave or other free propagating electromagnetic wave, electromagnetic wave (for example, light pulse through fiber optic cable) propagated by waveguide or other transmission medium or the electric signal emitted by wire.

[0077] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network can include copper transmission cables, transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0078] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data or source code or object code written in any combination of one or more programming languages, these programming languages include object-oriented programming languages (such as Smalltalk, C++ etc.) and conventional procedural programming languages (such as " C " programming languages or similar programming languages). The computer-readable program instructions can be performed completely on the user's computer, partly on the user's computer, performed as an independent software package, partly on the user's computer, partly on a remote computer or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer by any type of network (including local area network (LAN) or wide area network (WAN)), or can be connected to an external computer (for example, using an internet service provider through the internet). In certain embodiments, the electronic circuit device comprising for example programmable logic circuit device, field programmable gate array (FPGA) or programmable logic array (PLA) can make the electronic circuit personalized to perform computer-readable program instructions by utilizing the state information of computer-readable program instructions, so as to perform various aspects of the present invention.

[0079] The present invention is described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0080] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner. Thus, the computer-readable storage medium having the instructions stored therein includes an article of manufacture containing instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0081] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0082] The flow charts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the systems, methods and computer program products according to different embodiments of the present invention. To this end, each box in the flow chart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified (multiple) logical function. In some alternative implementations, the functions annotated in the box may not occur in the order annotated in the figure. For example, depending on the functions involved, the two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the opposite order. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart, can be implemented using a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0083] Although the present invention has been specifically illustrated with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention. For example, although various aspects have been described with respect to a data storage system comprising a flash memory controller that directs certain functions, it will be understood that the present invention may alternatively be implemented as a program product comprising a storage device that stores program code that can be processed by a processor to perform such functions or to cause such functions to be performed. As used herein, a "storage device" is specifically limited to only including legal products and excluding the form of the signal medium itself, the transient propagation signal itself, and the energy itself.

[0084] The above-mentioned drawings and the following written description of specific structures and functions are not intended to limit the scope of the applicant's invention or the scope of the appended claims. Rather, the drawings and written description are provided to teach those skilled in the art to make and use the invention for which patent protection is sought. Those skilled in the art will understand that, for the sake of clarity and understanding, not all features of the commercial embodiments of the present invention are described or shown. Those skilled in the art will also recognize that the development of an actual commercial embodiment incorporating various aspects of the present invention will require many implementation-specific decisions to achieve the developer's ultimate goal for the commercial embodiment. Such implementation-specific decisions may include, but may not be limited to, compliance with system-related, business-related, government-related, and other constraints, which may vary with the specific implementation, location, and time. While the developer's efforts may be complex and time-consuming in an absolute sense, such efforts remain a routine task for those skilled in the art who have the benefit of this disclosure. It must be understood that the inventions disclosed and taught herein are susceptible to multiple and different modifications and alternative forms. Finally, the use of singular terms (such as, but not limited to, "a") is not intended to limit the number of items.

Claims

1. An encoder for encoding input data using a binary symmetric invariant product code, wherein each dimension of the binary symmetric invariant product code includes D data bits and P parity check bits, the encoder comprising a circuit device, the circuit device comprising: a half-size data array comprising D rows, the D rows each having storage for H bits of input data, wherein D is an integer equal to 2×H+1, and wherein the encoder is configured to access bits of each row of the binary symmetric invariant product code by reading a first H-bit data word from a selected one of the D rows of the half-size data array and reading a second H-bit data word across H different rows of the half-size data array; a register configured to: receive the bits of each row of the binary symmetric invariant product code and rotate the bits as needed to obtain the row of the binary symmetric invariant product code; a row parity generator coupled to the register and configured to generate a row parity for each row of the binary symmetric invariant product code; as well as A column parity generator is configured to generate column parities for the P parity bits of all rows of the binary symmetric invariant product code based on the row parities generated by the row parity generator.

2. The encoder of claim 1, wherein the binary symmetric invariant product code is a half product code (HPC).

3. The encoder of claim 1, wherein the half-size data array comprises a plurality of shift registers.

4. The encoder of claim 1 , wherein the encoder is configured to shift bits between rows of the half-sized data array and recycle the first H-bit data word read from the half-sized data array back into the half-sized data array.

5. The encoder of claim 4, wherein the encoder forms all rows of the binary symmetric invariant product code by reading the same set of bit storage locations within the half-sized data array. 6 . The encoder of claim 1 , wherein the encoder is configured to pack the half-sized data array with H bits of input data at a time.

7. The encoder of claim 1, wherein the encoder is configured to output D sets of encoded data, each set of encoded data comprising H data bits and P parity bits. 8 . The encoder according to claim 7 , wherein the encoder is further configured to output P×(P−1) / 2 cross-parity check bits.

9. A data storage system comprising: non-volatile memory systems; as well as A controller coupled to the non-volatile memory system, wherein the controller comprises an encoder according to any one of claims 1 to 8.

10. A data communication system comprising: An encoder according to any one of claims 1 to 8; as well as A modulator is configured to receive the encoded data from the encoder, modulate the encoded data, and output the modulated encoded data on a communication channel.

11. A method for encoding a binary symmetric invariant product code, wherein each dimension of the binary symmetric invariant product code includes D data bits and P parity check bits, the method comprising: packing the input data in a half-size data array comprising D rows, each row having storage for H bits of the input data, where D is an integer equal to 2×H+1; iteratively accessing bits of each row of the binary symmetric invariant product code by reading a first H-bit data word from a selected one of the D rows of the half-sized data array and reading a second H-bit data word across H different rows of the half-sized data array; rotating the bits of each row of the binary symmetric invariant product code as needed to obtain the row of the binary symmetric invariant product code; generating a row parity for each row of the binary symmetric invariant product code, and generating a column parity for the P parity bits of all rows of the binary symmetric invariant product code based on the row parity generated by the row parity generator; and The first H-bit data word, row parity, and column parity are output.

12. The method of claim 11, wherein the binary symmetric invariant product code is a half product code (HPC).

13. The method of claim 11, wherein packing the half-size data array comprises packing a plurality of shift registers.

14. The method according to claim 11, further comprising: shifting bits between rows of the half-sized data array; as well as The first H-bit data word accessed from the half-sized data array is recycled back into the half-sized data array.

15. The method of claim 14, wherein the accessing comprises forming all rows of the binary symmetric invariant product code by reading a same set of bit storage locations within the half-sized data array.

16. The method of claim 11, wherein the packing comprises packing the half-sized data array with H bits of input data at a time.

17. The method of claim 11, wherein outputting the column parity comprises outputting P x (P-1) / 2 cross parity bits.

18. The method of claim 11 and further comprising storing the first H-bit data word, row parity, and column parity in a non-volatile memory system.

19. The method according to claim 11, further comprising: Modulating coded data including the first H-bit data word, row parity, and column parity, and transmitting the modulated coded data over a communication channel.

20. A computer program product comprising a computer-readable storage medium having computer-readable program instructions stored thereon, which, when the computer-readable program instructions are executed on a computer, cause the computer to perform the method according to any one of claims 11 to 19.

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