Light emitting element and method for manufacturing the same

Abstract

Improve the luminous efficiency of a light-emitting element. A light-emitting element comprising: a first InAs layer which is undoped or doped with an n-type dopant; y Sb 1‑y and a second InAs layer doped with a p-type dopant, wherein an Al layer having a thickness of 5 to 40 nm is provided between the active layer and the second InAs layer. x In 1‑x As electron blocking layer (0.05≤x≤0.40).

Description

Technical Field

[0001] The present invention relates to a light-emitting element and a manufacturing method thereof, and in particular to a semiconductor light-emitting element that emits infrared light. Background Art

[0002] In the past, semiconductor light-emitting elements that emit light or receive light in the mid-infrared region, such as semiconductor light-emitting elements that emit light in the mid-infrared region with a wavelength of 1700 nm or more and semiconductor light-receiving elements that detect light in the mid-infrared region, are known. For example, semiconductor light-emitting elements that emit light in the mid-infrared region are widely used in sensors, gas analysis, and the like.

[0003] When the wavelength of light received by such semiconductor optical devices is set to the mid-infrared region of 1.7 μm to 12 μm, usually, compound semiconductor substrates such as GaAs, InP, InAs, GaSb, and InSb are used as growth substrates in order of the smallest lattice constant, and a combination of mixed crystals of these compounds is epitaxially grown on the growth substrate to form the substrate. Among these compound substrates, the lattice constant of the light-emitting layer in the mid-infrared region of 1.7 μm to 12 μm is close to that of the InAs, GaSb, and InSb compound substrates. Therefore, it can be considered that InAs, GaSb, and InSb are preferably used as growth substrates for semiconductor optical devices in the mid-infrared region.

[0004] For example, in Patent Document 1, an InAsSbP active layer is formed after an InSbP barrier layer is formed on an InAs substrate. Alternatively, an InAsSb active layer is formed after an InSbP barrier layer is formed on an InAs substrate. In Patent Document 1, an InAs substrate having conductivity for a wavelength of 2.6 μm to 4.7 μm is directly used for a light-emitting element.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application No. 2015-534270 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In recent years, in order to improve the performance of sensors and gas analyzers, etc., mid-infrared light emitting elements need to improve their luminous efficiency (WPE: Wall-Plug Efficiency), that is, the ratio of light output to total input power.

[0010] Therefore, an object of the present invention is to provide a light emitting element and a method for manufacturing the same which can improve the light emitting efficiency of a light emitting element having an InAsSb light emitting layer even in a semiconductor optical device.

[0011] Solutions for solving problems

[0012] The present inventors have conducted intensive research on solutions to the above-mentioned technical problems and have conceived the idea of ​​providing an AlInAs electron blocking layer between the active layer and the p-type InAs layer, thereby completing the present invention. That is, the gist of the present invention is as follows.

[0013] (1) A light emitting element, characterized by comprising a semiconductor stack, wherein the semiconductor stack comprises:

[0014] A first InAs layer which is undoped or doped with an n-type dopant;

[0015] Contains InAs y Sb 1-y The active layer of the layer (0<y<1);

[0016] Al with a film thickness of 5 to 40 nm x In 1-x As electron blocking layer (0.05≤x≤0.4); and

[0017] The second InAs layer is doped with a p-type dopant.

[0018] (2) The light-emitting element according to (1) above, wherein:

[0019] The aforementioned active layer also has InAs z P 1-z Layer (0<z<1),

[0020] The active layer has the InAs y Sb 1-y The layer is a well layer, with the aforementioned InAs z P 1-z The layer is a quantum well structure with a barrier layer.

[0021] (3) The light-emitting element according to (1) or (2) above, wherein:

[0022] The light radiated from the active layer has a peak emission wavelength of 3.4 μm or more.

[0023] (4) The light-emitting element according to any one of (1) to (3) above, wherein:

[0024] In the aforementioned Al x In 1-x The As electron blocking layer is doped with a Zn dopant.

[0025] (5) The light-emitting element according to any one of (1) to (4) above, comprising:

[0026] support base plate;

[0027] A metal bonding layer disposed on the surface of the supporting substrate;

[0028] The power distribution part on the metal bonding layer has a transparent insulating layer with a through hole and an ohmic electrode part provided in the through hole;

[0029] The semiconductor stack is provided on the power distribution unit.

[0030] (6) A method for manufacturing the light-emitting element described in (1) above, characterized in that the method comprises:

[0031] A step of forming the first InAs layer;

[0032] forming the active layer on the first InAs layer;

[0033] The Al x In 1-x As electron blocking layer step; and

[0034] In the aforementioned Al x In 1-x A step of forming the second InAs layer on the As electron blocking layer.

[0035] (7) A method for manufacturing the light-emitting element described in (1) above, characterized in that the method comprises:

[0036] A step of forming the second InAs layer;

[0037] The Al layer is formed on the second InAs layer. x In 1-x As electron blocking layer process;

[0038] In the aforementioned Al x In 1-x The step of forming the aforementioned active layer on the As electron blocking layer; and

[0039] A step of forming the first InAs layer on the active layer.

[0040] Effects of the Invention

[0041] According to the present invention, a light-emitting element capable of improving light-emitting efficiency and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic cross-sectional view for explaining the first embodiment of the light emitting element of the present invention.

[0043] Figure 2 It is a schematic cross-sectional view for explaining a second embodiment of the light emitting element of the present invention.

[0044] Figure 3 It is a schematic cross-sectional view for explaining a modified form of the second embodiment of the light emitting element of the present invention.

[0045] Figure 4 This is a schematic cross-sectional view for explaining an example of a method for manufacturing the light-emitting element according to the second embodiment of the present invention.

[0046] Figure 5 For Figure 4 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0047] Figure 6 For Figure 5 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0048] Figure 7 For Figure 6 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0049] Figure 8 For Figure 7 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0050] Fig. 9 For Figure 8 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0051] Fig.10 For Fig. 9 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0052] Fig.11 For Fig.10 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0053] Fig.12 For Fig.11 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0054] Fig.13 For Fig.12 The following is a schematic cross-sectional view illustrating an example of the manufacturing method.

[0055] Fig.14 A schematic plan view showing an example of the shape and arrangement of the ohmic electrode portion after the power distribution portion is produced in the second embodiment.

[0056] Fig.15 A schematic plan view showing an example of the shape and arrangement of the upper electrodes in the second embodiment. DETAILED DESCRIPTION

[0057] Before describing the embodiments of the present invention, the following contents will be described.

[0058] <Composition and film thickness>

[0059] First, in this specification, the composition of each III-V group element of AlInGaAsSbP can be measured by photoluminescence measurement and X-ray diffraction measurement. In addition, the total thickness of each layer formed can be calculated by observing the cross section with a scanning electron microscope or a transmission electron microscope. In addition, the thickness of each layer can be calculated by observing the cross section of the growth layer with a transmission electron microscope. In addition, when the thickness of each layer is small like a quantum well structure, TEM-EDS can be used to measure the thickness and composition of each layer. It should be noted that in the cross-sectional view, when a specified layer has an inclined surface, the thickness of the layer is the maximum height from the flat surface of the layer directly below the layer.

[0060] When a specific group III element or group V element is excluded from the label of "AlInGaAsSbP", the group III element or group V element excluded from the label is not included in the composition except for components accidentally mixed in such as diffusion from adjacent layers or element residues in the epitaxial growth device.

[0061] <p-type, n-type, and undoped, and dopant concentration>

[0062] In this specification, a layer that functions as a p-type semiconductor layer is defined as a p-type semiconductor layer, and a layer that functions as an n-type semiconductor layer is defined as an n-type semiconductor layer by adding impurities. On the other hand, the case where impurities such as Si, Zn, S, Sn, Mg, and Te are not intentionally added is referred to as "undoped". Specifically, the concentration of the specific impurity dopant that would not be mixed in without intentional addition is low (for example, less than 5×10 16 atoms / cm 3 ), it is treated as “undoped” in this specification. Furthermore, no impurities are intentionally added to the III-V compound semiconductor layer, and even if 5×10 16 atoms / cm 3 The above unavoidable impurities (O, C, H, etc.) are also considered as undoped. It should be noted that since InAs functions as an n-type layer even when undoped, the InAs layer undoped or doped with an n-type dopant functions as an n-type layer.

[0063] In addition, the values ​​of impurity concentrations such as Zn and Te were obtained by SIMS analysis. It should be noted that since the values ​​of dopant concentrations vary greatly near the boundaries of each semiconductor layer, the value of dopant concentration at the center of each layer in the film thickness direction is set as the value of dopant concentration of the layer.

[0064] Hereinafter, the light emitting element and the manufacturing method thereof of the present invention will be described in sequence with reference to the accompanying drawings. It should be noted that, for the same constituent element, in principle, the last two digits of the three-digit number are assigned the same reference number, and repeated description is omitted. In each figure, for the convenience of explanation, the aspect ratio of the substrate and each layer is enlarged compared to the actual ratio.

[0065] (First embodiment)

[0066] Reference Figure 1 , a light emitting element 100 as a first embodiment of the light emitting element of the present invention is described. The light emitting element 100 includes at least a semiconductor stack 140, which includes, in order: a first InAs layer 141 which is undoped or doped with an n-type dopant; y Sb 1-y Active layer 145 of layer 145w (0<y<1); Al with a film thickness of 5 to 40 nm x In 1-x As electron blocking layer 146 (0.05≤x≤0.4); and a second InAs layer 147 doped with a p-type dopant. Figure 1 In the embodiment, the upper electrode 191 is provided on the second InAs layer 147 in the semiconductor stack 140, and the semiconductor stack 140 is provided on the substrate 105. In addition, a back surface electrode 195 is provided on the back surface of the substrate 105.

[0067] <Substrate>

[0068] Here, the substrate 105 may be a substrate having a thickness capable of mechanically maintaining the shape of the semiconductor stack 140 including the active layer 145, or may be a growth substrate for epitaxial growth when forming the semiconductor stack 140 of the light emitting element 100, or may refer to Figure 2 , Figure 3As in another example of the light emitting element 200 described later, a support substrate 280 different from the InAs growth substrate 210 is used. As the growth substrate, a compound substrate such as GaAs, InP, InAs, GaSb, InSb, etc. can be used. When forming the first InAs layer 141 and the second InAs layer 147, an InAs substrate is preferably used. As the support substrate, it is preferred that it is cheaper than the growth substrate and has higher thermal conductivity. For example, in addition to compound substrates such as Si, Ge, and GaAs, a metal substrate using a metal capable of suppressing the thermal expansion coefficient such as copper alloy, molybdenum, tungsten, and Kovar alloy, and a sub-mounting substrate in which a metal is attached to a ceramic substrate such as AlN can be used.

[0069] <Active layer>

[0070] The active layer 145 includes InAs y Sb 1-y Layer (0<y<1), InAs y Sb 1-y The layer becomes the light-emitting layer. Figure 1 In the example, the active layer also has InAs z P 1-z Layer 145b (0<z<1), InAs y Sb 1-y Layer 145w is a well layer with InAs z P 1-z Layer 145b is a quantum well structure of a barrier layer, and the active layer 145 can also be InAs y Sb 1-y However, in order to improve light output by suppressing crystal defects, the active layer 145 preferably has Figure 1 Such a multi-quantum well (MQW) structure can be formed by a structure in which the well layers and the barrier layers are alternately repeated.

[0071] - Active layer composition and peak emission wavelength -

[0072] InAs as well layer y Sb 1-y The As composition y of the layer 145w is preferably set to 0.7≤y<1.0, and more preferably set to 0.80≤y≤0.95. z P 1-zThe As composition z of layer 145b is preferably set to 0.50≤z<1, and more preferably to 0.8≤z<1≤0.95. It should be noted that in the case of a quantum well structure, in addition to changing the composition, it is also preferred to adjust the difference in composition between the well layer 145w and the barrier layer 145b to impart strain to the well layer. By changing the composition of the above-mentioned active layer 145, the peak wavelength of light emission of the light-emitting element 100 can be set to 1700~12000nm (1.7~12μm). The peak wavelength of light emission of the light-emitting element 100 can be set to above 3.1μm, and is preferably set to above 3.4μm.

[0073] <AlInAs electron blocking layer>

[0074] In the light emitting element 100, an Al layer with a thickness of 5 to 40 nm is provided between the active layer 145 and the second InAs layer 147. x In 1-x The As electron blocking layer 146 (0.05≤x≤0.40) can improve the light emission efficiency.

[0075] -Al composition x-

[0076] Al x In 1-x The Al composition x of the As electron blocking layer 146 is greater than 0.05 and less than 0.40, and more preferably greater than 0.10 and less than 0.35. This is because when the Al composition x is greater than 0.40, the forward voltage becomes higher and the luminous efficiency decreases, and when it is less than 0.05, the effect of improving the luminous efficiency by the electron blocking layer may not be obtained.

[0077] -Film thickness-

[0078] Al x In 1-x The thickness of the As electron blocking layer 146 is 5 to 40 nm, more preferably 10 to 35 nm. This is because when it is thicker than 40 nm, the forward voltage becomes higher and the luminous efficiency decreases, and when it is thinner than 5 nm, the electron blocking layer may not improve the luminous efficiency.

[0079] -Dopant-

[0080] Al x In 1-x The As electron blocking layer can be undoped or doped with a p-type dopant. Comparing the undoped and p-doped cases, the p-doped case has a greater effect on improving the luminous efficiency and is more preferred. Zn is particularly preferred as the p-type dopant. It should be noted that if the impurity concentration of the p-type dopant measured by SIMS analysis is set to 1×10 18 atoms / cm 3 Above and 8×10 18atoms / cm 3 Below, the effect of further improving the luminous efficiency can be reliably obtained, and more preferably 2×10 18 atoms / cm 3 above.

[0081] Hereinafter, specific forms applicable to the light emitting element 100 will be described in more detail.

[0082] <<InAs growth substrate>>

[0083] As an InAs growth substrate that can be suitably used as the substrate 105, a generally available n-type InAs substrate or an undoped InAs substrate can be used. Alternatively, a p-type InAs substrate can be used. In this case, Figure 1 Different from the substrate 105, the second InAs layer 147, Al x In 1-x The As electron blocking layer 146 , the active layer 145 , and the first InAs layer 141 may be used.

[0084] <<Semiconductor stack>>

[0085] In the semiconductor stack 140, a double heterogeneous (DH) structure may be provided in which the active layer 145 is sandwiched between the first InAs layer 141 and the second InAs layer 147. Figure 1 For convenience, the substrate 105 as the growth substrate and the first InAs layer 141 are shown separately. However, if the growth substrate is undoped or n-type, the growth substrate can also be directly used as the first InAs layer 141. As described above, the semiconductor stack 140 has Al x In 1-x As electron blocking layer 146 can improve light emitting efficiency.

[0086] The light emitting element 100 can be manufactured by the following steps, i.e., a step of forming the first InAs layer 141, a step of forming the active layer 145 on the first InAs layer 141, a step of forming the AlAs layer on the active layer 145, and a step of forming the InAs layer 141 on the active layer 145. x In 1-x As electron blocking layer 146 process, in Al x In 1-xOn the other hand, if the InAs growth substrate used for epitaxially growing each semiconductor layer of the semiconductor stack 140 is a p-type, the semiconductor stack 140 can be manufactured by the following steps, namely, the step of forming the second InAs layer 147, the step of forming Al on the second InAs layer 147, and the step of forming the second InAs layer 147. x In 1-x As electron blocking layer 146 process, in Al x In 1-x A step of forming the active layer 145 on the As electron blocking layer 146 , and a step of forming the first InAs layer 141 on the active layer 145 .

[0087] -Method for growing semiconductor stack-

[0088] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, by using trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) or triethyl gallium (TEGa) as a Ga source, trimethyl aluminum (TMAl) as an Al source, arsine (AsH3), tert-butyl arsenide (TBAs) as an As source, trimethyl antimony (TMSb), triethyl antimony (TESb), tris (dimethylamino) antimony (TDMASb) as an Sb source, phosphine (PH3), tert-butyl phosphine (TBP) as a P source in a prescribed mixing ratio, and by gas-phase growth of these raw material gases while using a carrier gas, it can be formed with a desired thickness according to the growth time. When each layer is doped into p-type or n-type, it is sufficient to further use a desired dopant source gas. For example, when doping with Zn, DEZn (diethyl zinc) gas may be used. As described above, InAs becomes n-type even when not doped.

[0089] -Other semiconductor layers in the semiconductor stack-

[0090] Although not shown in the figure, the semiconductor stack 140 is preferably provided on the side of the second InAs layer 147 opposite to the active layer 145 (ie, Figure 1 The semiconductor stack 140 may further include a contact layer that can reduce the contact resistance with the electrode. x In 1-x There is an undoped isolation layer (eg, an undoped InAs layer) between the As electron blocking layers.

[0091] -Thickness of semiconductor stacked body-

[0092] The overall film thickness of the semiconductor stack 140 is not limited, and can be set to 2 μm to 8 μm, for example. In addition, the film thickness of the first InAs layer 141 is not limited, and can be set to 0.1 μm to 5 μm, for example. In addition, the film thickness of the active layer 145 is not limited, and can be set to 3 nm to 3000 nm, for example. In addition, the film thickness of the second InAs layer 147 is not limited, and can be set to 0.1 μm to 3 μm, for example. When the active layer 145 has a quantum well structure, the InAs layer 147 as the well layer can be formed. y Sb 1-y The film thickness of the layer 145w is set to 3nm to 20nm, and the InAs z P 1-z The thickness of the layer 145b is set to 5 to 50 nm, and the number of sets of the well layers and barrier layers is set to 1 to 50.5 sets. When N sets (N is an integer) of well layers and barrier layers are alternately stacked after forming the barrier layers, a total of N.5 sets are formed.

[0093] -electrode-

[0094] In addition, if Figure 1 As shown, it is possible to form a semiconductor stack 140 ( Figure 1 The upper electrode 191 is formed on the second InAs layer 147 of the substrate 105, and the back electrode 195 is provided on the back side of the substrate 105. The upper electrode 191 may include a wiring portion and a pad portion. Although the pad portion is not shown, a bonding metal layer and solder may be added to the ohmic electrode. The upper electrode 191 and the back electrode 195 may use known metal materials and formation methods. As metal materials, Ti, Pt, Au, Ag, Al, Zn, Ni, etc. may be used. As a formation method, for example, sputtering, electron beam evaporation, or resistance heating may be used in combination with photolithography, a metal mask, etc.

[0095] (Second embodiment)

[0096] Reference Figure 2, a light-emitting element 200 according to a second embodiment of the present invention is described. The light-emitting element 200 is a junction-type light-emitting element obtained by removing a growth substrate on the basis of a junction support substrate. As described above, for the same components as the light-emitting element 100, in principle, the last two digits of the three-digit number are assigned the same reference number, and repeated descriptions are omitted. The light-emitting element 200 comprises at least: a support substrate 280; a metal bonding layer 279, which is disposed on the surface of the support substrate 280; a power distribution portion 260 on the metal bonding layer 279, which has a transparent insulating layer 261 having a through hole and an ohmic electrode portion 265 disposed in the through hole; and a semiconductor stack 240, which is disposed on the power distribution portion 260. The semiconductor stack 240 in the light-emitting element 200 comprises, in order from the side opposite to the support substrate 280, a first InAs layer 241, an active layer 245, an Al x In 1-x As electron blocking layer 246 and second InAs layer 247. It should be noted that Figure 3 In the light emitting element 300 shown in FIG. 1 , the semiconductor stack 340 includes a first InAs layer 341, an active layer 345, an Al x In 1-x As electron blocking layer 346 and second InAs layer 347 .

[0097] Back to Figure 2 After the support substrate 280 is bonded, the InAs growth substrate 210 (see Figure 4 ) of the present embodiment also has an Al layer with a thickness of 5 to 40 nm between the active layer 245 and the second InAs layer 247. x In 1- x As electron blocking layer 246 (0.05≤x≤0.4) can improve the luminous efficiency. Figures 4 to 15 , an example of an implementation of the light emitting element 200 and a method for manufacturing the same will be described in more detail.

[0098] Reference Figure 4 First, prepare the InAs growth substrate 210. Then, refer to Figure 5 An initial buffer layer 220 made of InAs is formed on the InAs growth substrate 210, and an etching stop layer 230 made of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb is formed. The formation of the initial buffer layer 220 may be omitted.

[0099] <Formation of Etching Stop Layer>

[0100] The etching stop layer 230 is a semiconductor layer whose etching rate is sufficiently low relative to the etching solution (concentrated hydrochloric acid with a concentration of 8M (mol / L) or more) when etching the InAs growth substrate 210 and which is insoluble before the InAs growth substrate 210 is completely removed. In addition, the etching stop layer 230 has a lattice constant that allows it to be grown on the InAs growth substrate 210.

[0101] Set the As component to x E When the composition range of the GaAsSb-based III-V compound semiconductor of the etching stop layer 230 is expressed as GaAs xE Sb 1-xE . And, As forms x E Preferably 0≤x E ≤0.4. As composition x E When it is greater than 0.4, the above etching solution may also be etched, and As constitutes x E When the thickness is within this range, the etching stop layer has the property of being insoluble in the above-mentioned etching solution and can be epitaxially grown on the InAs growth substrate 110. More preferably, 0.02≤x E ≤0.13. As composition x E When the lattice constant difference with the InAs growth substrate 210 can be reduced. Figure 5 As shown, the etching stop layer 230 is preferably a superlattice structure in which two types of GaAsSb-based III-V compound semiconductors 230 a and 230 b having different As compositions are repeatedly stacked.

[0102] <Formation of semiconductor stack>

[0103] Next, refer to Figure 6 A semiconductor stack 240 is formed on the etching stop layer 230. Similar to the semiconductor stack 140, the isolation layer and the contact layer may be formed when the semiconductor stack 240 is formed.

[0104] <Formation of the power distribution unit>

[0105] Reference Figure 7 A transparent insulating layer 261 ( 261A) having a through hole 261A is formed on the second InAs layer 247 (on the contact layer when a contact layer is further provided). Figure 8 ) and the power distribution unit 260 ( Fig. 9 The specific method of forming the power distribution unit 260 is arbitrary, and the following reference is made to Figure 7 to Figure 9 An example of a specific form of forming the power distribution unit 260 will be described.

[0106] First, a transparent insulating layer 261 is formed on the semiconductor stack 240 ( Figure 7As a film forming method, a known method such as a plasma CVD method and a sputtering method can be applied. Then, a resist pattern is formed on the transparent insulating layer 261 using a photomask. Next, etching is performed using the resist pattern to remove a portion of the transparent insulating layer 261, thereby forming a through hole 261A ( Figure 8 ). By providing the through hole 261A, a part of the outermost region of the semiconductor stack 240 is exposed. Then, if the ohmic electrode portion 265 is formed into a film and then peeled off using the resist pattern, the power distribution portion 260 ( Fig. 9 ). The transparent insulating layer 261 and the ohmic electrode portion 265 are arranged in parallel in the power distribution portion 260. It should be noted that, here, the resist pattern when etching the transparent insulating layer 261 and the resist pattern when stripping the ohmic electrode portion 265 can be the same, or they can be re-patterned. It should be noted that, for the sake of simplicity in the accompanying drawings, the ohmic electrode portion is shown in a manner of filling the through hole 261A, but is not limited to this. Although not shown in the figure, a gap can be generated between the transparent insulating layer 261 and the ohmic electrode portion by using a combination of resist patterns and resist patterns to expand the etching to the portion covered by the resist pattern during etching.

[0107] The ohmic electrode portion 265 can be formed by dispersing in a predetermined pattern into an island shape. An example of the pattern of the ohmic electrode portion 265 in this embodiment is shown in FIG. Fig.14 An example of the pattern of the upper electrode 291 to be formed later is shown by a dotted line. Fig.14 As the ohmic electrode portion 265, for example, Au, AuZn, AuBe, AuTi, etc. can be used, and a stacked structure of these can also be preferably used. For example, Ti / Au can be used as the ohmic electrode portion 265. The film thickness (or total film thickness) of the ohmic electrode portion 265 is not limited, and can be set to 300 to 1300 nm, and more preferably 350 nm to 800 nm.

[0108] It should be noted that, although not shown in the figure, the relationship between the film thickness H1 of the transparent insulating layer 261 and the film thickness H2 of the ohmic electrode portion 265 can be set to H1≥H2, and preferably to H1>H2. Under this condition, the film thickness of the transparent insulating layer 261 can be set to, for example, 360nm to 1600nm, and more preferably to 410nm to 1100nm. In addition, it is also preferred to set the difference H1-H2 between the film thickness H1 of the transparent insulating layer 261 and the film thickness H2 of the ohmic electrode portion 265 to be greater than 10nm and less than 100nm. In addition, in the case where a contact layer is also provided as described above, it can be formed in a manner that the contact layer remains only in the through hole 261A. In this case, the total thickness of the contact layer and the ohmic electrode portion can be set to the film thickness H2.

[0109] As the transparent insulating layer 261, SiO2, SiN, ITO, Al2O3, AlN, or the like can be used. In particular, the transparent insulating layer 261 is preferably made of SiO2 because SiO2 can be easily etched using BHF or the like.

[0110] <Formation of Metal Reflective Layer>

[0111] like Fig.10 As shown, it is also preferred to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 may include multiple metal layers, and the metal constituting the metal reflective layer 271 may include Al, Pt, Ti, Ag, etc. in addition to Au. For example, the metal reflective layer 271 may be a single layer consisting only of Au, and the metal reflective layer 271 may also include more than two Au metal layers. The metal reflective layer 271 preferably has more than 50 mass % of Au in the composition of the metal reflective layer 271. In order to reliably perform bonding with the metal bonding layer 279 in the subsequent process, it is preferred that the outermost layer of the metal reflective layer 271 (the surface on the side opposite to the semiconductor stack 240) is set to an Au metal layer.

[0112] For example, each metal layer may be formed in the order of Al, Au, Pt, and Au on the power distribution unit 260 (including the gap when the gap is provided), and the metal reflective layer 271 may be formed. The thickness of one Au metal layer in the metal reflective layer 271 may be set to, for example, 400 nm to 2000 nm, and the thickness of the metal layer composed of metals other than Au may be set to, for example, 5 nm to 200 nm. The metal reflective layer 271 may be formed by forming a film using a conventional method such as a vapor deposition method.

[0113] <Bonding with Support Substrate>

[0114] Reference Fig.11 The semiconductor stack 240 and the power distribution unit 260 are bonded to the support substrate 280 at least by means of the metal bonding layer 279. When the metal reflective layer 271 is provided, the metal reflective layer 271 can be bonded to the metal bonding layer 279. The metal bonding layer 279 and the metal reflective layer 271 can be bonded by arranging them opposite to each other and bonding them by heating and compression bonding at a temperature of about 250°C to 500°C.

[0115] <<Metallic bonding layer>>

[0116] The metal bonding layer 279 can be formed using metals such as Ti, Pt, Au, metals that form a eutectic alloy with Au (Sn, etc.), and solder, and it is preferred that these be stacked to form the metal bonding layer 279. For example, the metal bonding layer 279 can be formed by stacking Ti with a thickness of 400nm to 800nm, Pt with a thickness of 5nm to 20nm, and Au with a thickness of 700 to 1200nm in order from the surface of the support substrate 280. For example, when the metal reflective layer 271 is bonded to the metal bonding layer 279, the outermost layer of the metal bonding layer 279 can be set to Au metal, and the outermost layer of the metal reflective layer 271 can also be set to Au, and the Au can be bonded to each other by Au-Au diffusion.

[0117] <<Support substrate>>

[0118] The supporting substrate 280 may be a substrate different from the InAs growth substrate 210, and a sub-mounting substrate based on the above-mentioned semiconductor substrate, metal substrate, ceramic substrate, etc. may be used. Due to the use of the above-mentioned bonding method, the supporting substrate 280 may be lattice mismatched with each semiconductor layer formed in this embodiment. It should be noted that the supporting substrate 280 may be insulating depending on the purpose, but is preferably a conductive substrate. From the perspective of processability and price, it is preferred to use a Si substrate for the supporting substrate 280. By using a Si substrate, the thickness of the supporting substrate 280 can also be significantly smaller than the previous thickness, and it is also suitable for combined installation with various semiconductor devices. In addition, compared with the InAs substrate, the Si substrate is also advantageous in terms of heat dissipation.

[0119] <Removal of InAs growth substrate>

[0120] Reference Fig.12 , after bonding the support substrate 280, the InAs growth substrate 210 is removed. As a method of removing the InAs growth substrate 210 using the etching stop layer 230, the InAs growth substrate 210 may be etched only with concentrated hydrochloric acid, and an etching solution other than concentrated hydrochloric acid may be used in the stage before the etching stop layer is exposed. Fig.13 , the initial buffer layer 220 and the etching stop layer 230 can be removed in sequence after removing the InAs growth substrate 210. It should be noted that, since the etching stop layer 230 is a GaAsSb-based III-V compound semiconductor, it cannot be removed by concentrated hydrochloric acid, unlike the InAs growth substrate 210. For example, the etching stop layer 230 can be removed by wet etching using an ammonia-hydrogen peroxide mixture.

[0121] -Electrode formation process-

[0122] In addition, if Fig.15 and the above reference Figure 2 As shown, it is possible to form a semiconductor stack 240 ( Figure 2 The upper electrode 291 is formed on the first InAs layer 141 of the support substrate 280, and the back electrode 195 is formed on the back of the support substrate 280. The upper electrode 291 may include a wiring portion and a pad portion. The upper electrode 291 and the back electrode 295 may be formed using a known method, such as sputtering, electron beam evaporation, or resistance heating.

[0123] Through the above manufacturing method, it can be obtained Figure 2 As shown in FIG. 2 , the method for manufacturing the light emitting element 200 at least includes: forming a first InAs layer 241, forming an active layer 245 on the first InAs layer 241, and forming Al on the active layer 245. x In 1-x As electron blocking layer 246 process, and Al x In 1-x The second InAs layer 247 is formed on the As electron blocking layer 246. The formation method of each structure is performed in the same manner as that of the light emitting element 200. Figure 3 The manufacturing method of the light emitting element 300 shown in the figure at least includes the steps of forming a second InAs layer 347, forming an Al x In 1- x As electron blocking layer 346 process, in Al x In 1-x The step of forming the active layer 345 on the As electron blocking layer 346 and the step of forming the first InAs layer 341 on the active layer 345. When manufacturing the light emitting elements 200 and 300, the above steps including forming an etching stopper layer and removing the growth substrate using the etching stopper layer may be appropriately performed.

[0124] Example

[0125] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples.

[0126] [Experimental Example 1]

[0127] (Example 1)

[0128] First, a 100 nm undoped InAs layer was formed on the (100) surface of an undoped InAs substrate (substrate thickness: 475 μm). Next, the following active layers were formed on the undoped InAs layer using the MOCVD method: a quantum well structure active layer with a main emission wavelength of 4.5 μm, a Zn-doped p-type Al 0.15 In 0.85 As electron blocking layer (thickness 15nm, Zn concentration 4×10 18atoms / cm 3 ), Zn-doped p-type InAs layer (thickness 1 μm, Zn concentration 4.8×10 18 atoms / cm 3 ). It should be noted that when forming the active layer of the quantum well structure, when forming the InAs 0.99 P 0.01 After the barrier layer (thickness 30nm), InAs 0.85 Sb 0.15 Well layer (thickness 10nm) and InAs 0.99 P 0.01 The barrier layers (thickness 30 nm) were alternately stacked in order, 40 layers each, and 40.5 sets including the first barrier layer were set. It should be noted that, as described in the embodiment, both the undoped InAs substrate and the InAs layer were of electrical n-type.

[0129] Next, the resist pattern is formed, the electrode metal is evaporated, and the resist pattern is peeled off to refer to Fig.15 The pattern of the upper electrode 291 forms a p-type ohmic electrode (Ti / Au, total thickness: 1400nm) on the p-type InAs layer. However, no Fig.15 The ohmic electrode portion 265 is shown.

[0130] Next, a back electrode (Ti / Au, total thickness: 210 nm) was formed on an undoped InAs substrate by evaporation and heat treated at 300°C for 1 minute for alloying. Then, the chip was singulated by dicing to produce the infrared light-emitting element involved in Example 1. It should be noted that the chip size was 500 μm×500 μm.

[0131] (Example 2)

[0132] In Example 1, a Zn-doped p-type Al 0.15 In 0.85 As electron blocking layer, in addition to changing the Al composition to make Al 0.3 In 0.7 A light-emitting element according to Example 2 was produced in the same manner as in Example 1 except for As.

[0133] (Example 3)

[0134] In Example 1, a Zn-doped p-type Al 0.15 In 0.85 As electron blocking layer, in addition to changing the Al composition to make Al 0.075 In 0.925 A light-emitting element according to Example 3 was produced in the same manner as in Example 1 except for As.

[0135] (Example 4)

[0136] In Example 1, a Zn-doped p-type Al layer was formed with a film thickness of 15 nm. 0.15 In 0.85 A light-emitting element according to Example 4 was produced in the same manner as in Example 1 except that the film thickness of the As electron blocking layer was changed to 30 nm.

[0137] (Example 5)

[0138] In Example 1, a Zn-doped p-type Al layer was formed with a film thickness of 15 nm. 0.15 In 0.85 A light-emitting element according to Example 5 was produced in the same manner as in Example 1 except that the film thickness of the As electron blocking layer was changed to 7.5 nm.

[0139] (Example 6)

[0140] In Example 1, a Zn-doped p-type Al 0.15 In 0.85 As electron blocking layer, 5cc of DEZn (diethyl zinc) gas was flowed as Zn doping gas, except that DEZn gas was not flowed to form undoped Al 0.15 In 0.85 A light-emitting element according to Example 6 was produced in the same manner as in Example 1 except for the As electron blocking layer.

[0141] (Comparative Example 1)

[0142] In Example 1, a Zn-doped p-type Al layer was formed with a film thickness of 15 nm. 0.15 In 0.85 A light emitting element according to Comparative Example 1 was produced in the same manner as in Example 1 except that the As electron blocking layer was not formed and a p-type InAs layer was formed right above the active layer.

[0143] (Comparative Example 2)

[0144] In Example 1, a Zn-doped p-type Al 0.15 In 0.85 As electron blocking layer, in addition to changing the Al composition to make Al 0.60 In 0.40 The light emitting element according to Comparative Example 2 was prepared in the same manner as in Example 1 except for As.

[0145] (Comparative Example 3)

[0146] In Example 1, a Zn-doped p-type Al layer was formed with a film thickness of 15 nm. 0.15 In 0.85A light-emitting element according to Comparative Example 3 was produced in the same manner as in Example 1 except that the film thickness of the As electron blocking layer was changed to 60 nm.

[0147] <Evaluation: Light output evaluation>

[0148] A constant current voltage power supply was used to pass a current of 300 mA through the light-emitting elements obtained in Examples 1 to 6 and Comparative Example 3. The forward voltage Vf and the light-emitting output Po of the integrating sphere at each point were measured. The results are shown in Tables 1 to 3. It should be noted that each table also shows the light-emitting peak wavelength (λ p ) and luminous efficiency WPE(=Po / (I f ·V f )).

[0149] [Table 1]

[0150]

[0151] [Table 2]

[0152]

[0153] [Table 3]

[0154]

[0155] From the results of Examples 1 to 6 and Comparative Examples 1 to 3, it can be seen that by forming an Al layer with a thickness of 5 to 40 nm between the active layer and the p-type InAs layer (the second InAs layer in the embodiment), x In 1-x As electron blocking layer (0.05≤x≤0.4) can improve the luminous efficiency (WPE). In order to improve the luminous efficiency, the film thickness and Al composition x need to meet the conditions of the present invention. In addition, from the comparison results of Example 1 and Example 6, it can be seen that the electron blocking layer can obtain the luminous efficiency improvement effect even if it is not doped, but doping with Zn can further improve the luminous efficiency.

[0156] [Experimental Example 2]

[0157] In Experimental Example 1, a light emitting element was evaluated when an InAs substrate as a growth substrate was used as a substrate. Next, a junction type light emitting element was produced in which an InAs substrate was used as a growth substrate but the substrate was removed.

[0158] (Example 7)

[0159] First, a 100 nm undoped InAs layer was formed on the (100) plane of an undoped InAs substrate (substrate thickness: 475 μm). Next, 113 pairs of undoped GaSb layers (film thickness 0.9 nm) and GaAs layers were stacked. 0.34 Sb 0.66 Next, after forming a Te-doped n-type InAs layer (thickness 1 μm) on the superlattice stack, the following are sequentially formed by MOCVD in the same manner as in Example 1: an active layer of a quantum well structure with a main emission wavelength of 4.5 μm, a p-type Al doped with Zn, and a quartz crystal structure with a thickness of 0.1 nm. 0.15 In 0.85 As electron blocking layer (thickness 15nm, Zn concentration 4×10 18 atoms / cm 3 ), Zn-doped p-type InAs layer (thickness 1 μm, Zn concentration 4.8×10 18 atoms / cm 3 ). It should be noted that when forming the active layer of the quantum well structure, when forming the InAs 0.99 P 0.01 After the barrier layer (thickness 30nm), InAs 0.85 Sb 0.15 Well layer (thickness 10nm) and InAs 0.99 P 0.01 The barrier layers (film thickness 30 nm) were alternately stacked in order, 40 layers each, and 40.5 sets including the first barrier layer were set.

[0160] Next, a transparent insulating layer (thickness: 550 nm) made of SiO2 is formed on the entire surface of the p-type InAs layer by a plasma CVD method. Fig.14 The pattern shown in FIG. 1 is formed by removing part of SiO2 by wet etching with BHF to form a through hole, exposing the p-type InAs layer. Next, a p-type ohmic electrode portion (Ti / Au, total thickness: 540nm) is vapor-deposited in the through hole and the resist pattern is peeled off to form a transparent insulating layer and a p-type ohmic electrode portion in parallel to form a power distribution portion (which also serves as a current diffusion layer). It should be noted that the upper electrode to be formed later is indicated by a dotted line. Fig.14 middle.

[0161] Next, a metal reflective layer (Al / Au / Pt / Au) was formed on the entire surface of the power distribution unit by vapor deposition. The thickness of each metal layer of the metal reflective layer was 10 nm, 650 nm, 100 nm, and 900 nm, respectively.

[0162] On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on a conductive Si substrate (substrate thickness: 200 μm) as a support substrate. The thickness of each metal layer of the metal bonding layer was 650 nm, 20 nm, and 900 nm, respectively.

[0163] The metal reflective layer and the metal bonding layer were arranged opposite to each other and were heated and compressed at 300°C. Then, concentrated hydrochloric acid (manufactured by Kanto Chemical Co., Ltd.) with a concentration of 12M was poured into a beaker in a warm bath maintained at 25°C, and at least the InAs substrate, the initial buffer layer, and the etching stop layer were immersed in the concentrated hydrochloric acid for 10.5 hours to remove the InAs substrate and the initial buffer layer and to make the GaSb layer and the GaAs 0.34 Sb 0.66 The superlattice stacked body (etching stop layer) of the layer structure is exposed. Next, after washing with pure water and drying, the superlattice stacked body (etching stop layer) is removed by wet etching using an ammonia-hydrogen peroxide mixed solution to expose the n-type InAs layer.

[0164] Next, resist pattern formation, n-type electrode deposition, and resist pattern stripping are performed. Fig.15 The pattern shown in FIG. 1 forms an n-type electrode (Ti (film thickness: 150 nm) / Au (film thickness: 1250 nm)) on the n-type InAs layer. It should be noted that the pattern of the p-type ohmic electrode portion formed previously is shown by the dotted line. Fig.15 middle.

[0165] Finally, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the back side of the Si substrate and heat treated at 300°C for 1 minute for alloying. Then, the chip was singulated by dicing to produce the light-emitting element involved in Example 7. It should be noted that the chip size is 500 μm×500 μm.

[0166] <Evaluation>

[0167] A current of 300 mA was passed through the light emitting element of Example 7 using a constant current voltage power supply in the same manner as in Experimental Example 1. The forward voltage Vf at this time was 0.352 V, the light output Po of the integrating sphere was 75.3 μW, the peak wavelength λp was 4.2 μm, and the WPE was 0.0713%. Even in the case of removing the substrate and bonding to a supporting substrate, the light emitting efficiency can be improved by forming an electron blocking layer in the same manner as in Examples 1 to 6, compared to the case where the electron blocking layer is not formed.

[0168] Industrial Applicability

[0169] According to the present invention, a light-emitting element capable of improving light-emitting efficiency can be provided.

[0170] Description of Reference Numerals

[0171] 100 Light emitting elements

[0172] 105 substrate

[0173] 140 Semiconductor stack

[0174] 141 1st InAs layer

[0175] 145 Active layer

[0176] 145w InAs y Sb 1-y Layer (well layer)

[0177] 145b InAs z P 1-z Layer (barrier layer)

[0178] 146 Al x In 1-x As electron blocking layer

[0179] 147 2nd InAs layer

[0180] 191 Upper electrode

[0181] 195 Back electrode

[0182] 200 Light emitting elements

[0183] 210 InAs growth substrate

[0184] 220 Initial buffer layer

[0185] 230 Etch stop layer

[0186] 230a GaAsSb III-V compound semiconductor

[0187] 230b GaAsSb III-V compound semiconductor

[0188] 240 Semiconductor stack

[0189] 241 1st InAs layer

[0190] 245 Active layer

[0191] 246 Al x In 1-x As electron blocking layer

[0192] 247 2nd InAs layer

[0193] 260 Power Distribution Department

[0194] 261 Transparent insulation layer

[0195] 261A Through hole

[0196] 265 Ohm Electrode Section

[0197] 271 Metal reflective layer

[0198] 279 Metal bonding layer

[0199] 280 Support base plate

[0200] 291 Upper electrode

[0201] 295 Back electrode

[0202] 300 Light emitting elements

[0203] 340 Semiconductor stack

[0204] 341 1st InAs layer

[0205] 345 Active layer

[0206] 346 Al x In 1-x As electron blocking layer

[0207] 347 2nd InAs layer

[0208] 380 support base plate

Claims

1. A light emitting element, characterized in that: A semiconductor stack is provided, wherein the semiconductor stack comprises: A first InAs layer which is undoped or doped with an n-type dopant; Contains InAs y Sb 1-y The active layer of the layer (0<y<1); Al with a film thickness of 5 to 40 nm x In 1-x As electron blocking layer (0.05≤x≤0.4); and A second InAs layer doped with a p-type dopant.

2. The light-emitting element according to claim 1, wherein The active layer also has InAs z P 1-z Layer (0<z<1), The active layer has the InAs y Sb 1-y The layer is a well layer, with the InAs z P 1-z The layer is a quantum well structure of a barrier layer.

3. The light-emitting element according to claim 1 or 2, wherein: The light radiated from the active layer has a peak emission wavelength of 3.4 μm or more.

4. The light-emitting element according to claim 1 or 2, wherein: In the Al x In 1-x The As electron blocking layer is doped with a Zn dopant.

5. The light-emitting element according to claim 1 or 2, comprising: support base plate; A metal bonding layer disposed on a surface of the support substrate; The power distribution part on the metal bonding layer has a transparent insulating layer with a through hole and an ohmic electrode part provided in the through hole; and The semiconductor stack is provided on the power distribution unit.

6. A method for manufacturing a light-emitting element according to claim 1, characterized in that: The method comprises: A step of forming the first InAs layer; forming the active layer on the first InAs layer; The Al x In 1-x As electron blocking layer step; and In the Al x In 1-x A step of forming the second InAs layer on the As electron blocking layer.

7. A method for manufacturing a light-emitting element according to claim 1, characterized in that: The method comprises: A step of forming the second InAs layer; The Al is formed on the second InAs layer. x In 1-x As electron blocking layer process; In the Al x In 1-x The step of forming the active layer on the As electron blocking layer; and A step of forming the first InAs layer on the active layer.

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