Devices, power circuits, photoelectric conversion equipment, imaging equipment, and movable bodies

Abstract

The disclosed apparatus includes a plurality of differential transmitters and a power supply circuit supplying a power supply voltage to each of the plurality of differential transmitters. The power supply circuit includes: a common circuit unit defining the power supply voltage supplied to the plurality of differential transmitters; and a plurality of individual circuit units provided in association with and each connected to the common circuit unit. Each of the plurality of individual circuit units has an output node that outputs the power supply voltage defined by the common circuit unit to a corresponding differential transmitter among the plurality of differential transmitters, and the respective output nodes of the plurality of individual circuit units are connected to each other.

Description

Technical Field

[0001] The embodiments relate to differential signal driving circuits and photoelectric conversion devices. Background Technology

[0002] In recent years, differential signal transmission schemes such as Low Voltage Differential Signaling (LVDS) or Scalable Low Voltage Signaling (SLVS) have been widely used as high-speed data communication schemes. Patent Document 1 discloses an LVDS driver that suppresses variations in output amplitude caused by variations in resistor manufacturing.

[0003] Citation List

[0004] Patent documents

[0005] PTL 1: Japanese Patent Application Publication No. 2018-085713 Summary of the Invention

[0006] Technical issues

[0007] The LVDS driver disclosed in Patent Document 1 consists of an output circuit and multiple control circuits, and the high and low levels of the differential signal output from the output circuit are determined by using the control circuits. When data output from the LVDS driver is not required, for example, the current path of the LVDS driver's output circuit can be disconnected to reduce power consumption. However, in the LVDS driver disclosed in Patent Document 1, when data output begins after the current path is restored, the high level of the differential signal immediately following the start of output may have a higher voltage than the voltage during the LVDS driver's operating state. The same phenomenon may occur when starting the power supply, etc.

[0008] Solution to the problem

[0009] According to one aspect of an embodiment, an apparatus is provided, the apparatus including a plurality of differential transmitters and a power supply circuit supplying a power supply voltage to each of the plurality of differential transmitters. The power supply circuit includes: a common circuit unit defining the power supply voltage supplied to the plurality of differential transmitters; and a plurality of individual circuit units provided in association with the plurality of differential transmitters and each connected to the common circuit unit. Each of the plurality of individual circuit units has an output node that outputs the power supply voltage defined by the common circuit unit to a corresponding differential transmitter among the plurality of differential transmitters, and the output node of one of the plurality of individual circuit units is connected to the output node of another of the plurality of individual circuit units.

[0010] Furthermore, according to another aspect of the embodiments, a power supply circuit is provided that supplies power voltage to a plurality of differential transmitters corresponding to a plurality of channels, and the power supply circuit includes: a common circuit unit defining the power voltage supplied to the plurality of differential transmitters; and a plurality of individual circuit units provided in association with the plurality of differential transmitters and each connected to the common circuit unit. Each of the plurality of individual circuit units has an output node that outputs the power voltage defined by the common circuit unit to a corresponding one of the plurality of differential transmitters, and the output node of one of the plurality of individual circuit units is connected to the output node of another of the plurality of individual circuit units.

[0011] Other features of this disclosure will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a circuit diagram illustrating the overall configuration of a differential signal driving circuit according to a first embodiment of the present disclosure.

[0013] Figure 2 This is a circuit diagram illustrating an example configuration of a differential transmitter in a differential signal driving circuit according to a first embodiment of the present disclosure.

[0014] Figure 3 This is a diagram illustrating the operation of a differential signal driving circuit according to a first embodiment of the present disclosure.

[0015] Figure 4 This is a circuit diagram illustrating the overall configuration of the differential signal driving circuit according to the first reference example.

[0016] Figure 5 This is a diagram illustrating the operation of the differential signal drive circuit according to the first reference example.

[0017] Figure 6 This is a diagram illustrating the target of the differential signal driving circuit according to the first reference example.

[0018] Figure 7 This is a circuit diagram illustrating the overall configuration of the differential signal driving circuit according to the second reference example.

[0019] Figure 8 This is a circuit diagram illustrating the overall configuration of a differential signal driving circuit according to a modified example of the first embodiment of the present disclosure.

[0020] Figure 9 This is a block diagram illustrating the overall configuration of a photoelectric conversion device according to a second embodiment of the present disclosure.

[0021] Figure 10 This is a block diagram illustrating the overall configuration of an imaging system according to a third embodiment of the present disclosure.

[0022] Figure 11A This is a diagram illustrating an example configuration of an imaging system according to a fourth embodiment of the present disclosure.

[0023] Figure 11B This is a diagram illustrating an example configuration of a movable body according to a fourth embodiment of the present disclosure. Detailed Implementation

[0024] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0025] First Embodiment

[0026] Reference Figures 1 to 3 A differential signal driving circuit according to a first embodiment of the present disclosure is described. Figure 1 This is a circuit diagram illustrating the overall configuration of the differential signal driving circuit according to this embodiment. Figure 2 This is a circuit diagram illustrating an example configuration of a differential transmitter in a differential signal driving circuit according to this embodiment. Figure 3 This is a diagram illustrating the operation of the differential signal driving circuit according to this embodiment.

[0027] like Figure 1 As shown, the differential signal driving circuit 100 according to this embodiment includes a common circuit unit 10 and a plurality of individual circuit units 20. Each of the plurality of individual circuit units 20 is a circuit block corresponding to a channel. Although for the sake of simplicity, Figure 1 Only two separate circuit units 20 are shown in the figure, but the number of separate circuit units 20 is not particularly limited and can be appropriately increased or decreased according to the required number of channels.

[0028] The common circuit unit 10 includes a differential amplifier circuit 12, an n-channel MOS transistor SF0, and a load resistor R0. Each of the plurality of individual circuit units 20 includes an n-channel MOS transistor SF1 and a differential transmitter TX. The common circuit unit 10 defines the power supply voltage to be supplied to the plurality of differential transmitters TX. Furthermore, the n-channel MOS transistor SF1 of each individual circuit unit 20 outputs the power supply voltage defined by the common circuit unit 10 to the corresponding differential transmitter TX. That is, in the circuit elements forming the differential signal drive circuit 100, the common circuit unit 10 and the n-channel MOS transistor SF1 of each individual circuit unit 20 form a power supply circuit that supplies power supply voltage to the power supply voltage terminals of the differential transmitters TX.

[0029] The differential amplifier circuit 12 of the common circuit unit 10 has two input terminals (a non-inverting input terminal (+) and an inverting input terminal (-)) and an output terminal. The output terminal of the differential amplifier circuit 12 is connected to the gate of the n-channel MOS transistor SF0. ​​The n-channel MOS transistor SF0 has a drain connected to the power supply voltage node (voltage VDD) and forms a source follower circuit. The source of the n-channel MOS transistor SF0 is connected to one terminal of the load resistor R0 and the inverting input terminal of the differential amplifier circuit 12. The other terminal of the load resistor R0 is connected to the reference voltage node (GND node). In the following description, for illustrative purposes, the connection node of the source of the n-channel MOS transistor SF0, one terminal of the load resistor R0, and the inverting input terminal of the differential amplifier circuit 12 is referred to as node N1.

[0030] It should be noted that, although in Figure 1 The load resistor R0 is illustrated as a load element connected to the n-channel MOS transistor SF0, but different load elements, such as current sources, can be connected instead of the load resistor R0.

[0031] A reference voltage (voltage Vtx) is supplied to the non-inverting input terminal of the differential amplifier circuit 12. When the voltage at the inverting input terminal of the differential amplifier circuit 12 is expressed as VDDTX, since the differential amplifier circuit 12 is virtually short-circuited, voltage VDDTX is equal to voltage Vtx. That is, the source voltage of the n-channel MOS transistor SF0, i.e., the voltage at node N1, is voltage Vtx.

[0032] The differential transmitter TX of the individual circuit unit 20 has a power supply voltage terminal, a reference voltage terminal, a pair of differential input terminals, and a pair of differential output terminals. The n-channel MOS transistor SF1 has a drain connected to the power supply voltage node (voltage VDD) and forms a source follower circuit. The gate of the n-channel MOS transistor SF1 is connected to the gate of the n-channel MOS transistor SF0 and the output terminal of the differential amplifier circuit 12. The source of the n-channel MOS transistor SF1 is connected to node N1 and the power supply voltage terminal of the differential transmitter TX. That is, the source of the n-channel MOS transistor SF1 is the output node that outputs the power supply voltage to the differential transmitter TX.

[0033] The reference voltage terminal of the differential transmitter TX is connected to the reference voltage node (GND node). The differential output terminal of the differential transmitter TX is connected to the external terminating resistor Rt of the chip on which the differential signal drive circuit 100 is mounted.

[0034] In this manner, in the differential signal driving circuit 100 according to this embodiment, the n-channel MOS transistor SF0 of the common circuit unit 10 and the n-channel MOS transistor SF1 of the individual circuit unit 20 are connected such that their gates are commonly connected, their drains are commonly connected, and their sources are commonly connected. Therefore, the voltage at the source of each of the n-channel MOS transistors SF1, that is, the voltage supplied to the power supply voltage terminal of the differential transmitter TX of each of the individual circuit units 20, is voltage Vtx.

[0035] Differential transmitter TX, for example Figure 2 The diagram shown can be formed using n-channel MOS transistors M1, M2, M3, and M4, and resistors R1 and R2. The drains of n-channel MOS transistors M1 and M2 are connected to the power supply voltage terminal supplied by voltage VDDTX_I via resistor R1. The source of n-channel MOS transistor M1 is connected to the drain of n-channel MOS transistor M3. The source of n-channel MOS transistor M2 is connected to the drain of n-channel MOS transistor M4. The sources of n-channel MOS transistors M3 and M4 are connected to the reference voltage terminal (GND node) via resistor R2.

[0036] In the paired differential input terminals, one input terminal to which data D is input is connected to the gates of n-channel MOS transistor M1 and n-channel MOS transistor M4. In the paired differential input terminals, the other input terminal to which data DB, which is the inverted data of data D, is input, is connected to the gates of n-channel MOS transistor M2 and n-channel MOS transistor M3.

[0037] The connection point between the source of n-channel MOS transistor M1 and the drain of n-channel MOS transistor M3 is one of the output terminals in a pair of differential output terminals. For example, the signal output from one output terminal is, for example, data OUTP. Furthermore, the connection point between the source of n-channel MOS transistor M2 and the drain of n-channel MOS transistor M4 is the other output terminal in a pair of differential output terminals. The signal output from the other output terminal is, for example, data OUTN. A terminating resistor Rt is connected to the differential output terminals outside the chip on which the differential signal drive circuit 100 is mounted. Additionally, one of the differential output terminals is connected to the non-inverting input terminal of the receiver RX disposed on the receiver chip. The other differential output terminal is connected to the inverting input terminal of the receiver RX disposed on the receiver chip.

[0038] Next, we will refer to Figure 2 The voltage Vsigh describes the high-level signal output from the differential transmitter TX. This paper assumes that data D is at a high level and data DB is at a low level.

[0039] exist Figure 2 In the differential transmitter TX shown, when the high-level data D and the low-level data DB are input to the differential input terminals, n-channel MOS transistors M1 and M4 are turned on, and n-channel MOS transistors M2 and M3 are turned off. Thus, current flows from the power supply voltage terminal supplied with voltage VDDTX_I through resistor R1, n-channel MOS transistor M1, terminating resistor Rt, n-channel MOS transistor M4, and resistor R2 to the reference voltage terminal. If this paper assumes that the channel resistance of n-channel MOS transistors M1 and M4 is negligible, then the voltage Vsigh can be expressed as the following equation (1).

[0040] Vsigh=VDDIX_I×(Rt+R2) / (R1+Rt+R2)...(1)

[0041] In this paper, we consider the case where the common circuit unit 10 is in an operational state and the differential transmitter TX is in a non-operational state. Such a case could be, for example, the case during power-on, or the case where data does not need to be output to the outside of the chip.

[0042] When the differential transmitter TX is in a non-operating state, to reduce power consumption, the current path flowing from the power supply voltage terminal is disconnected from the reference voltage terminal. This current path can be disconnected, for example, by keeping both data D and data DB low to turn off all n-channel MOS transistors M1 to M4. Alternatively, the differential transmitter TX can be configured to have a component that connects the differential output terminal to a fixed potential when the differential transmitter TX is in a non-operating state.

[0043] Reference Figure 3 This describes the operation when the common circuit unit 10 is in the operating state and the differential transmitter TX is in the non-operating state. Note that in Figure 3 In the diagram, the circuit symbol for the differential transmitter TX is represented by a dashed line to visually indicate that the differential transmitter TX is in a non-operating state and that the path of current flowing from the power supply voltage terminal to the reference voltage terminal is broken, thus creating an open circuit.

[0044] As described above, the sources of the n-channel MOS transistor SF1 in the individual circuit unit 20 are commonly connected to node N1. Therefore, the source voltage VDDTX of the n-channel MOS transistor SF1 is voltage Vtx, and the voltage VDDTX_I supplied to the power supply voltage terminal of the differential transmitter TX is also voltage Vtx.

[0045] When the differential transmitter TX transitions from this state to the operating state, voltage Vtx continues to be supplied to the power supply voltage terminal of the differential transmitter TX. That is, the voltage at the power supply voltage terminal is still voltage Vtx even immediately after the differential transmitter TX returns to the operating state, and the signal output from the differential transmitter TX is within the desired voltage range as expressed in equation (1).

[0046] Note that when the differential transmitter TX returns to operating mode, resistors R1 and R2, along with the terminating resistor Rt, are connected as a load to the n-channel MOS transistor SF1. Therefore, upon return, current is supplied to these load resistors, which had no current flowing through them before return, causing a temporary drop in the source voltage of the n-channel MOS transistor SF1. However, because the output voltage of the differential amplifier circuit 12 increases in response to this voltage change, the source voltage of the n-channel MOS transistor SF1, i.e., the voltage at the power supply terminal of the differential transmitter TX, stabilizes at voltage Vtx.

[0047] Next, we will refer to Figures 4 to 7 The advantages of the differential signal driving circuit according to this embodiment are described in comparison with those of the differential signal driving circuit according to the reference example.

[0048] Figure 4 The difference between the differential signal driving circuit according to the first reference example and the differential signal driving circuit according to this embodiment is that the connection node between the source of the n-channel MOS transistor SF1 of the individual circuit unit 20 and the power supply voltage terminal of the differential transmitter TX is not connected to node N1. That is, in the differential signal driving circuit according to the first reference example, the voltage VDDTX1 at the source of the n-channel MOS transistor SF1 is the voltage supplied to the power supply voltage terminal of the differential transmitter TX.

[0049] In the differential signal driving circuit according to the first reference example, the circuit is designed such that the source voltage VDDTX of the n-channel MOS transistor SF0 and the source voltage VDDTX1 of the n-channel MOS transistor SF1 are the same when the differential transmitter TX is operating.

[0050] The conditions under which voltage VDDTX and voltage VDDTX1 are the same are expressed by the following equations (2) and (3).

[0051] R0=k×(R1+Rt+R2)...(2)

[0052] W0 / L0=W1 / (k×L1)...(3)

[0053] Equation (2) expresses the relationship between the sum of the resistors R1, R2, and the termination resistor Rt of the differential transmitter TX and the load resistor R0. Equation (3) expresses the relationship between the ratio of the gate width W0 to the gate length L0 (W0 / L0) of the n-channel MOS transistor SF0 and the ratio of the gate width W1 to the gate length L1 (W1 / L1) of the n-channel MOS transistor SF1. In equations (2) and (3), k is a constant. When both equations (2) and (3) are satisfied, the source voltage VDDTX of the n-channel MOS transistor SF0 and the source voltage VDDTX1 of the n-channel MOS transistor SF1 are the same.

[0054] In the differential signal driving circuit according to the first reference example, the reference signal is... Figure 5 Describe the operation when the differential transmitter TX transitions from a non-operating state to an operating state. Note that in Figure 5 In the diagram, the circuit symbol for the differential transmitter TX is represented by a dashed line to visually indicate that the differential transmitter TX is in a non-operating state and that the path of current flowing from the power supply voltage terminal to the reference voltage terminal is broken, thus creating an open circuit.

[0055] In the differential signal driving circuit according to the first reference example, when the differential transmitter TX is in a non-operating state, such as Figure 5 As shown, the source of the n-channel MOS transistor SF1 in the individual circuit unit 20 is in an open-circuit state. Therefore, no current flows in the n-channel MOS transistor SF1, and the source voltage VDDTX1 of the n-channel MOS transistor SF1 is higher than the voltage when the differential transmitter TX is operating. That is, the voltages at each point satisfy the relationship shown in the following equation (4).

[0056] VDDTX1>VDDTX=Vtx...(4)

[0057] Therefore, when the differential transmitter TX transitions from this state to the operating state, the voltage supplied to the power supply terminal of the differential transmitter TX immediately following the transition becomes higher than the voltage Vtx. As a result, for example, Figure 6 As shown, the high level of the output data from the differential transmitter TX is higher than the expected voltage.

[0058] When the signal level of the output data is higher than the expected voltage, it may exceed the rated voltage of the receiver receiving the data, and in the worst case, the receiver may fail. For example, when the voltage VDD and voltage VDDREC of the power supply connected to the drain of the n-channel MOS transistor SF1 of the separate circuit unit 20 satisfy the following equation (5), it is likely to exceed the maximum rated value of the receiver, where voltage VDDREC represents the power supply voltage of the receiver.

[0059] VDD>VDDREC...(5)

[0060] In this respect, in the differential signal driving circuit according to this embodiment, the voltage VDDTX_I supplied to the differential transmitter TX is always the voltage Vtx, and the signal level of the output data output from the differential transmitter TX can always be controlled within the desired voltage range. Therefore, the signal level of the output data output from the differential transmitter TX will not exceed the rated voltage of the receiver, and receiver failure due to the data signal output from the differential transmitter TX can be prevented.

[0061] Figure 7 The differential signal driving circuit shown according to the second reference example is an example in which a voltage VDDTX is generated in the power supply voltage generation unit 30 and this voltage VDDTX is supplied as a power supply voltage (voltage VDDTX_I) to the differential transmitters TX1 and TX2 on each channel. Figure 7 In this context, we assume a differential transmitter TX1 located closer to the power supply voltage generation unit 30 and a differential transmitter TX2 located farther from the power supply voltage generation unit 30. Furthermore, we assume that the interconnect resistance of the power supply interconnect between the power supply voltage generation unit 30 and the differential transmitter TX1 is Rp, and the interconnect resistance of the power supply interconnect between the power supply voltage generation unit 30 and the differential transmitter TX2 is 2Rp.

[0062] The power supply voltage generation unit 30 includes a differential amplifier circuit 32, an n-channel MOS transistor SF3, and a load resistor R3. The differential amplifier circuit 32 has two input terminals (a non-inverting input terminal (+) and an inverting input terminal (-)) and an output terminal. A voltage Vtx is supplied to the non-inverting input terminal of the differential amplifier circuit 32. The output terminal of the differential amplifier circuit 32 is connected to the gate of the n-channel MOS transistor SF3. The n-channel MOS transistor SF3 has a drain connected to the power supply voltage node (voltage VDD) and forms a source follower circuit. The source of the n-channel MOS transistor SF3 is connected to one terminal of the load resistor R3 and the inverting input terminal of the differential amplifier circuit 32. The other terminal of the load resistor R3 is connected to the reference voltage node (GND node).

[0063] In this document, for illustrative purposes, the connection node between the source of the n-channel MOS transistor SF3, one terminal of the load resistor R3, and the inverting input terminal of the differential amplifier circuit 32 is referred to as node N3. Furthermore, the other terminal of the load resistor R3 connected to the GND node is referred to as node N4. The voltage VDDTX at node N3 is the same as the voltage Vtx at node N1 of the common circuit unit 10. The power supply voltage and reference voltage are supplied from nodes N3 and N4, respectively, to the differential transmitters TX1 and TX2 on the respective channels via interconnects.

[0064] When the differential transmitters TX1 and TX2 on each channel are operating, current always flows from the power supply voltage terminal to the reference voltage terminal. Figure 2 In the circuit example of the differential transmitter TX shown, the current Itx flowing from the power supply voltage terminal to the reference voltage terminal is expressed by the following equation (6).

[0065] Itx=VDDTX_I / (R1+Rt+R2)...(6)

[0066] Furthermore, the power supply voltages supplied from the power supply voltage generation unit 30 to the differential transmitters TX1 and TX2 are reduced due to the interconnection resistance between the power supply voltage generation unit 30 and the differential transmitters TX1 and TX2. That is, the voltage VDDTX_I supplied from the power supply voltage generation unit 30 to the differential transmitter TX1 is expressed as equation (7) below. Furthermore, the voltage VDDTX_I supplied from the power supply voltage generation unit 30 to the differential transmitter TX2 is expressed as equation (8) below.

[0067] VDDTX_I=VDDTX-Rp×Itx...(7)

[0068] VDDTX_I=VDDTX-2xRpxItx...(8)

[0069] As described above, in the differential signal driving circuit according to the second reference example, the voltage supplied to the power supply voltage terminal will be lower for the differential transmitter TX which is further away from the power supply voltage generation unit 30. Furthermore, this also applies to the voltage on the GND node side, and the voltage supplied to the reference voltage terminal will be higher for the differential transmitter TX which is further away from the power supply voltage generation unit 30.

[0070] Therefore, in the differential signal driving circuit according to the second reference example, the power supply voltage supplied to the differential transmitter TX varies depending on the channel, so the amplitude of the data signal output from the differential transmitter TX will be different between channels.

[0071] In this respect, in the differential signal driving circuit according to this embodiment, such as Figure 1As shown, the voltage VDDTX is supplied from the power supply voltage node to the power supply voltage terminal of the differential transmitter TX via the n-channel MOS transistor SF1 on each channel. Furthermore, in this case, although a voltage drop occurs in the voltage VDD supplied to the individual circuit unit 20 on each channel due to the interconnect resistance of the power supply voltage interconnect, the voltage drop occurs at the drain of the n-channel MOS transistor SF1, which forms the source follower circuit. When the n-channel MOS transistor SF1 is operating in the saturation region, the change in drain voltage has a small effect on the drain current, and therefore has a small effect on the voltage VDDTX supplied to the differential transmitter TX on each channel. Therefore, compared to the case of the differential signal drive circuit according to the second reference example, the impact on the amplitude of the data signal output from the differential transmitter TX can be reduced even more significantly. The effect on the voltage on the GND node side in the differential signal drive circuit according to this embodiment is the same as in the case of the differential signal drive circuit according to the second reference example.

[0072] Note that although the gates of the n-channel MOS transistor SF0 in the common circuit unit 10 and the gates of the n-channel MOS transistor SF1 in the separate circuit unit 20 are directly connected to each other in this embodiment, these gates do not necessarily need to be directly connected to each other. For example, as Figure 8 As shown, the gates of n-channel MOS transistors SF0 and SF1 can be connected via gate resistor Rg. Furthermore, the gates of one n-channel MOS transistor SF1 in a separate circuit unit 20 and the gate of another n-channel MOS transistor SF1 in a separate circuit unit 20 can be connected via gate resistor Rg. Moreover, when the differential signal drive circuit is configured in this manner, the same advantageous effects as described in this embodiment can be obtained. The gate resistor Rg can be configured by arranging resistive elements, or by locally reducing the width of the interconnect to increase the interconnect resistance.

[0073] As described above, according to this embodiment, a signal with a stable amplitude can be output even when the operating state of the differential signal drive circuit is switched. Therefore, the quality of the signal output from the differential transmitter can be improved. Furthermore, malfunctions in the receiver receiving the signal from the differential transmitter can be prevented.

[0074] Second Embodiment

[0075] Reference Figure 9 A photoelectric conversion device according to a second embodiment of the present disclosure is described. Components identical to those in the differential signal driving circuit according to the first embodiment are labeled with the same symbols, and their descriptions will be omitted or simplified. Figure 9 This is a block diagram illustrating the overall configuration of the photoelectric conversion device according to this embodiment.

[0076] Although there are no particular limitations, the differential signal driving circuit 100 according to the first embodiment can be used, for example, as an output circuit unit of a photoelectric conversion device. In this embodiment, an example of a photoelectric conversion device to which the differential signal driving circuit according to the first embodiment is applied will be described.

[0077] like Figure 9 As shown, the photoelectric conversion device 200 according to this embodiment includes a pixel region 110, a vertical scanning circuit 120, an AD conversion circuit unit 130, a memory unit 140, a horizontal scanning circuit 150, a computing unit 160, a signal processing circuit 170, and a differential signal driving circuit 100.

[0078] In pixel region 110, a plurality of pixels 112 are provided in a matrix arrangement to form a plurality of rows and a plurality of columns. Each of the pixels 112 includes a photoelectric conversion unit formed by a photoelectric conversion element such as a photodiode and has the function of outputting a pixel signal according to the amount of incident light. Vertical scanning circuit 120 is a control circuit unit that supplies control signals for driving the pixels 112 via control lines provided on each row of the pixel array when the pixel signal is read from pixel region 110.

[0079] The AD conversion circuit unit 130 includes a plurality of column AD conversion circuits 132 provided in association with each column of the pixel array. The column AD conversion circuits 132 convert analog pixel signals output from pixels 112 in the corresponding column into digital data. The memory unit 140 includes a plurality of column memories 142 provided in association with each column of the pixel array. The column memories 142 store the digital data converted by the column AD conversion circuits 132 in the corresponding column. The horizontal scanning circuit 150 sequentially selects the column memories 142 in each column and outputs the digital data stored in the selected column memories 142 to the computing unit 160.

[0080] The computing unit 160 performs predetermined computational processing on the digital data transferred from the memory unit 140, such as amplification processing, digital correlation double sampling (CDS) processing, etc., and outputs the processed digital data to the signal processing circuit 170. The signal processing circuit 170 includes a parallel-to-serial conversion circuit, which converts the parallel data output from the computing unit 160 into serial data, and outputs the converted serial data to the differential signal driving circuit 100.

[0081] The differential signal driving circuit 100 is the differential signal driving circuit 100 described in the first embodiment. The differential signal driving circuit 100 converts the serial data received from the signal processing circuit 170 into a differential signal, and outputs the differential signal to the outside of the photoelectric conversion device 200 via the differential transmitter TX. Note that, for the sake of simplicity, in... Figure 9 Only one individual circuit unit 20 corresponding to one channel of the plurality of individual circuit units 20 forming the differential signal drive circuit 100 is illustrated. The power supply voltage is supplied to the differential transmitter TX through the individual circuit unit 20. Furthermore, the gate and source voltages of the n-channel MOS transistors supplied to the individual circuit unit 20 are generated by a common circuit unit 10.

[0082] By applying the differential signal driving circuit 100 of the first embodiment to the signal output unit of the photoelectric conversion device, the signal output from the differential transmitter TX can be controlled to always be within a desired range. Therefore, signal quality can be improved, and damage to the receiver receiving the signal can be prevented. Furthermore, since the power supply voltage of the differential transmitter TX is generated internally within the chip, a power supply IC is not required externally. Therefore, the number of components can be reduced, and costs can be lowered.

[0083] Third Embodiment

[0084] Reference Figure 10 An imaging system according to a third embodiment of the present disclosure is described. Figure 10 This is a block diagram illustrating the overall configuration of the imaging system according to this embodiment.

[0085] The photoelectric conversion device 200 described in the second embodiment above can be applied to various imaging systems. Examples of applicable imaging systems may include digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, etc. Furthermore, camera modules, including optical systems such as lenses and imaging devices, are also included in the imaging system. Figure 10 A block diagram of a digital still camera, used as an example in these examples, is shown.

[0086] Figure 10 The imaging system 300 illustrated as an example includes an imaging device 301, a lens 302 that captures an optical image of an object onto the imaging device 301, an aperture 304 for changing the amount of light passing through the lens 302, and a barrier 306 for protecting the lens 302. The lens 302 and the aperture 304 form an optical system that converges light onto the imaging device 301. The imaging device 301 is the photoelectric conversion device 200 described in the second embodiment, and converts the optical image captured by the lens 302 into image data.

[0087] Furthermore, the imaging system 300 includes a signal processing unit 308 that processes the output signal output from the imaging device 301. The signal processing unit 308 generates image data from the digital signal output by the imaging device 301. Additionally, as needed, the signal processing unit 308 performs various corrections or compressions to output image data. The imaging device 301 may have an AD conversion unit that generates the digital signal processed in the signal processing unit 308. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 301 is formed, or it may be formed on a different semiconductor substrate than the semiconductor layer on which the photoelectric conversion unit of the imaging device 301 is formed. Furthermore, the signal processing unit 308 may be formed on the same semiconductor substrate as the imaging device 301.

[0088] Furthermore, the imaging system 300 includes a memory unit 310 for temporarily storing image data therein and an external interface unit (external I / F unit) 312 for communicating with an external computer or the like. The imaging system 300 also includes a storage medium 314, such as a semiconductor memory, for performing the storage or retrieval of imaging data, and a storage medium control interface unit (storage medium control I / F unit) 316 for performing storage or retrieval of the storage medium 314. Note that the storage medium 314 may be embedded in the imaging system 300 or may be removable.

[0089] Furthermore, the imaging system 300 includes a general control / computation unit 318 that performs various calculations and controls the entire digital still camera, and a timing generation unit 320 that outputs various timing signals to the imaging device 301 and the signal processing unit 308. Here, timing signals, etc., can be input from the outside, and the imaging system 300 may have at least an imaging device 301 and a signal processing unit 308 that processes the output signals output from the imaging device 301.

[0090] Imaging device 301 outputs an imaging signal to signal processing unit 308. Signal processing unit 308 performs predetermined signal processing on the imaging signal output from imaging device 301 and outputs image data. Signal processing unit 308 uses the imaging signal to generate an image.

[0091] As described above, according to this embodiment, the imaging system to which the photoelectric conversion device 200 according to the second embodiment is applied can be realized.

[0092] Fourth embodiment

[0093] Reference Figure 11A and Figure 11B An imaging system and a movable body according to a fourth embodiment of the present disclosure are described. Figure 11A This is a diagram illustrating the configuration of the imaging system according to this embodiment. Figure 11BThis is a diagram illustrating the configuration of the movable body according to this embodiment.

[0094] Figure 11A An example of an imaging system related to a vehicle-mounted camera is illustrated. Imaging system 400 includes imaging device 410. Imaging device 410 is the photoelectric conversion device 200 described in the second embodiment above. Imaging system 400 includes an image processing unit 412 that performs image processing on multiple image data acquired by imaging device 410, and a disparity acquisition unit 414 that calculates disparity (phase difference of the disparity image) from the multiple image data acquired by imaging system 400. Furthermore, imaging system 400 includes a distance acquisition unit 416 that calculates the distance to an object based on the calculated disparity, and a collision determination unit 418 that determines the possibility of a collision based on the calculated distance. Here, disparity acquisition unit 414 and distance acquisition unit 416 are examples of distance information acquisition units that acquire distance information about the distance to an object. That is, the distance information is information about disparity, defocus, distance to an object, etc. Collision determination unit 418 can use any distance information to determine the possibility of a collision. The distance information acquisition unit can be implemented by specially designed hardware or by a software module. In addition, the distance information acquisition unit can be implemented by field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or a combination thereof.

[0095] The imaging system 400 is connected to the vehicle information acquisition device 420 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Furthermore, the imaging system 400 is connected to a control ECU 430, which is a control device that outputs a control signal to generate braking force for the vehicle based on the determination result of the collision determination unit 418. Additionally, the imaging system 400 is connected to a warning device 440, which issues a warning to the driver based on the determination result of the collision determination unit 418. For example, when the collision probability is determined to be high by the collision determination unit 418, the control ECU 430 performs vehicle control to avoid a collision or reduce damage by applying brakes, retracting the accelerator, or suppressing engine power. The warning device 440 warns the user by issuing warnings such as audible warnings, displaying warning information on a display such as a car navigation system, or providing vibrations to the seat belt or steering wheel.

[0096] In this embodiment, the imaging system 400 is used to capture the area around the vehicle, such as the area in front or behind. Figure 11B The diagram illustrates an imaging system capturing the area in front of a vehicle (capture area 450). Vehicle information acquisition device 420 sends commands to imaging system 400 or imaging device 410. This configuration can further improve ranging accuracy.

[0097] While examples of controls for avoiding collisions with other vehicles have been described above, these embodiments can be applied to autonomous driving controls that follow other vehicles, autonomous driving controls that do not leave their lanes, and so on. Furthermore, the imaging system is not limited to vehicles such as the vehicle in question, but can be applied to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. Moreover, the imaging system can be widely applied to devices that utilize object recognition, such as intelligent transportation systems (ITS), and is not limited to mobile bodies.

[0098] Modified Implementation

[0099] This disclosure is not limited to the embodiments described above, and various modifications are possible. For example, an example in which a portion of the configuration of any one of the embodiments is added to another embodiment, or an example in which a portion of the configuration of any one of the embodiments is replaced by a portion of the configuration of another embodiment, is also an embodiment of this disclosure.

[0100] Furthermore, the power supply voltage supplied to the differential amplifier circuit 12 of the common circuit unit 10, as well as the power supply voltage supplied to the n-channel MOS transistor SF0 of the common circuit unit 10 and the n-channel MOS transistor SF1 of the individual circuit unit 20, can be the same or different from each other. For example, the power supply voltage supplied to the differential amplifier circuit 12 can be set to a higher voltage than the power supply voltage supplied to the n-channel MOS transistors SF0 and SF1.

[0101] Furthermore, the reference voltage of the differential amplifier circuit 12 in the common circuit unit 10 and the reference voltage of the differential transmitter TX can be the same or different from each other.

[0102] Furthermore, although the power supply voltage supplied to the n-channel MOS transistor SF0 in the common circuit unit 10 and the power supply voltage supplied to the n-channel MOS transistor SF1 in the individual circuit unit 20 are both voltage VDD in the above embodiments, these power supply voltages can be different from each other.

[0103] Furthermore, although examples of using n-channel MOS transistors to form power supply circuits and differential transmitters have been illustrated in the above embodiments, p-channel MOS transistors can also be used to form power supply circuits or differential transmitters.

[0104] Furthermore, as an example of a photoelectric conversion device to which the differential signal driving circuit of the first embodiment can be applied, the photoelectric conversion device shown in the second embodiment above is provided, and the devices to which this differential signal driving circuit can be applied are not limited to... Figure 9 The configuration shown.

[0105] Furthermore, as an example of an imaging system to which the photoelectric conversion device can be applied as a second embodiment, the imaging systems shown in the third and fourth embodiments above are provided, and the imaging systems to which the photoelectric conversion device can be applied are not limited to... Figure 10 and Figure 11A The configuration shown.

[0106] While this disclosure has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be given the broadest interpretation in order to cover all such modifications and equivalent structures and functions.

[0107] This application claims the benefit of Japanese Patent Application No. 2019-197616, filed on October 30, 2019, which is hereby incorporated herein by reference in its entirety.

[0108] [List of Reference Symbols]

[0109] 10 Common circuit units

[0110] 12 Differential Amplifier Circuit

[0111] 20 individual circuit units

[0112] 100 Differential Signal Drive Circuit

[0113] R0 load resistor

[0114] Rt terminating resistor

[0115] Rx receiver

[0116] SF0, SF1 n-channel MOS transistors

[0117] TX, TX1, TX2 differential transmitters.

Claims

1. A differential signal driving circuit, comprising: Multiple differential transmitters, each corresponding to a multiple channel; as well as A power supply circuit supplies power voltage to each of the plurality of differential transmitters. The power supply circuit includes A common circuit unit, which defines the power supply voltage supplied to the plurality of differential transmitters, and Multiple individual circuit units are provided in association with the multiple differential transmitters and each is connected to the common circuit unit. Each of the plurality of individual circuit units includes a first transistor and has an output node. The first transistor forms a source follower circuit and outputs a power supply voltage defined by the common circuit unit. The output node outputs the power supply voltage to a corresponding differential transmitter among the plurality of differential transmitters. The common circuit unit includes A differential amplifier circuit, comprising a non-inverting input terminal, an inverting input terminal, and an output terminal. The second transistor forms a source follower circuit and its gate is connected to the output terminal of the differential amplifier circuit. A load element, wherein the load element is connected between the source of the second transistor and the reference voltage node. In this configuration, the output node of one of the plurality of individual circuit units and the output node of another of the plurality of individual circuit units are connected to each other, and The output node of each of the plurality of individual circuit units is connected to the connection node between the source of the second transistor and the load element.

2. The differential signal driving circuit according to claim 1, wherein, In the differential amplifier circuit, a reference voltage is supplied to the non-inverting input terminal, and the inverting input terminal is connected to the connection node.

3. The differential signal driving circuit according to claim 1, wherein, The load element is a resistor.

4. The differential signal driving circuit according to claim 1, wherein, The load element is a current source.

5. The differential signal driving circuit according to any one of claims 1-4, wherein, The gate of the first transistor is connected to the output terminal of the differential amplifier circuit and the gate of the second transistor.

6. The differential signal driving circuit according to any one of claims 1-4, wherein, The gates of the first transistor and the second transistor are connected via a resistor.

7. The differential signal driving circuit according to any one of claims 1-4, wherein, The power supply voltage supplied to the differential amplifier circuit and the power supply voltage supplied to the source follower circuit are different from each other.

8. The differential signal driving circuit according to any one of claims 1-4, wherein, The gate of the first transistor in one of the plurality of individual circuit units and the gate of the first transistor in another of the plurality of individual circuit units are connected via a resistor.

9. The differential signal driving circuit according to any one of claims 1-4, in, Each of the plurality of differential transmitters includes A power supply voltage terminal, wherein the power supply voltage is supplied from the power supply circuit to the power supply voltage terminal. A first resistor, one terminal of which is connected to the power supply voltage terminal. A third transistor and a fourth transistor, the drains of which are connected to another terminal of the first resistor. A fifth transistor, the drain of which is connected to the source of the third transistor. A sixth transistor, the drain of which is connected to the source of the fourth transistor. A second resistor, one terminal of which is connected to the source of the fifth transistor and the source of the sixth transistor, and A reference voltage terminal, which is connected to another terminal of the second resistor. Wherein, the first node to which the gates of the third transistor and the sixth transistor are connected, and the second node to which the gates of the fourth transistor and the fifth transistor are connected, form a pair of differential input terminals, and The third node, to which the source of the third transistor and the drain of the fifth transistor are connected, and the fourth node, to which the source of the fourth transistor and the drain of the sixth transistor are connected, form a pair of differential output terminals.

10. A power supply circuit, comprising: A common circuit unit, which defines the power supply voltage supplied to the plurality of differential transmitters; as well as Multiple individual circuit units are provided in association with the multiple differential transmitters and each is connected to the common circuit unit. Each of the plurality of individual circuit units includes a first transistor and has an output node. The first transistor forms a source follower circuit and outputs a power supply voltage defined by the common circuit unit. The output node outputs the power supply voltage to a corresponding one of the plurality of differential transmitters. The common circuit unit includes A differential amplifier circuit, comprising a non-inverting input terminal, an inverting input terminal, and an output terminal. The second transistor forms a source follower circuit and its gate is connected to the output terminal of the differential amplifier circuit. A load element, wherein the load element is connected between the source of the second transistor and the reference voltage node. In this configuration, the output node of one of the plurality of individual circuit units and the output node of another of the plurality of individual circuit units are connected to each other, and The output node of each of the plurality of individual circuit units is connected to the connection node between the source of the second transistor and the load element.

11. The power supply circuit according to claim 10, wherein, In the differential amplifier circuit, a reference voltage is supplied to the non-inverting input terminal, and the inverting input terminal is connected to the connection node.

12. The power supply circuit according to claim 10 or 11, wherein, The gate of the first transistor is connected to the output terminal of the differential amplifier circuit and the gate of the second transistor.

13. A photoelectric conversion device, comprising: A pixel, wherein the pixel outputs a signal based on the amount of incident light; as well as Output circuit unit, the output circuit unit outputs the signal from the pixel to the outside. The output circuit unit includes a differential signal driving circuit according to any one of claims 1-9.

14. An imaging system, comprising: The photoelectric conversion device according to claim 13; as well as A signal processing unit that processes the signal output from the photoelectric conversion device.

15. A movable body, comprising: The photoelectric conversion device according to claim 13; A distance information acquisition unit acquires distance information about the distance to an object from a parallax image based on a signal output from the photoelectric conversion device; as well as A control unit that controls the movable body based on the distance information.

Images