A CMOS temperature sensor

Abstract

The present invention belongs to the technical field of integrated sensors and proposes a CMOS temperature sensor, comprising: a startup circuit, a bandgap reference circuit, a third branch, a mirror current source, a voltage calibration circuit, an analog-to-digital conversion circuit, and a temperature calibration module. The CMOS temperature sensor of the present invention overcomes the problem that the offset voltage of the operational amplifier in the bandgap reference circuit affects the reference voltage V under various process angles. BG The influence of temperature is reduced, making the temperature detection more accurate, and the entire temperature sensor has lower power consumption and higher linearity.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated sensors, and in particular relates to a CMOS temperature sensor. Background Art

[0002] In recent years, the Internet of Things technology has developed rapidly and has set off a wave of enthusiasm around the world. As the basic component of the Internet of Things system, the temperature sensor has been expanding its market application scope and the demand has been gradually increasing. As the main semiconductor technology at present, CMOS technology has the characteristics of miniaturization and easy integration, which makes the temperature sensor smaller in size, more functional, and lower in power consumption, and can meet more application needs. The BJT-based temperature sensor is a high-precision CMOS temperature sensor that uses the base-emitter voltage V BE The temperature characteristics of BJT are used to measure the temperature. Because of the good temperature characteristics of BJT, this temperature sensor can achieve very high accuracy. With the development in recent years, the area and power consumption of this type of sensor have also been greatly improved. With the new digital calibration technology, it can improve the calibration efficiency and reduce the cost.

[0003] In the design of temperature sensors based on BJT, the offset voltage of the operational amplifier in the bandgap reference circuit has a greater impact on the bandgap reference voltage under different process angles. In the traditional bandgap reference circuit, the offset voltage across the operational amplifier is amplified by the resistor in series with the transistor and coupled to the bandgap reference output voltage V BG On, due to the reference voltage V BG The error in the digital code output by the subsequent analog-to-digital conversion circuit causes an error, which in turn causes an error in the temperature measurement. In traditional solutions, eliminating the offset voltage of the operational amplifier often requires chopping technology, but this technology requires chopping modulation of multiple nodes in the circuit, which will introduce additional circuits, increasing the complexity of the circuit and power consumption.

[0004] In summary, it is important to avoid the operational amplifier offset voltage causing the reference voltage V BG The temperature measurement error caused by drastic changes is a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0005] The object of the present invention is to provide a CMOS temperature sensor to overcome the effect of the offset voltage of the operational amplifier on the reference voltage V in the bandgap reference circuit under various process angles. BG The temperature sensor has lower power consumption and higher linearity.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] A CMOS temperature sensor is characterized by comprising: a startup circuit, a bandgap reference circuit, a third branch, a mirror current source, a voltage calibration circuit, an analog-to-digital conversion circuit, and a temperature calibration module.

[0008] The bandgap reference circuit comprises: a first folded cascode operational amplifier (hereinafter referred to as the first operational amplifier), a first NMOS, a first branch, and a second branch, wherein:

[0009] The gate of the first NMOS tube is connected to the first operational amplifier, and the drain of the first NMOS tube is connected to the mirror current source;

[0010] The first branch is connected to the first NMOS tube;

[0011] The second branch is connected to the first NMOS tube;

[0012] The bandgap reference circuit outputs a bandgap reference voltage V to the analog-to-digital conversion circuit when the analog-to-digital conversion circuit is in the sampling phase. BG With positive temperature coefficient voltage V PTAT .

[0013] The first branch includes: a first triode, a third resistor, and a first resistor, wherein:

[0014] The third resistor is connected in series with the first transistor, and the first resistor is connected in series with the third resistor.

[0015] The first resistor is connected to the source of the first NMOS tube.

[0016] The second branch includes: a second triode and a second resistor, which are connected in series, and the second resistor is connected to the source of the first NMOS tube.

[0017] The positive input terminal of the first operational amplifier is connected to the upper end of the third resistor, and the negative input terminal thereof is connected to the lower end of the second resistor, and the first operational amplifier makes the voltage drops of the first resistor and the second resistor equal;

[0018] The third branch includes: a third triode and a fourth resistor, which are connected in series and used to generate a common mode level required by the analog-to-digital conversion circuit. The fourth resistor is connected to the source of the first NMOS tube.

[0019] The analog-to-digital conversion circuit is used to utilize a reference voltage V BG_REF Quantify the voltage drop across the second resistor, the positive temperature coefficient voltage V PTAT , and use V PTAT With reference voltage V BG_REF The ratio μ determines the ambient temperature.

[0020] The analog-to-digital conversion circuit comprises:

[0021] A shift register for generating a successive approximation comparison clock;

[0022] A sampling and holding circuit, wherein a first terminal of the sampling and holding circuit is connected to the bandgap reference voltage V BG The second end of the transistor is connected to the emitter of the second transistor, and is used to sample and hold the voltage αΔV during the sampling phase of the analog-to-digital conversion circuit. BE , this voltage is the differential voltage;

[0023] A comparator with a differential structure, wherein the first terminal and the second terminal of the comparator receive the differential voltage αΔV output by the sampling and holding circuit BE , a third terminal thereof receives the comparison clock output by the shift register, and a fourth terminal thereof outputs the digital code after analog-to-digital conversion;

[0024] For successive approximation of the differential voltage αΔV BE Capacitor array;

[0025] Capacitor switching control circuit, the capacitor switching control circuit uses V BG_REF As a reference voltage and controlled by the comparator output terminal signal and the comparator output terminal inversion signal;

[0026] A clock generating circuit, wherein a first terminal of the clock generating circuit is connected to the sampling and holding circuit, and a second terminal and a third terminal of the clock generating circuit are connected to the capacitor switching control circuit, and is used to provide a corresponding clock control signal;

[0027] A digital output register is connected to the output terminal of the comparator and is used to capture and store the digital code output by the comparator during the successive approximation process.

[0028] The voltage signals at the differential input terminals of the comparator are V IP 、V IN .

[0029] The comparator comprises:

[0030] A fifth PMOS tube, whose source is connected to the power supply and whose gate is connected to its own drain;

[0031] A sixth PMOS tube, whose source is connected to the power supply and whose gate is connected to its own drain;

[0032] a sixth resistor having a second end grounded;

[0033] The ninth NMOS tube has a gate connected to the inverted signal of the temperature sensor enable control signal PWD. connected, with its source connected to the sixth resistor;

[0034] The seventh NMOS tube has a gate connected to the voltage signal V IP connected, its drain is connected to the drain of the fifth PMOS tube, and its source is connected to the ninth NMOS tube;

[0035] The eighth NMOS tube has a gate connected to the voltage signal V IN connected, its drain is connected to the drain of the sixth PMOS tube, and its source is connected to the ninth NMOS tube;

[0036] A first capacitor, a first end of which is connected to the seventh NMOS transistor, and a second end of which is grounded;

[0037] A second capacitor, a first end of which is connected to the eighth NMOS transistor, and a second end of which is grounded;

[0038] The latch has a first end and a second end receiving the drain differential voltage signal of the seventh NMOS tube and the eighth NMOS tube, and a third end and a fourth end outputting the differential voltage signal after the comparison is completed.

[0039] The first transistor, the second transistor and the third transistor are all PNP transistors.

[0040] The gate of the first NMOS tube is connected to the output terminal of the first operational amplifier and the second terminal of the startup circuit, and the drain of the first NMOS tube is connected to the mirror current source and the first terminal of the startup circuit.

[0041] The source of the first NMOS tube is connected to the first end of the first resistor;

[0042] The second end of the first resistor is connected to the first end of the third resistor,

[0043] The second end of the third resistor is connected to the emitter of the first transistor.

[0044] The collector and base of the first transistor are grounded;

[0045] The first end of the second resistor is connected to the source of the first NMOS transistor, the second end of the second resistor is connected to the emitter of the second transistor, and the collector and base of the second transistor are grounded;

[0046] A first end of the fourth resistor is connected to the mirror current source, a second end of the fourth resistor is connected to the emitter of the third triode, and the collector and base of the third triode are grounded;

[0047] During the sampling phase of the analog-to-digital conversion circuit, the second branch provides the voltage αΔV to the analog-to-digital conversion circuit. BE And the bandgap reference voltage V BG, the third branch is used to generate the common mode level required by the analog-to-digital conversion circuit.

[0048] The area ratio of the first transistor to the second transistor is P:1, P=24, ΔV BE is the voltage drop across the third resistor, αΔV BE is the voltage drop across the second resistor, i.e. αΔV BE =V PTAT ,

[0049] The mirror current source is used to provide a bias current to the first operational amplifier, to provide a bias current to the analog-to-digital conversion circuit, and to provide a bias current to the first branch, the second branch, and the third branch, and the bias current is a positive temperature coefficient current I PTAT ;

[0050] The mirror current source comprises:

[0051] The gates of the first transmission gate switch and the second transmission gate switch both receive the temperature sensor enable control signal PWD and the inverted signal in

[0052] a seventh PMOS transistor, whose source is connected to the power supply, whose drain is connected to the first end of the first transmission gate switch, and whose gate is connected to the second end of the first transmission gate switch;

[0053] The eighth PMOS tube has a gate connected to the temperature sensor to enable the control inverting signal connected, its source is connected to the power supply, and its drain is connected to the gate of the seventh PMOS tube;

[0054] a ninth PMOS tube, whose source is connected to the power supply, whose gate is connected to the drain of the eighth PMOS tube, and whose drain outputs the first bias current;

[0055] a tenth PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the ninth PMOS tube, and whose drain outputs the second bias current;

[0056] an eleventh PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the tenth PMOS tube, and whose drain outputs a third bias current;

[0057] a twelfth PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the eleventh PMOS tube, and whose drain outputs a fourth bias current;

[0058] a thirteenth PMOS tube, whose source is connected to the power supply and whose gate is connected to the gate of the twelfth PMOS tube;

[0059] A twenty-second NMOS transistor, whose source is connected to the ground, whose drain is connected to the drain of the thirteenth PMOS transistor, and whose gate is connected to the second end of the second transmission gate switch;

[0060] The twenty-third NMOS tube has a source connected to the ground, a drain connected to the gate of the twenty-second NMOS tube, and a gate connected to the temperature sensor enable control signal PWD.

[0061] The drain of the seventh PMOS tube is connected to the drain of the first NMOS tube, and the gate of the twenty-second NMOS tube provides a control signal V of the startup circuit. ST , a first end of the second transmission gate switch is connected to a power source.

[0062] The startup circuit has a first end connected to the drain of the first NMOS transistor and a second end connected to the gate of the first NMOS transistor, and is used to enable the bandgap reference loop to self-start.

[0063] The startup circuit comprises:

[0064] Its gate receives the temperature sensor enable control signal PWD and the inverting signal a third transmission gate switch and a fourth transmission gate switch;

[0065] The second NMOS tube has a gate connected to the control signal V ST connected, with its source connected to ground and its drain connected to the first end of the third transmission gate switch;

[0066] a fifth resistor, a second end of which is connected to the drain of the second NMOS tube;

[0067] A first PMOS tube, whose gate is connected to the temperature sensor enable control signal PWD, whose source is connected to the power supply, and whose drain is connected to the first end of the fifth resistor;

[0068] A third NMOS transistor, whose gate is connected to the second end of the third transmission gate switch, whose drain is connected to the second end of the fifth resistor, and whose source is connected to the ground;

[0069] a fifth NMOS transistor, whose gate is connected to the temperature sensor enable control signal PWD, whose drain is connected to the gate of the third NMOS transistor, and whose source is connected to ground;

[0070] a fourth NMOS transistor, whose gate is connected to the third NMOS transistor, whose source is connected to the ground, and whose drain is connected to the first end of the fourth transmission gate switch;

[0071] The third PMOS tube has a gate connected to the temperature sensor to enable the control of the inverting signal connected, its source is connected to the power supply, and its drain is connected to the gate of the second PMOS tube;

[0072] a fourth PMOS tube, whose gate is connected to the gate of the second PMOS tube, whose source is connected to a power source, and whose drain is connected to the gate of the first NMOS tube;

[0073] A sixth NMOS tube has a gate connected to the drain of the fifth NMOS tube, a source connected to the ground, and a drain connected to the drain of the first NMOS tube.

[0074] The voltage calibration circuit has a first end connected to the source of the first NMOS tube and a second end connected to the analog-to-digital converter, and is used to calibrate the bandgap reference voltage V BG , so that it can overcome the influence of the offset voltage of the first operational amplifier and provide a more accurate reference voltage V for the analog-to-digital conversion circuit. BG_REF .

[0075] The voltage calibration circuit comprises:

[0076] A second operational amplifier, a first input terminal of which is connected to the bandgap reference voltage V BG connect;

[0077] A third capacitor, a first end of which is connected to the output end of the second operational amplifier, and a second end of which is grounded;

[0078] A twenty-first NMOS transistor, a gate of which is connected to the output terminal of the second operational amplifier, and a drain of which is connected to a power supply;

[0079] A resistor array, a first input terminal of which receives an 8-bit control word, and a second input terminal of which is connected to a second input terminal of the second operational amplifier;

[0080] A seventh resistor has a first end connected to the lower end of the resistor array and a second end grounded.

[0081] The source of the twenty-first NMOS tube is connected to the upper end of the resistor array, and the resistor array outputs the calibrated bandgap reference voltage V BG_REF .

[0082] The resistor array comprises:

[0083] an eleventh NMOS tube whose gate receives the seventh-bit control word level;

[0084] A twelfth NMOS tube whose gate receives the inverted level of the seventh control word, wherein the eleventh NMOS tube and the twelfth NMOS tube form a pair of complementary switches;

[0085] The eighth resistor to the one hundred and thirty-sixth resistor connected in series, a total of 128 resistors;

[0086] A thirteenth NMOS tube whose gate receives the level of the zeroth control word;

[0087] A fourteenth NMOS tube whose gate receives the inverted level of the zeroth control word, the thirteenth NMOS tube and the fourteenth NMOS tube form a pair of complementary switches, and a total of 64 pairs of complementary switches of the same type controlled by the zeroth control word level and its inverted level are distributed vertically;

[0088] There are 32 pairs of complementary switches controlled by the first control word level and its inverted level on the right side of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level;

[0089] There are 16 pairs of complementary switches controlled by the second control word level and its inverted level on the right side of the 32 pairs of complementary switches controlled by the first control word level and its inverted level;

[0090] There are a total of 8 pairs of complementary switches controlled by the third control word level and its inverted level, which are located on the right side of the 16 pairs of complementary switches controlled by the second control word level and its inverted level;

[0091] There are a total of 4 pairs of complementary switches controlled by the fourth control word level and its inverted level located on the right side of the 8 pairs of complementary switches controlled by the third control word level and its inverted level;

[0092] There are two pairs of complementary switches controlled by the fifth control word level and its inverted level on the right side of the four pairs of complementary switches controlled by the fourth control word level and its inverted level;

[0093] There is a total of one pair of complementary switches controlled by the sixth control word level and its inverted level located on the right side of the two pairs of complementary switches controlled by the fifth control word level and its inverted level, namely the nineteenth NMOS tube and the twentieth NMOS tube.

[0094] The drain of the eleventh NMOS tube is connected to the second input terminal of the resistor array, the source of the eleventh NMOS tube is connected to the second terminal of the eighth resistor, and the source of the twelfth NMOS tube is connected to the second terminal of the first one hundred and thirty-sixth resistor;

[0095] The drains of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level are sequentially connected to the ends of the ninth resistor, the eleventh resistor, the thirteenth resistor, ..., the first one hundred and thirty-sixth resistor;

[0096] The drains of the 32 pairs of complementary switches controlled by the first control word level and its inverted level are connected to the sources of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level in a binary decreasing arrangement;

[0097] The drains of the 16 pairs of complementary switches controlled by the second control word level and its inverted level are connected to the sources of the 32 pairs of complementary switches controlled by the first control word level and its inverted level in a binary decreasing arrangement;

[0098] The drains of the eight pairs of complementary switches controlled by the third control word level and its inverted level are connected to the sources of the 16 pairs of complementary switches controlled by the second control word level and its inverted level in a binary decreasing arrangement;

[0099] The drains of the four pairs of complementary switches controlled by the fourth control word level and its inverted level are connected to the sources of the eight pairs of complementary switches controlled by the third control word level and its inverted level in a binary decreasing arrangement;

[0100] The drains of the two pairs of complementary switches controlled by the fifth control word level and its inverted level are connected to the sources of the four pairs of complementary switches controlled by the fourth control word level and its inverted level in a binary decreasing arrangement;

[0101] The drains of the pair of complementary switches controlled by the sixth control word level and its inverted level are connected to the sources of the two pairs of complementary switches controlled by the fifth control word level and its inverted level in a binary decreasing arrangement;

[0102] The resistor array has a "pyramid" structure, and the voltage at the output end of the resistor array is a voltage value of a node among the 128 nodes of the 128 series resistors.

[0103] The resistor array makes the bandgap reference voltage V BG_REF calibrated to 1.2V, thus increasing the The linearity with temperature is improved, thus overcoming the influence of operational amplifier offset voltage on temperature measurement accuracy under different process angles. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. The drawings in the following description are only one embodiment of the present invention.

[0105] Figure 1 It is a schematic structural diagram of a temperature sensor according to an embodiment of the present invention;

[0106] Figure 2 It is a structural schematic diagram of the mirror current source in one embodiment of the present invention;

[0107] Figure 3 It is a schematic diagram of the structure of the starting circuit in one embodiment of the present invention;

[0108] Figure 4 is a schematic diagram of the structure of the voltage calibration circuit in one embodiment of the present invention;

[0109] Figure 5 is a schematic diagram of the structure of the resistor array in one embodiment of the present invention;

[0110] Figure 6 It is a structural schematic diagram of the analog-to-digital conversion circuit in one embodiment of the present invention;

[0111] Figure 7 This is a temperature measurement error diagram of a temperature sensor described in the present invention simulated under different process angles. DETAILED DESCRIPTION

[0112] The core of the present invention is to provide a CMOS temperature sensor, which avoids the situation where the test accuracy of the CMOS temperature sensor decreases due to the influence of the operational amplifier offset voltage on the bandgap reference voltage under different process angles.

[0113] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0114] It should be noted that the diagrams provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated. The described embodiments are only part of the embodiments of the present invention, not all of them.

[0115] See also Figure 1 , which is a schematic structural diagram of a CMOS temperature sensor provided by the present invention in one embodiment.

[0116] like Figure 1 The CMOS temperature sensor shown includes: a startup circuit 1, a bandgap reference circuit, a third branch, a mirror current source 2, a voltage calibration circuit 3, an analog-to-digital conversion circuit 4, and a temperature calibration module, wherein:

[0117] The bandgap reference circuit comprises:

[0118] A first folded cascode operational amplifier (hereinafter referred to as the first operational amplifier) ​​A1;

[0119] A first NMOS transistor Mn1 of deep N-well technology with a gate connected to the first operational amplifier A1 and a drain connected to the mirror current source 2;

[0120] A first branch connected to the first NMOS transistor Mn1;

[0121] A second branch connected to the first NMOS transistor Mn1;

[0122] The bandgap reference circuit outputs a bandgap reference voltage V to the analog-to-digital conversion circuit 4 when the analog-to-digital conversion circuit 4 is in the sampling phase. BG With positive temperature coefficient voltage V PTAT ; (PTAT, proportional to absolute temperature, positively correlated with absolute temperature)

[0123] The mirror current source 2 provides a bias current to the first operational amplifier A1;

[0124] The two output terminals of the startup circuit 1 are respectively connected to the gate and drain of the first NMOS transistor Mn1 to start the bandgap reference circuit.

[0125] The first branch comprises:

[0126] The first transistor Q1;

[0127] A third resistor R3 connected in series with the first transistor Q1;

[0128] A first resistor R1 connected in series with a third resistor R3, wherein the first resistor R1 is connected to a source of the first NMOS transistor Mn1;

[0129] The second branch comprises:

[0130] The second transistor Q2;

[0131] A second resistor R2 connected in series with the second transistor Q2, wherein the second resistor R2 is connected to the source of the first NMOS transistor Mn1;

[0132] The third branch comprises:

[0133] The third transistor Q3;

[0134] A fourth resistor R4 connected in series with the third transistor Q3 is used to generate a common mode level required by the analog-to-digital conversion circuit;

[0135] The fourth resistor R4 is connected to the source of the first NMOS transistor Mn1; the positive input terminal of the first operational amplifier A1 is connected to the upper end of the third resistor R3, and the negative input terminal is connected to the lower end of the second resistor R2, and the first operational amplifier A1 makes the voltage drop of the first resistor R1 and the second resistor R2 equal;

[0136] The voltage difference between the base and emitter of the transistor is V BE It can be expressed as, Since the base of the transistor is connected to the collector and grounded, and the influence of the base current is ignored, it is considered that I C =I E , that is, the emitter current is equal to the collector current, and I E =I PTAT , so Where k is the Boltzmann constant, T is the absolute temperature, q is the charge constant, and I S is the saturation current, I C is the transistor collector current, I E is the transistor emitter current, I PTAT is the positive temperature coefficient current.

[0137] Since the PNP transistor is commonly used in this application, the following is Figure 1 The implementation method is described as an example. For NPN transistors, the principle can be referenced thereto.

[0138] Figure 1 In the bandgap reference circuit shown in FIG. 1 , the first transistor Q1 of the first branch, V BE1 V is the absolute value of the voltage drop between the base of the first transistor Q1 and the emitter of the first transistor Q1, that is, V is obtained by subtracting the base potential of the first transistor Q1 from the emitter potential of the first transistor Q1. BE1 ; Accordingly, the second transistor Q2 of the second branch, V BE2 is the absolute value of the voltage drop between the base of the second transistor Q2 and the emitter of the second transistor Q2.

[0139] In this embodiment, since the area ratio of the first transistor Q1 to the second transistor Q2 is P:1, P=24. S1 =I S2 , I S1 is the saturation current of the first transistor Q1, I S2is the saturation current of the second transistor Q2. It should be noted that, in practical applications, a transistor can be used as the first transistor Q1, and its area is P times that of the second transistor Q2, or multiple transistors can be connected in parallel, which is equivalent to the first transistor Q1 required by this application. In practical applications, P transistors are usually connected in parallel, which is equivalent to the first transistor Q1 required by this application. Each of the P transistors in parallel is a transistor of the same size and model as the second transistor Q2. This embodiment adopts this parallel connection method.

[0140] Due to the "virtual short" effect, the two input terminals of the first operational amplifier A1 clamp the voltage at the second terminal of the second resistor R2 and the voltage at the first terminal of the third resistor R3 to the same potential. Therefore, the voltage drop across the third resistor R3 is V BE2 -V BE1 , that is, the base-emitter voltage difference between the second transistor Q2 and the first transistor Q1 is ΔV BE =V BE2 -V BE1 ,and The positive temperature coefficient current Since the current of the first branch is the same as that of the second branch, the voltage drop across the second resistor R2 is The ratio of the second resistor R2 to the third resistor R3 is α, so the voltage drop across the second resistor R2 is The bandgap reference voltage It can be seen that the bandgap reference voltage V BG =ΔV BE With V BE2 A linear combination of the V BE2 is a negative temperature coefficient voltage, the ΔV BE is a positive temperature coefficient voltage, from which a zero temperature coefficient voltage V BG , that is, the bandgap reference voltage V BG In this embodiment, the ratio α of the second resistor R2 to the third resistor R3 is 5.78, and the obtained bandgap reference voltage V BG The value is 1.2V under the tt (NMOS Typical, PMOSTypical) process corner.

[0141] In the third branch, the size of the third transistor Q3 is the same as that of the second transistor Q2, the third branch is provided with a bias current by the mirror current source 2, and the resistance of the fourth resistor R4 is the same as that of the second resistor R2. Therefore, the voltage value outputted from the first end of the fourth resistor R4 is equal to the bandgap reference voltage V BGSimilarly, this voltage is used to generate a common-mode level provided to the analog-to-digital conversion circuit. It should be noted that the common-mode level generating circuit is Figure 1 Not shown.

[0142] See also Figure 2 , which is a schematic diagram of the structure of an embodiment of the mirror current in the present invention.

[0143] In this embodiment, the mirror current source 2 includes:

[0144] The gate receives the temperature sensor enable control signal PWD and the inverting signal A first transmission gate switch T1 and a second transmission gate switch T2;

[0145] A seventh PMOS transistor Mp7 having a source connected to a power source, a drain connected to a first end of the first transmission gate switch T1, and a gate connected to a second end of the first transmission gate switch T1;

[0146] The gate and the temperature sensor enable control inverting signal An eighth PMOS tube Mp8 connected with a source electrode connected to a power supply and a drain electrode connected to a gate electrode of the seventh PMOS tube Mp7;

[0147] A ninth PMOS tube Mp9 having a source connected to a power supply, a gate connected to a drain of the eighth PMOS tube Mp8, and a drain outputting a first bias current;

[0148] A tenth PMOS tube Mp10 having a source connected to a power supply, a gate connected to the gate of the ninth PMOS tube Mp9, and a drain outputting a second bias current;

[0149] An eleventh PMOS tube Mp11 having a source connected to a power supply, a gate connected to the gate of the tenth PMOS tube Mp10, and a drain outputting a third bias current;

[0150] A twelfth PMOS tube Mp12 having a source connected to a power supply, a gate connected to the gate of the eleventh PMOS tube Mp11, and a drain outputting a fourth bias current;

[0151] A thirteenth PMOS transistor Mp13 having a source connected to a power source and a gate connected to the gate of the twelfth PMOS transistor Mp12;

[0152] A twenty-second NMOS transistor Mn22 having a source connected to the ground, a drain connected to the drain of the thirteenth PMOS transistor Mp13, and a gate connected to the second end of the second transmission gate switch T2;

[0153] A twenty-third NMOS transistor Mn23 having a source connected to the ground, a drain connected to the gate of the twenty-second NMOS transistor Mn22, and a gate connected to the temperature sensor enable control signal PWD;

[0154] The drain of the seventh PMOS transistor Mp7 is connected to the drain of the first NMOS transistor Mn1, and the gate of the twenty-second NMOS transistor Mn22 provides a control signal V of the startup circuit. ST , a first end of the second transmission gate switch is connected to a power source.

[0155] In this embodiment, when the enable control signal PWD is at a low level, the CMOS temperature sensor is in a working state, the seventh PMOS tube Mp7 provides a bias current to the first NMOS tube Mn1, the ninth PMOS tube Mp9 provides a bias current to the first operational amplifier A1, the tenth PMOS tube Mp10 provides a bias current to the third branch, the eleventh PMOS tube Mp11 provides a bias current to the voltage calibration circuit 3, and the twelfth PMOS tube Mp12 provides a bias current to the common-mode level generating circuit. It should be noted that the common-mode level generating circuit is not shown in the schematic diagram of this example.

[0156] See also Figure 3 , which is a schematic diagram of the structure of the startup circuit in one embodiment of the present invention.

[0157] In this embodiment, the startup circuit 1 includes:

[0158] The gate receives the temperature sensor enable control signal PWD and the inverting signal A third transmission gate switch T3 and a fourth transmission gate switch T4;

[0159] The gate and the control signal V ST A second NMOS transistor Mn2 connected with a source connected to ground and a drain connected to a first end of the third transmission gate switch T3;

[0160] A fifth resistor R5 with a second end connected to the drain of the second NMOS transistor Mn2;

[0161] A first PMOS transistor Mp1 having a gate connected to the temperature sensor enable control signal PWD, a source connected to a power supply, and a drain connected to the first end of the fifth resistor R5;

[0162] A third NMOS transistor Mn3 having a gate connected to the second end of the third transmission gate switch T3, a drain connected to the second end of the fifth resistor R5, and a source connected to the ground;

[0163] A fifth NMOS transistor Mn5 having a gate connected to the temperature sensor enable control signal PWD, a drain connected to the gate of the third NMOS transistor Mn3, and a source connected to the ground;

[0164] A fourth NMOS transistor Mn4 having a gate connected to the third NMOS transistor Mn3, a source connected to the ground, and a drain connected to the first end of the fourth transmission gate switch T4;

[0165] The gate and the temperature sensor enable control inverting signal A third PMOS transistor Mp3 having a source connected to a power supply and a drain connected to a gate of the second PMOS transistor Mp2;

[0166] A fourth PMOS transistor Mp4 having a gate connected to the gate of the second PMOS transistor Mp2, a source connected to a power source, and a drain connected to the gate of the first NMOS transistor Mn1;

[0167] A sixth NMOS transistor Mn6 having a gate connected to the drain of the fifth NMOS transistor Mn5 , a source connected to the ground, and a drain connected to the drain of the first NMOS transistor Mn1 .

[0168] In this embodiment, when the temperature sensor enable control signal PWD is at a low level, the first PMOS tube Mp1 in the startup circuit 3 is turned on, and at this time, a current will flow through the resistor R5. Usually, the value of R5 is very large, at the megohm level. When the third NMOS tube Mn3 enters the saturation region, the fourth NMOS tube Mn4 mirrors the current flowing through the third NMOS tube Mn3, and the fourth PMOS tube Mp4 mirrors the current flowing through the fourth NMOS tube, raising the gate voltage of the first NMOS tube Mn1. The sixth NMOS tube Mn6 mirrors the current of the third NMOS tube Mn3, and the sixth NMOS tube extracts current from the branch where the seventh PMOS tube Mp7 in the mirror current source 2 is located, so that the drain voltage of the first NMOS tube Mn1 reaches a steady-state value, ensuring that the first NMOS tube Mn1 is turned on and enters the saturation region; thereafter, the thirteenth PMOS tube Mp13 in the mirror current source 2 mirrors the current of the seventh PMOS tube Mp7, so that the control signal V ST The level rises, and the second NMOS tube Mn2 in the startup circuit 3 enters the linear region, so that the drain voltage of the second NMOS tube Mn2 drops to zero level, prompting the third NMOS tube Mn3 in the startup circuit 3 to be turned off. At this point, the startup circuit 3 stops working, and the startup of the bandgap reference circuit is completed.

[0169] See also Figure 4 , which is a schematic diagram of the structure of the voltage calibration circuit in one embodiment of the present invention. The voltage calibration circuit 3 includes:

[0170] The first input terminal is connected to the bandgap reference voltage V BG A second operational amplifier A2 connected;

[0171] A third capacitor C3 having a first end connected to the output end of the second operational amplifier A2 and a second end connected to ground;

[0172] A twenty-first NMOS transistor Mn21 having a gate connected to the output terminal of the second operational amplifier A2 and a drain connected to a power supply;

[0173] The resistor array 31 having a first input terminal receiving an 8-bit control word and a second input terminal connected to a second input terminal of the second operational amplifier A2;

[0174] A seventh resistor R7 has a first end connected to the lower end of the resistor array 31 and a second end grounded.

[0175] In this embodiment, the first input terminal of the second operational amplifier A2 receives the bandgap reference voltage V BG The output end of the second operational amplifier A2 drives the gate of the twenty-first NMOS tube Mn21, the twenty-first NMOS tube Mn21 acts as a source follower, the third capacitor C3 adjusts the loop pole of the entire voltage calibration circuit 3, and the seventh resistor R7 is usually larger to limit the current flowing through the twenty-first NMOS tube Mn21.

[0176] See also Figure 5 , which is a schematic diagram of the structure of the resistor array in one embodiment of the present invention. The highest bit D7 of the 8-bit control word is used to control the bandgap reference voltage V BG When the highest bit D7 is at a high level, the bandgap reference voltage V BG The second end of the eighth resistor R8 is connected to realize the voltage downward step by step adjustment; when the highest bit D7 is at a low level, the bandgap reference voltage V BG Connect to the second end of the 136th resistor to achieve voltage adjustment upward step by step. It should be noted that Figure 5 Not all components in this embodiment are shown. For the specific location distribution and connection relationship of each component, please refer to the previous description and will not be repeated here.

[0177] In this embodiment, the value of the 8-bit control word determines the calibrated bandgap reference voltage V BG_REF The 8-bit control word determines the bandgap reference voltage V by selecting 128 voltage nodes with different series resistances. BG_REF When the bandgap reference voltage V input by the voltage calibration circuit 3 BGWhen the input 8-bit control word changes, the output bandgap reference voltage V BG_REF is 1.2V. It should be noted that in order to determine the output bandgap reference voltage V BG_REF The size of the bandgap reference voltage V BG_REF It can be set according to actual needs. In other implementations, different numbers of bits of the input control word and other circuit structures matching them can also be set according to needs, which does not affect the implementation of the present invention.

[0178] See also Figure 6 , which is a schematic diagram of the structure of the analog-to-digital conversion circuit in one embodiment of the present invention.

[0179] In this embodiment, the analog-to-digital conversion circuit 4 includes:

[0180] A shift register for generating a successive approximation comparison clock;

[0181] The first terminal is connected to the bandgap reference voltage V BG A sampling and holding circuit is connected to the emitter of the second transistor Q2, and is used to sample and hold the voltage αΔV during the sampling phase of the analog-to-digital conversion circuit. BE , this voltage is the differential voltage;

[0182] The first end and the second end receive the differential voltage αΔV output by the sampling and holding circuit BE , a comparator of a differential structure receiving a comparison clock output by the shift register at a third terminal and outputting a digital code after analog-to-digital conversion at a fourth terminal;

[0183] For successive approximation of the differential voltage αΔV BE Capacitor array;

[0184] V BG_REF A capacitor switching control circuit as a reference voltage and controlled by the comparator output terminal signal and the comparator output terminal inversion signal;

[0185] The first end is connected to the sampling and holding circuit, and the second end and the third end are connected to the capacitor switching control circuit, and are used to provide a clock generation circuit for providing a corresponding clock control signal;

[0186] A digital output register connected to the output terminal of the comparator and used to capture and store the digital code output by the comparator in the successive approximation process.

[0187] The comparator comprises:

[0188] A fifth PMOS transistor Mp5 having a source connected to a power source and a gate connected to its own drain;

[0189] A sixth PMOS transistor Mp6 having a source connected to a power source and a gate connected to its own drain;

[0190] The fifth PMOS tube Mp5 and the sixth PMOS tube Mp6 are connected in a diode manner as loads;

[0191] A sixth resistor R6 with a second end grounded, used for limiting the operating current of the comparator;

[0192] The gate and temperature sensor enable control signal PWD is an inverted signal A ninth NMOS transistor Mp9 whose source is connected to the sixth resistor R6;

[0193] The gate voltage is related to the voltage signal V IP A seventh NMOS transistor Mn7 connected to the drain of the fifth PMOS transistor Mp5 and a source connected to the ninth NMOS transistor Mn9;

[0194] The gate voltage is related to the voltage signal V IN An eighth NMOS transistor Mn8 connected to the drain of the sixth PMOS transistor Mp6 and connected to the source of the ninth NMOS transistor Mn9;

[0195] A first capacitor C1 having a first end connected to the seventh NMOS transistor Mn7 and a second end connected to ground, and used to reduce equivalent input noise of the comparator;

[0196] A second capacitor C2 having a first end connected to the eighth NMOS transistor Mn8 and a second end connected to ground, and used to reduce the equivalent input noise of the comparator;

[0197] The first and second ends of the latch receive the drain differential voltage signal of the seventh NMOS transistor Mn7 and the eighth NMOS transistor Mn8, and the third and fourth ends output the differential voltage signal after comparison, and are used to latch and output digital codes.

[0198] During the sampling phase of the analog-to-digital conversion circuit 4, the sampling circuit receives the differential voltage αΔV from the bandgap reference circuit. BE In the comparison stage of the analog-to-digital conversion circuit 4, the differential voltage αΔV BE The two input terminals of the comparator are connected to the calibrated bandgap reference voltage V BG_REFIt should be noted that the control logic of the analog-to-digital conversion circuit 4 in this embodiment is a successive approximation control logic, and the comparator will perform successive comparison and approximation in the comparison phase of the analog-to-digital conversion circuit 4, and finally quantify the ratio linearly related to temperature. The digital output register is used to capture the digital codes outputted successively by the comparator in a comparison phase and realize synchronous output. It should also be noted that, considering that the clock cycle of the analog-to-digital conversion circuit is relatively long, the speed requirement of the comparator is not high. In order to limit the power consumption of the comparator, the comparator used in this example is a static comparator, and the use of a dynamic comparator can also meet the functional requirements. The capacitor array described in this embodiment adopts an 11-bit redundant capacitor structure. The specific capacitor array structure can be set and adjusted according to the actual required accuracy and other requirements, and does not affect the implementation of the present invention.

[0199] Simulation experiment

[0200] To further prove the effectiveness of the CMOS temperature sensor product of this embodiment, the following simulation experiment was conducted. Using Cadence simulation software, SMIC 180nm CMOS process, power supply voltage value of 3.3V, simulation was performed under various combinations of process angles of resistors, capacitors, MOS tubes, and triodes. The output digital code data was processed by Matlab software to obtain the temperature measurement error. Figure 7 , which shows a temperature measurement error diagram of the temperature sensor simulated under different process angles.

[0201] In summary, the CMOS temperature sensor provided by the present invention utilizes voltage calibration to overcome the effect of operational amplifier offset voltage on reference voltage V under different process angles. BG The influence of temperature measurement is more accurate.

[0202] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "upper end", "lower end", "left side", "right side", and "vertical" are used only to indicate the positional relationship of components in the schematic diagram of the embodiment of this document, and do not represent the actual positional relationship.

[0203] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. For those skilled in the art, the above embodiments may be modified or changed without violating the spirit and scope of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A CMOS temperature sensor, characterized in that: include: Start-up circuit, bandgap reference circuit, third branch, mirror current source, voltage calibration circuit, analog-to-digital conversion circuit, temperature calibration module; The bandgap reference circuit comprises: a first operational amplifier, a first NMOS transistor, a first branch, and a second branch, wherein: The gate of the first NMOS tube is connected to the first operational amplifier, and the drain of the first NMOS tube is connected to the mirror current source; The first branch is connected to the first NMOS tube; The second branch is connected to the first NMOS tube; The bandgap reference circuit outputs a bandgap reference voltage to the analog-to-digital conversion circuit when the analog-to-digital conversion circuit is in the sampling phase With positive temperature coefficient voltage ; The first branch includes: a first triode, a third resistor, and a first resistor, wherein: The third resistor is connected in series with the first transistor, and the first resistor is connected in series with the third resistor. The first resistor is connected to the source of the first NMOS tube; The second branch includes: a second triode and a second resistor, which are connected in series, and the second resistor is connected to the source of the first NMOS transistor; The positive input terminal of the first operational amplifier is connected to the upper end of the third resistor, and the negative input terminal thereof is connected to the lower end of the second resistor, and the first operational amplifier makes the voltage drops of the first resistor and the second resistor equal; The third branch includes: a third triode and a fourth resistor, which are connected in series and used to generate a common mode level required by the analog-to-digital conversion circuit, and the fourth resistor is connected to the source of the first NMOS tube; The first transistor, the second transistor and the third transistor are all PNP transistors. The gate of the first NMOS tube is connected to the output terminal of the first operational amplifier and the second terminal of the startup circuit, and the drain of the first NMOS tube is connected to the mirror current source and the first terminal of the startup circuit. The source of the first NMOS tube is connected to the first end of the first resistor; The second end of the first resistor is connected to the first end of the third resistor, The second end of the third resistor is connected to the emitter of the first transistor. The collector and base of the first transistor are grounded; The first end of the second resistor is connected to the source of the first NMOS transistor, the second end of the second resistor is connected to the emitter of the second transistor, and the collector and base of the second transistor are grounded; A first end of the fourth resistor is connected to the mirror current source, a second end of the fourth resistor is connected to the emitter of the third triode, and the collector and base of the third triode are grounded; During the sampling phase of the analog-to-digital conversion circuit, the second branch provides the voltage to the analog-to-digital conversion circuit. and the bandgap reference voltage , the third branch is used to generate the common mode level required by the analog-to-digital conversion circuit; The area ratio of the first transistor to the second transistor is P:1, P=24, is the voltage drop across the third resistor, is the voltage drop across the second resistor, that is, = , .

2. A CMOS temperature sensor as claimed in claim 1, characterized in that: The analog-to-digital conversion circuit is used to utilize a reference voltage Quantify the voltage drop across the second resistor, the positive temperature coefficient voltage , and use With reference voltage Ratio Determine the ambient temperature; The analog-to-digital conversion circuit comprises: A shift register for generating a successive approximation comparison clock; A sampling and holding circuit, wherein a first terminal of the sampling and holding circuit is connected to the bandgap reference voltage The second end of the transistor is connected to the emitter of the second transistor, and is used to sample and hold the voltage during the sampling phase of the analog-to-digital conversion circuit. , this voltage is the differential voltage; A comparator with a differential structure, wherein the first terminal and the second terminal of the comparator receive the differential voltage output by the sampling and holding circuit , a third terminal thereof receives the comparison clock output by the shift register, and a fourth terminal thereof outputs the digital code after analog-to-digital conversion; For successive approximation of the differential voltage Capacitor array; A capacitor switching control circuit, wherein the capacitor switching control circuit is As a reference voltage and controlled by the comparator output terminal signal and the comparator output terminal inversion signal; A clock generating circuit, wherein a first terminal of the clock generating circuit is connected to the sampling and holding circuit, and a second terminal and a third terminal of the clock generating circuit are connected to the capacitor switching control circuit, and is used to provide a corresponding clock control signal; A digital output register, connected to the output terminal of the comparator, for capturing and storing a digital code output by the comparator during a successive approximation process; The voltage signals at the differential input terminals of the comparator are respectively , ; The comparator comprises: A fifth PMOS tube, whose source is connected to the power supply and whose gate is connected to its own drain; A sixth PMOS tube, whose source is connected to the power supply and whose gate is connected to its own drain; a sixth resistor having a second end grounded; The ninth NMOS tube has a gate connected to the temperature sensor enable control signal The inverted signal connected, with its source connected to the sixth resistor; The seventh NMOS tube has a gate connected to the voltage signal connected, its drain is connected to the drain of the fifth PMOS tube, and its source is connected to the ninth NMOS tube; The eighth NMOS tube has a gate connected to the voltage signal connected, its drain is connected to the drain of the sixth PMOS tube, and its source is connected to the ninth NMOS tube; A first capacitor, a first end of which is connected to the seventh NMOS transistor, and a second end of which is grounded; A second capacitor, a first end of which is connected to the eighth NMOS transistor, and a second end of which is grounded; The latch has a first end and a second end receiving the drain differential voltage signal of the seventh NMOS tube and the eighth NMOS tube, and a third end and a fourth end outputting the differential voltage signal after the comparison is completed.

3. A CMOS temperature sensor as claimed in claim 1, characterized in that: The mirror current source is used to provide a bias current to the first operational amplifier, to provide a bias current to the analog-to-digital conversion circuit, and to provide a bias current to the first branch, the second branch, and the third branch, and the bias current is a positive temperature coefficient current. ; The mirror current source comprises: The gates of the first transmission gate switch and the second transmission gate switch both receive the temperature sensor enable control signal And the inverted signal ;in a seventh PMOS transistor, whose source is connected to the power supply, whose drain is connected to the first end of the first transmission gate switch, and whose gate is connected to the second end of the first transmission gate switch; The eighth PMOS tube has a gate connected to the temperature sensor to enable the control inverting signal connected, its source is connected to the power supply, and its drain is connected to the gate of the seventh PMOS tube; a ninth PMOS tube, whose source is connected to the power supply, whose gate is connected to the drain of the eighth PMOS tube, and whose drain outputs the first bias current; a tenth PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the ninth PMOS tube, and whose drain outputs the second bias current; an eleventh PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the tenth PMOS tube, and whose drain outputs a third bias current; a twelfth PMOS tube, whose source is connected to the power supply, whose gate is connected to the gate of the eleventh PMOS tube, and whose drain outputs a fourth bias current; a thirteenth PMOS tube, whose source is connected to the power supply and whose gate is connected to the gate of the twelfth PMOS tube; A twenty-second NMOS transistor, whose source is connected to the ground, whose drain is connected to the drain of the thirteenth PMOS transistor, and whose gate is connected to the second end of the second transmission gate switch; The source of the twenty-third NMOS tube is connected to the ground, the drain of the twenty-second NMOS tube is connected to the gate of the twenty-second NMOS tube, and the gate of the twenty-third NMOS tube is connected to the temperature sensor enable control signal. connect; The drain of the seventh PMOS tube is connected to the drain of the first NMOS tube, and the gate of the twenty-second NMOS tube provides a control signal for the startup circuit. , a first end of the second transmission gate switch is connected to a power source.

4. A CMOS temperature sensor as claimed in claim 1, characterized in that: The startup circuit has a first end connected to the drain of the first NMOS transistor and a second end connected to the gate of the first NMOS transistor, and is used to enable the bandgap reference loop to self-start; The startup circuit comprises: Its gate receives the temperature sensor enable control signal And the inverted signal a third transmission gate switch and a fourth transmission gate switch; The second NMOS tube has a gate connected to the control signal connected, with its source connected to ground and its drain connected to the first end of the third transmission gate switch; a fifth resistor, a second end of which is connected to the drain of the second NMOS tube; The first PMOS tube has its gate connected to the temperature sensor enable control signal connected, its source is connected to the power supply, and its drain is connected to the first end of the fifth resistor; A third NMOS transistor, whose gate is connected to the second end of the third transmission gate switch, whose drain is connected to the second end of the fifth resistor, and whose source is connected to the ground; The fifth NMOS tube has a gate connected to the temperature sensor enable control signal connected, its drain is connected to the gate of the third NMOS tube, and its source is connected to the ground; a fourth NMOS transistor, whose gate is connected to the third NMOS transistor, whose source is connected to the ground, and whose drain is connected to the first end of the fourth transmission gate switch; The third PMOS tube has a gate connected to the temperature sensor to enable the control of the inverting signal connected, its source is connected to the power supply, and its drain is connected to the gate of the second PMOS tube; a fourth PMOS tube, whose gate is connected to the gate of the second PMOS tube, whose source is connected to the power supply, and whose drain is connected to the gate of the first NMOS tube; A sixth NMOS tube has a gate connected to the drain of the fifth NMOS tube, a source connected to the ground, and a drain connected to the drain of the first NMOS tube.

5. A CMOS temperature sensor as claimed in claim 1, characterized in that: The voltage calibration circuit has a first end connected to the source of the first NMOS tube and a second end connected to the analog-to-digital conversion circuit, and is used to calibrate the bandgap reference voltage. , so that it can overcome the influence of the offset voltage of the first operational amplifier and provide a more accurate reference voltage for the analog-to-digital conversion circuit ; The voltage calibration circuit comprises: A second operational amplifier, a first input terminal of which is connected to the bandgap reference voltage connect; A third capacitor, a first end of which is connected to the output end of the second operational amplifier, and a second end of which is grounded; A twenty-first NMOS transistor, a gate of which is connected to the output terminal of the second operational amplifier, and a drain of which is connected to a power supply; A resistor array, a first input terminal of which receives an 8-bit control word, and a second input terminal of which is connected to a second input terminal of the second operational amplifier; a seventh resistor, a first end of which is connected to the lower end of the resistor array, and a second end of which is grounded; The source of the twenty-first NMOS tube is connected to the upper end of the resistor array, and the resistor array outputs the calibrated bandgap reference voltage .

6. A CMOS temperature sensor as claimed in claim 5, characterized in that: The resistor array comprises: an eleventh NMOS tube whose gate receives the seventh-bit control word level; A twelfth NMOS tube whose gate receives the inverted level of the seventh control word, wherein the eleventh NMOS tube and the twelfth NMOS tube form a pair of complementary switches; The eighth resistor to the one hundred and thirty-sixth resistor connected in series, a total of 128 resistors; A thirteenth NMOS tube whose gate receives the level of the zeroth control word; A fourteenth NMOS tube whose gate receives the inverted level of the zeroth control word, the thirteenth NMOS tube and the fourteenth NMOS tube form a pair of complementary switches, and a total of 64 pairs of complementary switches of the same type controlled by the zeroth control word level and its inverted level are distributed vertically; There are 32 pairs of complementary switches controlled by the first control word level and its inverted level on the right side of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level; There are 16 pairs of complementary switches controlled by the second control word level and its inverted level on the right side of the 32 pairs of complementary switches controlled by the first control word level and its inverted level; There are a total of 8 pairs of complementary switches controlled by the third control word level and its inverted level, which are located on the right side of the 16 pairs of complementary switches controlled by the second control word level and its inverted level; There are a total of 4 pairs of complementary switches controlled by the fourth control word level and its inverted level located on the right side of the 8 pairs of complementary switches controlled by the third control word level and its inverted level; There are two pairs of complementary switches controlled by the fifth control word level and its inverted level on the right side of the four pairs of complementary switches controlled by the fourth control word level and its inverted level; A total of one pair of complementary switches controlled by the sixth control word level and its inverted level, located on the right side of the two pairs of complementary switches controlled by the fifth control word level and its inverted level, are the nineteenth NMOS tube and the twentieth NMOS tube; in: The drain of the eleventh NMOS tube is connected to the second input terminal of the resistor array, the source of the eleventh NMOS tube is connected to the second terminal of the eighth resistor, and the source of the twelfth NMOS tube is connected to the second terminal of the first one hundred and thirty-sixth resistor; The drains of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level are sequentially connected to the ends of the ninth resistor, the eleventh resistor, the thirteenth resistor, ..., the first one hundred and thirty-sixth resistor; The drains of the 32 pairs of complementary switches controlled by the first control word level and its inverted level are connected to the sources of the 64 pairs of complementary switches controlled by the zeroth control word level and its inverted level in a binary decreasing arrangement; The drains of the 16 pairs of complementary switches controlled by the second control word level and its inverted level are connected to the sources of the 32 pairs of complementary switches controlled by the first control word level and its inverted level in a binary decreasing arrangement; The drains of the eight pairs of complementary switches controlled by the third control word level and its inverted level are connected to the sources of the 16 pairs of complementary switches controlled by the second control word level and its inverted level in a binary decreasing arrangement; The drains of the four pairs of complementary switches controlled by the fourth control word level and its inverted level are connected to the sources of the eight pairs of complementary switches controlled by the third control word level and its inverted level in a binary decreasing arrangement; The drains of the two pairs of complementary switches controlled by the fifth control word level and its inverted level are connected to the sources of the four pairs of complementary switches controlled by the fourth control word level and its inverted level in a binary decreasing arrangement; The drains of the pair of complementary switches controlled by the sixth control word level and its inverted level are connected to the sources of the two pairs of complementary switches controlled by the fifth control word level and its inverted level in a binary decreasing arrangement; The resistor array has a "pyramid" structure, and the output terminal voltage of the resistor array is a node voltage value among the 128 nodes of the 128 series resistors; The resistor array enables the bandgap reference voltage calibrated to 1.2V, thus increasing the The linearity with temperature is improved, thus overcoming the influence of operational amplifier offset voltage on temperature measurement accuracy under different process angles.

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