Testing methods for semiconductor components

Abstract

This invention provides a method for testing semiconductor components. The main steps include fabricating a circuit redistribution layer on the semiconductor component under test using photolithography; then, test probes contact the circuit redistribution layer instead of directly contacting the semiconductor component; and finally, the circuit redistribution layer is removed using dry, wet, or mechanical polishing processes. This invention can improve the testing speed of semiconductor components, reduce testing costs, and leave no test probe marks on the semiconductor component after testing.

Description

Technical Field

[0001] This invention relates to a testing method for semiconductor components, and more particularly to a method for testing semiconductor components using circuit redistribution layers. Background Technology

[0002] Please see Figure 1 , Figure 1 This is a schematic diagram of an existing semiconductor component testing method. As shown in the figure, a plurality of semiconductor components 10 are located on a substrate SUB. Each semiconductor component 10 includes a first metal pad 11 and a second metal pad 13. If the semiconductor component 10 is, for example, a diode, then the first metal pad 11 and the second metal pad 13 are connected to the anode and cathode, respectively. The probe card 20 includes a plurality of probes 21, as shown in the figure. The spacing between the probes 21 is equal to the spacing between the first metal pad 11 and the second metal pad 13.

[0003] The smaller the probe spacing of the probe card 20, the higher its manufacturing cost. Conversely, the maintenance cost of a finely manufactured probe card is also relatively higher. For example, after the probe 21 comes into contact with the metal pad several times, it is easy for metal or metal oxide to adhere to it. Therefore, after several uses, the probe needs to be cleaned or sent back to the original manufacturer for repair, which requires the production line to purchase more probe cards, thus increasing production costs.

[0004] In particular, for sub-millimeter light-emitting diodes (mini LEDs) with a die size of approximately 100μm and micro light-emitting diodes (micro LEDs) with an even smaller die spacing, the detection technology has become a major bottleneck in the production process. Summary of the Invention

[0005] One objective of this invention is to provide a method for testing semiconductor components. The main steps include fabricating a circuit redistribution layer on the semiconductor component under test using a photolithography process, then testing probes do not directly contact the semiconductor component under test, but instead contact the circuit redistribution layer for testing, and finally removing the circuit redistribution layer using a dry, wet, or mechanical polishing process.

[0006] One objective of this invention is to provide a testing method for semiconductor components, wherein when measuring semiconductor components, the probe spacing of the probe card is greater than the spacing between the metal pads of the semiconductor components, so that the testing process only requires the use of low-cost probe cards, and does not require the use of finely manufactured and expensive probe cards.

[0007] One objective of this invention is to provide a method for testing semiconductor components, which can use a set of probes to test multiple semiconductor components, thereby increasing the speed of testing semiconductor components.

[0008] One objective of this invention is to provide a testing method for semiconductor components, which mainly uses a circuit redistribution layer on the semiconductor component under test, so that no test pin marks are left on the semiconductor component under test after the test is completed.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] A method for testing a semiconductor component includes: (1) fabricating at least one redistribution layer on a chip to be tested; (2) testing an array of semiconductor components on the chip using the redistribution layer; and (3) removing the redistribution layer on the chip; wherein the length of the semiconductor component is between 2 μm and 150 μm, and the width is between 2 μm and 150 μm.

[0011] Preferably, the semiconductor component is a sub-millimeter light-emitting diode, a micrometer light-emitting diode, a driver IC, or an RFID IC.

[0012] Preferably, step (2) includes: testing the semiconductor component array on the chip with a probe card, wherein the probes on the probe card do not directly contact the semiconductor components, but contact the circuit redistribution layer for testing.

[0013] Preferably, the semiconductor component has a plurality of metal pads, and the spacing between probes on the probe card is greater than the spacing between metal pads on the semiconductor component.

[0014] Preferably, step (1) includes: coating a first photoresist layer on the chip; forming a first via opening on the first photoresist layer; depositing a metal seed layer on the surface of the chip; coating a second photoresist layer on the metal seed layer; forming a second via opening above the first via; electroplating a copper pillar layer on the exposed metal seed layer; removing the second photoresist layer; and removing the exposed metal seed layer.

[0015] Preferably, the thickness of the first photoresist layer is between 1 μm and 30 μm; the width of the first via is between 0.5 μm and 40 μm, and the depth is between 0.5 μm and 10 μm; the thickness of the metal seed layer is between 0.02 μm and 3 μm; the width of the second via is between 0.5 μm and 200 μm, and the depth is between 0.5 μm and 30 μm; and the thickness of the copper pillar layer is between 0.5 μm and 25 μm.

[0016] Preferably, step (3) includes: removing the copper pillar layer; removing the metal seed layer; and removing the first photoresist layer.

[0017] Preferably, the material of the first photoresist layer is polyimide, diazonaphthoquinone, polyolefin, or chemically amplified photoresist material, and the material of the metal seed layer is one of copper, titanium, gold, or silver.

[0018] A semiconductor component tested by the above-described test method, wherein the tested semiconductor component has no test pin marks.

[0019] A semiconductor component tested by the above-described test method, wherein a metal reaction related to the metal seed layer can be measured on the surface of the tested semiconductor component; and a material reaction related to the first photoresist layer can be measured on the surface of the tested semiconductor component. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of existing semiconductor component testing methods.

[0021] Figure 2A , 2B This is a schematic diagram of an embodiment of the semiconductor component testing method of the present invention.

[0022] Figure 3 This is a schematic diagram of an embodiment of the semiconductor component testing method of the present invention.

[0023] Figure 4 This is a schematic diagram of an embodiment of the semiconductor component testing method of the present invention.

[0024] Figure 5 This is a schematic diagram of an embodiment of the semiconductor component testing method of the present invention.

[0025] Figures 6A to 6L This is a schematic diagram of an embodiment of a step in the semiconductor component testing method of the present invention.

[0026] Figure 7 This is a cross-sectional view of another embodiment of the semiconductor component testing method of the present invention.

[0027] Figures 8A to 8C This is a flowchart of an embodiment of the semiconductor component testing method of the present invention.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1-Chip; 10-Semiconductor component; 11-First metal pad; 13-Second metal pad; 20-Probe card; 21-Probe; 40-First photoresist layer; 50-Metal seed layer; 60-Second photoresist layer; 70-Copper pillar layer; RDL1, RDL2, RDL3, RDL4, RDL5, RDL6-Circuit redistribution layers; SUB-Substrate; S10, S20, S30, S101, S102, S103, S104, S105, S301, S302, S303-Steps; via-Through hole; via1-First through hole; via2-Second through hole Detailed Implementation

[0030] Please see Figure 2A and Figure 2B This is a schematic diagram of an embodiment of the semiconductor component testing method of the present invention. Figure 2A This is a schematic diagram of the semiconductor component under test, illustrated here using an array of six semiconductor components 10 as an example. Each semiconductor component 10 has a first metal pad 11 and a second metal pad 13. The length of the semiconductor component 10 is between 2 μm and 150 μm, and the width is between 2 μm and 150 μm. Please refer to [link to next section]. Figure 2B This method utilizes photolithography to fabricate redistribution layers on the semiconductor components under test, as shown in the diagram as RDL1 and RDL2. Redistribution layer RDL1 connects to the first metal pads 11 of the six semiconductor components 10, and redistribution layer RDL2 connects to the second metal pads 12 of the six semiconductor components 10. The wider areas P1 of RDL1 and P2 of RDL2 are the probe contact points. In this way, a single set of probes can complete the testing of all six semiconductor components 10, and the probe spacing is several times the spacing between the metal pads of the semiconductor components 10.

[0031] and Figure 2B This embodiment means that a set of probes can be used to test two rows or two columns of semiconductor components in a semiconductor component array. In actual semiconductor component array products, a row or column of a semiconductor component array usually has dozens, hundreds, or thousands of semiconductor components. Therefore, this embodiment can test an array very efficiently.

[0032] Please refer to the following: Figure 3This is a schematic diagram of another embodiment of the semiconductor component testing method of the present invention. As shown, chip 1 includes a plurality of semiconductor components 10 located on a substrate SUB. Each semiconductor component 10 includes a first metal pad 11 and a second metal pad 13. For testing the semiconductor components 10, a circuit redistribution layer is fabricated on chip 1 using a photolithography process, including RDL1 to RDL6 and other circuit redistribution layers not shown in the figure. As shown, due to the narrow space between the boundaries of chip 1 and the semiconductor components 10, this embodiment does not test the top, bottom, rightmost, and leftmost rows of semiconductor components 10 on chip 1. Although some semiconductor components 10 are not tested, according to the characteristics of semiconductor manufacturing processes, if the semiconductor components 10 are arranged in a matrix with N columns and M rows, and if (N-2) x (M-2) semiconductor components 10 all pass the test, the defect rate of the untested semiconductor components 10 at the boundaries is quite low, making it a test method accepted by quality control based on probabilistic statistical derivation.

[0033] like Figure 3 As shown, the redistribution layers RDL1 to RDL6 respectively connect the first metal pads 11 or second metal pads 13 of N-2 semiconductor components 10 in a row. For example, the redistribution layers RDL1 and the first metal pads 11 of the N-2 semiconductor components 10 are connected by vias. A via is an opening between the redistribution layer and the metal pad, filled with conductive metal to connect the redistribution layer and the metal pad. The via is located between the redistribution layer and the metal pad; for ease of explanation, in... Figure 3 The presence of vias on the trace redistribution layer indicates that the trace redistribution layer is connected to the underlying metal pads through the vias; otherwise, there is an insulating layer separating the trace redistribution layer from the metal pads. For example, the wider area at the top of the trace redistribution layer RDL1 is where the probe is to be tested. Although it overlaps with the first metal pad 11 or the second metal pad 13 below, there is an insulating layer separating the two metal layers.

[0034] like Figure 3 As shown, redistribution layers RDL1 and RDL2, RDL3 and RDL4, and RDL5 and RDL6 are paired up to test N-2 semiconductor components 10. Since the probe area needs to be relatively large, in this embodiment, the probes for adjacent rows of semiconductor components 10 are located in the top and bottom columns, respectively. For example, the probes will test the wider area of ​​the top column for redistribution layers RDL1 and RDL2, and the probes will test the wider area of ​​the bottom column (not shown) for redistribution layers RDL3 and RDL4.

[0035] like Figure 3 In the illustrated embodiment, (N-2)x(M-2) semiconductor components 10 were tested in an NxM semiconductor component array, and the detection rate was (N-2)x(M-2) / (NxM). When the semiconductor process is stable, the yield steadily increases with tracking test data, and the analysis data can control the failure mode, the detection rate can be appropriately reduced, making the circuit redistribution process simpler and easier to control.

[0036] Please see Figure 4 This is a schematic diagram of another embodiment of the semiconductor component testing method of the present invention. As shown, chip 1 includes a plurality of semiconductor components 10 located on a substrate SUB. Each semiconductor component 10 includes a first metal pad 11 and a second metal pad 13. For testing the semiconductor components 10, a circuit redistribution layer is fabricated on chip 1 using photolithography, including RDL1 to RDL6 and other circuit redistribution layers not shown in the figure. Due to the narrow boundaries of chip 1 and the limited space for the semiconductor components 10, this embodiment does not test the top, bottom, right, and leftmost rows of semiconductor components 10 on chip 1. The number of vias in this embodiment is... Figure 3 The detection rate is about half that of the example. Figure 3 Half of the example. As... Figure 4 As shown, the distribution of its various vias is relatively dispersed and wide, making it easier to achieve in the manufacturing process and less susceptible to process defects. Similarly, Figure 4 The shortest distance between the line redistribution layers RDL1 to RDL6 in the embodiment is relative to each other. Figure 4 The implementation of the far-reaching embodiments is easier to achieve in terms of manufacturing process and is less affected by process defects.

[0037] Please refer to the following: Figure 5 This is a schematic diagram of another embodiment of the semiconductor component testing method of the present invention. As shown, chip 1 includes a plurality of semiconductor components 10 located on a substrate SUB. Each semiconductor component 10 includes a first metal pad 11 and a second metal pad 13. For testing the semiconductor components 10, a circuit redistribution layer is fabricated on chip 1 using photolithography, including RDL1 to RDL6 and other unlabeled circuit redistribution layers. Figure 5 As shown, the detection rate in this embodiment is 50%, and the semiconductor components 10 are tested independently. The circuit redistribution layout and testing method in this embodiment are suitable for the early stages of mass production, and can collect a large number of failure modes for yield improvement reference. Figure 5As shown, redistribution layers RDL1 and RDL2 can measure the semiconductor component 10 in the top left corner, but the semiconductor component 10 in the second column below it is not tested; while redistribution layers RDL3 and RDL4 can measure the semiconductor components 10 in the second row and sixth column, but the semiconductor component 10 in the fifth column above it is not tested. That is, this embodiment is a conventional checkerboard test. In this embodiment, the redistribution layers are vertical, but the present invention is not limited to this. When the length and width of the semiconductor components 10 are different, the redistribution layers can be arranged horizontally, or even in a square layout, all of which can achieve a checkerboard test with a detection rate of 50%. Other similar embodiments will not be described in detail here.

[0038] As can be seen from the above, based on the stability and maturity of semiconductor manufacturing processes and the test yield data of semiconductor components, big data analysis can be used to select appropriate detection rates and appropriate circuit redistribution layer layouts to realize the test method of the semiconductor components of this invention.

[0039] Please refer to the following: Figures 6A to 6F The diagram illustrates the process steps of the semiconductor component testing method of the present invention. Figure 6A The diagram shows a cross-sectional view of a semiconductor component embodiment. Chip 1 includes a plurality of semiconductor components 10 located on a substrate SUB. Each semiconductor component 10 includes a first metal pad 11 and a second metal pad 13. The first metal pad 11 and the second metal pad 12 are metal layers with a thickness between 0.1 μm and 1 μm, and are made of metals such as gold. The size W2 of the semiconductor component 10 is between 2 μm and 150 μm, and its thickness is between 3 μm and 20 μm. It is made of epitaxial substrates such as sapphire (Al2O3), silicon (Si), silicon carbide (SiC), or gallium nitride (GaN wafer). Chip 1 can be a complete wafer with a size between 4 inches and 8 inches, or a diced die.

[0040] Please refer to the following: Figure 6B This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6B As shown, a first photoresist layer 40 is coated on the surface of the chip 1 to be tested. The thickness T4 is between 1 μm and 30 μm. It can be a positive photoresist or a negative photoresist. The material can be a photoresist material such as polyimide (PI), diazonaphthoquinone (DNQ), chemical amplification (CA), or polyolefin.

[0041] Please refer to the following: Figure 6C This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6C As shown, in order to remove an opening in the first photoresist layer 40 above the first metal pad 11 and the second metal pad 13, the first via 1 is fabricated using a photolithography process involving exposure and development. The exposure light source can be ultraviolet light, such as I-line (365nm). The development process can use developing solutions such as tetramethylammonium hydroxide (TMAH), propylene glycol methyl ether acetate (PGMEA), monoethanolamine (MEA), or cyclopentanone to perform a wet process development operation to remove the photoresist. The development mode can include tank type, single-piece rotation type, or horizontal line conveyor type. The width W3 of the first via 1 is between 0.5μm and 40μm, and the depth T5 is between 0.5μm and 10μm.

[0042] like Figure 6C In the illustrated embodiment, both the first metal pads 11 and the second metal pads 13 on an entire column or row of conductor assemblies 10 have first vias 1. In other embodiments, the arrangement of the first vias 1 on which metal pads are arranged depends on their different detection rates, as described above. Figures 3 to 5 As shown in the embodiments, they will not be described again here.

[0043] Please refer to the following: Figure 6D This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. To ensure that the selected first metal pad 11 or second metal pad 13 can establish a good electrical connection with the future overlaid circuit layer, a metal seed layer 50 is deposited on the surface of the first via 1 and the existing first photoresist layer 40 using methods such as vapor deposition or sputtering. The material of the metal seed layer 50 can be copper (Cu), titanium (Ti), gold (Au), or silver (Ag), and its thickness is between 0.02 μm and 3 μm. When the material of the metal seed layer 50 is copper (Cu), its thickness is between 0.05 μm and 3 μm; when the material of the metal seed layer 50 is titanium (Ti), its thickness is between 0.02 μm and 1 μm.

[0044] Please refer to the following: Figure 6E This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Next, a second photoresist layer 60 is coated on the wafer surface, with a thickness T6 between 1 μm and 30 μm. This layer can be a positive photoresist or a negative photoresist, and its material can be a photoresist material such as polyimide (PI), diazonaphthoquinone (DNQ), chemical amplification (CA), or polyolefin.

[0045] Please refer to the following: Figure 6F This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6F As shown, in order for the metal seed layer 50 on the first via 1 to be filled with metal, an opening needs to be made above the original first via 1. The second via 2 is fabricated using photolithography, exposure, and development. The exposure light source can be ultraviolet light, such as I-line (wavelength 365nm). The development can be performed using a wet process to remove photoresist, using developers such as tetramethylammonium hydroxide (TMAH), propylene glycol methyl ether acetate (PGMEA), monoethanolamine (MEA), or cyclopentanone. The development mode can include tank type, single-piece rotary type, or horizontal line conveyor type. The width W4 of the second via 2 is between 0.5μm and 200μm, and the depth T7 is between 0.5μm and 30μm.

[0046] Please refer to the following: Figure 6G This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6G As shown, a copper pillar layer 70 is plated on the metal seed layer 50 on the second via 2. Using a metal electroplating process, copper (Cu) is electroplated, and copper (Cu) will adhere and deposit on the surface of the metal seed layer 50 to form the copper pillar layer 70, as shown. Figure 6G As shown. The thickness of the copper pillar layer 70 is between 0.5 μm and 25 μm.

[0047] Please refer to the following: Figure 6H This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6H The image shown is a cross-sectional view of the area after the second photoresist layer 60 has been removed. The removal of the second photoresist layer 60 is performed using a photoresist removal process, which can include methods such as wet chemical removal and dry plasma bombardment removal.

[0048] Please refer to the following: Figure 6I This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6I The image shown is a cross-sectional view of the first photoresist layer 40 after the metal seed layer 50 has been removed. The exposed metal seed layer 50 was removed using a chemical wet etching method, thus completing the circuit redistribution layer.

[0049] Please refer to the following: Figure 6J This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6JAs shown, after the circuit redistribution layer formed by the copper pillar layer 70 is completed, it is tested with probe 21. The number of semiconductor components 10 tested at one time varies depending on the circuit redistribution layer layout mode, ranging from 1 to 100,000 components per test unit, and they are tested sequentially until completion.

[0050] Please refer to the following: Figure 6K This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6K As shown, after the test is completed, the copper pillar layer 70 and the metal seed layer 50 and other metal materials are removed by chemical wet etching.

[0051] Please refer to the following: Figure 6L This is a schematic diagram illustrating one of the process steps of an embodiment of the semiconductor component testing method of the present invention. Figure 6L The image shown is a cross-sectional view after the first photoresist layer 40 has been removed following testing. The removal of the first photoresist layer 40 was performed using a photoresist removal process, which can employ methods such as wet chemical removal or dry plasma bombardment removal to remove the photoresist from the substrate SUB and semiconductor component 10 on the wafer. After all the related process materials for the circuit redistribution layer have been removed, it appears as if the circuit has returned to its original state. Figure 6A A similar situation occurred during the test. However, although the metal seed layer 50 that previously existed on the first metal pad 11 and the second metal pad 13 of the semiconductor component 10 has been removed, metal reactions related to the metal seed layer 50 can still be measured on them. Similarly, although the first photoresist layer 40 at other locations has also been removed, material reactions related to the first photoresist layer 40 can still be measured on it. Figure 6L The tested chip 1 may not show any probe marks from the test probes, or may only have a few marks, but the test data has already been collected on the test equipment.

[0052] Please refer to the following: Figure 7 This is a schematic diagram illustrating an embodiment of the semiconductor component testing method of the present invention. Figure 7 As shown, the copper pillar layer 70 forms a redistribution layer that spans two semiconductor components 10 and covers the first metal pad 11 of one semiconductor component 10 and the second metal pad 13 of the other semiconductor component 10. To fabricate a wider redistribution layer formed by the copper pillar layer 70, the width of the second via 2 in the manufacturing process must be wider, and its manufacturing process is similar to... Figures 6A to 6I Similarly, I will not go into details here. Figure 7 It can be regarded as Figure 5A cross-sectional view of an embodiment of a semiconductor component testing method shows two adjacent semiconductor components 10. Only one of the semiconductor components 10 has through-holes between its first metal pad 11 and second metal pad 13, resulting in a detection rate of 50%. This is particularly useful for semiconductor components with very small metal pad sizes, where even using expensive precision probe cards presents a testing bottleneck. Figure 7 This embodiment is an efficient, low-cost alternative, particularly because it eliminates the need for large metal pads on the wafer surface, allowing for the fabrication of more semiconductor components per unit wafer. For applications requiring 100% detection rate, this can be achieved by altering the via's position and performing two 50% detection rate semiconductor component tests. Another 50% detection rate embodiment is... Figure 7 Similarly, I will not go into details here.

[0053] Figure 2 to Figure 7 These are merely different embodiments of the present invention and not limitations on the scope of the invention. The present invention demonstrates its advantages particularly in testing semiconductor components arranged in an array, but this application is not limited to this. For various reasons, it is not desirable to directly test the metal pads of a semiconductor component; the present invention can be used to complete semiconductor component testing. Especially with the continuous miniaturization of semiconductor manufacturing technology, metal pads that can be directly tested often occupy a significant area of ​​the semiconductor chip; the present invention can reduce the chip size. Therefore, integrated circuits such as Mini LEDs, Micro LEDs, driver ICs, and radio frequency identification (RFID) ICs, whole wafers, and chips that have been diced or are being packaged are all targets for the implementation of this invention, and the implementation methods are similar, so they will not be described in detail here.

[0054] In semiconductor manufacturing processes, multiple metal layers are commonly used to complete wire connections in order to reduce chip size. The circuit redistribution layer of this invention can also employ a multi-layer circuit redistribution structure to complete the testing of semiconductor components; that is, there are insulating layers separating different circuit redistribution layers, and the lower circuit redistribution layers are connected to the uppermost circuit redistribution layer via vias. For example, in similar... Figures 6A to 6L Another embodiment includes a plurality of copper pillar layers, and uses inter-gold dielectric (IMD) layers such as undoped silicon glass and fluorinated silicon glass to space different copper pillar layers. The upper and lower copper pillar layers are connected by through-holes. Other processes are similar and will not be described in detail here.

[0055] Please refer to the following: Figure 8AThe flowchart below illustrates a semiconductor component testing method according to the present invention, comprising: step S10, fabricating at least one redistribution layer on the chip under test; step S20, testing the semiconductor component on the chip using the redistribution layer; and step S30, removing the redistribution layer from the chip. In one embodiment, the length of the semiconductor component is between 2 μm and 150 μm, and the width is between 2 μm and 150 μm. In another embodiment, the test probe does not directly contact the semiconductor component under test, but rather contacts the redistribution layer for testing.

[0056] Please refer to the following: Figure 8B ,for Figure 8A The flowchart of step S10 of the semiconductor component testing method of the present invention includes: step S101, coating a first photoresist layer on the chip under test; step S102, fabricating a first via opening on the first photoresist layer; step S103, depositing a metal seed layer on the wafer surface; step S104, coating a second photoresist layer on the metal seed layer; step S105, fabricating a second via opening above the first via; step S106, electroplating a copper pillar layer on the exposed metal seed layer; step S107, removing the second photoresist layer; and step S108, removing the exposed metal seed layer. In one embodiment, the thickness of the first photoresist layer is between 1 μm and 30 μm. In one embodiment, the width of the first via is between 0.5 μm and 40 μm, and the depth is between 0.5 μm and 10 μm. In one embodiment, the thickness of the metal seed layer is between 0.02 μm and 3 μm. In one embodiment, the width of the second through-hole is between 0.5 μm and 200 μm, and the depth is between 0.5 μm and 30 μm. In another embodiment, the thickness of the copper pillar layer is between 0.5 μm and 25 μm.

[0057] Please refer to the following: Figure 8C ,for Figure 8A The flowchart of step S30 of the semiconductor component testing method of the present invention includes: step S301, removing the copper pillar layer; step S302, removing the metal seed layer; and step S303, removing the first photoresist layer.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A method of testing a semiconductor assembly, characterized by, The semiconductor components are arranged in an array on a substrate of a chip, the array having columns and rows of semiconductor components, wherein each semiconductor component includes a first metal pad and a second metal pad, and the testing method includes: (1) applying a first photoresist layer on the chip to be tested; performing a first via opening on the first photoresist layer; plating a metal seed layer on the first via on the chip and on the surface of the first photoresist layer; applying a second photoresist layer on the metal seed layer; performing a second via opening on the second photoresist layer on the first via; electroplating a copper pillar layer on the exposed metal seed layer; removing the second photoresist layer; and removing the exposed metal seed layer on the surface of the first photoresist layer; thereby forming at least one redistribution layer on the chip; (2) testing the array of semiconductor components on the chip with a probe card, wherein the probes on the probe card do not directly contact the semiconductor components, but contact the redistribution layer for testing; and (3) removing the redistribution layer on the chip; wherein the semiconductor components have a length of 2 µm to 150 µm and a width of 2 µm to 150 µm, and the spacing between the probes on the probe card is greater than the spacing between the first metal pad and the second metal pad on the semiconductor components.

2. The test method of claim 1, wherein, The semiconductor components are submillimeter light emitting diodes, micrometer light emitting diodes, driver ICs, or RFID ICs.

3. The test method of claim 1, wherein, The first photoresist layer has a thickness of 1 µm to 30 µm; the first via has a width of 0.5 µm to 40 µm and a depth of 0.5 µm to 10 µm; the metal seed layer has a thickness of 0.02 µm to 3 µm; the second via has a width of 0.5 µm to 200 µm and a depth of 0.5 µm to 30 µm; and the copper pillar layer has a thickness of 0.5 µm to 25 µm.

4. The test method of claim 1, wherein, Step (3) includes: removing the copper pillar layer; removing the metal seed layer; and removing the first photoresist layer.

5. The test method of claim 1, wherein, The material of the first photoresist layer is polyimide, diazonaphthoquinone, polyolefin, or a chemically amplified photoresist material, and wherein the material of the metal seed layer is one of copper, titanium, gold, or silver.

6. A semiconductor assembly completed by the testing method of claim 3, wherein, The surface of the tested semiconductor components is capable of measuring a metal reaction related to the metal seed layer; and the surface of the tested semiconductor components is capable of measuring a material reaction related to the first photoresist layer.

Images