Computer-readable storage medium, data reading method and device of flash memory chip

Abstract

The present application relates to a computer readable storage medium, a data reading method and device for a flash memory chip, the method is implemented when a processing unit loads and executes program code, comprising: issuing a read instruction to a flash interface, driving the flash interface to start a data reading operation for reading data from a location of the chip; calculating an output time point corresponding to the read instruction; and when the current time reaches or is later than the output time point, issuing a random output instruction corresponding to the read instruction to the flash interface, driving the flash interface to store the data to a random access memory. Thus, the present application determines the timing of issuing the random output instruction by the output time point as described above, which can avoid the NAND bus being occupied by unnecessary waiting for a read busy instruction and inquiring a NAND state instruction.

Description

TECHNICAL FIELD

[0001] The present invention relates to a storage device, in particular, the present invention relates to a computer readable storage medium, a data read method and apparatus for multiple flash memory chips. BACKGROUND

[0002] Flash memories are generally classified into NOR flash memories and NAND flash memories. NOR flash memories are random access devices, in which a host can provide any address for accessing the NOR flash memories on an address pin and obtain data stored at the address from a data pin of the NOR flash memories in time. On the contrary, NAND flash memories are not random access but serial access. Unlike NOR flash memories, NAND flash memories cannot access any random address, and a host needs to write values of serial bytes into the NAND flash memories for defining a type of a command (e.g., read, write, erase, etc.) and an address used in the command. The address can point to a page (a minimum data block for a write operation in the flash memory) or a block (a minimum data block for an erase operation in the flash memory).

[0003] Efficiently reading data from flash memory cells in multiple chips has been an important issue in flash memory controllers. Therefore, the present invention proposes a computer readable storage medium, a data read method and apparatus for multiple flash memory chips for shortening a time for performing a read operation. SUMMARY

[0004] In view of the above, how to alleviate or eliminate the deficiencies in the related art is a problem to be solved.

[0005] The present invention relates to a data read method for multiple flash memory chips, implemented when a program code is loaded and executed by a processing unit, comprising: issuing a read instruction to a flash memory interface, driving the flash memory interface to initiate a data read operation for reading data from a location of a chip; calculating an output time point corresponding to the read instruction; and issuing a random output instruction corresponding to the read instruction to the flash memory interface when a current time reaches or is later than the output time point, driving the flash memory interface to store the data into a random access memory.

[0006] The present invention also relates to a computer readable storage medium for storing a program code capable of being executed by a processing unit, and the program code is implemented as the data read method for multiple flash memory chips as described above when executed by the processing unit.

[0007] The present application also relates to a data reading device for multiple flash memory chips, comprising a flash memory interface and a processing unit. The flash memory interface is coupled to a first chip and a second chip through the same channel. The processing unit is coupled to the flash memory interface, sends a first reading instruction to the flash memory interface, drives the flash memory interface to start a first data reading operation for reading first data from a first location of the first chip, calculates a first output time point corresponding to the first reading instruction, sends a second reading instruction to the flash memory interface, drives the flash memory interface to start a second data reading operation for reading second data from a second location of the second chip, calculates a second output time point corresponding to the second reading instruction, and sends a random output instruction corresponding to the second reading instruction to the flash memory interface when the current time has not reached or is later than the first output time point but has reached or is later than the second output time point, and drives the flash memory interface to store the second data into a random access memory.

[0008] One of the advantages of the above-mentioned embodiments is that the timing of sending the random output instruction is determined by the output time points, which can avoid the NAND bus being occupied by unnecessary waiting reading busy instruction and querying NAND state instruction.

[0009] Other advantages of the present application will be illustrated in more detail in conjunction with the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of this application and illustrate embodiments of the present application and together with the description serve to explain the present application, but do not limit the present application in any manner.

[0011] Figure 1 A system architecture diagram of an electronic device according to an embodiment of the present application.

[0012] Figure 2 A schematic diagram of a flash memory module according to an embodiment of the present application.

[0013] Figure 3 A time sequence diagram of sending a reading instruction and a random output instruction for some embodiments.

[0014] Figure 4 A flowchart of a data reading method for multiple flash memory chips according to an embodiment of the present application.

[0015] Figure 5 A schematic diagram of judging the relationship between the current time and the output time points according to an embodiment of the present application.

[0016] Figure 6 A time sequence diagram of sending a reading instruction and a random output instruction according to an embodiment of the present application.

[0017] In the drawings:

[0018] 10 electronic device

[0019] 110 host

[0020] 130 flash controller

[0021] 131 host interface

[0022] 132 bus architecture

[0023] 134 processing unit

[0024] 136 random access memory

[0025] 139 flash interface

[0026] 150 flash module

[0027] 151 interface

[0028] 153 #0-153 #15 NAND flash cell

[0029] CH #0-CH #3 channel

[0030] CE #0-CE #3 enable signal

[0031] t31, t33, t35 time point

[0032] RE #0, RE #1 read instruction

[0033] tLead #0, tLead #1 read lead time

[0034] RO #0, RO #1 random output instruction

[0035] tMove #0, tMove #1 data output time

[0036] S410-S470 method steps

[0037] T now time point

[0038] t out , t out #0, t out #1 output time point DETAILED DESCRIPTION

[0039] Embodiments of the present application will be described below with reference to the accompanying drawings. In these drawings, the same reference numbers indicate the same or similar components or method flows.

[0040] It must be understood that the terms "comprise", "comprising", "include", "including", or "has" or "having" used in the specification, are used in the sense of "including" rather than "consisting of".

[0041] The use of the terms "first", "second", "third", etc. in the present disclosure is used to modify components in the claims and is not used to designate priority, precedence, or order of execution, or time of execution, but is used only to distinguish one component from another component having a same name.

[0042] It must be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or intervening components can be present. In contrast, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present. Other words used to describe the relationship between components should be interpreted in a like fashion, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

[0043] Reference Figure 1The electronic device 10 includes a host side 110, a flash controller 130, and a flash module 150, and the flash controller 130 and the flash module 150 can be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as personal computers, laptop PCs, tablet computers, mobile phones, digital cameras, digital video cameras, and the like. The host side 110 and a host interface 131 of the flash controller 130 can communicate with each other using a communication protocol such as a universal serial bus (USB), an advanced technology attachment (ATA), a serial advanced technology attachment (SATA), a peripheral component interconnect express (PCI-E), a universal flash storage (UFS), an embedded multi-media card (eMMC), or the like. A flash interface 139 of the flash controller 130 and the flash module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as an open NAND flash interface (ONFI), a DDR toggle, or other communication protocols. The flash controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (e.g., a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and provides functions described later when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as read commands, write commands, erase commands, and the like, through the host interface 131, schedules, and executes these commands.The flash controller 130 also includes a random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two, for configuration space as a data buffer, to store user data (also referred to as host data) read from the host 110 and to be written to the flash memory 150, and to store user data read from the flash memory 150 and to be output to the host 110. The random access memory 136 can also store data required during execution of a process, such as variables, data tables, a host-to-flash (H2F) table, a flash-to-host (F2H) table, and the like. The flash interface 139 includes a NAND flash controller (NFC) to provide functionality required for accessing the flash memory 150, such as a command sequencer, low density parity check (LDPC), and the like. A bus architecture 132 can be configured in the flash controller 130 to allow components to be coupled to each other to transfer data, addresses, control signals, and the like, including the host interface 131, the processing unit 134, the RAM 136, the flash interface 139, and the like.

[0044] The flash module 150 provides a large amount of storage space, typically hundreds of Gigabytes (GB) or even multiple Terabytes (TB), for storing a large amount of user data, such as high-resolution pictures, videos, and the like. The flash module 150 includes a control circuit and a memory array, and the memory cells in the memory array can be configured as Single Level Cells (SLCs), Multiple Level Cells (MLCs), Triple Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination thereof after being erased. The processing unit 134 writes user data to a specified address (destination address) in the flash module 150 and reads user data from a specified address (source address) in the flash module 150 through the flash interface 139. The flash interface 139 uses a plurality of electronic signals to coordinate the transfer of data and commands between the flash controller 130 and the flash module 150, including data lines, clock signals, and control signals. The data lines can be used to transfer commands, addresses, read and write data; the control signal lines can be used to transfer control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), Write Enable (WE), and the like.

[0045] Referring to Figure 2 , the interface 151 in the flash module 150 can include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash cells, for example, channel CH#0 is connected to NAND flash cells 153#0, 153#4, 153#8, and 153#12, and so on. Each NAND flash cell can be packaged as an independent die. The flash interface 139 can activate one of the activation signals CE#0 to CE#3 through the interface 151 to activate the NAND flash cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the activated NAND flash cells or write user data to the activated NAND flash cells in a parallel manner.

[0046] The flash interface 139 also includes an instruction queue, a cache, and a controller. The instruction queue can sequentially store a series of instructions, such as Read, Wait RB, Polling NAND Status, Random Out, and the like, issued by the processing unit 134 for completing a data read operation according to the time of arrival. The controller extracts the instructions from the instruction queue in a first-in first-out (FIFO) manner and executes them. The cache provides temporary storage space for the data read out from the flash module 150.

[0047] To execute a host read command issued by the host 110, or to perform a background operation for improving the storage performance of the flash module 150, the processing unit 134 can issue a read instruction to the flash interface 139 for driving the flash interface 139 to initiate a data read operation. The background operation includes garbage collection (GC), wear leveling, read refresh, read reclaim, etc. The read instruction includes a die number, a row address, a column address, etc. so that the controller can use the data lines and control signals between the flash interface 139 and the flash module 150 to read data of a specified column on a specified row from a specified NAND flash cell (e.g., one of the NAND flash cells 153#0 to 153#15). The NAND flash cell needs a period of time to prepare the data, and after the data preparation is completed, a read ready signal is used to notify the flash interface 139, and then the flash interface 139 can start to acquire the specified data from the NAND flash cell through the data lines and store the data in a buffer therein. The period of time from when the read instruction is issued from the processing unit 134 to the flash interface 139 to when the flash interface 139 starts to acquire the specified data from the flash module 150 can be referred to as the actual read lead time. Then, the processing unit 134 can issue a random output instruction to the flash interface 139 for instructing the flash interface 139 to store the corresponding data in the buffer to a specified location in the RAM 136 through the bus architecture 132. The random output instruction corresponds to a read instruction issued previously and includes a die number, a row address, a column address, etc. so that the controller can store the specified data in the buffer to the specified location in the RAM 136 according to the information. For example, the processing unit 134 can issue a read instruction including a die number "Die#0", a row address "R#100", and a column address "C#0~4095" to the flash interface 139, and after the read lead time, issue a random output instruction including the die number "Die#0", the row address "R#100", and the column address "C#0~4095" to the flash interface 139 for acquiring the data of the specified location in the flash module 150.

[0048] In some implementations, after issuing a read command to the flash interface 139, the processing unit 134 may issue a corresponding "wait to read busy" command or "query NAND status" command to the flash interface 139, and determine whether the flash interface 139 can begin acquiring the specified data from the flash module 150 based on the response from the flash interface 139. When it is found that the data requested by the read command is ready, the processing unit 134 issues a corresponding random output command to the flash interface 139. However, when the flash interface 139 receives a read busy command or a NAND status query command, it will occupy the bus (also known as the NAND bus) between the flash interface 139 and the flash module 150 until the data specified by the read command has been acquired by the flash interface 139, resulting in a decrease in bandwidth utilization. (See reference...) Figure 3 The example shown has two NAND flash memory cells (also called chips) on the same channel. Processing unit 134 sequentially issues read commands "RE#0" and "RE#1" to flash interface 139 at times t31 and t33, respectively. Read command "RE#0" requests to read data from a specified location in chip "Die#0" of flash module 150, and read command "RE#1" requests to read data from a specified location in chip "Die#1" of flash module 150. Then, at time t35, processing unit 134 issues a read-read busy command or a NAND status query command corresponding to read command "RE#0" to flash interface 139, causing flash interface 139 to occupy the NAND bus for read command "RE#0". Assume the read lead time required for read command "RE#0" is shown as... Figure 3 The dashed box “tLead#0” in the text, and the read lead time required for the read command “RE#1” are displayed. Figure 3 The dashed box “tLead#1” is shorter than the read lead time required for the read command “RE#0”: after time point t35, the NAND bus is occupied by the read command “RE#0”, but no data is transmitted.

[0049] This invention provides a data reading method for multiple flash memory chips, executed when specific program code is loaded and executed by the processing unit 134. In one aspect, this method issues a read instruction to the flash memory interface 139, calculates the output time point corresponding to this read instruction, and stores the output time point in a cache in the processing unit 134. When the current time reaches or exceeds the output time point of this read instruction, a corresponding random output instruction is issued to the flash memory interface 139. This method repeatedly executes a loop and is applied to data reading operations of all chips associated with a specific channel, as detailed below:

[0050] Step S410: issue one or more read instructions to the flash interface 139 and calculate the output time point for each read instruction. Note that this step can be skipped if there is no read operation to perform. An example of the formula for calculating the output time point is as follows:

[0051] t out = T now + t prep

[0052] where t out represents the output time point of this read instruction, T now represents the time stamp of the current time, and t prep represents the estimated read lead time associated with this read instruction.

[0053] In some embodiments, t prep may vary with the chip associated with this read instruction, as shown in Table 1:

[0054] Table 1

[0055] Die #0 Read Latency Die #0 t prep = t0 Die #1 t prep = t1

[0056] The processing unit 134 can set the read lead time of this read instruction according to the chip number associated with this read instruction. For example, if the data to be read by this read instruction is stored in chip Die#0, the read lead time of this read instruction is set to t prep = t0.

[0057] In other embodiments, t prep may vary with the chip and the type of storage unit associated with this read instruction, as shown in Table 2:

[0058] Table 2

[0059] Die #0 SLC TLC Die #0 t prep = t0 t prep = t1 Die #1 t prep = t2 t prep = t3

[0060] The processing unit 134 can set the read lead time of this read instruction according to the chip number and the type of storage unit associated with this read instruction. For example, if the data to be read by this read instruction is stored in an SLC page in chip Die#0, the read lead time of this read instruction is set to t prep = t0. If the data to be read by this read instruction is stored in a TLC page in chip Die#1, the read lead time of this read instruction is set to t prep = t3.

[0061] In other embodiments, t prep may vary with the chip and the type of page associated with this read instruction, as shown in Table 3:

[0062] Table 3

[0063] Die #0 SLC Page TLC / L Page TLC / X Page TLC / U Page Die #0 t prep = t0 t prep = t1 t prep = t2 t prep = t3 Die #1 t prep = t4 t prep = t5 t prep = t6 t prep = t7

[0064] Each chip contains multiple physical blocks, each of which can be configured as an SLC block or a TLC block.

[0065] Each memory cell in an SLC block can store one of two states, denoted as "0b0" or "0b1". Each word line in an SLC block can store one page of data, referred to as an SLC page. Each memory cell in a TLC block can store one of eight states, denoted as "0b000", "0b001", "0b010", "0b011", "0b100", "0b101", "0b110", or "0b111". Each word line in a TLC block can store three pages of data, including a low page (TLC / L Page), a middle page (TLC / X Page), and a high page (TLC / U Page). The processing unit 134 can set the read latency of a read instruction according to the chip number and page type associated with the read instruction. For example, if the data to be read by the read instruction is stored on an SLC page in chip Die#0, the read latency of the read instruction is set to t prep = t0. If the data to be read by the read instruction is stored on a TLC / U page in chip Die#1, the read latency of the read instruction is set to t prep = t7.

[0066] In other embodiments, the setting of t prep may be based on the contents shown in Table 4:

[0067] Table 4

[0068]

[0069] Each chip contains multiple physical blocks, each of which can be configured as an SLC block or a QLC block. Each memory cell in a QLC block can store one of sixteen states, denoted as one of "0b0000" to "0b1111". Each word line in a QLC block can store four pages of data, including a low page (QLC / L Page), a middle page (QLC / X Page), a high page (QLC / U Page), and a top page (QLC / T Page). For example, if the data to be read by the read instruction is stored on an SLC page in chip Die#0, the read latency of the read instruction is set to t prep= t0. If the data desired to be read by this read instruction is stored on a QLC / T page in chip Die#1, the read lead time of this read instruction is set to t prep = t9.

[0070] Step S420: Prepare the random output instruction corresponding to each read instruction and store in the buffer in processing unit 134. It is noted that this step can be skipped if there is no read operation to be performed.

[0071] Step S430: Set variable i to i = 0.

[0072] Step S440: Determine if the current time is the same as or later than the output time point associated with the read instruction of the i-th chip. If yes, it means that the data required by the read instruction associated with the i-th chip is ready or has been prepared, then the flow continues with the processing of step S450; otherwise, it means that the data required by the read instruction associated with the i-th chip has not been prepared, then the flow proceeds with the processing of step S460. For example, referring to Figure 5 , the upper (A) part shows that the current time T now is later than the output time point t out of the read instruction associated with the i-th chip, while the lower (A) part shows that the current time T now is earlier than the output time point t out of the read instruction associated with the i-th chip.

[0073] Step S450: Issue the random output instruction associated with the i-th chip to the flash interface 139, which corresponds to the read instruction of the i-th chip.

[0074] Step S460: Set variable i to i = i + 1.

[0075] Step S470: Determine if the value of variable i is equal to the total number of chips connected to this channel. If yes, the flow continues with the processing of step S410; otherwise, the flow proceeds with the processing of step S440.

[0076] It is noted here that one skilled in the art can combine the operation of step S420 into step S450, and the present application is not limited in this regard.

[0077] Referring to the example shown in Figure 6 , there are two NAND flash units (also referred to as chips) on the same channel. The processing unit 134 sequentially issues the read instructions "RE#0" and "RE#1" to the flash interface 139 at time points t61 and t63, and calculates the output times "t out #0" and "t out#1", wherein the read instruction "RE#0" requests to read data from a specified location of chip "Die#0" in flash memory module 150, and the read instruction "RE#1" requests to read data from a specified location of chip "Die#1" in flash memory module 150 (step S410). Assume the read lead time required for the read instruction "RE#0" is displayed as... Figure 3 The dashed box “tLead#0” in the text, and the read lead time required for the read command “RE#1” are displayed. Figure 3 The dashed box “tLead#1” is shorter than the read lead time required for the read instruction “RE#0”. Then, when processing unit 134 is at time point T... now Determine if the current time has not arrived or is later than the output time point "t" of the read instruction "RE#0" associated with chip "Die#0". out When #0 is reached (the path of "No" in step S440), no operation is performed on the read instruction "RE#0". When processing unit 134 is at time point T now The current time is determined to be later than the output time of the read instruction "RE#1" associated with chip "Die#1". out When #1 is reached (the path of "Yes" in step S440), a corresponding random output command "RO#1" is issued to the flash interface 139, so that the data requested by the read command "RE#1" can be stored in the specified location in RAM 136 via the flash interface 139 at the data output time "tMove#1". Those skilled in the art will understand that the method described above does not issue wait-to-read busy commands or query NAND status to the flash interface 139, thus avoiding the NAND bus being occupied by unnecessary wait-to-read busy commands and query NAND status commands.

[0078] All or part of the steps in the method described in this invention can be implemented by a computer program, such as a Firmware Translation Layer (FTL) in a storage device, a driver for specific hardware in a computer, etc. Furthermore, they can also be implemented in other types of programs as shown above. Those skilled in the art can write the methods of the embodiments of this invention into program code, which will not be described further for the sake of brevity. The computer program implementing the method according to the embodiments of this invention can be stored on a suitable computer-readable storage medium, such as a DVD, CD-ROM, USB flash drive, or hard disk, or placed on a network server accessible via a network (e.g., the Internet, or other suitable media).

[0079] Although Figure 1 , Figure 2 It includes the components described above, but does not preclude the use of other additional components to achieve better technical results without violating the spirit of the invention. Furthermore, although...Figure 4 The flowcharts of the methods described herein are merely illustrative of the steps involved in the methods and the order in which the steps are performed. The steps can be modified, omitted, or supplemented with further steps, and the order of the steps can be changed, without departing from the spirit and scope of the invention. Furthermore, some steps can be performed concurrently, or in a different order than as described herein. Thus, the present invention should not be construed as limited to the order in which the steps are performed.

[0080] The above description is merely illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modifications, equivalents, and / or improvements, without departing from the spirit and scope of the present application, can be made thereto by one skilled in the art, and the present application should be construed as limited only by the claims.

Claims

1. A method for reading data from multiple flash memory chips, implemented by a processing unit when loading and executing program code, characterized in that, The method of reading data from a plurality of flash memory chips comprises: issuing a read command to a flash memory interface to drive the flash memory interface to initiate a data read operation for reading data from a specified location in a chip; providing a lookup table, wherein the lookup table stores information of a read latency associated with each of the plurality of chips; searching the lookup table to obtain a read latency of the specified chip as an estimated read latency; calculating an output time point corresponding to the read command, wherein the output time point is calculated using the following equation: t out = T now + t prep , t out a timestamp, t, representing a current time now a timestamp, t, representing a current time prep a timestamp, t, representing a current time issuing a random output command corresponding to the read command to the flash memory interface to drive the flash memory interface to store the data to a random access memory when a current time reaches or is later than the output time point.

2. The method of claim 1, wherein the data read request is received from the host device. The chip requires a period of time to prepare the data.

3. The method of claim 1, wherein the data read request is received from the host device, and the data read request includes a logical block address (LBA) of the data to be read. The estimated read latency corresponds to the chip associated with the read command.

4. The method of claim 1, wherein the data read request is received from the host device, and the data read request includes a logical block address (LBA) of the data to be read. The estimated read latency corresponds to the chip and a memory cell type associated with the read command, and the memory cell type is a single-level cell, a multi-level cell, a triple-level cell, or a quad-level cell.

5. The method of claim 1, wherein the data read request is received from the host device, and the data read request includes a logical block address (LBA) of the data to be read. The estimated read latency corresponds to the chip and a page type associated with the read command, and the page type is a single-level cell page, a low page in a triple-level cell block, a middle page in a triple-level cell block, or a high page in a triple-level cell block.

6. The method of claim 1, wherein the step of reading data from the plurality of flash memory chips comprises the steps of: reading data from the plurality of flash memory chips in a first mode; and reading data from the plurality of flash memory chips in a second mode. The estimated read latency corresponds to the chip and a page type associated with the read command, and the page type is a single-level cell page, a low page in a quad-level cell block, a middle page in a quad-level cell block, a high page in a quad-level cell block, or a top page in a quad-level cell block.

7. A computer readable storage medium storing program code executable by a processing unit, characterized in that, The program code, which causes the processing unit to execute, implements the method of reading data from a plurality of flash memory chips as claimed in any one of claims 1 to 6.

8. A data reading apparatus for multiple flash memory chips, characterized by comprising: The apparatus for reading data from a plurality of flash memory chips comprises: a flash memory interface to couple a first chip and a second chip in the same channel; and a processing unit coupled to the flash memory interface to issue a first read command to the flash memory interface to drive the flash memory interface to initiate a first data read operation for reading first data from a first location in the first chip, to calculate a first output time point corresponding to the first read command, to issue a second read command to the flash memory interface to drive the flash memory interface to initiate a second data read operation for reading second data from a second location in the second chip, to provide a lookup table storing information of a first read latency associated with the first chip and a second read latency associated with the second chip, to search the lookup table to obtain the second read latency of the second chip as an estimated read latency, and to calculate a second output time point corresponding to the second read command, wherein the second output time point is calculated using the following equation: t out =T now +t prep , t out a timestamp t representing a current time now a timestamp t representing a current time prep the estimated read latency associated with the second chip; and when the current time has not reached or is later than the first output time point but has reached or is later than the second output time point, issuing a random output instruction corresponding to the second read instruction to the flash interface to drive the flash interface to store the second data to a random access memory.

9. The data reading apparatus of multiple flash memory chips according to claim 8, wherein, The second chip requires a period of time to prepare the second data.

10. The data reading apparatus of multiple flash memory chips according to claim 8, wherein, The estimated read latency corresponds to the second chip associated with the second read command. The estimated read latency corresponds to the second chip associated with the second read command.

11. The data reading apparatus of multiple flash memory chips as claimed in claim 8, wherein, The estimated read latency corresponds to the second chip and memory cell type associated with the second read instruction, and the memory cell type is single-level cells, multi-level cells, triple-level cells, or quad-level cells.

12. The data reading apparatus of multiple flash memory chips according to claim 8, wherein, The estimated read latency corresponds to the second chip and page type associated with the second read instruction, and the page type is single-level cell pages, low pages in a triple-level cell block, middle pages in a triple-level cell block, or high pages in a triple-level cell block.

13. The data reading apparatus of multiple flash memory chips according to claim 8, wherein, The estimated read latency corresponds to the second chip and page type associated with the second read instruction, and the page type is single-level cell pages, low pages in a quad-level cell block, middle pages in a quad-level cell block, high pages in a quad-level cell block, or top pages in a quad-level cell block.

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