System and method for power management in memory design

Abstract

This disclosure relates to systems and methods for power management in memory design. One device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wake-up detector. The first and second virtual power lines are coupled to a power source via a first set of transistor switches and a second set of transistor switches. The first delay circuit is coupled between the gate terminals of the first and second sets of transistor switches. The first wake-up detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for power management in memory design. Background Technology

[0002] Static random access memory (SRAM) typically comprises bit cells distributed throughout a memory bank, along with various control circuitry that controls the read and write operations of these bit cells. Examples of control circuitry include local input / output circuitry, master input / output circuitry, local control circuitry, and master control circuitry. SRAM also includes power management circuitry for turning the power to the bit cells and the control circuitry on or off. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first virtual power line located in a first memory bank, the first virtual power line being configured to be coupled to a power source via a first set of transistor switches; a second virtual power line located in a second memory bank, the second virtual power line being configured to receive the power source via a second set of transistor switches; a first delay circuit having a first input coupled to a gate terminal of the first set of transistor switches and a first output coupled to a gate terminal of the second set of transistor switches; and a first wake-up detector configured to generate a first trigger signal after receiving a signal from the first output of the first delay circuit.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a plurality of main input / output (MIO) controllers configured to be coupled to a power supply via a first set of wake-up switches and a first set of function switches; a first set of local input / output (LIO) controllers configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches; a wake-up detector configured to generate a trigger signal when a voltage level supplying power to the plurality of MIO controllers and the first set of LIO controllers reaches a predetermined value; and a plurality of drivers having driver outputs coupled to gate terminals of the first set of function switches and gate terminals of the second set of function switches, and having driver inputs configured to receive the trigger signal.

[0005] According to another embodiment of this disclosure, a method for activating a memory device is provided, the memory device including a plurality of main input / output (MIO) controllers, a plurality of local input / output (LIO) controllers, a plurality of wake-up switches, a plurality of function switches, and a plurality of memory banks, wherein each memory bank includes a plurality of memory cells, the method comprising: establishing a power connection to memory cells in a first memory bank via a wake-up switch associated with a first memory bank; establishing a power connection to memory cells in a second memory bank via a wake-up switch associated with a second memory bank after a predetermined time period following the establishment of the power connection to the memory cells in the first memory bank; and providing power connections to the MIO controllers and the LIO controllers after the power connection to the memory cells in the second memory bank is completed. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram of a portion of a power management circuit having virtual power lines that power memory cells in a memory device, according to some embodiments.

[0008] Figure 2 This is a schematic diagram of a portion of a power management circuit having virtual power lines that supply power to various control circuits in a memory device, according to some embodiments.

[0009] Figure 3 According to some embodiments Figure 1 and Figure 2 A schematic diagram of the circuit combination of the power management circuit in the diagram.

[0010] Figure 4A This is a plan view illustration of a portion of a functional block in an SRAM according to some embodiments.

[0011] Figure 4B This is an illustration of a plan view of a portion of a functional block in another SRAM according to some embodiments.

[0012] Figure 5 This is a schematic diagram of a portion of a modified power management circuit having a virtual power line that powers memory cells in a memory device, according to some embodiments.

[0013] Figure 6This is a schematic diagram of an implementation of a wake-up switch and a function switch for managing power connections to a virtual power line, according to some embodiments.

[0014] Figures 7A-7C These are schematic diagrams illustrating various implementations of wake-up switches and function switches for managing power connections to virtual power lines, according to some embodiments.

[0015] Figure 8A It is a power management circuit according to some embodiments for managing power connections to memory cells in a memory device. Figure 1 A schematic diagram of another implementation of the wake-up detector.

[0016] Figure 8B It is a power management circuit according to some embodiments for managing power connections to various control circuits in a memory device. Figure 2 A schematic diagram of another implementation of the wake-up detector.

[0017] Figure 9 This is a flowchart of a method for activating a memory device according to some embodiments.

[0018] Figure 10A Based on some embodiments Figure 9 A flowchart of another method for activating a memory device, a variation of the method described in the diagram.

[0019] Figure 10B Based on some embodiments Figure 2 A schematic diagram of a portion of a modified power management circuit. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used in this document to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0022] Static Random Access Memory (SRAM) includes power management circuitry for turning the power to bit cells and the power to control circuitry on or off. Examples of control circuitry include Local Input / Output (LIO) circuitry, Master Input / Output (MIO) circuitry, Word Line Driver (WLDRV), Local Control Circuitry (LCTRL), and Master Control Circuitry (MCTRL). The LIO provides a data interface between the MIO and bit cells in one or more memory banks. The Word Line Driver is configured to select rows of bit cells to participate in read and / or write operations. The MIO provides a data interface between the SRAM and external circuitry. The Local Control Circuitry is configured to control the LIO. In some embodiments, the Local Control Circuitry includes a column address decoder and a row address decoder. The Master Control Circuitry includes an address pre-decoder and a synchronization clock.

[0023] In some SRAM design implementations, when a bit cell is powered by a dummy power line, the bit cell's power supply is managed by a field-effect transistor (FET) switch between the actual power supply (e.g., pull-up power supply VDD or pull-down power supply VSS) and the corresponding dummy power line. In some SRAM design implementations, when the SRAM's control circuitry is powered by a dummy power line, the SRAM's control circuitry's power supply is managed by a transistor switch (e.g., a FET switch between the actual power supply and the SRAM's control circuitry).

[0024] In some SRAM design implementations, to power the SRAM bit cells and control circuitry, the bit cells are divided into groups, and a daisy-chain wake-up scheme with time delays between different groups powers the bit cells through each group. The SRAM control circuitry is similarly powered, and the various parts of the SRAM are powered using a daisy-chain wake-up scheme with time delays between different parts. In some SRAM design implementations, when using a simple daisy-chain wake-up scheme, the balance between peak current and the time required to power the SRAM is not optimized. A power management method and system with a better balance between providing peak current and the time required to power the SRAM is desired.

[0025] Figure 1This is a schematic diagram of a portion of a power management circuit 100 according to some embodiments, the power management circuit 100 having virtual power lines supplying power to memory cells in a memory device. Figure 1 In this configuration, bit cells are distributed across four memory banks (e.g., 110, 120, 130, and 140). For clarity, details of the bit cells are omitted. Various types of bit cells used for the memory banks, as well as different configurations of the memory banks, are within the scope of this disclosure. Examples of bit cells used to construct the memory banks include synchronous bit cells, asynchronous bit cells, single-port SRAM bit cells, two-port SRAM bit cells, four-port SRAM bit cells, six-transistor 6T SRAM cells, eight-transistor 8T SRAM cells, ten-transistor 10T SRAM cells, or twelve-transistor 12T SRAM cells. Figure 1 In this system, bit cells in the memory bank are powered by virtual power lines.

[0026] Unlike physical power lines (e.g., the power rail of a pull-up power supply VDD or the power rail of a pull-down power supply VSS), the voltage level on a virtual power line is dynamically managed and can depend on the state of the memory device. As an example, in some embodiments, when the memory device changes from a powered mode to a sleep mode, the voltage level on the virtual power line of the pull-up power supply changes from the voltage level of VDD to a floating level (or ground level), while the voltage level on the physical power line of the pull-up power supply remains at a constant level of VDD. In some embodiments, the voltage level on the virtual power line is determined by one or more switching elements between the virtual power line and the corresponding physical power line. For example, when a header switch (e.g., a FET) is operatively coupled between the virtual power line of VDD and the power rail of the pull-up power supply VDD, the state of the header switch determines the voltage level on the virtual power line of VDD. When the header switch is closed, the virtual power line of VDD functions as a voltage source with the voltage level of VDD. When the header switch is open, the voltage level on the virtual power line of VDD is floating, and the virtual power line of VDD is not used as a voltage source to provide power. Similarly, when a footer switch (e.g., a FET) is operatively coupled between the dummy power line of the VSS and the power rail of the pull-down power supply VSS, the state of the footer switch determines the voltage level on the dummy power line of the VSS.

[0027] exist Figure 1In each of the memory banks (e.g., 110, 120, 130, and 140), there is a row with a fixed number of bit cells (e.g., bits [0], [1], ..., and bits [n-1]). The bit cells in memory bank 110 are powered by a virtual power line VDDAI[1]. The bit cells in memory bank 120 are powered by a virtual power line VDDAI[2]. The bit cells in memory bank 130 are powered by a virtual power line VDDAI[3]. The bit cells in memory bank 140 are powered by a virtual power line VDDAI[4]. The virtual power lines are coupled to the power supply voltage VDD via wake-up switches. Specifically, the virtual power line VDDAI[1] is coupled to the power supply voltage VDD via wake-up switches T11, T12, ..., and T19. The virtual power line VDDAI[2] is coupled to the power supply voltage VDD via wake-up switches T21, T22, ..., and T29. The virtual power line VDDAI[3] is coupled to the power supply voltage VDD through wake-up switches T31, T32, ..., and T39. The virtual power line VDDAI[4] is coupled to the power supply voltage VDD through wake-up switches T41, T42, ..., and T49.

[0028] In some alternative embodiments, the virtual power line of VDD is used to provide VDD power to all bit cells in the memory bank. In some alternative embodiments, the virtual power line of VDD is used to provide VDD power specifically to a row of bit cells in the memory bank. In some alternative embodiments, the virtual power line of VDD is used to provide VDD power specifically to a column of bit cells in the memory bank. In still other alternative embodiments, the virtual power line of VDD is used to provide VDD power specifically to several bit cells (e.g., one or two bit cells) in the memory bank.

[0029] exist Figure 1 In this circuit, the power management circuit includes a wake-up detector 150 and several delay circuits (e.g., 112, 114, 122, 124, 132, 134, 142, and 144). Each of the delay circuits (e.g., 112, 114, 122, 124, 132, 134, 142, and 144) has a first input and an output. Each of the delay circuits 122, 132, and 142 also has a second input. The first input of delay circuit 112 and the second inputs of delay circuits 122, 132, and 142 are coupled to a control line connected to a control input 101 of the power management circuit 100.

[0030] The gate terminals of the wake-up switches (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1] are connected to control line 113 and coupled to both the output of delay circuit 112 and the first input of delay circuit 114. The wake-up switches (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1] control the power connection between the virtual power line VDDAI[1] and the power node of the power supply voltage VDD. The gate terminals of the wake-up switches (e.g., T21, T22, ..., and T29) of the virtual power line VDDAI[2] are connected to control line 123 and coupled to both the output of delay circuit 122 and the first input of delay circuit 124. The wake-up switches (e.g., T21, T22, ..., and T29) of the virtual power line VDDAI[2] control the power connection between the virtual power line VDDAI[2] and the power node of the power supply voltage VDD. The gate terminals of the wake-up switches (e.g., T31, T32, ..., and T39) of the virtual power line VDDAI[3] are connected to control line 133 and coupled to both the output of delay circuit 132 and the first input of delay circuit 134. The wake-up switches (e.g., T31, T32, ..., and T39) of the virtual power line VDDAI[3] control the power connection between the virtual power line VDDAI[3] and the power node of the power supply voltage VDD. The gate terminals of the wake-up switches (e.g., T41, T42, ..., and T49) of the virtual power line VDDAI[4] are connected to control line 143 and coupled to both the output of delay circuit 142 and the first input of delay circuit 144. The wake-up switches (e.g., T41, T42, ..., and T49) of the virtual power line VDDAI[4] control the power connection between the virtual power line VDDAI[4] and the power node of the power supply voltage VDD. The output of delay circuit 144 is coupled to the input of wake-up detector 150. The output of wake-up detector 150 is coupled to control output 109. Figure 1 In this context, the wake-up switch is a transistor switch such as a FET switch.

[0031] In operation, when the control signal SD on control input 101 indicates the VDDAI falling state, the VDDAI falling signal is applied to control lines 113, 123, 133, and 143 respectively through delay circuits 112, 122, 132, and 142. The VDDAI falling signal on control line 113 is sent to the gate terminal of the wake-up switch (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1]. When the VDDAI falling signal is applied to control line 113, the wake-up switch (e.g., T11, T12, and T19) of the virtual power line VDDAI[1] is set to the off state, and the conductive connection between the virtual power line VDDAI[1] and the power node of the power supply voltage VDD is disconnected. As a result, the bit cells in memory bank 110 lose power connection. Similarly, when the VDDAI falling signal is applied to control line 123, the wake-up switches (e.g., T21, T22, and T29) of the virtual power line VDDAI[2] disconnect the conductive connection between the virtual power line VDDAI[2] and the power node of the power supply voltage VDD, and the bit cells in memory bank 120 lose power connection. When the VDDAI falling signal is applied to control line 133, the wake-up switches (e.g., T31, T32, and T39) of the virtual power line VDDAI[3] disconnect the conductive connection between the virtual power line VDDAI[3] and the power node of the power supply voltage VDD, and the bit cells in memory bank 130 lose power connection. When the VDDAI falling signal is applied to control line 143, the wake-up switches (e.g., T41, T42, and T49) of the virtual power line VDDAI[4] disconnect the conductive connection between the virtual power line VDDAI[4] and the power node of the power supply voltage VDD, and the bit cells in memory bank 140 lose power connection.

[0032] In operation, when the control signal SD on control input 101 indicates a change from a VDDAI falling state to a VDDAI rising state, a VDDAI rising signal is applied to the first input of delay circuit 112 and the second inputs of delay circuits 122, 132, and 142. Because the first inputs of delay circuits 122, 132, and 142 maintain logic HIGH when the bit cells in the memory bank (e.g., 110, 120, 130, and 140) are in the VDDAI falling state, the VDDAI rising signal (logic LOW) applied to the second inputs of delay circuits 122, 132, and 142 does not immediately change the logic level at the outputs of delay circuits 122, 132, and 142. At the instant the control signal SD changes to a VDDAI rising signal, the bit cells in the memory bank (e.g., 110, 120, 130, and 140) remain in the VDDAI falling state.

[0033] After the VDDAI rising signal is applied to the first input of the delay circuit 112, a switch-on signal is applied to the control line 113 and transmitted to the gate terminal of the wake-up switch (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1], and the wake-up switch (e.g., T11, T12, ..., and T19) changes to the closed state. Therefore, the virtual power line VDDAI[1] is conductively connected to the power node of the power supply voltage VDD through the wake-up switch (e.g., T11, T12, ..., and T19), and the bit cells in the memory bank 110 gain power connection.

[0034] After a delay from when the turn-on signal is applied to control line 113, the turn-on signal is transmitted to the first input of delay circuit 122 via delay circuit 114. After a further delay caused by delay circuit 122, the turn-on signal is applied to control line 123 and transmitted to the gate terminal of the wake-up switch (e.g., T21, T22, ..., and T29) of the virtual power line VDDAI[2]. The turn-on signal at the gate terminal causes the wake-up switch (e.g., T21, T22, ..., and T29) of the virtual power line VDDAI[2] to become closed, so the virtual power line VDDAI[2] is conductively connected to the power node of the power supply voltage VDD via the wake-up switch (e.g., T21, T22, ..., and T29), and the bit cells in memory bank 120 are powered.

[0035] The delay time Δt

[12] between the time the turn-on signal is applied to control line 113 and the time the turn-on signal is applied to control line 123 is selected to reduce the total peak current. When the delay time Δt

[12] is less than a certain critical value, the peak value of the sum of currents I-AI[1] and I-AI[2] can be greater than the peak value of current I-AI[1] or the peak value of current I-AI[2]. Generally, when the peak value of the sum of currents I-AI[1] and I-AI[2] is greater than the peak value of each of currents I-AI[1] and I-AI[2], increasing the delay time Δt

[12] reduces the peak value of the sum of currents I-AI[1] and I-AI[2]. However, increasing the delay time Δt

[12] will increase the time required for the memory device to wake up from sleep mode. The delay time Δt

[12] has an optimal value. In some embodiments, the delay time Δt

[12] is selected as the smallest possible delay time that satisfies the following criterion: the peak value caused by the sum of currents I-AI[1] and I-AI[2] is less than a predetermined current value. In some embodiments, the predetermined current value is less than or equal to the peak read or write current, which is designed based on considerations regarding the power management capacity of the system-on-chip (SOC). In some embodiments, the predetermined current value is 120% of the peak value of current I-AI[1] or 120% of the peak value of current I-AI[2].

[0036] Similarly, after a delay from the time the turn-on signal is applied to control line 123, the turn-on signal is transmitted to the first input of delay circuit 132 via delay circuit 124. After a further delay caused by delay circuit 132, the turn-on signal is applied to control line 133 and transmitted to the gate terminal of the wake-up switch (e.g., T31, T32, ..., and T39) of the virtual power line VDDAI[3]. The turn-on signal at the gate terminal causes the wake-up switch (e.g., T31, T32, ..., and T39) of the virtual power line VDDAI[3] to become closed, so the virtual power line VDDAI[3] is conductively connected to the power node of the power supply voltage VDD via the wake-up switch (e.g., T31, T32, ..., and T39), and the bit cells in memory bank 130 are powered. The delay time Δt

[23] between the time the turn-on signal is applied to control line 123 and the time the turn-on signal is applied to control line 133 is selected to reduce the total peak current. The selected delay time Δt

[23] depends on both the current I-AI[2] flowing into the virtual power line VDDAI[2] and the current I-AI[3] flowing into the virtual power line VDDAI[3]. In some embodiments, the delay time Δt

[23] is selected as the minimum possible delay time that satisfies the following criterion: the peak value caused by the sum of currents I-AI[2] and I-AI[3] is less than a predetermined current value. In some embodiments, the predetermined current value is less than or equal to the peak current for reading or writing, which is designed based on considerations regarding the power management capacity of the system-on-chip (SOC). In some embodiments, the predetermined current value is 120% of the peak value of current I-AI[2] or 120% of the peak value of current I-AI[3].

[0037] After a delay from the time the turn-on signal is applied to control line 133, the turn-on signal is transmitted to the first input of delay circuit 142 via delay circuit 134. After a further delay caused by delay circuit 142, the turn-on signal is applied to control line 143 and transmitted to the gate terminal of the wake-up switch (e.g., T41, T42, ..., and T49) of the virtual power line VDDAI[4]. The turn-on signal at the gate terminal causes the wake-up switch (e.g., T41, T42, ..., and T49) of the virtual power line VDDAI[4] to become closed, so the virtual power line VDDAI[4] is conductively connected to the power node of the power supply voltage VDD via the wake-up switch (e.g., T41, T42, ..., and T49), and the bit cells in memory bank 140 are powered. The delay time Δt

[34] between the time the turn-on signal is applied to control line 133 and the time the turn-on signal is applied to control line 143 is selected to reduce the total peak current.

[0038] After a delay from when the enable signal is applied to control line 143, the enable signal is transmitted to the input of wake-up detector 150 via delay circuit 144. Wake-up detector 150 is designed to generate a trigger signal SLPWK when the voltage level on the virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]) reaches a designed level. Figure 1 In this circuit, the wake-up detector 150 detects the voltage level on the virtual power line VDDAI[4]. After the wake-up detector 150 receives an on signal from the output of the delay circuit 144, if the voltage level on the virtual power line VDDAI[4] is higher than a predetermined level, a trigger signal SLPWK is generated at the output and transmitted to the control output 109. Figure 1 Because the start time for connecting the power node to the virtual power line VDDAI[4] is after the start time for connecting the power node to other virtual power lines (e.g., VDDAI[1], VDDAI[2], and VDDAI[3]), when the voltage level on the virtual power line VDDAI[4] is above a predetermined threshold level, the voltage levels on the other virtual power lines (e.g., VDDAI[1], VDDAI[2], and VDDAI[3]) are also expected to be above a predetermined threshold level. That is, when the trigger signal SLPWK is generated at the output and transmitted to the control output 109, the voltage levels on all virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]) are expected to be above a predetermined threshold level.

[0039] exist Figure 1In the wake-up detector 150, there are inverters 152, half-Schmitt triggers 155, inverters 156 and 158. Half-Schmitt trigger 155 includes a PMOS transistor T1 and three NMOS transistors T2, T3 and T4. The trigger threshold of half-Schmitt trigger 155 is adjusted by changing the size of the feedback NMOS T4. Inverter 152 has an input that receives a signal from delay circuit 144 and an output that generates a trigger signal SLPWK based on the signal received at the input of inverter 156. Inverter 152 is powered by a voltage on the virtual power line VDDAI[4]. When the voltage on the virtual power line VDDAI[4] is lower than a predetermined threshold level, inverter 152 is not in operating mode and the logic level at the input of inverter 152 is not inverted at the output of inverter 152. In operation, once the voltage on the virtual power line VDDAI[4] exceeds a predetermined threshold level, the logic level at the input of inverter 152 is inverted at the output of inverter 152. The change in the logic level at the output of inverter 152 triggers half-Schmitt trigger 155, which generates a signal change at the output of half-Schmitt trigger 155. The signal change at the output of half-Schmitt trigger 155, after passing through inverters 156 and 158, generates a trigger signal SLPWK at the output of wake-up detector 150. The trigger signal SLPWK transmitted to control output 109 indicates that the voltage level on the virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]) exceeds a predetermined threshold level. The trigger signal SLPWK on control output 109 is coupled to a power management circuit (e.g., a virtual power line that powers various control circuits in the memory device) that supplies power to the virtual power lines. Figure 2 (Circuit in the middle).

[0040] exist Figure 1In this embodiment, a VDD voltage is applied to each of the virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], or VDDAI[4]) when each of them is sequentially turned on after a corresponding delay time (e.g., Δt

[12] , Δt

[23] , or Δt

[34] ). In some embodiments, the VDD voltage is applied sequentially to each virtual power line after a corresponding delay time. However, in some alternative embodiments, the VDD voltage is applied together as a group of two or more virtual power lines, even if each virtual power line is sequentially turned on after a corresponding delay time. For example, the VDD voltage is applied together as a group of all virtual power lines when all virtual power lines VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4] are conductively connected. As another example, when virtual power lines VDDAI[1] and VDDAI[2] are connected together as a first group of conductors and virtual power lines VDDAI[3] and VDDAI[4] are connected together as a second group of conductors, the VDD voltage is applied to all virtual power lines in the first group before the VDD voltage is applied to all virtual power lines in the second group. In some embodiments, all or some of the virtual power lines are conductively connected together to reduce IR drop caused by read and / or write operations to the memory bank.

[0041] Figure 2 This is a schematic diagram of a portion of a power management circuit having virtual power lines supplying power to various control circuits in a memory device, according to some embodiments. In some embodiments, the control circuitry includes a Local Input / Output circuit (LIO), a Master Input / Output circuit (MIO), a Word Line Driver (WLDRV), a Local Control Circuit (LCTRL), and a Master Control Circuit (MCTRL). Figure 2 In this configuration, MIO 207 and the corresponding MCTRL 205 are powered by the virtual power line VDDHD[0]. LIO 217, WLDRV 118 and the corresponding LCTRL 215 are powered by the virtual power line VDDHD[1]. Some WLDRVs associated with LCTRL 215 are also powered by the virtual power line VDDHD[1]. LIO 227, WLDRV 128 and the corresponding LCTRL 225 are powered by the virtual power line VDDHD[2]. Some WLDRVs associated with LCTRL 225 are also powered by the virtual power line VDDHD[2].

[0042] exist Figure 2In this configuration, the virtual power line is coupled to the power supply voltage VDD via wake-up switches. The virtual power line VDDHD[0] is coupled to the power supply voltage VDD via a wake-up switch array (e.g., W00, W01, W02, ..., and W09) and a functional switch array (e.g., T00, F00, F01, F02, ..., and F09). The virtual power line VDDHD[1] is coupled to the power supply voltage VDD via a wake-up switch array (e.g., W10, W11, W12, ..., and W19) and a functional switch array (e.g., T10, F10, F11, F12, ..., and F19). The virtual power line VDDHD[2] is coupled to the power supply voltage VDD via a wake-up switch array (e.g., W20, W21, W22, ..., and W29) and a functional switch array (e.g., T20, F20, F21, F22, ..., and F29). Figure 2 In this system, the wake-up switch and function switch are implemented as transistor switches, such as FET switches.

[0043] exist Figure 2 In this circuit, the power management circuit 200 includes a wake-up detector 250 and a plurality of delay circuits (e.g., 202, 204, 208, 212, 214, 218, 222, 224, and 228). Each of the delay circuits (e.g., 202, 204, 208, 212, 214, 218, 222, 224, and 228) has a first input and an output. The first input of the delay circuit 202 is coupled to a first control input 261 of the power management circuit 200. Each of the delay circuits 202, 208, 212, 218, 222, and 228 has a second input coupled to a control line connected to a second control input 201 of the power management circuit 200.

[0044] The gate terminals of the wake-up switches (e.g., W00, W01, W02, ..., and W09) of the virtual power line VDDHD[0] are connected to control line 203 and coupled to both the output of delay circuit 202 and the first input of delay circuit 204. The gate terminals of the function switches (e.g., T00, F00, F01, F02, ..., and F09) of the virtual power line VDDHD[0] are connected to control line 209 and coupled to the output of delay circuit 208. The wake-up switches (e.g., W00, W01, W02, ..., and W09) of the virtual power line VDDHD[0] control the power connection between the virtual power line VDDHD[0] and the power node of the power supply voltage VDD. The function switches (e.g., T00, F00, F01, F02, ..., and F09) of the virtual power line VDDHD[0] control the additional power connection between the virtual power line VDDHD[0] and the power node of the power supply voltage VDD.

[0045] The gate terminals of the wake-up switches (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1] are connected to control line 213 and coupled to both the output of delay circuit 212 and the first input of delay circuit 214. The gate terminals of the function switches (e.g., T10, F10, F11, F12, ..., and F19) of the virtual power line VDDHD[1] are connected to control line 219 and coupled to the output of delay circuit 218. The wake-up switches (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1] control the power connection between the virtual power line VDDHD[1] and the power node of the power supply voltage VDD. The function switches (e.g., T10, F10, F11, F12, ..., and F19) of the virtual power line VDDHD[1] control the additional power connection between the virtual power line VDDHD[1] and the power node of the power supply voltage VDD.

[0046] The gate terminals of the wake-up switches (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2] are connected to control line 223 and coupled to both the output of delay circuit 222 and the first input of delay circuit 224. The gate terminals of the function switches (e.g., T20, F20, F21, F22, ..., and F29) of the virtual power line VDDHD[2] are connected to control line 229 and coupled to the output of delay circuit 228. The wake-up switches (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2] control the power connection between the virtual power line VDDHD[2] and the power node of the power supply voltage VDD. The function switches (e.g., T20, F20, F21, F22, ..., and F29) of the virtual power line VDDHD[2] control the additional power connection between the virtual power line VDDHD[2] and the power node of the power supply voltage VDD.

[0047] The output of delay circuit 224 is coupled to the input of wake-up detector 250. The output of wake-up detector 250 is coupled to the first input of delay circuits 208, 218, and 228. Wake-up detector 250 includes inverter 252, half-Schmitt trigger 255, inverter 256, and inverter 258. Half-Schmitt trigger 255 includes PMOS transistor T1 and three NMOS transistors T2, T3, and T4. The trigger threshold of half-Schmitt trigger 255 is adjusted by changing the size of feedback NMOS T4. Inverter 252 has an input that receives a signal from delay circuit 244 and an output coupled to the input of half-Schmitt trigger 255. Inverter 252 is powered by a voltage on virtual power line VDDHD[2]. When the voltage on virtual power line VDDHD[2] is below a predetermined threshold level, inverter 252 is not in operating mode, and the inverted logic level at the output of inverter 252 is not the inversion of the logic level at the input of inverter 252. When the voltage on the virtual power line VDDHD[2] is higher than the predetermined threshold level, if the input of the wake-up detector 250 receives the SLPWK_D signal from the delay circuit 224, a trigger signal SLPWK_TRK will be generated at the output of the wake-up detector 250.

[0048] In some embodiments, such as Figure 3 As shown, Figure 2 The power management circuit 200 in the middle and Figure 1 The power management circuit 100 works together. Figure 3 In this circuit, the first control input 261 of the power management circuit 200 is connected to the control output 109 of the power management circuit 100. The second control input 201 of the power management circuit 200 is connected to the output of the OR gate 320. The control input 101 of the power management circuit 100 and / or the first input 321 of the OR gate 320 are configured to receive a control signal SD. The second input 322 of the OR gate 320 is configured to receive a control signal SLP. In some embodiments, the control signal SD uses logic HIGH to indicate a power-down signal and logic LOW to indicate a power-on signal. In some embodiments, the control signal SLP uses logic HIGH to indicate a sleep signal and logic LOW to indicate a sleep-wake signal. The output of the OR gate 320 generates a control signal SLPD based on the control signal SD received at the first input 321 and the control signal SLP received at the second input 322. The control signal SLPD is at logic LOW whenever the control signal SD is at logic LOW or the control signal SLP is at logic LOW.

[0049] In some embodiments, by Figure 3The power management circuit in the power management circuit 100 controls the memory bank to be in one of three modes: operating mode, shutdown mode, or sleep mode. When the memory bank is in operating mode, the virtual power line VDDAI in power management circuit 100 is turned on, and the virtual power line VDDHD in power management circuit 200 is also turned on. When the memory bank is in shutdown mode, the virtual power line VDDAI in power management circuit 100 is turned off, and the virtual power line VDDHD in power management circuit 200 is also turned off. When the memory bank is in sleep mode, the virtual power line VDDAI in power management circuit 100 is turned on, and the virtual power line VDDHD in power management circuit 200 is turned off. In some embodiments, when the virtual power line VDDAI in power management circuit 100 is turned on, the SLPWK signal from the control output 109 of power management circuit 100 is set to logic LOW.

[0050] During operation, when the control signal SD is set to logic HIGH, the memory bank enters the off mode. When the control signal SD changes from logic HIGH to logic LOW, the memory bank changes from the off mode to the operating mode. When the control signal SLP is set to logic HIGH, the memory bank enters the sleep mode. When the control signal SLP changes from logic HIGH to logic LOW, the memory bank wakes up from the sleep mode and enters the operating mode.

[0051] During operation, when the control signal SD is set to logic HIGH to put the memory bank into a shutdown mode, or when the control signal SLP is set to logic HIGH to put the memory bank into a sleep mode, Figure 3 The control signal SLPD at the output of OR gate 320 is changed to logic HIGH in response and coupled to the second control input 201 of power management circuit 200.

[0052] exist Figure 2In the second control input 201, when the control signal SLPD received is at logic HIGH to indicate the VDDHD falling state, the VDDHD falling signal is applied to control lines 203, 213, and 223 respectively through delay circuits 202, 212, and 222, and the wake-up switches of virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are all set to the off state. In addition, the VDDHD falling signal is applied to control lines 209, 219, and 229 respectively through delay circuits 208, 218, and 228, and the function switches of virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are all set to the off state. Since the power connection between virtual power line VDDHD[0] and power supply voltage VDD is disconnected by the corresponding wake-up switch and the corresponding function switch, MIO 207 and MCTRL 205 lose their power connection. Because the power connection between the virtual power line VDDHD[1] and the power supply voltage VDD is disconnected by the corresponding wake-up switch and the corresponding function switch, LIO 217, WLDRV 118 and the corresponding LCTRL 215 are not connected to power. Because the power connection between the virtual power line VDDHD[2] and the power supply voltage VDD is disconnected by the corresponding wake-up switch and the corresponding function switch, LIO 227, WLDRV 128 and the corresponding LCTRL 225 are not connected to power. In addition, WLDRVs that receive power from the virtual power lines VDDHD[0], VDDHD[1] and VDDHD[2] are not connected to power.

[0053] During operation, when the control signal SD changes from logic HIGH to logic LOW to switch the memory bank from shutdown mode to operating mode, Figure 3 The power management circuit 100 receives the control signal SD at its control input 101. Figure 3 The first input 321 of the OR gate 320 also receives the control signal SD. If the control signal SLP at the second input 322 of the OR gate 320 remains at logic LOW to indicate that the memory bank is not in sleep mode, then when the control signal SD changes from logic HIGH to logic LOW, the control signal SLPD at the output of the OR gate 320 changes from logic HIGH to logic HIGH accordingly and is coupled to the second control input 201 of the power management circuit 200.

[0054] The control signal SD (with logic LOW) received at control input 101 will turn on the virtual power line VDDAI in the power management circuit 100. The control signal SLPD (with logic LOW) received at the second control input 201 will not immediately turn on the virtual power line VDDHD in the power management circuit 200. Instead, the control signal SLPD (with logic LOW) received at the second control input 201 will turn on the virtual power line VDDHD in the power management circuit 200 after a certain delay time, during which the virtual power line VDDAI in the power management circuit 100 has been turned on by the control signal SD (with logic LOW) received at control input 101. Figure 3 In the power management circuit 100, when the virtual power line VDDAI in the power management circuit 100 is turned on, an SLPWK signal is generated at the control output 109 of the power management circuit 100. The SLPWK signal from the power management circuit 100 is coupled to the first control input 261 of the power management circuit 200. When the control signal SLPD received at the second control input 201 is logic LOW, the SLPWK signal received by the power management circuit will turn on the virtual power line VDDHD in the power management circuit 200.

[0055] exist Figure 2 In this circuit, when the control signal SLPD received at the second control input 201 changes from logic HIGH to logic LOW to indicate a change from a VDDHD falling state to a VDDHD rising state, a VDDHD rising signal (with logic LOW) is applied to the second inputs of delay circuits 202, 212, 222, 208, 218, and 228. When the first inputs of delay circuits 202, 212, and 222 remain at logic HIGH, the VDDHD rising signal (with logic LOW) applied to the second inputs of delay circuits 202, 212, and 222 does not immediately change the logic level of the outputs of delay circuits 202, 212, and 222. Similarly, when the first inputs of delay circuits 208, 218, and 228 remain at logic HIGH, the VDDHD rising signal (with logic LOW) applied to the second inputs of delay circuits 208, 218, and 228 does not immediately change the logic level of the outputs of delay circuits 208, 218, and 228. When the control signal SLPD changes to the rising signal VDDHD, the power connection between the power supply voltage VDD and the virtual power lines VDDHD[0], VDDHD[1] and VDDHD[2] remains disconnected.

[0056] After a certain delay after the virtual power line VDDAI in the power management circuit 100 is turned on, the SLPWK signal (with logic LOW) generated by the power management circuit 100 is transmitted to the first control input 261 of the power management circuit 200. When the SLPWK signal is received by the first input of the delay circuit 202, an on signal is applied to the control line 203 through the delay circuit 202 and transmitted to the gate terminal of the wake-up switch (e.g., W00, W01, W02, ..., and W09) of the virtual power line VDDHD[0]. When the on signal is applied to the control line 203 through the delay circuit 202, after the SLPWK signal is received by the first input of the delay circuit 202, the wake-up switch (e.g., W00, W01, W02, ..., and W09) of the virtual power line VDDHD[0] becomes closed. Therefore, the virtual power line VDDHD[0] is conductively connected to the power node of the power supply voltage VDD via wake-up switches (e.g., W00, W01, W02, ..., and W09), enabling MIO 207 and MCTRL 205 to acquire a power connection.

[0057] After a delay from the time the turn-on signal is applied to control line 203, the turn-on signal is transmitted to the first input of delay circuit 212 via delay circuit 204. After a further delay caused by delay circuit 212, the turn-on signal is applied to control line 213 and transmitted to the gate terminal of the wake-up switch (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1]. The turn-on signal at the gate terminal causes the wake-up switch (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1] to become closed, so that the virtual power line VDDHD[1] is conductively connected to the power node of the power supply voltage VDD via the wake-up switch (e.g., W10, W11, W12, ..., and W19), enabling LIO 217, WLDRV 118 and the corresponding LCTRL 215 to obtain power connection.

[0058] The delay time between the time the turn-on signal is applied to control line 203 and the time the turn-on signal is applied to control line 213 is selected to reduce the total peak current. The selected delay time depends on both the current I-HD[0] flowing into the virtual power line VDDHD[0] and the current I-HD[1] flowing into the virtual power line VDDHD[1]. In some embodiments, the delay time is selected as the minimum possible delay time that satisfies the following criterion: the peak value caused by the sum of currents I-HD[0] and I-HD[1] is less than a predetermined current value. In some embodiments, the predetermined current value is less than or equal to the peak read or write current, which is designed based on considerations regarding the power management capacity of the system-on-chip (SOC). In some embodiments, the predetermined current value is 120% of the peak value of current I-HD[0] or 120% of the peak value of current I-HD[1].

[0059] Similarly, after a delay from when the turn-on signal is applied to control line 213, the turn-on signal is transmitted to the first input of delay circuit 222 via delay circuit 214. After a further delay caused by delay circuit 222, the turn-on signal is applied to control line 223 and transmitted to the gate terminal of the wake-up switch (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2]. The turn-on signal at the gate terminal causes the wake-up switch (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2] to become closed, so that the virtual power line VDDHD[2] is conductively connected to the power node of the power supply voltage VDD via the wake-up switch (e.g., W20, W21, W22, ..., and W29), enabling LIO 227, WLDRV 128 and the corresponding LCTRL 225 to obtain power connection. The delay between the time when the turn-on signal is applied to control line 213 and the time when the turn-on signal is applied to control line 223 is selected to reduce the total peak current.

[0060] After a delay from when the enable signal is applied to control line 223, the enable signal is transmitted to the input of wake-up detector 250 via delay circuit 224. Wake-up detector 250 is designed to generate a trigger signal SLPWK_TRK when the voltage levels on virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are higher than a predetermined voltage level. Figure 2In this circuit, the wake-up detector 250 detects the voltage level on the virtual power line VDDHD[2]. After the wake-up detector 250 receives the SLPWK_D signal from the output of the delay circuit 244, if the voltage level on the virtual power line VDDHD[2] is higher than a predetermined voltage level, a trigger signal SLPWK_TRK is generated at the output and sent to the first input of the delay circuits 208, 218 and 228.

[0061] After the first input of the delay circuits 208, 218, and 228 receives the trigger signal SLPWK_TRK, the turn-on signal is applied to the control lines 209, 219, and 229 by the corresponding delay circuits 208, 218, and 228. The turn-on signal applied to the control lines 209, 219, and 229 drives all function switches into the closed state. The function switches that become closed include the function switches of the virtual power line VDDHD[0] (e.g., T00, F00, F01, F02, ..., and F09), the function switches of the virtual power line VDDHD[1] (e.g., T10, F10, F11, F12, ..., and F19), and the function switches of the virtual power line VDDHD[2] (e.g., T20, F20, F21, F22, ..., and F29). When the turn-on signal is applied to the gate terminal of the function switch, the voltage levels on the virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are all higher than predetermined voltage levels based on the trigger signal SLPWK_TRK from the wake-up detector 250. After the function switch is driven into the closed state, the IR drop between the pull-up power supply VDD and the virtual power lines (e.g., VDDHD[0], VDDHD[1], or VDDHD[2]) decreases because the closed function switch reduces the resistivity of the current path from the pull-up power supply VDD to the virtual power lines.

[0062] From the moment the enable signal is applied to the gate terminal of the function switch, the voltage levels on the virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] further tend towards the final voltage levels designed for the virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2]. The total current flowing from the pull-up power supply VDD to the virtual power lines depends on the difference between the final voltage level and the voltage level on the virtual power lines when the enable signal is applied. The smaller the difference between the final voltage level and the voltage level on the virtual power lines, the smaller the total current. On the other hand, reducing the difference between the final voltage level and the voltage level on the virtual power lines by relying on the current path established by the wake-up switches (e.g., W00-W09, W10-W19, and W20-W29) increases the time required for the memory device to wake up from sleep mode. The wake-up detector 250 is implemented to set the optimal voltage level on the virtual power lines when the enable signal is applied. The optimal voltage level on the virtual power line when the enable signal is applied is designed to be close to the final voltage level in order to limit the total current flowing from the pull-up power supply VDD to the virtual power line, thus balancing the need to reduce the wake-up time of the memory device.

[0063] exist Figure 2 In this embodiment, a VDD voltage is applied to each of the virtual power lines (e.g., VDDHD[0], VDDHD[1], or VDDHD[2]) when each of them is sequentially turned on after a corresponding delay time. In some embodiments, the VDD voltage is applied sequentially to each virtual power line after a corresponding delay time. However, in some alternative embodiments, the VDD voltage is applied to two or more virtual power lines together as a group, even if each virtual power line is sequentially turned on after a corresponding delay time. For example, when all virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are conductively connected, the VDD voltage is applied to all virtual power lines together as a group. As another example, when virtual power lines VDDHD[1] and VDDHD[2] are conductively connected together as a group, the VDD voltage is applied to virtual power line VDDHD[0] before the VDD voltage is applied to both virtual power lines VDDHD[1] and VDDHD[2]. In some embodiments, all or some of the virtual power lines are conductively connected together to reduce IR drop caused by read and / or write operations to the memory bank.

[0064] exist Figure 3 In the process, the control signal SLP controls whether the memory bank is set to sleep mode or operating mode. During operation, when the control signal SLP changes from logic HIGH to logic LOW to switch the memory bank from sleep mode to operating mode, Figure 3The control signal SLPD at the output of OR gate 320 changes from logic HIGH to logic LOW accordingly and is coupled to the second control input 201 of power management circuit 200. When the memory bank is in sleep mode, the virtual power line VDDAI in power management circuit 100 remains on, while the virtual power line VDDHD in power management circuit 200 is off. In some embodiments, when the memory bank is in sleep mode, the control signal SD remains at logic LOW and comes from... Figure 3 The SLPWK signal of the control output 109 of the power management circuit 100 is set to logic LOW and coupled to the first control input 261 of the power management circuit 200.

[0065] exist Figure 2 When the memory bank wakes up from sleep mode, the first inputs of delay circuits 202, 212, and 222 are maintained at logic LOW because the first control input 261 of power management circuit 200 is maintained at logic LOW by the SLPWK signal from control output 109 of power management circuit 100. When the memory bank wakes up from sleep mode, the control signal SLPD received at the second control input 201 of power management circuit 200 changes from logic HIGH to logic LOW to indicate the change from VDDHD falling state to VDDHD rising state. Because the control signal SLPD (with logic LOW) is received at the second control input 201, the VDDHD rising signal (with logic LOW) is applied to the second inputs of delay circuits 202, 212, 222, 208, 218, and 228. Since the first inputs of delay circuits 202, 212, and 222 are maintained at logic LOW by the SLPWK signal, and since the rising VDDHD signal (with logic LOW) is applied to the second inputs of delay circuits 202, 212, and 222, turn-on signals from the outputs of delay circuits 202, 212, and 222 are correspondingly applied to control lines 203, 213, and 223. The turn-on signals on control lines 203, 213, and 223 are correspondingly transmitted to the gate terminals of wake-up switches (e.g., W00-W09), wake-up switches (e.g., W10-W19), and wake-up switches (e.g., W20-W29). Then, the virtual power lines (VDDHD[0], VDDHD[1], and VDDHD[2]) are turned on by the wake-up switches (e.g., W00-W09, W10-W19, and W20-W29).

[0066] When the voltage levels on the virtual power lines VDDHD[0], VDDHD[1], and VDDHD[2] are higher than a predetermined voltage level, the wake-up detector 250 generates a trigger signal SLPWK_TRK. After the trigger signal SLPWK_TRK is received at the first input of the delay circuits 208, 218, and 228, an on signal is applied to the control lines 209, 219, and 229 by the corresponding delay circuits 208, 218, and 228. The on signals on the control lines 209, 219, and 229 drive all function switches into a closed state. The function switches that become closed include the function switches of the virtual power line VDDHD[0] (e.g., T00 and F00-F09), the function switches of the virtual power line VDDHD[1] (e.g., T10 and F10-F19), and the function switches of the virtual power line VDDHD[2] (e.g., T20 and F20-F29).

[0067] Figure 4A This is a plan view illustration of a portion of a functional block in an SRAM according to some embodiments. Figure 4A The SRAM functional blocks include: memory banks (e.g., 110, 120, 130, and 140), LIO 217 and its associated LCTRL 215, LIO 227 and its associated LCTRL 225, MIO 207 and MCTRL 205, and WLDRV (e.g., 118, 128, 138, and 148). LIO 217 is coupled to both memory banks 110 and 120. LIO 227 is coupled to both memory banks 130 and 140. Figure 4A As shown, memory banks 110, 120, 130, and 140 are respectively powered by virtual power lines VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]. According to some embodiments, power management circuitry for supplying power to the memory banks (e.g., 110, 120, 130, and 140) is... Figure 1 As shown in the image.

[0068] exist Figure 4A In this configuration, MIO 207 and MCTRL 205 are powered by a virtual power line VDDHD[0]. LIO 217, LCTRL 215, and WLDRV 118 and 128 are powered by a virtual power line VDDHD[1]. LIO 227, LCTRL 225, and WLDRV 138 and 148 are powered by a virtual power line VDDHD[2]. According to some embodiments, the power management circuitry used to power various control circuits (e.g., LIO 217-227, LCTRL 215-225, MIO 207, and MCTRL 205) and WLDRVs (e.g., 118 and 128) is... Figure 2 As shown in the image.

[0069] Figure 4B This is a high-level illustration of a plan view of a portion of a functional block in another SRAM according to some embodiments. Figure 4B The SRAM functional blocks in the memory include: memory banks (e.g., 110 and 120), LIO 217 and its associated LCTRL 215, LIO 227 and its associated LCTRL 225, MIO 207 and MCTRL 205, and WLDRV 118 and 128. LIO 217 is coupled to memory bank 110, and LIO 227 is coupled to memory bank 120. Figure 4A In this configuration, MIO 207 and MCTRL 205 are powered by the virtual power line VDDHD[0]. LIO 217, LCTRL 215 and WLDRV 118 are powered by the virtual power line VDDHD[1]. LIO 227, LCTRL 225 and WLDRV 128 are powered by the virtual power line VDDHD[2].

[0070] Figure 5 According to some embodiments, from Figure 1 A schematic diagram of a portion of the modified power management circuit 500 is shown below. The modification includes adding a function switch between the dummy power line and the power supply voltage VDD, and adding delay circuitry (e.g., 518-548) between the wake-up detector 150 and the gate of the function switch. The output of the wake-up detector 150 is coupled to a first input of the delay circuitry 518-548. A second input of the delay circuitry 518-548 is coupled to a control input 101 of the power management circuit 100.

[0071] exist Figure 5 In this configuration, a first functional switch array (e.g., FT11, FT12, ..., and FT19) is placed between the virtual power line VDDAI[1] and the power supply voltage VDD. A second functional switch array (e.g., FT21, FT22, ..., and FT29) is placed between the virtual power line VDDAI[2] and the power supply voltage VDD. A third functional switch array (e.g., FT31, FT32, ..., and FT39) is placed between the virtual power line VDDAI[3] and the power supply voltage VDD. A fourth functional switch array (e.g., FT41, FT42, ..., and FT49) is placed between the virtual power line VDDAI[4] and the power supply voltage VDD. Figure 5 In this context, the functional switch is implemented as a transistor switch, such as a FET switch.

[0072] The gate terminals of the function switches (e.g., FT11-FT19) of the virtual power line VDDAI[1] are connected to control line 119 and coupled to the output of delay circuit 518. The gate terminals of the function switches (e.g., FT21-FT29) of the virtual power line VDDAI[2] are connected to control line 129 and coupled to the output of delay circuit 528. The gate terminals of the function switches (e.g., FT31-FT39) of the virtual power line VDDAI[3] are connected to control line 139 and coupled to the output of delay circuit 538. The gate terminals of the function switches (e.g., FT41-FT49) of the virtual power line VDDAI[4] are connected to control line 149 and coupled to the output of delay circuit 548.

[0073] In operation, when the control signal SD (with logic LOW) on control input 101 indicates a change from the VDDAI falling state to the VDDAI rising state, each of the virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], or VDDAI[4]) is sequentially connected to the power supply voltage VDD via wake-up switches (e.g., T11-T19, T21-T29, T31-T39, and T41-T49) after a corresponding delay time (e.g., Δt

[12] , Δt

[23] , or Δt

[34] ). When the voltage level on the virtual power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]) reaches the designed level, a trigger signal SLPWK (with logic LOW) is generated at the output of wake-up detector 150 and coupled to the first input of delay circuits 518-548. In response to the trigger signal SLPWK, an on signal (with logic LOW) is generated at the output of delay circuits 518-548. The on signal is applied to control lines 119, 129, 139, and 149 to drive all function switches (e.g., FT11-T19, FT21-T29, FT31-FT39, and FT41-FT49) into a closed state. When the function switches are driven into a closed state, the IR drop between the pull-up power supply VDD and the dummy power lines (e.g., VDDAI[1], VDDAI[2], VDDAI[3], and VDDAI[4]) is reduced.

[0074] Figure 2 The arrangement and connection of the wake-up switch and function switch in the power management circuit 200 can have different variations. Figure 6 and Figures 7A-7B Some variations are shown in the figure.

[0075] Figure 6This is a schematic diagram of an implementation of wake-up switches and function switches for managing power connections to a virtual power line according to some embodiments. The wake-up switches of the virtual power line VDDHD[1] are divided into two groups. Each group of wake-up switches is controlled by one of control lines 213A and 213B. The gate terminals of the wake-up switches in the first group (e.g., W10A, W11A, W12A, ..., and W19A) are connected to control line 213A and coupled to the output of delay circuit 212 and the input of delay circuit 212B. The gate terminals of the wake-up switches in the second group (e.g., W10B, W11B, W12B, ..., and W19B) are connected to control line 213B and coupled to the output of delay circuit 212B and the input of delay circuit 214. The gate terminals of the function switches of the virtual power line VDDHD[1] (e.g., T10, F10, F11, F12, ..., and F19) are connected to control line 219 and coupled to the output of delay circuit 218.

[0076] In operation, when the input of delay circuit 212 receives an enable signal, the enable signal is applied to control line 213A, causing the wake-up switches in the first group (e.g., W10A, W11A, W12A, ..., and W19A) to turn off. After a delay from when the enable signal is applied to control line 213A, the enable signal is transmitted to control line 213B via delay circuit 212B. The enable signal causes the wake-up switches in the second group (e.g., W10B, W11B, W12B, ..., and W19B) to turn closed. The enable signal on control line 213B is received by the input of delay circuit 214 and transmitted to the control line of the next-stage wake-up switch for controlling the power connection of the virtual power line in the next stage.

[0077] Figures 7A-7C These are schematic diagrams illustrating various implementations of wake-up switches and function switches for managing power connections to virtual power lines, according to some embodiments. Figures 7A-7C In this circuit, the gate terminal of the wake-up switch of the virtual power line VDDHD[1] is connected to the control line 213 and coupled to both the output of the delay circuit 212 and the first input of the delay circuit 214. The terminals of the function switches (e.g., T10, F10, F11, F12, ..., and F19) of the virtual power line VDDHD[1] are connected to the control line 219 and coupled to the output of the delay circuit 218.

[0078] exist Figure 7AIn this configuration, each LIO is associated with a wake-up switch and a function switch. For example, the LIOs for bits [0], [1], [2], [3], [4], and [5] are associated with wake-up switches W11, W12, W13, W14, W15, and W16, respectively. The LIOs for bits [0], [1], [2], [3], [4], and [5] are also associated with function switches F11, F12, F13, F14, F15, and F16, respectively.

[0079] exist Figure 7B In this configuration, each of the two LIOs is associated with a wake-up switch and a function switch. Each of the remaining LIOs is associated with two function switches. For example, the LIOs for bits [0], [2], and [4] are associated with wake-up switches W11, W13, and W15, respectively. The LIOs for bits [0], [2], and [4] are also associated with function switches F11, F13, and F15, respectively. The LIO for bit [1] is associated with function switches F12A and F12B. The LIO for bit [3] is associated with function switches F14A and F14B. The LIO for bit [5] is associated with function switches F16A and F16B.

[0080] exist Figure 7C In this configuration, each of the three LIOs is associated with a wake-up switch and a function switch. Each of the remaining LIOs is associated with two function switches. For example, the LIOs for bits [0] and [3] are associated with wake-up switches W11 and W14 respectively. The LIOs for bits [0] and [3] are also associated with function switches F11 and F14 respectively. The LIO for bit [1] is associated with function switches F12A and F12B. The LIO for bit [2] is associated with function switches F13A and F13B. The LIO for bit [4] is associated with function switches F15A and F15B. The LIO for bit [5] is associated with function switches F16A and F16B.

[0081] Figure 1 and Figure 2 The wake-up detector in the power management circuit has different variations. Figure 8A This is a schematic diagram of another embodiment of a wake-up detector 150 in a power management circuit for managing power connections to memory cells in a memory device, according to some embodiments. Figure 8A The wake-up detector 150 is implemented as an inverter daisy chain with a predetermined delay time based on design requirements. Figure 8AIn this process, when the wake-up detector 150 receives an enable signal from the delay circuit 144, an SLPWK signal is generated at the output of the wake-up detector 150 after a predetermined delay period. In some embodiments, the SLPWK signal is generated by... Figure 2 The first input of the delay circuit 202 in the power management circuit is received, which initiates the power connection process of various control circuits in the memory device.

[0082] Figure 8B This is a schematic diagram of another embodiment of a wake-up detector in a power management circuit for managing power connections to various control circuits in a memory device, according to some embodiments. Figure 8B The wake-up detector 250 is implemented as an inverter daisy chain with a predetermined delay time based on design requirements. Figure 8B In this process, when the wake-up detector 250 receives an enable signal from the delay circuit 224, an SLPWK_TRK signal is generated at the output of the wake-up detector 250 after a predetermined delay period. In some embodiments, the SLPWK_TRK signal is transmitted to... Figure 2 The first input of the delay circuits 208, 218 and 228 in the power management circuit is the process of starting to turn on the functional switches of the virtual power lines VDDHD[0], VDDHD[1] and VDDHD[2].

[0083] Figure 9 This is a flowchart of a method for activating a memory device according to some embodiments. At operation 410, a wake-up switch is turned on to establish a power connection to a memory cell in a first memory bank. Figure 1 In one embodiment, the wake-up switches (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1] are turned on to establish a power connection to the memory cells in the first memory bank 110. Figure 1 In the process, after the virtual power line VDDAI[1] is connected to the VDD power supply via a wake-up switch, the memory cells in the first memory bank 110 draw power from the virtual power line VDDAI[1]. Figure 1 In this implementation, the wake-up switch is implemented as a head switch between a virtual power line VDDAI[1] and a pull-up power supply VDD. In some alternative embodiments, a power connection to the memory cell is established by turning on a wake-up switch implemented as a foot switch between a virtual power line (e.g., VSSAI[1]) and a pull-down power supply VSS. In still other alternative embodiments, a power connection to the memory cell is established by turning on both the head switch and the foot switch. In some embodiments, the foot switch is implemented as a transistor switch, such as a FET switch.

[0084] exist Figure 9In operation 412, after a predetermined delay period, at operation 420, the wake-up switch is turned on to establish a power connection to the memory cell in the next memory bank. For example, in... Figure 1 In one embodiment, after a predetermined time delay from the gate delay of the wake-up switches (e.g., T11, T12, ..., and T19) of the virtual power line VDDAI[1], the wake-up switches (e.g., T21, T22, ..., and T29) of the virtual power line VDDAI[2] are turned on to establish a power connection to the memory cell in the next memory bank 120.

[0085] exist Figure 9 In the process, operations at 412 and 420 are repeated until the wake-up switches are turned on for all memory banks. Then, at operation 430, a trigger signal is generated when the voltage level of a memory cell is higher than a threshold. For example, in Figure 1 In one embodiment, after the wake-up switch is turned on to establish power connections to memory cells in all memory banks (e.g., 110, 120, 130, and 140), a trigger signal SLPWK is generated at the output of the wake-up detector 150 when the voltage level on the virtual power line is higher than a predetermined level.

[0086] exist Figure 9 In operation 440, based on a trigger signal, the wake-up switch is turned on to initiate power connection to the MIO controller. In some embodiments, at operation 440, the wake-up switch is turned on to initiate power connection to both the MIO controller and the main control circuit (MCTRL). For example, in Figure 2 In one embodiment, based on the SLPWK signal received by the delay circuit 202, the wake-up switches (e.g., W00, W01, W02, ..., and W09) of the virtual power line VDDHD[0] are turned on, and a power connection to MIO207 and MCTRL 205 is established. Figure 9 In operation 442, after a predetermined time delay, a wake-up switch is activated at operation 450 to establish a power connection to the first group of LIO controllers. In some embodiments, the wake-up switch is activated at operation 450 to establish a power connection to the first group of LIO controllers and the corresponding local control circuit (LCTRL). In some embodiments, the wake-up switch is activated at operation 450 to establish a power connection to the first group of LIO controllers, the corresponding local control circuit (LCTRL), and the corresponding word line driver (WLDRV). Figure 2In one embodiment, after a delay caused by delay circuits 204 and 212, the wake-up switches (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1] are turned on to establish a power connection to the LIO controller 217, WLDRV 118 and the corresponding LCTRL 215.

[0087] exist Figure 9 In operation 452, after a predetermined delay period, at operation 460, a wake-up switch is turned on to establish a power connection to the next set of LIO controllers. In some embodiments, at operation 460, the wake-up switch is turned on to establish a power connection to the next set of LIO controllers and the corresponding local control circuitry (LCTRL). In some embodiments, at operation 460, the wake-up switch is turned on to establish a power connection to the next set of LIO controllers, the corresponding local control circuitry (LCTRL), and the corresponding word line driver (WLDRV). Figure 2 In the embodiment, after a delay caused by delay circuits 214 and 222, the wake-up switches (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2] are turned on to establish power connections to LIO controller 227, WLDRV 128, and the corresponding LCTRL 225. Operations at 452 and 460 are repeated until the wake-up switches are turned on for all LIO controller groups. Then, at operation 470, a trigger signal is generated after the voltage level of the LIO controller exceeds a threshold. Figure 2 In one embodiment, when the voltage levels on the virtual power lines VDDHD[0], VDDHD[1] and VDDHD[2] are higher than a predetermined voltage level, the wake-up detector 250 generates a trigger signal SLPWK_TRK.

[0088] exist Figure 9 In this configuration, after triggering at operation 470, a function switch is activated at operation 480 to establish further power connections to the MIO controller and LIO controller. In some embodiments, the function switch is activated at operation 480 to establish further power connections to the MIO controller, LIO controller, main control circuitry (MCTRL), local control circuitry (LCTRL), and word line driver (WLDRV). Figure 2In this embodiment, after the wake-up detector 250 generates the trigger signal SLPWK_TRK, a function switch for the virtual power lines (e.g., VDDHD[0], VDDHD[1], and VDDHD[2]) is turned on to establish further power connections to the MIO controller 207, LIO controllers 217 and 227, LCTRL 215 and 225, and WLDRV 118 and 128. The function switch reduces the IR drop between the virtual power lines and the power supply VDD.

[0089] Figure 10A Based on some embodiments Figure 9 A flowchart of another method for activating a memory device, a variation of the method described in the diagram. Figure 10B It is an implementation based on some embodiments. Figure 10A A schematic diagram of a portion of the power management circuitry, showing some of the operations in the flowchart. Figure 10A In the process, after generating a trigger signal indicating that the voltage level of the memory cell is higher than a threshold at operation 430, a wake-up switch is turned on at operation 450 to establish a power connection to the first group of LIO controllers. After a predetermined delay period at operation 452, the wake-up switch is turned on at operation 460 to establish a power connection to the next group of LIO controllers. The operations at 452 and 460 are repeated until the wake-up switch is turned on for all LIO controller groups. Then, after a predetermined delay period at operation 462, the wake-up switch is turned on at operation 440 to initiate a power connection to the MIO controller.

[0090] In some embodiments, at operation 450, the wake-up switch is turned on to establish a power connection to the first set of LIO controllers and the corresponding local control circuit (LCTRL). In some embodiments, at operation 450, the wake-up switch is turned on to establish a power connection to the first set of LIO controllers, the corresponding local control circuit (LCTRL), and the corresponding word line driver (WLDRV). In some embodiments, at operation 460, the wake-up switch is turned on to establish a power connection to the next set of LIO controllers and the corresponding local control circuit (LCTRL). In some embodiments, at operation 460, the wake-up switch is turned on to establish a power connection to the next set of LIO controllers, the corresponding local control circuit (LCTRL), and the corresponding word line driver (WLDRV). In some embodiments, at operation 440, the wake-up switch is turned on to initiate a power connection to both the MIO controller and the main control circuit (MCTRL).

[0091] exist Figure 10BIn one embodiment, after the delay circuit 222 receives the SLPWK signal, the wake-up switches (e.g., W20, W21, W22, ..., and W29) of the virtual power line VDDHD[2] are turned on to establish power connections to the LIO controller 227, WLDRV 118, and the corresponding LCTRL 215. Then, after a delay caused by the delay circuits 224 and 212, the wake-up switches (e.g., W10, W11, W12, ..., and W19) of the virtual power line VDDHD[1] are turned on to establish power connections to the LIO controller 217, WLDRV 118, and the corresponding LCTRL 215. Next, after a delay caused by delay circuits 214 and 202, the wake-up switches of the virtual power line VDDHD[0] (e.g., W00, W01, W02, ..., and W09) are turned on, and power connections to MIO 207 and MCTRL 205 are established.

[0092] exist Figure 10A In operation 445, a trigger is generated after the voltage level of the MIO controller exceeds a threshold. Then, in operation 480, a function switch is turned on to establish further power connections to the MIO and LIO controllers. Figure 10B In this embodiment, after the wake-up detector 250 generates the trigger signal SLPWK_TRK, a function switch for the virtual power lines (e.g., VDDHD[0], VDDHD[1], and VDDHD[2]) is turned on to establish further power connections to the MIO controller 207, LIO controllers 217 and 227, LCTRL 215 and 225, and WLDRV 118 and 128. The function switch reduces the IR drop between the virtual power lines and the power supply VDD.

[0093] One aspect of this specification relates to a device. The device includes a first virtual power line in a first memory bank, a second virtual power line in a second memory bank, a first delay circuit, and a first wake-up detector. The first virtual power line is configured to be coupled to a power source via a first set of transistor switches. The second virtual power line is configured to receive power via a second set of transistor switches. The first delay circuit has a first input coupled to the gate terminal of the first set of transistor switches and a first output coupled to the gate terminal of the second set of transistor switches. The first wake-up detector is configured to generate a first trigger signal after receiving a signal from the first output of the first delay circuit.

[0094] One aspect of this specification relates to a device. The device includes a plurality of MIO controllers, a first set of LIO controllers, a wake-up detector, and a plurality of drivers. The plurality of MIO controllers are configured to be coupled to a power supply via a first set of wake-up switches and a first set of function switches. The first set of LIO controllers is configured to be coupled to a power supply via a second set of wake-up switches and a second set of function switches. The wake-up detector is configured to generate a trigger signal when the voltage level supplying the plurality of MIO controllers and the first set of LIO controllers reaches a predetermined value. The plurality of drivers have driver outputs coupled to the gate terminals of the first set of function switches and the gate terminals of the second set of function switches, and the plurality of drivers have driver inputs configured to receive the trigger signal.

[0095] Another aspect of this specification relates to a method for activating a memory device. The memory device includes multiple main input / output (MIO) controllers, multiple local input / output (LIO) controllers, multiple wake-up switches, multiple function switches, and multiple memory banks. Each memory bank includes multiple memory cells. The method includes establishing a power connection to memory cells in a first memory bank via a wake-up switch associated with a first memory bank. The method includes establishing a power connection to memory cells in a second memory bank via a wake-up switch associated with a second memory bank after a predetermined time period following the establishment of the power connection to the memory cells in the first memory bank. The method includes providing power connections to the MIO controllers and LIO controllers after the power connection to the memory cells in the second memory bank is completed.

[0096] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages set forth above. Having read the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and other embodiments as broadly disclosed herein. Therefore, the protection intended to be granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0097] Example 1 is a semiconductor device comprising: a first virtual power line located in a first memory bank, the first virtual power line being configured to be coupled to a power source via a first set of transistor switches; a second virtual power line located in a second memory bank, the second virtual power line being configured to receive the power source via a second set of transistor switches; a first delay circuit having a first input coupled to a gate terminal of the first set of transistor switches and a first output coupled to a gate terminal of the second set of transistor switches; and a first wake-up detector configured to generate a first trigger signal after receiving a signal from the first output of the first delay circuit.

[0098] Example 2 is the device described in Example 1, wherein: the first memory bank includes a first bit unit that receives power from the first virtual power line; and the second memory bank includes a second bit unit that receives power from the second virtual power line.

[0099] Example 3 is the device described in Example 1, wherein the power supply is a power rail.

[0100] Example 4 is the device described in Example 1, further comprising: a plurality of main input / output (MIO) controllers configured to be coupled to the power supply via a first set of wake-up switches and a first set of function switches, wherein the gate terminals of the first set of wake-up switches are configured to receive the first trigger signal; and a first set of local input / output (LIO) controllers configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches, wherein the gate terminals of the second set of wake-up switches are configured to receive a delayed signal from the gate terminals of the first set of wake-up switches via one or more stages of delay circuitry.

[0101] Example 5 is the device described in Example 4, further comprising: a second wake-up detector having an input coupled to a gate terminal of a second set of wake-up switches in the first set of LIO controllers and configured to generate a second trigger signal; and a plurality of drivers having driver inputs configured to receive the second trigger signal and driver outputs coupled to gate terminals of the first set of function switches and gate terminals of the second set of function switches.

[0102] Example 6 is the device described in Example 4, further comprising: a second set of LIO controllers configured to be coupled to the power supply via a third set of wake-up switches and a third set of function switches; and a second delay circuit having a second output coupled to a gate terminal in the third set of wake-up switches and a second input coupled to a gate terminal in the second set of wake-up switches in the first set of LIO controllers.

[0103] Example 7 is the device described in Example 1, further comprising: a plurality of MIO controllers configured to be coupled to the power supply via a first set of wake-up switches and a first set of function switches; a first set of LIO controllers configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches, wherein the gate terminal of the second set of wake-up switches is configured to receive the first trigger signal; and wherein the gate terminal of the first set of wake-up switches is configured to receive a delayed signal from the gate terminal of the second set of wake-up switches via one or more stages of delay circuitry.

[0104] Example 8 is the device described in Example 7, further comprising: a second wake-up detector coupled to a gate terminal in the first set of wake-up switches and configured to generate a second trigger signal; and a plurality of drivers having driver inputs configured to receive the second trigger signal and driver outputs coupled to gate terminals in the first set of function switches and gate terminals in the second set of function switches.

[0105] Example 9 is the device described in Example 7, further comprising: a second set of LIO controllers configured to be coupled to the power supply via a third set of wake-up switches and a third set of function switches; and a second delay circuit having a second output coupled to a gate terminal in the third set of wake-up switches and a second input coupled to a gate terminal in the second set of wake-up switches in the first set of LIO controllers.

[0106] Example 10 is a semiconductor device comprising: a plurality of MIO controllers configured to be coupled to a power supply via a first set of wake-up switches and a first set of function switches; a first set of LIO controllers configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches; a wake-up detector configured to generate a trigger signal when a voltage level supplying power to the plurality of MIO controllers and the first set of LIO controllers reaches a predetermined value; and a plurality of drivers having driver outputs coupled to gate terminals of the first set of function switches and gate terminals of the second set of function switches, and having driver inputs configured to receive the trigger signal.

[0107] Example 11 is the device described in Example 10, wherein the wake-up detector has an input coupled to a gate terminal of a second set of wake-up switches in the first set of LIO controllers.

[0108] Example 12 is the device described in Example 11, further comprising: a second set of LIO controllers configured to be coupled to the power supply via a third set of wake-up switches and a third set of function switches; and a delay circuit having an output coupled to a gate terminal of the second set of wake-up switches in the first set of LIO controllers, and an input coupled to a gate terminal of the third set of wake-up switches.

[0109] Example 13 is the device described in Example 10, wherein the wake-up detector has an input coupled to the gate terminal of the first set of wake-up switches in the MIO controller.

[0110] Example 14 is the device described in Example 13, further comprising: a delay circuit having an output coupled to a gate terminal of the first set of wake-up switches in the MIO controller, and an input coupled to a gate terminal of the second set of wake-up switches in the first set of LIO controllers.

[0111] Example 15 is a method for activating a memory device including multiple main input / output (MIO) controllers, multiple local input / output (LIO) controllers, multiple wake-up switches, multiple function switches, and multiple memory banks, wherein each memory bank includes multiple memory cells. The method includes: establishing a power connection to memory cells in a first memory bank via a wake-up switch associated with a first memory bank; establishing a power connection to memory cells in a second memory bank via a wake-up switch associated with a second memory bank after a predetermined time period following the establishment of the power connection to the memory cells in the first memory bank; and providing power connections to the MIO controllers and the LIO controllers after the power connection to the memory cells in the second memory bank is completed.

[0112] Example 16 is the method described in Example 15, wherein establishing a power connection to the memory cell includes: turning on a power node and a transistor switch conductively connected to a power bus of the memory cell.

[0113] Example 17 is the method described in Example 15, wherein providing power connections to the MIO controller and the LIO controller includes: establishing a power connection to the first group of LIO controllers via a wake-up switch associated with the first group of LIO controllers at a first time; establishing a power connection to the second group of LIO controllers via a wake-up switch associated with the second group of LIO controllers at a second time; and establishing a power connection to the MIO controller via a wake-up switch associated with the MIO controller at a third time.

[0114] Example 18 is the method described in Example 17, wherein providing power connections to the MIO controller and the LIO controller further includes: after completing power connections to the MIO controller and to the first group of LIO controllers and the second group of LIO controllers via the wake-up switch, establishing further power connections to the MIO controller and to the first group of LIO controllers and the second group of LIO controllers via the function switch.

[0115] Example 19 is the method of Example 17, further comprising: establishing a power connection to the first set of LIO controllers based on a trigger signal generated immediately after power connection to a memory cell in the second memory bank is completed.

[0116] Example 20 is the method of Example 17, further comprising: establishing a power connection to the MIO controller based on a trigger signal generated immediately after power connection to a memory cell in the second memory bank is completed.

Claims

1. A semiconductor device, comprising: A first virtual power line, located in a first memory bank, is configured to be coupled to a power source via a first set of transistor switches; A second virtual power line, located in a second memory bank, is configured to receive power through a second set of transistor switches; A first delay circuit, contained in the first memory bank, has a first input coupled to the gate terminal of the first set of transistor switches; The second delay circuit, included in the second memory bank, has a first input coupled to the first output of the first delay circuit, wherein the first output of the second delay circuit is coupled to the gate terminal of the second set of transistor switches; A third delay circuit, included in the second memory bank, has a first input coupled to the gate terminal of the second set of transistor switches; and The first wake-up detector is configured to generate a first trigger signal after receiving a signal from the first output of the third delay circuit.

2. The device according to claim 1, wherein: The first memory bank includes a first set of bit units, which receive power from the first virtual power line; and The second memory bank includes a second set of bit units that receive power from the second virtual power line.

3. The device according to claim 1, wherein, The power source is a power rail.

4. The device according to claim 1, further comprising: Multiple main input / output (MIO) controllers are configured to be coupled to the power supply via a first set of wake-up switches and a first set of function switches, wherein the gate terminals of the first set of wake-up switches are configured to receive the first trigger signal; and The first set of local input / output (LIO) controllers is configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches, wherein the gate terminals of the second set of wake-up switches are configured to receive delayed signals from the gate terminals of the first set of wake-up switches via one or more stages of delay circuitry.

5. The device according to claim 4, further comprising: The second wake-up detector has an input coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers and is configured to generate a second trigger signal; as well as Multiple drivers, having driver inputs configured to receive the second trigger signal, and driver outputs coupled to gate terminals in the first set of function switches and gate terminals in the second set of function switches.

6. The device according to claim 4, further comprising: The second set of LIO controllers is configured to be coupled to the power supply via a third set of wake-up switches and a third set of function switches; and wherein... The second delay circuit has a first output coupled to the gate terminal of the third set of wake-up switches, and the first delay circuit has a first input coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers.

7. The device according to claim 1, further comprising: Multiple MIO controllers are configured to be coupled to the power supply via a first set of wake-up switches and a first set of function switches; The first set of LIO controllers is configured to be coupled to the power supply via a second set of wake-up switches and a second set of function switches, wherein the gate terminal of the second set of wake-up switches is configured to receive the first trigger signal; and The gate terminals of the first set of wake-up switches are configured to receive delayed signals from the gate terminals of the second set of wake-up switches through one or more delay circuits.

8. The device according to claim 7, further comprising: The second wake-up detector is coupled to the gate terminal of the first set of wake-up switches and is configured to generate a second trigger signal; as well as Multiple drivers, having driver inputs configured to receive the second trigger signal, and driver outputs coupled to gate terminals in the first set of function switches and gate terminals in the second set of function switches.

9. The device according to claim 7, further comprising: The second set of LIO controllers is configured to be coupled to the power supply via a third set of wake-up switches and a third set of function switches; and in The second delay circuit has a first output coupled to the gate terminal of the third set of wake-up switches, and the first delay circuit has a first input coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers.

10. A semiconductor device, comprising: Multiple main input / output (MIO) controllers are configured to be coupled to the power supply via a first set of wake-up switches and a first set of function switches; The first set of local input / output (LIO) controllers is configured to be coupled to the power supply via the second set of wake-up switches and the second set of function switches; A wake-up detector is configured to generate a trigger signal when the voltage level supplying the plurality of MIO controllers and the first group of LIO controllers reaches a predetermined value; as well as Multiple drivers have driver outputs coupled to the gate terminals of the first set of functional switches and the gate terminals of the second set of functional switches, and driver inputs configured to receive the trigger signal.

11. The device according to claim 10, wherein, The wake-up detector has an input coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers.

12. The device according to claim 11, further comprising: The second set of LIO controllers is configured to be coupled to the power supply via the third set of wake-up switches and the third set of function switches; as well as The delay circuit has an output coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers, and an input coupled to the gate terminal of the third set of wake-up switches.

13. The device according to claim 10, wherein, The wake-up detector has an input coupled to the gate terminal of the first set of wake-up switches in the MIO controller.

14. The device according to claim 13, further comprising: The delay circuit has an output coupled to the gate terminal of the first set of wake-up switches in the MIO controller, and an input coupled to the gate terminal of the second set of wake-up switches in the first set of LIO controllers.

15. A method for activating a memory device, the memory device comprising a plurality of main input / output (MIO) controllers, a plurality of local input / output (LIO) controllers, a plurality of wake-up switches, a plurality of function switches, and a plurality of memory banks, wherein, Each memory bank includes multiple memory units, and the method includes: A power connection to the memory cells in the first memory bank is established via a wake-up switch associated with the first memory bank. After a predetermined time period following the establishment of a power connection to a memory cell in the first memory bank, a power connection to a memory cell in the second memory bank is established via a wake-up switch associated with the second memory bank; and After power connections to the memory cells in the second memory bank are established, power connections are provided to the MIO controller and the LIO controller. The power connections provided to the MIO controller and the LIO controller include: In the first instance, a power connection to the first group of LIO controllers is established via a wake-up switch associated with the first group of LIO controllers; At the second time, a power connection to the second set of LIO controllers is established via a wake-up switch associated with the second set of LIO controllers; and At the third time, a power connection to the MIO controller is established via a wake-up switch associated with the MIO controller.

16. The method according to claim 15, wherein, Establishing a power connection to a memory cell includes turning on a power node and a transistor switch that is conductively connected to a power bus of the memory cell.

17. The method according to claim 15, wherein, The power connections provided to the MIO controller and the LIO controller also include: After the power connection to the MIO controller and the first group of LIO controllers and the second group of LIO controllers is completed through the wake-up switch, a further power connection to the MIO controller and the first group of LIO controllers and the second group of LIO controllers is established through the function switch.

18. The method of claim 15, further comprising: A power connection to the first set of LIO controllers is established based on a trigger signal generated immediately after the power connection to the memory cell in the second memory bank is completed.

19. The method of claim 15, further comprising: A power connection to the MIO controller is established based on a trigger signal generated immediately after the power connection to the memory cell in the second memory bank is completed.

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