Memory device and data output method thereof

Abstract

A memory device and a data output method thereof are provided. The memory device includes a memory cell array, a data selector configured to receive data from the memory cell array and output the received data as first sub-data and second sub-data, a cyclic redundancy check (CRC) generator configured to generate a first CRC value corresponding to the first sub-data and a second CRC value corresponding to the second sub-data, a CRC selector configured to determine an order of the first CRC value and the second CRC value and output the first CRC value and the second CRC value according to the determined order, and a transmitter configured to receive the first CRC value and the second CRC value according to the determined order and transmit the ordered first CRC value and second CRC value through a multi-level signaling method.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0173059, entitled "Memory Device, Data Outputting Method thereof, and Memory System Having the Same", filed on December 11, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to storage devices, data output methods for storage devices, and storage systems having storage devices. Background Technology

[0004] Typically, with the rapid availability of mobile devices and the rapid increase in internet access, the demand for high-capacity and high-speed data transmission is increasing. Summary of the Invention

[0005] An embodiment relates to a storage device, comprising: a memory cell array; a data selector configured to receive data from the memory cell array and output the received data as a first sub-data and a second sub-data; a cyclic redundancy check (CRC) generator configured to generate a first CRC value corresponding to the first sub-data and a second CRC value corresponding to the second sub-data; a CRC selector configured to determine the order of the first CRC value and the second CRC value and output the first CRC value and the second CRC value according to the determined order; and a transmitter configured to receive the first CRC value and the second CRC value according to the determined order and transmit the ordered first CRC value and the second CRC value via a multi-level signaling method.

[0006] The embodiment also relates to a storage device, including: a memory cell array; a plurality of transceivers configured to transmit / receive data of the memory cell array via a data line using a multi-level signaling method; a data bus inverting (DBI) transceiver configured to transmit / receive DBI data via a data bus inverting line using the multi-level signaling method; and a cyclic redundancy check (CRC) transceiver configured to transmit / receive CRC values ​​of the data via an error detection check (EDC) line using the multi-level signaling method. The storage device may be configured to divide the data into a plurality of sub-data, generate a CRC value corresponding to each of the plurality of sub-data, and sort the CRC values. The CRC transceiver may include a transmitter configured to transmit the sorted CRC values ​​via the multi-level signaling method.

[0007] The embodiments also relate to a data output method for a storage device including a storage cell array, the method comprising: dividing data read from the storage cell array into multiple sub-data; calculating cyclic redundancy check (CRC) values ​​corresponding to the multiple sub-data respectively; sorting the calculated CRC values; and sending the sorted CRC values ​​together with the data using a multi-level signaling method.

[0008] Example embodiments also relate to a storage system including: a storage device; and a controller configured to control the storage device, the controller including: a plurality of transceivers configured to transmit / receive data of the storage device via a data line using a multi-level signaling method; a data bus inverting (DBI) transceiver configured to transmit / receive DBI data via the multi-level signaling method using a data bus inverting line; and a cyclic redundancy check (CRC) transceiver configured to transmit / receive the CRC value of the data via the multi-level signaling method using an error detection check (EDC) line. Attached Figure Description

[0009] The features will become clear to those skilled in the art by referring to the detailed description of the exemplary embodiments in the accompanying drawings, in which:

[0010] Figure 1 This is a diagram illustrating a storage system 10 according to an exemplary embodiment by way of example;

[0011] Figure 2A This is a diagram illustrating PAM4 signaling according to an example embodiment. Figure 2B This is a diagram illustrating the transmitter TX of a transceiver according to an example embodiment, and... Figure 2CThis is a diagram illustrating the signal level transmitted by the transmitter (TX) through examples;

[0012] Figure 3 The diagram illustrates the storage device 100 according to an exemplary embodiment by way of example.

[0013] Figure 4 This is a diagram illustrating, by way of example, the output device of the data input / output circuit 190 according to an exemplary embodiment;

[0014] Figure 5 The diagram illustrates the CRC generator 192 according to an example embodiment by way of example.

[0015] Figure 6 This is a diagram illustrating the output timing of EDC data from the storage device 100 according to this example embodiment by way of example;

[0016] Figure 7 The diagram illustrates the transmitter 194 according to an exemplary embodiment by way of example.

[0017] Figure 8 This is a diagram illustrating the CRC encoding method based on the data selection method according to an example embodiment;

[0018] Figure 9 This is a diagram illustrating a CRC encoding method based on a data selection method according to another example embodiment, by way of example.

[0019] Figure 10 This is a diagram illustrating, by way of example, the output device of a data input / output circuit 190 according to another exemplary embodiment;

[0020] Figure 11 This is a diagram illustrating a data output device 300 according to an exemplary embodiment by way of example;

[0021] Figure 12 This is a flowchart illustrating a data output method of a storage device 100 according to an exemplary embodiment by way of example;

[0022] Figure 13 This is a flowchart illustrating, by way of example, a data receiving method of controller 200 according to an exemplary embodiment;

[0023] Figure 14A and Figure 14B The diagram illustrates a storage system based on the PAM4 and NRZ dual-mode approach through examples.

[0024] Figure 15This is a diagram illustrating a storage system performing at least one command / address calibration according to an example embodiment;

[0025] Figure 16 The diagram illustrates a computing system 3000 according to an exemplary embodiment by way of example.

[0026] Figure 17 The diagram illustrates a computing system 4000 according to another exemplary embodiment by way of example; and

[0027] Figure 18 This is a diagram illustrating, by way of example, a data center in which a storage device according to an embodiment of this example is applied. Detailed Implementation

[0028] The storage device and its data output method according to the example embodiment can calculate CRC by mapping cell data to the input of a parallel cyclic redundancy check (CRC) calculator according to the settings of the memory register, sorting each output of the parallel CRC calculator, and sending the sorted output to a transmitter using a multi-level signaling method, thereby calculating CRC with low latency while maintaining the code rate.

[0029] Figure 1 The diagram illustrates the storage system 10 according to an example embodiment by way of example.

[0030] Reference Figure 1 The storage system 10 may include a storage device 100 and a controller (CNTL) 200. The storage system 10 may be implemented as a multi-chip package (MCP) or a system-on-a-chip (SoC).

[0031] Storage device 100 can be implemented to store data received from controller 200 or to output read data to controller 200. Storage device 100 can be used as operational memory, working memory, or buffer memory in a computing system. In example embodiments, storage device 100 can be implemented as a single in-line memory module (SIMM), dual in-line memory module (DIMM), small DIMM (SODIMM), unbuffered DIMM (UDIMM), fully buffered DIMM (FBDIMM), column buffered DIMM (RBDIMM), mini-DIMM, micro-DIMM, registered DIMM (RDIMM), or low-load DIMM (LRDIMM).

[0032] In an example embodiment, the storage device 100 may be implemented as volatile memory. For example, the volatile memory may include at least one of dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), low power double data rate SDRAM (LPDDRSDRAM), graphics double data rate SDRAM (GDDRSDRAM), Rambus DRAM (RDRAM), and static RAM (SRAM). In another example embodiment, the storage device 100 may be implemented as non-volatile memory. For example, the non-volatile memory may include one of NAND flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and NOR flash memory.

[0033] Although not shown, storage device 100 may include a serial presence detection (SPD) chip. The SPD chip may be implemented to store information about the characteristics of storage device 100. In an example embodiment, the SPD chip may store storage device information such as the module type, operating environment, wiring layout, module configuration, and storage capacity of storage device 100. In an example embodiment, the SPD chip may include a programmable read-only memory, such as an electrically erasable programmable read-only memory (EEPROM).

[0034] The storage device 100 may include a memory cell array (MCA) 110 and multiple transceivers (PAM4 XCVR) 101.

[0035] Each of the multiple transceivers can be implemented to transmit and receive data via data lines DQ0 to DQ7, the data bus inversion (DBI) line, and the error detection code (EDC) line according to a 4-level pulse amplitude modulation (PAM4) signaling method. Meanwhile, although... Figure 1 The number of data lines shown is 8, but it should be understood that the number of data lines is not limited to this. Also, although combined with... Figure 1 The transmission signaling method described is PAM4, but it should be understood that the implementation is not limited to PAM4, and PAM8, PAM16, etc. can also be applied.

[0036] The controller 200 can be implemented to control the storage device 100. The controller 200 can know the transmission signaling pattern stored in the storage device 100. The controller 200 can send data to and receive data from the storage device 100 via a data channel according to the transmission signaling pattern.

[0037] The controller 200 may include multiple transceivers 201. Each transceiver may include a transmitter and a receiver. The transmitter of the controller 200 may be configured to send write data to the storage device 100 via data lines DQ0 to DQ7 according to a transmission signaling method. The receiver of the controller 200 may be configured to receive read data from the storage device 100 via data lines DQ0 to DQ7 according to a transmission signaling method.

[0038] In example embodiments, controller 200 may be configured as a separate chip or may be integrated with memory device 100. For example, controller 200 may be implemented on a motherboard. Furthermore, controller 200 may be implemented as an integrated memory controller (IMC) included in a microprocessor. Additionally, controller 200 may reside in an input / output hub. The input / output hub including controller 200 may be referred to as a memory controller hub (MCH).

[0039] Typically, when the I / O interface speed (data frequency) increases due to PAM4 signaling, the core speed of storage devices (e.g., DRAM) can increase, or the number of prefetched bits can increase. Error checking efficiency may decrease due to the increase in the number of prefetched bits and the change in the code rate (the ratio of data bits to parity bits). Furthermore, as data increases, the latency of CRC calculation may increase, thus potentially degrading system performance. Therefore, a CRC encoding method that maintains the code rate in PAM4 signaling while reducing latency is needed.

[0040] The storage system 10 according to this example embodiment can divide cell data according to PAM4 signaling, perform CRC calculation in parallel according to the divided cell data, and send the output of the parallel CRC using a multi-level signaling method. The storage system can reduce the latency of CRC calculation while maintaining the code rate.

[0041] Figure 2A This is a diagram illustrating PAM4 signaling according to an example embodiment. Figure 2B This is a diagram illustrating the transmitter TX of a transceiver according to an example embodiment, and... Figure 2C This is a diagram illustrating the signal level transmitted by the transmitter (TX) through examples.

[0042] Reference Figure 2A It can send 2-bit data "00", "01", "10", and "11" corresponding to the four voltage levels V1 to V4 according to PAM4 signaling. (See reference...) Figure 2B It can send 1-bit data "1" and "0" corresponding to the two voltage levels VL and VH according to NRZ (non-return to zero) transmission signaling.

[0043] Figure 2B This is a diagram illustrating the transmitter (TX) of transceiver 101 according to this example embodiment by way of example.

[0044] Reference Figure 2B The transmitter TX may include a most significant bit (MSB) driver (pull-up / pull-down driver; MSB DRV) and a least significant bit (LSB) driver (pull-up / pull-down driver; LSB DRV) connected to the DQ pad (data pad). The MSB driver may include multiple P-channel metal-oxide-semiconductor (PMOS) transistors connected in parallel between the power supply terminal (VDD) and the DQ pad, and multiple N-channel metal-oxide-semiconductor (NMOS) transistors connected in parallel between the DQ pad and the ground terminal (GND). The LSB driver may include multiple PMOS transistors connected in parallel between the power supply terminal VDD and the DQ pad, and multiple NMOS transistors connected in parallel between the DQ pad and the ground terminal GND.

[0045] Figure 2C This diagram illustrates the signal levels V1 to V4 of the transmitter TX according to the pull-up / pull-down drive resistors, using examples. (Refer to...) Figure 2C When the pull-up resistor is R and the pull-down resistor is infinite, the transmitter TX can send a first signal level V1; when the pull-up resistor is 1.5R and the pull-down resistor is 3R, the transmitter TX can send a second signal level V2; when the pull-up resistor is 3R and the pull-down resistor is 1.5R, the transmitter TX can send a third signal level V3; and when the pull-up resistor is infinite and the pull-down resistor is R, the transmitter TX can send a fourth signal level V4. Here, R can be the resistance value corresponding to the characteristic impedance Z0. In the example embodiment, R can be the same regardless of the channel. In another example embodiment, R can vary depending on the channel. It should be understood that the relationship between signal level and resistance is not limited to... Figure 2C .

[0046] Figure 3 The diagram illustrates the storage device 100 according to an exemplary embodiment by way of example.

[0047] Reference Figure 3 The storage device 100 may include a memory cell array (MCA) 110, a row decoder 120, a column decoder 130, a sense amplifier circuit 140, an address register 150, a memory bank control logic 152, a refresh counter 154, a row address multiplexer (RA MUX) 156, a column address (CA) latch 158, control logic 160, a repair control circuit 166, a timing control circuit 164, an input / output (I / O) gate circuit 170, an error correction circuit 180, and a data input / output circuit 190.

[0048] The memory cell array 110 may include a first memory bank 111 to an eighth memory bank 118. It should be understood that the number of memory banks in the memory cell array 110 is not limited to this.

[0049] For each of the first memory bank 111 to the eighth memory bank 118, there may be associated with a row decoder 121 to the row decoder 128, a column decoder 131 to the column decoder 138, and a sense amplifier 141 to the sense amplifier 148. Each of the first memory bank 111 to the eighth memory bank 118 may include a plurality of memory cells MC formed at the intersection of the word line WL and the bit line BL.

[0050] The row decoder 120 may include first memory row decoders 121 to eighth memory row decoders 128 respectively connected to the first memory bank 111 to the eighth memory bank 118.

[0051] The column decoder 130 may include first memory column decoders 131 to eighth memory column decoders 138 respectively connected to the first memory bank 111 to the eighth memory bank 118.

[0052] The readout amplifier circuit 140 may include first memory readout amplifiers 141 to eighth memory readout amplifiers 148 respectively connected to the first memory bank 111 to the eighth memory bank 118.

[0053] Address register 150 can receive and store addresses ADDR (which have bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR) from the external memory controller. Address register 150 can provide the received bank address BANK_ADDR to the bank control logic 152, the received row address ROW_ADDR to the row address multiplexer 156, and the received column address COL_ADDR to the column address latch 158.

[0054] The memory bank control logic 152 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoders corresponding to the memory bank address BANK_ADDR among the first memory bank row decoders 121 to the eighth memory bank row decoders 128 can be activated. In response to the memory bank control signal, the memory bank column decoders corresponding to the memory bank address BANK_ADDR among the first memory bank column decoders 131 to the eighth memory bank column decoders 138 can be activated.

[0055] The row address multiplexer 156 can receive the row address ROW_ADDR from the address register 150 and the refresh row address REF_ADDR from the refresh counter 154. The row address multiplexer 156 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 156 can be applied to the first memory bank row decoders 121 to the eighth memory bank row decoders 128, respectively.

[0056] The bank row decoders activated by the bank control logic 152, among the first bank row decoders 121 to the eighth bank row decoders 128, can decode the row address RA output from the row address multiplexer 156 and activate the word lines corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. The activated bank row decoder can also activate the redundant word line corresponding to the redundant row address output from the repair control circuit 166 while activating the word line corresponding to the row address.

[0057] Column address latch 158 can receive column address COL_ADDR from address register 150 and temporarily store the received column address COL_ADDR. Column address latch 158 can gradually increment the received column address COL_ADDR in burst mode. Column address latch 158 can apply the temporarily stored or gradually incremented column address COL_ADDR to the first memory bank column decoder 131 to the eighth memory bank column decoder 138, respectively.

[0058] In the first to eighth bank column decoders 131, the bank column decoder activated by the bank control logic 152 can activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 170. The activated bank column decoder can perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 166.

[0059] Control logic 160 can be implemented to control the operation of storage device 100. For example, control logic 160 can generate control signals that cause storage device 100 to perform write or read operations. Control logic 160 may include a command decoder 161 for decoding commands CMD received from the memory controller, and may include a mode register group 162 for setting the operating mode of storage device 100.

[0060] For example, command decoder 161 can decode write enable signal ( / WE), row address strobe signal ( / RAS), column address strobe signal ( / CAS), chip select signal ( / CS), etc., to generate operation control signals ACT, PCH, WR, and RD corresponding to command CMD. Control logic 160 can provide operation control signals ACT, PCH, WR, and RD to timing control circuit 164. Control signals ACT, PCH, WR, and RD may include activation signal ACT, precharge signal PCH, write signal WR, and read signal RD. Timing control circuit 164 can, in response to operation control signals ACT, PCH, WR, and RD, generate a first control signal CTL1 for controlling the voltage level of word line WL, and generate a second control signal CTL2 for controlling the voltage level of bit line BL, and provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 110.

[0061] The repair control circuit 166 can generate repair control signals CRP and SRP for controlling the repair operation of at least one of the first and second cell regions of the memory bank, based on the row address ROW_ADDR, column address COL_ADDR in the address (ADDR or access address), and the fuse information of each word line in the word line. The repair control circuit 166 can provide the redundant row address to the corresponding memory bank row decoder, provide the column repair signal CRP to the corresponding memory bank column decoder, and provide the select signal and enable signal SRA to the block control circuit associated with the corresponding redundant array block.

[0062] In the hPPR (hard post package repair) mode stored in mode register group 162, the repair control circuit 166 can generate an hPPR word line activation signal in response to address ADDR. In the sPPR (soft post package repair) mode stored in mode register group 162, the repair control circuit 166 can generate an sPPR word line activation signal sPPR_WL_EN in response to address ADDR. In the sPPR_OFF mode stored in mode register group 162, the repair control circuit 166 can disable the sPPR logic and generate a normal word line activation signal to access previous data. In the example embodiment, the repair control circuit 166 can change the repair unit based on address ADDR and fuse information. For example, the repair control circuit 166 can change the type and number of repair address bits for address ADDR and fuse information.

[0063] Each input / output gating circuit in the input / output gating circuit 170 may include input data mask logic, a read data latch for storing data output from the first memory bank 111 to the eighth memory bank 118, a write driver for writing data to the first memory bank 111 to the eighth memory bank 118, and circuitry for gating input / output data.

[0064] The codeword (CW) to be read from one of the first memory bank 111 to the eighth memory bank 118 can be sensed by a sense amplifier corresponding to a memory bank and can be stored in a read data latch. After ECC decoding is performed by the error correction circuit 180, the codeword CW stored in the read data latch can be provided to the memory controller via the data input / output circuit 190. The data DQ to be written to one of the first memory bank 111 to the eighth memory bank 118 can be written to a memory bank via a write driver after ECC encoding is performed by the error correction circuit 180.

[0065] The data input / output circuit 190 can provide data DQ to the error correction circuit 180 based on a clock signal CLK provided from the memory controller during a write operation, and provide data DQ provided from the error correction circuit 180 to the memory controller during a read operation. The data input / output circuit 190 may include a data selector 191 for sending and receiving data (see...). Figure 4 In an example embodiment, the data input / output circuit 190 can be implemented to transmit data and CRC values ​​according to the PAM4 signaling method. In an example embodiment, the data input / output circuit 190 can be implemented to receive data and CRC values ​​according to the PAM4 signaling method.

[0066] Error correction circuit 180 can generate parity bits based on the data bits of data DQ provided from data input / output circuit 190 during write operations, and can provide codeword CW including data DQ and parity bits to input / output gating circuit 170. Input / output gating circuit 170 can write codeword CW to memory.

[0067] Error correction circuit 180 can receive codeword CW read from a memory bank from input / output gate circuit 170 during a read operation. Error correction circuit 180 can correct at least one erroneous bit included in data DQ by performing ECC decoding on data DQ using parity bits included in the read codeword CW, and provide the corrected erroneous bit to data input / output circuit 190.

[0068] Figure 4 This is a diagram illustrating, by way of example, the output device of a data input / output circuit 190 according to an exemplary embodiment. (Refer to...) Figure 4The output device of the data input / output circuit 190 may include a data selector 191, a CRC generator 192, a CRC selector 193, and a transmitter 194.

[0069] Data selector 191 can receive cell data (e.g., 2k bits of data, where k is an integer greater than or equal to 2) from the memory cell array MCA. Data selector 191 can select the received 2k bits of data as k bits of first sub-data and k bits of second sub-data. In an example embodiment, data selector 191 can divide the received cell data into first sub-data and second sub-data according to the settings of the memory registers.

[0070] The CRC generator 192 can be implemented to receive a first sub-data and a second sub-data, and generate a first CRC value of r bits and a second CRC value of r bits corresponding to the first sub-data and the second sub-data, respectively. The CRC generator 192 may include a first CRC calculator 192-1 and a second CRC calculator 192-2.

[0071] The first CRC calculator 192-1 can receive first sub-data or inverted first sub-data, and can generate a first CRC value by dividing the first sub-data by the CRC polynomial. In an example embodiment, the first CRC value can be the most significant bit (MSB) CRC value.

[0072] The second CRC calculator 192-2 can receive a second sub-data or an inverted second sub-data, and can generate a second CRC value by dividing the second sub-data by the CRC polynomial. In an example embodiment, the first CRC value can be the least significant bit (LSB) CRC value.

[0073] The CRC selector 193 can be implemented to receive a first CRC value and a second CRC value, sort the first CRC value and the second CRC value, and output the sorted CRC value to the transmitter 194.

[0074] Transmitter 194 can be implemented to receive ordered CRC values ​​and output CRC data via the EDC pin according to the transmission signaling method (PAM4 method).

[0075] When the PAM4 I / O interface is applied to DRAM, the data rate doubles for the same data conversion time; therefore, the amount of data processed by the storage data path doubles for the same latency. Consequently, the latency of Cyclic Redundancy Check (CRC) calculation, which can be used as an error correction method in DRAM, increases.

[0076] When the PAM4 I / O interface is applied, the memory device 100 (i.e., DRAM) can double (k bits) the amount of data to be processed in a single read / write operation compared to NRZ. In this case, two CRC calculators can be connected in parallel, and the CRC calculation time can be equal to NRZ by calculating the CRC in units of k / 2 bits. Each CRC value (r / 2 bits) output from the two CRC calculators can be serialized and applied from the CRC selector 193, which includes the CRC sorting circuit 193-1, to the MSB / LSB node of the PAM4 transmitter 194. The DRAM can then output the CRC information as a PAM4 signal to the host (or controller). The host can check for errors by dividing the received PAM4 CRC signal into MSB / LSBs and decoding these MSB / LSBs.

[0077] Figure 5 The diagram illustrates the CRC generator 192 according to the example embodiment by way of example.

[0078] Reference Figure 5 The CRC generator 192 may include a first CRC calculator 192-1, a second CRC calculator 192-2, a first DBI determiner 192-3, a second DBI determiner 192-4, a first inverter INV1, and a second inverter INV2.

[0079] The first CRC calculator 192-1 can be implemented to receive the first sub-data or the inverted first sub-data, and output the first CRC value corresponding to the first sub-data. The first DBI determiner 192-3 can be implemented to determine whether the data has been inverted based on the number of 1s in the first sub-data, and output the first DBI data. The first inverter INV1 can be implemented to invert the first sub-data based on the first DBI data.

[0080] In the example embodiment, the first sub-data can be 64 bits, the first DBI data can be 8 bits, and the first CRC value can be 8 bits. It should be understood that the number of bits in the first sub-data, the first DBI data, and the first CRC value is not limited to these.

[0081] The second CRC calculator 192-2 can be implemented to receive the second sub-data or the inverted second sub-data and output the second CRC value corresponding to the second sub-data. The second DBI determiner 192-4 can be implemented to determine whether the data has been inverted based on the number of 1s in the second sub-data and output the second DBI data. The second inverter INV2 can be implemented to invert the second sub-data based on the second DBI data.

[0082] In the example embodiment, the second sub-data can be 64 bits, the second DBI data can be 8 bits, and the second CRC value can be 8 bits. It should be understood that the number of bits in the second sub-data, the second DBI data, and the second CRC value is not limited to these.

[0083] Figure 6 This is a diagram illustrating the output timing of EDC data from the storage device 100 according to this example embodiment by way of example.

[0084] Reference Figure 6 Data / DBI data can be sent to the DQ and DBI pins within a predetermined time (e.g., 2CK). During the CRC delay, a CRC value can be calculated, and the calculated CRC value can be sent using a multi-level signaling transmission method. In an example embodiment, the CRC calculation operation can be performed within a predetermined clock cycle after the DQ data is output.

[0085] Figure 7 The diagram illustrates the transmitter 194 according to an example embodiment by way of example.

[0086] Reference Figure 7 The transmitter 194 may include an MSB driver (DRV) 194-1 and an LSB driver (DRV) 194-2.

[0087] The MSB driver 194-1 may include multiple pull-up transistors connected between the power supply terminal VDDQ and the input terminal D1, and multiple pull-down transistors connected between the input terminal D1 and the ground terminal GND. The MSB CRC value can be received at the input terminal D1.

[0088] The LSB driver 194-2 may include a pull-up transistor connected between the power supply terminal VDDQ and the input terminal D0, and a pull-down transistor connected between the input terminal D0 and the ground terminal GND. The LSB CRC value can be received at the input terminal D0.

[0089] It should be understood that, in combination Figure 7 The transmitter 194 described is just an example.

[0090] Figure 8 This is a diagram illustrating the CRC encoding method based on the data selection method according to an example embodiment.

[0091] Typically, in the case of CRC-8, the storage device calculates 72 bits of data in the CRC calculator and outputs 8 CRC bits. When the PAM4 method is applied, the input to the CRC calculator can be increased to 144 bits. By dividing the increased 144-bit input data in half and applying the half to two CRC calculators, the 8 CRC bits can be calculated separately. Furthermore, the calculation results can be separately applied to the MSB and LSB drivers of the PAM4 transmitter by concatenating the CRC sorting circuit and the MUX circuit in a predetermined manner. The PAM4 transmitter can generate and output a PAM4 signal by combining each CRC with either the MSB or LSB.

[0092] Use data selector 191 (see Figure 4 The MSB data of the read data can be mapped to a first sub-data, and the LSB data of the read data can be mapped to a second sub-data. In an example embodiment, the MSB / LSB data may include DQ data and DBI data.

[0093] During data reading, MSB and LSB data can be sent to CRC calculator 192-1 and CRC calculator 192-2 respectively (see...). Figure 4 ).

[0094] Each of CRC calculators 192-1 and 192-2 can calculate the CRC using an r-bit polynomial. The outputs of CRC calculators 192-1 and 192-2 can be serialized after being sorted according to the burst length BL. For example, the output of the first CRC calculator 192-1 can be connected to the MSB driver 194-1 of transmitter 194 (see...). Figure 7 Furthermore, the output of the second CRC calculator 192-2 can be connected to the LSB driver 194-2 of the transmitter 194.

[0095] Subsequently, transmitter 194 can transmit the outputs of CRC calculator 192-1 and CRC calculator 192-2 using a multi-level signaling method.

[0096] Controller 200 (see Figure 1 (or host) can detect errors by dividing the transmitted multilevel data into MSB / LSB and decoding the MSB / LSB data in reverse order.

[0097] Combination Figure 8 The described CRC encoding method is an example of a method of sending each of the MSB and LSB data to the corresponding CRC calculator, and the embodiments are not limited thereto.

[0098] Figure 9This is an example illustrating a CRC encoding method based on a data selection method according to another example embodiment.

[0099] Reference Figure 9 In the read data, data selector 191 can send the first half of the BL data to CRC calculator 192-1 and CRC calculator 192-2 (see...). Figure 4 Each of the BL data and the latter half of the BL data is sent to CRC calculator 192-1 and CRC calculator 192-2 (see CRC calculator 192-2). Figure 4 Each of them.

[0100] Each of CRC calculators 192-1 and CRC calculator 192-2 can use an r-bit polynomial to calculate the CRC.

[0101] CRC Selector 193 (see) Figure 4 The sorting can be performed to correspond to the first half of the four burst lengths BL0 to BL3 (i.e., the first half of the burst lengths BL0 to BL7). The output of the first CRC calculator 192-1 is connected to the transmitter 194 (see...). Figure 4 MSB driver 194-1 and LSB driver 194-2.

[0102] The CRC selector 193 can perform sorting to correspond to the four burst lengths BL4 to BL7 (i.e., the latter half of the burst lengths among the multiple burst lengths BL0 to BL7) and connect the output of the second CRC calculator 192-2 to the MSB driver 194-1 and LSB driver 194-2 of the transmitter 194.

[0103] Subsequently, transmitter 194 can transmit the outputs of CRC calculator 192-1 and CRC calculator 192-2 using a multi-level signaling method.

[0104] Controller 200 (see Figure 1 (or host) can detect errors by dividing the transmitted multilevel data into MSB / LSB and decoding the MSB / LSB in reverse order.

[0105] The storage device 100 according to this example embodiment can selectively run the CRC encoding method.

[0106] Figure 10 This is a diagram illustrating, by way of example, the output device of a data input / output device 190a according to another example embodiment.

[0107] Reference Figure 10 Combined with the above Figure 4 Compared to the description, the data input / output device 190a may also include a memory register 195.

[0108] Memory register 195 can store mode information used to determine the CRC encoding method of data selector 191, CRC generator 192, and CRC selector 193. Based on this CRC encoding mode information, it can be determined whether a combination of methods is used. Figure 8 The described CRC encoding method still uses a combination Figure 9 The CRC encoding method described.

[0109] Figures 1 to 10 CRC generation based on the PAM4 signaling method is described, but the embodiments are not limited thereto.

[0110] Figure 11 This is a diagram illustrating a data output device 300 according to an exemplary embodiment by way of example.

[0111] Reference Figure 11 The data output device 300 may include multiple CRC generators, such as first CRC generator 311 to fourth CRC generator 314, and may include sorting circuit 320 and output driver 330.

[0112] Each of the first CRC generator 311 to the fourth CRC generator 314 can be implemented to receive sub-data associated with the corresponding CRC bit and output the CRC value of the sub-data through a CRC polynomial.

[0113] The sorting circuit 320 can sort the output values ​​of the first CRC generator 311 to the fourth CRC generator 314, and can send the sorted output values ​​to the output driver 330.

[0114] The output driver 330 can be implemented to receive ordered output values ​​and transmit the received ordered output values ​​using a multilevel signaling method. In an example embodiment, the multilevel signaling can be 8 levels.

[0115] Figure 12 This is a flowchart illustrating, by way of example, a data output method of a storage device 100 according to an exemplary embodiment.

[0116] Reference Figure 12 The data output method of the storage device 100 can be executed as follows: Data read from the storage cell array MCA can be divided into multiple sub-data (S110). A CRC value for each sub-data segment can be calculated (S120). The calculated CRC values ​​can be sorted for multi-level transmission (S130). Data can be output along with the sorted CRC values ​​using a multi-level signaling method (S140).

[0117] In the example embodiment, the CRC encoding method can be determined based on the settings of the memory register. In the example embodiment, the multilevel signaling method can be a 4-level pulse amplitude modulation (PAM4) signaling method.

[0118] In an example embodiment, data can be divided into a first sub-data with MSB data corresponding to multiple burst lengths and a second sub-data with LSB data corresponding to multiple burst lengths, according to the CRC encoding method.

[0119] In an example embodiment, data can be divided into a first sub-data with MSB data and LSB data corresponding to a first burst length and a second sub-data with MSB data and LSB data corresponding to a second burst length, according to the CRC encoding method.

[0120] In the example embodiment, data, inverted data on the data bus, and CRC values ​​can be transmitted using a multi-level signaling method.

[0121] Figure 13 This is a diagram illustrating, by way of example, a data receiving method of controller 200 according to an example embodiment.

[0122] Reference Figure 13 The controller 200 can receive data in the following ways: Data can be received along with the CRC using the PAM4 signaling method (S210). The PAM4 CRC can be decoded using the NRZ signaling method (S220). The NRZ CRC can be divided in the same way as the encoding method (S230). The divided CRC value can be used to verify the integrity of the transmitted data (S240).

[0123] Figures 1 to 13 A multilevel signaling method is described. An example can be implemented by combining it with NRZ transmission signaling.

[0124] Figure 14A and Figure 14B This is a diagram illustrating a storage system based on the PAM4 and NRZ dual-mode approach, presented as an example.

[0125] Reference Figure 14A The storage system 20 may include a dual-mode transceiver (PAM4 / NRZ XCVR) for both DQ / DBI and EDC transmissions.

[0126] Reference Figure 14BThe storage system 30 may include a PAM4 / NRZ dual-mode transceiver (PAM4 / NRZ XCVR) for DQ / DBI transmission and an NRZ transceiver (NRZ XCVR) for EDC transmission. For EDC transmission, CRC values ​​can be calculated in parallel, and the NRZ transceiver (NRZ XCVR) can send the calculated CRC values ​​via the NRZ method.

[0127] Figure 15 This is a diagram illustrating, by way of example, a storage system performing at least one command / address calibration according to an example embodiment.

[0128] Reference Figure 15 The storage system 1000 may include a controller 1800 and a storage device 1900. The controller 1800 may include a clock generator 1801, a command / address (CA) generator 1802, a command / address reference generator 1803, a register 1804, a comparator 1806, a phase / timing controller 1808, a data input device 1810, and a data output device 1812.

[0129] The controller 1800 can provide the clock signal CK generated by the clock generator 1801 to the storage device 1900 via the clock signal line.

[0130] In an example embodiment, the storage system 1000 may separately include a command / address reference signal line CA_Ref in the interface. The command / address reference signal line CA_Ref can be used to send and receive a command / address reference signal as a reference value for the command / address in calibration mode.

[0131] The calibration result value using the command / address reference value can be provided to the phase / timing controller 1808 to adjust the phase / timing of the command / address signal CA. Because a separate command / address reference signal line (CA_Ref) exists, it has the advantage of performing the calibration operation to adjust the phase / timing of the command / address (CA) signal simultaneously with the operation of sending the command / address (CA) signal.

[0132] The CA generator 1802 can generate a phase- or timing-adjusted command / address signal CA in response to the control signal CTR of the phase / timing controller 1808, and send the generated command / address signal CA to the storage device 1900 via the CA bus.

[0133] Command / address reference generator 1803 can be configured in the same way as command / address generator 1802, and can generate the same first command / address reference signal CA_Refl as the command / address signal CA generated from command / address generator 1802.

[0134] The first command / address reference signal CA_Refl can be provided to register 1804. Furthermore, the first command / address reference signal CA_Refl can be sent to the CA reference bus via data output device 1812 and can be provided to storage device 1900 via the CA reference bus.

[0135] Register 1804 can store the first command / address reference signal CA_Ref1. Comparator 1806 can compare the first command / address reference signal CA_Ref1 stored in register 1804 with the third command / address reference signal CA_Ref3 output from data input device 1810. Comparator 1806 can generate a pass or fail signal P / F by comparing the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3.

[0136] The phase / timing controller 1808 can generate a control signal CTR that indicates the phase shift of the command / address signal CA based on the pass or failure signal P / F from the comparator 1806. The control signal CTR can generate a phase-adjusted command / address signal CA by adjusting the phase or timing of the command / address signal CA.

[0137] The data input device 1810 can receive the second command / address reference signal CA_Ref2 sent from the storage device 1900 via the CA reference bus, and send the received command / address reference signal CA_Ref2 as the third command / address reference signal CA_Ref3 to the comparator 1806.

[0138] The data output device 1812 can receive the first command / address reference signal CA_Refl generated by the command / address reference generator 1803, and send the received first command / address reference signal CA_Refl to the CA reference bus CA_Ref.

[0139] The storage device 1900 may include a clock buffer 1902, a command / address (CA) receiver 1904, a command / address reference receiver 1906, a data input device 1908, and a data output device 1910.

[0140] Clock buffer 1902 can generate an internal clock signal ICK by receiving a clock signal CK transmitted via a clock signal line. CA receiver 1904 can receive a chip select signal / CS, a clock enable signal CKE, and a command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK.

[0141] The clock enable signal CKE can be used as a pseudo command to read the command / address signal CA sent via the CA bus. When the clock enable signal CKE is activated, the CA receiver 1904 can receive the command / address signal CA.

[0142] Data input device 1908 can receive a first command / address reference signal CA_Ref1 transmitted via the CA reference bus from controller 1800, and can transmit the received first command / address reference signal CA_Ref1 to command / address reference receiver 1906. Command / address reference receiver 1906 can be configured in the same manner as CA receiver 1904. Command / address reference receiver 1906 can receive chip select signal / CS, clock enable signal CKE and first command / address reference signal CA_Ref1 transmitted via the CA reference bus in response to internal clock signal ICK, and can generate a second command / address reference signal CA_Ref2.

[0143] The second command / address reference signal CA_Ref2 can be the same as the signal output from the CA receiver 1904, wherein the CA receiver 1904 receives the chip select signal / CS, the clock enable signal CKE, and the command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK. The second command / address reference signal CA_Ref2 can be sent to the CA reference bus via the data output device 1910.

[0144] The CA calibration performed in the storage system 1000 can be as follows. The CA generator 1802 of the controller 1800 can generate a phase- or timing-adjusted command / address signal CA in response to the control signal CTR of the phase / timing controller 1808, and can send the generated command / address signal CA to the storage device 1900 via the CA bus. The command / address reference generator 1803 can generate a first command / address reference signal CA_Ref1 identical to the command / address signal CA, and can send the generated first command / address reference signal CA_Ref1 to the CA reference bus.

[0145] The CA reference receiver 1906 of the storage device 1900 can receive the first command / address reference signal CA_Ref1 according to the internal clock signal ICK and the clock enable signal CKE, and can generate a second command / address reference signal CA_Ref2. The second command / address reference signal CA_Ref2 of the storage device 1900 can be sent to the CA reference bus.

[0146] The controller 1800 can send the second command / address reference signal CA_Ref2, transmitted via the CA reference bus, as the third command / address reference signal CA_Ref3 to the comparator 1806. The comparator 1806 can generate a pass or fail signal P / F by comparing the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3. The phase / timing controller 1808 can generate a control signal CTR indicating the phase shift of the command / address signal CA based on the pass or fail signal P / F from the comparator 1806. The CA generator 1802 can generate a phase-adjusted command / address signal CA based on the control signal CTR.

[0147] By repeating this CA calibration operation, the phase / timing controller 1808 of the controller 1800 can determine the middle of the passed (P) positions as the middle of the command / address signal CA window, and generate a command / address signal CA such that the middle of the command / address signal (CA) window reaches the edge of the clock signal (CK), and provide the generated command / address signal CA to the storage device 1900. Therefore, the storage device 1900 can receive the command / address signal CA at the rising / falling edge of the clock signal CK, in which the middle of the effective window of the command / address signal CA is located at the rising / falling edge of the clock signal pair CK and CKB.

[0148] The storage system 1000 according to this example embodiment may include in each of the controller 1800 and the storage device 1900. Figures 1 to 14B The dual-mode transceivers 1820 and 1920 are described in the document.

[0149] In the example embodiment, each of the dual-mode transceivers 1820 and 1920 can select NRZ mode or PAM4 mode in real time via multiple data channels (DQ) and transmit data in the selected mode.

[0150] The storage device according to the example embodiment can be applied to a computing system.

[0151] Figure 16 The diagram illustrates a computing system 3000 according to an example embodiment by way of example.

[0152] Reference Figure 16 The computing system 3000 includes at least one volatile memory module (DIMM) 3100, at least one non-volatile memory module (NVDIMM) 3200, and at least one processor (e.g., central processing unit, CPU) 3300.

[0153] The computing system 3000 can be implemented as a computer, portable computer, ultra-mobile PC (UMPC), workstation, data server, netbook, personal digital assistant (PDA), tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), digital camera, digital recorder / player, digital camera / video recorder / player, portable game console, navigation system, block box, wearable device, 3D TV, device for receiving and transmitting information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, radio frequency identification (RFID), or one of the various electronic devices constituting a computing system.

[0154] At least one non-volatile memory module 3200 may include at least one non-volatile memory. In an example embodiment, the at least one non-volatile memory may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), thyristor random access memory (TRAM), etc.

[0155] In an example embodiment, at least one of the volatile storage module 3100 and the non-volatile storage module 3200 may include transmitting using a multi-level signaling method. Figures 1 to 14B The CRC value described in the document is used to perform data communication with the processor 3300 via the interface circuit IF.

[0156] In an example embodiment, the volatile memory module 3100 and the non-volatile memory module 3200 can be connected to the processor 3300 via a DDRx interface (x is an integer greater than or equal to 1).

[0157] At least one processor 3300 may be implemented to control the volatile memory module 3100 and the non-volatile memory module 3200. In an example embodiment, the processor 3300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0158] The method for changing the transmission signaling mode according to the example embodiment can be performed inside the stacked memory package chip.

[0159] Figure 17 The diagram illustrates a computing system 4000 according to another example embodiment by way of example.

[0160] Reference Figure 17The computing system 4000 may include a host processor 4100 and at least one memory package chip 4210 controlled by the host processor 4100.

[0161] In an example embodiment, the host processor 4100 and the memory package chip 4210 can send and receive data via channel 4001.

[0162] The memory package chip 4210 can be a stacked memory package chip that includes stacked memory chips and a controller chip. (See reference...) Figure 17 The memory package chip 4210 may include multiple DRAM chips formed on the DRAM controller chip. It should be understood that the configuration of the memory package chip is not limited to this.

[0163] In an example embodiment, the signaling transmitted between the stacked memory chips of the memory package chip 4210 and the controller chip can calculate the CRC by mapping cell data to the input of a parallel CRC calculator according to the settings of the memory registers, and can be combined as follows: Figures 1 to 14A The described method sorts the output of a parallel CRC calculator and sends the sorted output using a multi-level signaling method.

[0164] The data communication method according to the example embodiment can be applied to a data center.

[0165] Figure 18 This is a diagram illustrating a data center using a storage device according to an example embodiment.

[0166] Reference Figure 18 Data center 7000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 7000 can be a system for operating search engines and databases, and can be a computing system used by companies such as banks or government agencies. Data center 7000 can include application servers 7100 to 7100n and storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can be selected differently according to example embodiments, and the number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can be different.

[0167] Application server 7100 or storage server 7200 may include at least one of processors (e.g., CPU) 7110 and 7210 and memory (MEM) 7120 and 7220.

[0168] The storage server 7200 is described by way of example. The processor 7210 can control the overall operation of the storage server 7200 and access the memory 7220 to execute commands or data loaded in the memory 7220. The memory 7220 can be Double Data Rate Synchronous DRAM (DDR SDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Module (DIMM), Optane DIMM, or Non-Volatile DIMM (NVMDIMM). According to the example embodiment, the number of processors 7210 and the number of memories 7220 included in the storage server 7200 can be selected differently.

[0169] In an example embodiment, processor 7210 and memory 7220 may provide a processor-memory pair. In an example embodiment, the number of processors 7210 and the number of memories 7220 may differ from each other. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to an example embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one storage device 7250. Storage device 7250 may be as described in... Figures 1 to 17 The description states that DQ / DBI data and EDC data are sent according to the transmission signaling.

[0170] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC), Ethernet, etc. FC can be a medium for relatively high-speed data transmission and can use optical switches that provide high performance / high availability. Depending on the access method of network 7300, storage servers 7200 to 7200m can be configured as file storage, block storage, or object storage.

[0171] In an example embodiment, network 7300 can be a storage-only network such as a Storage Area Network (SAN). For example, the SAN can be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN can be an IP-SAN implemented using a TCP / IP network and according to SCSI over TCP / IP or Internet SCSI (iSCSI) protocols. In another example embodiment, network 7300 can be a general-purpose network such as a TCP / IP network. For example, network 7300 can be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or NVMe over Fabrics (NVMe-oF).

[0172] The following description will focus on application server 7100 and storage server 7200. The description of application server 7100 can be applied to other application servers 7100n, and the description of storage server 7200 can be applied to other storage servers 7200m.

[0173] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server, database management system (DBMS), etc.

[0174] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Application server 7100 can perform various operations on data stored in application servers 7100 to 7100n or storage servers 7200 to 7200m. For example, application server 7100 can execute commands for moving or copying data between application servers 7100 to 7100n or storage servers 7200 to 7200m. In this scenario, data can be moved from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7120 to 7120n of application servers 7100 to 7100n via storage devices 7220 to 7220m of storage servers 7200 to 7200m, or directly from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7120 to 7120n of application servers 7100 to 7100n. Data moved via network 7300 can be encrypted data for security or privacy purposes.

[0175] The storage server 7200 is further described by way of example. Interface NIC 7254 provides physical connectivity between processor 7210 and controller (CTRL) 7251, and between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using a direct-attach storage (DAS) method, in which storage device 7250 is directly connected using a dedicated cable. As another example, interface 7254 can be implemented using various interface methods such as: Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), Fast PCI (PCIe), Fast NVM (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), and Compact Flash Memory (CF) card interface.

[0176] The storage server 7200 may also include a switch 7230 and a NIC 7240. The switch 7230 can selectively connect the processor 7210 and the storage device 7250 under the control of the processor 7210, or selectively connect the NIC 7240 and the storage device 7250.

[0177] In an example embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and can be connected to processor 7210 or switch 7230 via the host bus interface. The host bus interface can be implemented as one of the examples of interface 7254 described above. In an example embodiment, NIC 7240 can be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0178] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send commands to storage devices 7130 to 7130n and 7250 to 7250m or memories 7120 to 7120n and 7220 to 7220m to program or read data. In this case, the data can be data corrected via an error-correcting code (ECC) engine. The data can be data processed via data bus inversion (DBI) or data masking (DM) and can include cyclic redundancy check (CRC) information. The data can be encrypted data for security or privacy purposes.

[0179] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, the read enable (RE) signal can be input as a data output control signal, and data can be output to the DQ bus. A data strobe signal (DQS) can be generated using the RE signal. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0180] Controller 7251 can control the overall operation of storage device 7250. In an example embodiment, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory device 7252 in response to a write command, or can read data from NAND flash memory device 7252 in response to a read command. For example, write or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 can temporarily store (buffer) data to be written to or read from NAND flash memory device 7252. DRAM 7253 can store metadata. Metadata may be user data or data generated by controller 7251 for managing NAND flash memory device 7252. Storage device 7250 may include a security element (SE) for security or privacy.

[0181] As described above, the storage device (e.g., DRAM) according to the example embodiment can divide cell data into a data selector according to the setting value of the memory register, map the divided cell data to the input of the sub-CRC calculator, and calculate the CRC in parallel.

[0182] In an example embodiment, the storage device can map the output of the parallel CRC calculator to the PAM4 transmitter according to the settings of the memory register, and can generate the mapped output as a PAM4CRC. In an example embodiment, the output of the first sub-block can be used as the MSB of the PAM4 Tx pre-driver, and the output of the second sub-block can be used as the LSB of the PAM4 Tx pre-driver (MSB / LSB partitioning method).

[0183] In the example embodiment, a mapping can be performed such that the CRC result of the first half of the BL data is sent first, and then the CRC result of the second half of the BL data is sent to the PAM4 output. Therefore, the system can start CRC decoding 2 CLK earlier than the MSB / LSB partitioning method described above.

[0184] The CRC encoding method and system for error checking of multilevel data (PAM4) according to the example embodiment may include a CRC calculator, a CRC MUX including a CRC sorting circuit, and a PAM4 transmitter, and can maintain the error checking rate by using the same polynomial while having the same CRC calculation speed, even as the number of data bits increases.

[0185] After calculating the CRC using the formula based on the data and the polynomial, the presence or absence of an error can be checked. In this case, when using a multi-level I / O interface, the number of data bits may increase compared to binary data, and consequently, the CRC calculation time may increase.

[0186] According to the example embodiment, the storage device, the data output method of the storage device, and the storage system having the storage device can use a CRC calculator that receives parallel data and has the same delay arranged in parallel, and the output of the parallel CRC calculator can be multiplexed with PAM4 Tx to output dual CRC codes simultaneously.

[0187] According to the example embodiment, the storage device, the data output method of the storage device, and the storage system having the storage device can divide data into sub-data, calculate the CRC value corresponding to the divided sub-data, sort the calculated CRC values, and send the sorted calculated CRC values ​​using a multi-level signaling method. This can reduce the delay of CRC encoding while maintaining the code rate and maximizing system performance.

[0188] By summarizing and reviewing, signal modulation methods based on non-return-to-zero (NRZ) coding may be difficult to implement under conditions of high data capacity and high-speed data transmission. The 4-level pulse amplitude modulation (PAM4) method can be used as a signal modulation method for large-capacity and high-speed data transmission.

[0189] As described above, the example embodiments provide a storage device that maintains the code rate while reducing CRC latency when transmitting multi-level data, a data output method for the storage device, and a storage system having the storage device.

[0190] Example embodiments have been disclosed herein, and while specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, unless specifically indicated otherwise, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A storage device, comprising: Storage cell array; A data selector configured to receive data from the storage cell array, divide the received data into a first sub-data and a second sub-data, and output the first sub-data and the second sub-data; A CRC generator, configured to generate a first CRC value corresponding to the first sub-data and a second CRC value corresponding to the second sub-data, wherein CRC stands for Cyclic Redundancy Check. A CRC selector, configured to determine the order of the first CRC value and the second CRC value, and output the first CRC value and the second CRC value according to the determined order; and A transmitter configured to receive the first CRC value and the second CRC value in a determined order, and to transmit the ordered first CRC value and the second CRC value via a multi-level signaling method. The CRC generator performs calculations for generating the first CRC value and the second CRC value in parallel.

2. The storage device according to claim 1, wherein: The first sub-data is MSB data corresponding to multiple burst lengths, where MSB is the most significant bit, and The second sub-data is LSB data corresponding to the multiple burst lengths, where LSB is the least significant bit.

3. The storage device according to claim 1, wherein: The first sub-data includes MSB data and LSB data corresponding to the first half of the burst length in a plurality of burst lengths, wherein the MSB is the most significant bit and the LSB is the least significant bit. The second sub-data includes MSB data and LSB data corresponding to the second half of the burst length among the plurality of burst lengths.

4. The storage device according to claim 1, wherein, The CRC generator includes: A first CRC calculator, configured to receive one of the first sub-data and the inverted first sub-data, and calculate the first CRC value; and A second CRC calculator is configured to receive one of the second sub-data and the inverted second sub-data, and to calculate the second CRC value.

5. The storage device according to claim 4, wherein, The CRC generator also includes: A first DBI determiner is configured to determine whether a data bus inversion has occurred based on the first sub-data and generate first DBI data, where DBI stands for data bus inversion. A first inverter, configured to invert the first sub-data according to the first DBI data; A second DBI determiner, configured to determine whether the data bus inversion has occurred based on the second sub-data, and generate second DBI data; and A second inverter is configured to invert the second sub-data based on the second DBI data.

6. The storage device according to claim 1, wherein, The CRC selector includes a CRC sorting circuit that determines the order of the first CRC value and the second CRC value.

7. The storage device according to claim 1, wherein, The transmitter includes: The MSB driver is configured to receive the first CRC value and send the corresponding MSB (most significant bit) to the EDC pin; and the EDC (Error Detection and Verification) pin is configured to receive the first CRC value and send the corresponding MSB to the EDC pin. The LSB driver is configured to receive the second CRC value and send the corresponding LSB to the EDC pin, where the LSB is the least significant bit.

8. The storage device according to claim 7, wherein, The MSB driver includes: Multiple pull-up transistors are connected between the power supply terminal and the EDC pin; and Multiple pull-down transistors are connected between the EDC pin and the ground terminal.

9. The storage device according to claim 8, wherein, The LSB driver includes: A pull-up transistor is connected between the power supply terminal and the EDC pin; and A pull-down transistor is connected between the EDC pin and the ground terminal.

10. The storage device according to claim 1, further comprising: A memory register configured to store mode information for setting the CRC encoding mode of the data selector, the CRC generator, and the CRC selector.

11. A storage device comprising: Storage cell array; Multiple transceivers are configured to transmit / receive data from the memory cell array via data lines using a multi-level signaling method; DBI transceiver, the DBI transceiver being configured to transmit / receive DBI data via the data bus inverting line through the multi-level signaling method, wherein DBI is the data bus inverting line; as well as A CRC transceiver, configured to send / receive the CRC value of the data via an error detection check line using the multi-level signaling method, wherein CRC stands for Cyclic Redundancy Check, and: The storage device is configured to divide the data into multiple sub-data, generate multiple CRC values, and sort the CRC values, each CRC value corresponding to a specific sub-data within the multiple sub-data. The calculation of generating the multiple CRC values ​​corresponding to the multiple sub-data is performed in parallel. The CRC transceiver includes a transmitter configured to transmit sorted CRC values ​​via the multi-level signaling method.

12. The storage device according to claim 11, wherein, The multilevel signaling method is the PAM4 signaling method, where PAM4 is 4-level pulse amplitude modulation.

13. The storage device according to claim 11, further comprising an output device, wherein, The output device performs the following actions: dividing the data into the plurality of sub-data, generating the CRC value, and sorting the CRC value.

14. The storage device according to claim 13, wherein, The output device includes: Multiple CRC generators, configured to generate the CRC value corresponding to the multiple sub-data respectively; and A sorting circuit configured to sort the CRC values ​​output from the plurality of CRC generators.

15. The storage device according to claim 14, wherein, At least one of the plurality of transceivers, the DBI transceiver, and the CRC transceiver is implemented by dual-mode signaling that selectively operates with non-return-to-zero signaling or PAM4 signaling.

16. A method for outputting data from a storage device including an array of storage cells, the method comprising: The data read from the storage unit array is divided into multiple sub-data; Multiple CRC values ​​corresponding to the multiple sub-data are calculated in parallel, where CRC stands for Cyclic Redundancy Check. Sort the calculated CRC values; and The sorted CRC values ​​are sent together with the data using a multi-level signaling method.

17. The method according to claim 16, further comprising: The CRC encoding method is determined based on the settings of the memory registers included in the storage device.

18. The method of claim 17, wherein: The multi-level signaling method is a 4-level pulse amplitude modulation signaling method, and The step of dividing the data read from the storage cell array into multiple sub-data includes dividing the data into a first sub-data having the most significant bit data corresponding to multiple burst lengths and a second sub-data having the least significant bit data corresponding to the multiple burst lengths, according to the CRC encoding method.

19. The method of claim 17, wherein: The multi-level signaling method is a 4-level pulse amplitude modulation signaling method, and The step of dividing the data read from the storage cell array into multiple sub-data includes dividing the data into a first sub-data with MSB data and LSB data corresponding to the first half of the burst length in the multiple burst lengths, and a second sub-data with MSB data and LSB data corresponding to the second half of the burst length in the multiple burst lengths, according to the CRC encoding method. The MSB is the most significant bit, and the LSB is the least significant bit.

20. The method of claim 16, wherein, The sending includes: The data is transmitted using the multi-level signaling method. The data bus inverted data corresponding to the data is transmitted through the multi-level signaling method; and The sorted CRC values ​​are sent using the multi-level signaling method.

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