Memory module, semiconductor memory device and memory system including the same

Abstract

A memory module and a semiconductor memory device and a memory system including the same are disclosed. The memory module can include J memory chips that input / output data in response to each of a plurality of converted address signals, and an address remapping circuit that generates a plurality of preliminary converted address signals by adding a first correction value to a target address signal provided from an outside of the memory module, and generates the plurality of converted address signals by shifting all bits of each of the plurality of preliminary converted address signals such that K bit positions included in a bit string of each of the plurality of preliminary converted address signals are moved to other bit positions of each bit string.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 124,245, filed December 11, 2020, and Korean Patent Application No. 10-2021-0142969, filed October 25, 2021, with the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference. Technical Field

[0003] Various embodiments generally relate to semiconductor devices, and more particularly to semiconductor memory devices, memory modules, and memory systems including memory modules. Background Technology

[0004] For example, semiconductor devices such as volatile memory devices (e.g., dynamic random access memory (DRAM)) determine data based on the charge stored in capacitors. However, because the charge stored in capacitors can leak out in various forms over time, volatile memory devices periodically perform refresh operations. As the manufacturing processes for memory devices miniaturize and the spacing between word lines gradually narrows, the impact of voltage distribution on the charge of memory cells connected to adjacent word lines increases. Furthermore, when a word line is accessed in a concentrated manner, data loss occurs due to the row hammer phenomenon, where data stored in memory cells connected to adjacent word lines is lost when the voltage of a word line is active.

[0005] Figure 1 This diagram is used to explain the row hammer phenomenon in a typical semiconductor memory module.

[0006] Figure 1A memory module comprising multiple memory chips CHIP0 to CHIPn-1 is shown. Each of the multiple memory chips CHIP0 to CHIPn-1 includes multiple row lines, for example, multiple word lines ROW0 to ROWk+1. Based on a row address signal provided externally to the memory module, a word line (e.g., ROW1) with substantially the same index is selected from each of the multiple memory chips CHIP0 to CHIPn-1. Repeatedly accessing word line ROW1 of the multiple memory chips CHIP0 to CHIPn-1 causes a row hammer phenomenon, in which the charge of memory cells connected to adjacent word lines ROW0 and ROW2 is affected. The currently accessed word line can be referred to as the attacker row. The word line attacked by the attacked row (i.e., the word line physically adjacent to the attacker row and losing data due to the activation of the attacker row) can be referred to as the victim row. In the example above, word line ROW1 is the attacker row, and word lines ROW0 and ROW2 adjacent to word line ROW1 are the victim rows. In this scenario, for ease of description, we assume that the victim line consists of two word lines adjacent to the attacker line, but the number of victim lines increases as the distance between word lines decreases. Summary of the Invention

[0007] A memory module according to an embodiment of the present disclosure may include: J memory chips that input / output data in response to each of a plurality of translation address signals; and an address remapping circuit that: generates a plurality of preliminary translation address signals by adding a first correction value to a target address signal provided from outside the memory module; and generates a plurality of translation address signals by shifting all bits of each of the plurality of preliminary translation address signals such that K bits in a bit string included in each of the plurality of preliminary translation address signals are moved to other positions in each bit string.

[0008] A memory module according to an embodiment of the present disclosure may include: J memory chips, each memory chip including a plurality of cell memory regions, and inputting / outputting data by accessing a cell memory region having a non-overlapping sequence number among the plurality of cell memory regions in response to each of a plurality of translation address signals; and an address remapping circuit that: generates a plurality of preliminary translation address signals by adding a first correction value to a row address signal included in a target address signal provided from outside the memory module; shifts all bits of each of the plurality of preliminary translation address signals such that K bits in the bit string included in each of the plurality of preliminary translation address signals are moved to other positions in each bit string; and generates a plurality of translation address signals by adding a second correction value to a cell region address included in the target address signal.

[0009] A memory system according to an embodiment of the present disclosure may include: a memory controller that generates a plurality of preliminary translation address signals by adding a correction value to a target address signal; and generates the plurality of translation address signals by shifting all bits of each of the plurality of preliminary translation address signals such that K bits in a bit string including each of the plurality of preliminary translation address signals are moved to other positions in each bit string; and a memory module including J memory chips, the memory module receiving the plurality of translation address signals and configured such that the J memory chips perform data input / output with the memory controller in response to each of the plurality of translation address signals.

[0010] A memory system according to an embodiment of the present disclosure may include: a memory controller that: generates a plurality of preliminary translation address signals by adding a first correction value to a row address signal included in a target address signal; shifts all bits of each of the plurality of preliminary translation address signals such that K bits in a bit string included in each of the plurality of preliminary translation address signals are moved to other positions in each bit string; and generates the plurality of translation address signals by adding a second correction value to a cell region address included in the target address signal; and a memory module including J memory chips, each memory chip including a plurality of cell memory regions, and the memory module being configured such that: the J memory chips, in response to each of the plurality of translation address signals, perform data input / output with the memory controller by accessing cell memory regions having non-overlapping sequence numbers among the plurality of cell memory regions.

[0011] A semiconductor memory device according to an embodiment of the present disclosure may include: a memory region including J cell memory regions; a control circuit that: generates a plurality of translated address signals by remapping a target address signal provided from outside the memory module; and outputs any one of the plurality of translated address signals corresponding to a cell region address included in the target address signal; and an address decoder that: decodes any one of the translated address signals; and accesses the memory region based on the decoding result. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating the row access method of a typical semiconductor memory module.

[0013] Figure 2 This is a diagram illustrating the configuration of a memory system 10 according to an embodiment of the present disclosure.

[0014] Figure 3 This is a diagram illustrating the configuration of a memory chip 100-1 according to an embodiment of the present disclosure.

[0015] Figure 4This is a diagram illustrating an example of an address remapping method according to an embodiment of the present disclosure.

[0016] Figure 5 This is a diagram illustrating an access method for a memory module 12 according to an embodiment of the present disclosure.

[0017] Figure 6 This is a diagram illustrating the configuration of a memory system 20 according to another embodiment of the present disclosure.

[0018] Figure 7 This is a diagram illustrating an access method for a memory module 22 according to another embodiment of the present disclosure.

[0019] Figure 8 This is a diagram illustrating the configuration of a memory system 30 according to yet another embodiment of the present disclosure.

[0020] Figure 9 This is a diagram illustrating the configuration of a memory system 40 according to yet another embodiment of the present disclosure.

[0021] Figure 10 This is a diagram illustrating the configuration of a memory chip 500 according to an embodiment of the present disclosure. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0023] Various embodiments relate to providing a semiconductor memory device, memory module, and memory system including the memory module that can minimize data loss caused by row hammer. Data loss caused by row hammer occurs when the voltage of a word line is active, data stored in memory cells connected to adjacent word lines is lost.

[0024] In some embodiments, data loss caused by row hammers is minimized.

[0025] Figure 2 This is a diagram illustrating the configuration of a memory system 10 according to an embodiment of the present disclosure.

[0026] Reference Figure 2 The memory system 10 may include a memory controller 11 and a memory module 12.

[0027] The memory controller 11 can provide the memory module 12 with a command signal CMD and a target address signal ADDR. The memory controller 11 can generate the target address signal ADDR by mapping physical address signals provided from an external host (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) into a form suitable for memory access. The target address signal ADDR may include address signals (e.g., row address signals, column address signals, and bank address signals) for selecting row lines, column lines, and cell memory blocks of the semiconductor memory.

[0028] Memory module 12 may be a dual in-line memory module (hereinafter referred to as DIMM) or a memory module having a 3D structure in which memory dies are stacked. Memory module 12 may perform input / output of data DQ with memory controller 11 in response to command signal CMD and target address signal ADDR. Memory module 12 may include multiple memory chips (CHIP0 to CHIPn-1) 100-1 to 100-n and address remapping circuitry 110. Memory module 12 may access multiple memory chips 100-1 to 100-n according to multiple translation address signals ADDRMF<0:n-1> generated by remapping the row address signal included in the target address signal ADDR. Multiple translation address signals ADDRMF<0:n-1> can have values ​​satisfying a first condition and a second condition, wherein the first condition is that the accessed row lines (e.g., word lines) in each of the multiple memory chips 100-1 to 100-n do not overlap with each other, and the second condition is that the victim row number among the accessed row lines in each of the multiple memory chips 100-1 to 100-n does not overlap with the victim row number of a neighboring memory chip. The multiple translation address signals ADDRMF<0:n-1> can include address signals generated by remapping the row address signals, column address signals, and bank address signals included in the target address signal ADDR.

[0029] Multiple memory chips 100-1 to 100-n can have substantially the same configuration. Multiple memory chips 100-1 to 100-n can be configured to access corresponding row lines in response to multiple translation address signals ADDRMF<0:n-1>.

[0030] Address remapping circuit 110 may include remapping logic for remapping a target address signal ADDR such that the target address signal ADDR satisfies a first condition and a second condition. In one embodiment, address remapping circuit 110 may receive the target address signal ADDR from outside the memory module 12. In one embodiment, address remapping circuit 110 may receive the target address signal ADDR from outside the memory module 12 and from, for example (but not limited to), a memory controller 11. (Refer to...) Figure 4 and Figure 5 Describe the operation method of address remapping circuit 110.

[0031] Figure 3 This is a diagram illustrating the configuration of a memory chip 100-1 according to an embodiment of the present disclosure.

[0032] Reference Figure 3 According to an embodiment of the present disclosure, the memory chip 100-1 may include a memory region 101, an address decoder 102, a pin array 103, a data input / output circuit 104, and a control circuit 105.

[0033] Memory region 101 may include multiple memory cells, and these memory cells may include at least one of volatile memory and non-volatile memory. Examples of volatile memory may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM), and examples of non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc. During a read operation of memory chip 100-1, data stored in memory region 101 is output, and during a write operation of memory chip 100-1, data input from memory controller 11 may be stored in memory region 101. The memory cells of memory region 101 may be divided into multiple cell memory regions, for example, multiple memory banks BK0 to BKn-1.

[0034] Address decoder 102 can be connected to control circuit 105 and memory region 101. Address decoder 102 can decode address signals provided from control circuit 105 and access memory region 101 based on the decoding result.

[0035] Pin array 103 may include command and address integrated pin (CA) 103-1. Command signal CMD and translation address signal ADDRMF0 may be sequentially input via command and address integrated pin (CA) 103-1 at predetermined timings. The term "predetermined" (such as "predetermined timing") as used herein with respect to parameters means that the value of the parameter is determined before it is used in the processing or algorithm. In some embodiments, the value of the parameter is determined before the processing or algorithm begins. In other embodiments, the value of the parameter is determined during the processing or algorithm, but before it is used in the processing or algorithm.

[0036] Data input / output circuitry 104 can be connected to memory region 101. Data input / output circuitry 104 can exchange data with memory controller 11 or memory region 101. Data input / output circuitry 104 may include data input buffers, data output buffers, data input / output pads, etc.

[0037] Control circuit 105 can be connected to memory region 101, address decoder 102, and data input / output circuit 104. Control circuit 105 can perform control operations related to read operations, write operations, and address processing of memory chip 100-1. Control circuit 105 can receive command signal CMD and translation address signal ADDRMF0 via command and address integrated pin (CA) 103-1.

[0038] Figure 4 This is a diagram illustrating an example of an address remapping method according to an embodiment of the present disclosure.

[0039] The address remapping circuit 110 can generate multiple translation address signals ADDRMF<0:n-1> by performing address remapping on the target address signal ADDR through a first address translation operation based on a first condition and a second address translation operation based on a second condition. The first condition is that the row numbers accessed by the multiple translation address signals ADDRMF<0:n-1> in each of the multiple memory chips 100-1 to 100-n do not overlap with each other. The second condition is that the row number of the victim row in each of the multiple memory chips 100-1 to 100-n accessed by the multiple translation address signals ADDRMF<0:n-1> does not overlap with the row number of the victim row in a neighboring memory chip.

[0040] The address remapping circuit 110 can perform a first address translation operation on the row address signal ADDR_R included in the target address signal ADDR, such that the target address signal ADDR satisfies a first condition. As one method for satisfying the first condition, the address remapping circuit 110 can perform the first address translation operation by adding a first correction value (e.g., corresponding to numbers 0 to n-1 of the plurality of memory chips 100-1 to 100-n) to the row address signal ADDR_R one by one. The address signal generated according to the first address translation operation is called a plurality of preliminary translation address signals ADDRMF<0:n-1>_PRE. As one method for satisfying a second condition, the address remapping circuit 110 can perform a second address translation operation, which shifts all bits of each of the plurality of preliminary translation address signals ADDRMF<0:n-1>_PRE, such that "K" least significant bits (LSBs) are moved to the position of the most significant bit (MSB). The address signal generated according to the second address translation operation is called a plurality of translation address signals ADDRMF<0:n-1>.

[0041] In this case, "K" can be determined using Log2[Max(I,J)]. "I" is a value set to ensure the reliability of memory chip access operations, and can be, for example, the distance affected by row hammer attacks, i.e., the total number of victim rows adjacent to the attacker's row. "J" is the number of memory chips in the memory module.

[0042] Figure 4 This example illustrates the address remapping method when I=6, J=8, and the row address signal ADDR_R has a value of "4246(001000010010110)". See also... Figure 4 By performing a first address translation operation that adds each of the first correction values ​​0 to 7 to the row address signal ADDR_R, multiple preliminary translation address signals ADDRMF<0:n-1>_PRE can have different values.

[0043] The initial translation address signal ADDRMF0_PRE corresponding to the first memory chip 100-1 can be converted to "4246(001000010010110)" by adding "0" to "4246(001000010010110)". The initial translation address signal ADDRMF1_PRE corresponding to the second memory chip 100-2 can be converted to "4247(001000010010111)" by adding "1" to "4246(001000010010110)". The initial translation address signal ADDRMF2_PRE corresponding to the third memory chip 100-3 can be converted to "4248(001000010011000)" by adding "2" to "4246(001000010010110)". The initial translation address signal ADDRMF3_PRE corresponding to the fourth memory chip 100-4 can be converted to "4249(001000010011001)" by adding "3" to "4246(001000010010110)". The initial translation address signal ADDRMF4_PRE corresponding to the fifth memory chip 100-5 can be converted to "4250(001000010011010)" by adding "4" to "4246(001000010010110)". The initial translation address signal ADDRMF5_PRE corresponding to the sixth memory chip 100-6 can be converted to "4251(001000010011011)" by adding "5" to "4246(001000010010110)". The initial translation address signal ADDRMF6_PRE corresponding to the seventh memory chip 100-7 can be converted to "4252(001000010011100)" by adding "6" to "4246(001000010010110)". The initial translation address signal ADDRMF7_PRE corresponding to the eighth memory chip 100-8 can be converted to "4253(001000010011101)" by adding "7" to "4246(001000010010110)".

[0044] Since K = Log2[Max(6,8)] = Log2[8] = 3 for multiple initial address translation signals ADDRMF<0:n-1>_PRE, a second address translation operation is performed to shift the three LSBs to the MSB position, thereby essentially preventing the victim row number in the row accessed by multiple address translation signals ADDRMF<0:7> from overlapping with the adjacent memory chip.

[0045] By shifting the three LSB bits of “4246(001000010010110)” to three MSB bits, the conversion address signal ADDRMF0 corresponding to the first memory chip 100-1 can be converted to “25106(110001000010010)”. By shifting the three LSB bits of “4247(001000010010111)” to three MSB bits, the conversion address signal ADDRMF1 corresponding to the second memory chip 100-2 can be converted to “29202(111001000010010)”. By shifting the three LSB bits of “4248(001000010011000)” to three MSB bits, the conversion address signal ADDRMF2 corresponding to the third memory chip 100-3 can be converted to “531(000001000010011)”. By shifting the three LSB bits of “4249(001000010011001)” to three MSB bits, the conversion address signal ADDRMF3 corresponding to the fourth memory chip 100-4 can be converted to “4627(001001000010011)”. By shifting the three LSB bits of “4250(001000010011010)” to three MSB bits, the conversion address signal ADDRMF4 corresponding to the fifth memory chip 100-5 can be converted to “8723(010001000010011)”. By shifting the three LSB bits of “4251(001000010011011)” to three MSB bits, the conversion address signal ADDRMF5 corresponding to the sixth memory chip 100-6 can be converted to “12819(011001000010011)”. By shifting the three LSB bits of “4252(001000010011100)” to three MSB bits, the conversion address signal ADDRMF6 corresponding to the seventh memory chip 100-7 can be converted to “16915(100001000010011)”. By shifting the three LSB bits of “4253(001000010011101)” to three MSB bits, the conversion address signal ADDRMF7 corresponding to the eighth memory chip 100-8 can be converted to “21011(101001000010011)”.

[0046] Although for ease of description, Figure 4 Only the address bits corresponding to the row address signal ADDR_R are shown, but the multiple preliminary translation address signals ADDRMF<0:n-1>_PRE and / or multiple translation address signals ADDRMF<0:n-1> may also include column address signals and memory bank address signals.

[0047] Figure 5 This is a diagram illustrating an access method for a memory module 12 according to an embodiment of the present disclosure.

[0048] In the memory module 12, among the multiple memory chips 100-1 to 100-n, row lines of cell memory blocks with substantially the same serial number can be generated by an execution such as Figure 4 The address remapping operation shown uses the address remapping circuit 110 to generate multiple conversion address signals ADDRMF<0:n-1> for access.

[0049] Figure 5 An example of an access method is shown when the number of multiple memory chips 100-1 to 100-n is 8.

[0050] Reference Figure 5 In the first memory chip 100-1, row line ROWk+1 of the first memory bank BK0 can be accessed by the address translation signal ADDRMF0. The attacker's row can be ROWk+1, and the victim's row can be ROWk. In the second memory chip 100-2, row line ROW2 of the first memory bank BK0 can be accessed by the address translation signal ADDRMF1. The attacker's row can be ROW2, and the victim's rows can be ROW1 and ROW3. In the third memory chip 100-3, row line ROWk of the first memory bank BK0 can be accessed by the address translation signal ADDRMF2. The attacker's row can be ROWk, and the victim's rows can be ROWk-1 and ROWk+1. In the eighth memory chip 100-8, row line ROW1 of the first memory bank BK0 can be accessed by the address translation signal ADDRMF7. The attacker's row can be ROW1, and the victim's rows can be ROW0 and ROW2. Therefore, the first condition is satisfied because the row numbers accessed by the multiple translation address signals ADDRMF<0:7> in each of the multiple memory chips 100-1 to 100-8 do not overlap. Furthermore, the second condition is satisfied because the victim row number in the row lines accessed by the multiple translation address signals ADDRMF<0:7> in each of the multiple memory chips 100-1 to 100-8 does not overlap with the victim row number of a neighboring memory chip. For example, the second memory chip 100-2 is adjacent to the first memory chip 100-1 and the third memory chip 100-3, making the first and third memory chips neighboring memory chips. Therefore, for example, the victim row ROW1 of the second memory chip 100-2 does not overlap with the victim row ROWk of the first memory chip 100-1 (i.e., the neighboring memory chip) or the victim row ROWk+1 of the third memory chip 100-3 (i.e., another neighboring memory chip), thus satisfying the second condition.

[0051] Figure 6 This is a diagram illustrating the configuration of a memory system 20 according to another embodiment of the present disclosure.

[0052] Reference Figure 6 The memory system 20 may include a memory controller 21 and a memory module 22.

[0053] The memory controller 21 can provide the memory module 22 with a command signal CMD and a target address signal ADDR. The memory controller 21 can generate the target address signal ADDR by mapping the physical address signal provided from an external host (e.g., CPU or GPU) into a form suitable for memory access.

[0054] Memory module 22 may be a DIMM or a 3D memory module having memory dies stacked therein. Memory module 22 may perform data DQ input / output with memory controller 21 in response to command signal CMD and target address signal ADDR. Memory module 22 may include multiple memory chips CHIP0 to CHIPn-1 (200-1 to 200-n) and address remapping circuitry 210. Memory module 22 may access multiple memory chips 200-1 to 200-n according to multiple translation address signals ADDRMS<0:n-1> generated by remapping the row address signal and bank address signal included in the target address signal ADDR. The multiple translation address signals ADDRMS<0:n-1> can have values ​​satisfying a first condition, a second condition, and a third condition, wherein the first condition is used to substantially prevent the accessed row lines (e.g., word lines) in each of the multiple memory chips 200-1 to 200-n from overlapping with each other; the second condition is used to substantially prevent the victim row number in each of the accessed row lines in the multiple memory chips 200-1 to 200-n from overlapping with the victim row number of a neighboring memory chip; and the third condition substantially prevents the accessed cell memory regions (e.g., banks) in each of the multiple memory chips 200-1 to 200-n from overlapping with each other. The multiple translation address signals ADDRMS<0:n-1> may include address signals generated by remapping row address signals, address signals generated by remapping bank address signals, and column address signals included in the target address signal ADDR.

[0055] Multiple memory chips 200-1 to 200-n can have substantially the same configuration. Each of the multiple memory chips 200-1 to 200-n can have the same configuration as... Figure 3The first memory chip 100-1 has essentially the same configuration. Multiple memory chips 200-1 to 200-n can be configured to access corresponding row lines of corresponding cell memory regions in response to multiple translation address signals ADDRMS<0:n-1>.

[0056] The address remapping circuit 210 may include remapping logic for remapping the target address signal ADDR such that the target address signal ADDR satisfies a first condition, a second condition, and a third condition. The logic configuration of the address remapping circuit 210 for remapping the target address signal ADDR to satisfy the first and second conditions can be referenced. Figure 2 and Figure 4 The remapping logic of the address remapping circuit 110 described is basically the same.

[0057] Address remapping circuit 210 can perform a first address translation operation by adding each of the first correction values ​​0 to 7 to the row address signal ADDR_R included in the target address signal ADDR. Address remapping circuit 210 can perform a second address translation operation on each of the address signals generated based on the result of the first address translation operation. Address remapping circuit 210 can perform a third address translation operation independently of the first and second address translation operations, which adds each of the second correction values ​​to the cell region address (e.g., a bank address signal) included in the target address signal ADDR. The second correction values ​​can be substantially the same as the first correction values. By performing the third address translation operation, an address remapping operation can be performed to satisfy a third condition that the sequence numbers of the accessed bank in each of the plurality of memory chips 200-1 to 200-n do not overlap. A plurality of preliminary translated address signals can be generated by the first and third address translation operations. A plurality of translated address signals ADDRMS<0:n-1> can be generated by the second address translation operation.

[0058] Figure 7 This is a diagram illustrating an access method for a memory module 22 according to another embodiment of the present disclosure.

[0059] In the memory module 22, among the multiple memory chips 200-1 to 200-n, the cell memory regions and row lines corresponding to the multiple translation address signals ADDRMS<0:n-1> provided by the address remapping circuit 210 can be accessed.

[0060] Figure 7 This illustrates an access method when the number of multiple memory chips 200-1 to 200-n is 8 and the number of cell memory blocks (e.g., memory banks) included in each of the multiple memory chips 200-1 to 200-n is 8.

[0061] Reference Figure 7 In the first memory chip 200-1, row line ROWk+1 of the first memory bank BK0 can be accessed by the address translation signal ADDRMS0. The attacker's row can be ROWk+1, and the victim's row can be ROWk. In the second memory chip 200-2, row line ROW2 of the second memory bank BK1 can be accessed by the address translation signal ADDRMS1. The attacker's row can be ROW2, and the victim's rows can be ROW1 and ROW3. In the third memory chip 200-3, row line ROWk of the third memory bank BK2 can be accessed by the address translation signal ADDRMS2. The attacker's row can be ROWk, and the victim's rows can be ROWk-1 and ROWk+1. In the eighth memory chip 200-8, row line ROW1 of the eighth memory bank BK7 can be accessed by the address translation signal ADDRMS7. The attacker's row can be ROW1, and the victim's rows can be ROW0 and ROW2. As can be seen from the example of the aforementioned access method, the first condition is satisfied because the row numbers accessed by the multiple translation address signals ADDRMS<0:7> in each of the plurality of memory chips 200-1 to 200-8 do not overlap. The second condition is satisfied because the row number of the victim row in each of the plurality of memory chips 200-1 to 200-8 accessed by the multiple translation address signals ADDRMS<0:7> does not overlap with that of a neighboring memory chip. Furthermore, the third condition is satisfied because the accessed memory cell numbers in each of the plurality of memory chips 200-1 to 200-n do not overlap.

[0062] Figure 8 This is a diagram illustrating the configuration of a memory system 30 according to yet another embodiment of the present disclosure.

[0063] refer to Figure 8 The memory system 30 may include a memory controller 31 and a memory module 32.

[0064] The memory controller 31 can provide the memory module 32 with a command signal CMD and multiple translation address signals ADDRMF<0:n-1>. The memory controller 31 can generate a target address signal ADDR by mapping a physical address signal provided from an external host (e.g., a CPU or GPU) into a form suitable for memory access, and generate the multiple translation address signals ADDRMF<0:n-1> by performing an address remapping operation on the row address signals included in the target address signal ADDR. The target address signal ADDR may include address signals (e.g., row address signals, column address signals, and bank address signals) for selecting row lines, column lines, and cell memory blocks of the semiconductor memory. The multiple translation address signals ADDRMF<0:n-1> may include address signals generated by performing a remapping operation on the row address signals, column address signals, and bank address signals.

[0065] The memory controller 31 may include an address remapping circuit 311. The address remapping circuit 311 can generate multiple translation address signals ADDRMF<0:n-1> by performing an address remapping operation on the target address signal ADDR. The logic configuration of the address remapping circuit 311 can be related to a reference... Figure 2 and Figure 4 The remapping logic of the address remapping circuit 110 described is essentially the same. The memory controller 31 can be configured to send multiple translation address signals ADDRMF<0:n-1> sequentially to the memory module 32 in a preset order.

[0066] The memory module 32 may be a DIMM or a memory module having a 3D structure in which memory dies are stacked. The memory module 32 may include multiple memory chips CHIP0 to CHIPn-1 (321-1 to 321-n) and address control circuitry 322. The memory module 32 may perform data DQ input / output with the memory controller 31 by accessing the multiple memory chips 321-1 to 321-n in response to a command signal CMD and multiple translation address signals ADDRMF<0:n-1>. The multiple memory chips 321-1 to 321-n may have substantially the same configuration. The multiple memory chips 321-1 to 321-n may be configured to access corresponding row lines in response to the multiple translation address signals ADDRMF<0:n-1>, thereby satisfying a first condition and a second condition. Address control circuit 322 can be configured to allocate multiple translation address signals ADDRMF<0:n-1> to multiple memory chips 321-1 to 321-n according to their sequence numbers. Address control circuit 322 can parallelize the multiple translation address signals ADDRMF<0:n-1> in serial form and allocate the parallelized signals to the multiple memory chips 321-1 to 321-n according to their sequence numbers. Address control circuit 322 can store and align the multiple translation address signals ADDRMF<0:n-1> provided serially from memory controller 31 to parallelize them into first translation address signals ADDRMF0 to nth translation address signals ADDRMFn-1, and allocate the parallelized first translation address signals ADDRMF0 to nth translation address signals ADDRMFn-1 to the multiple memory chips 321-1 to 321-n respectively. For example, the address control circuit 322 can provide a first conversion address signal ADDRMF0 to the first memory chip 321-1, a second conversion address signal ADDRMF1 to the second memory chip 321-2, and in this way, provide an nth conversion address signal ADDRMFn-1 to the nth memory chip 321-n.

[0067] Figure 9 This is a diagram illustrating the configuration of a memory system 40 according to yet another embodiment of the present disclosure.

[0068] Reference Figure 9 The memory system 40 may include a memory controller 41 and a memory module 42.

[0069] The memory controller 41 can provide the memory module 42 with a command signal CMD and multiple translation address signals ADDRMS<0:n-1>. The memory controller 41 can generate a target address signal ADDR by mapping a physical address signal provided from an external host (e.g., a CPU or GPU) into a form suitable for memory access, and generate the multiple translation address signals ADDRMS<0:n-1> by performing an address remapping operation on the row address signals and bank address signals included in the target address signal ADDR. The target address signal ADDR may include address signals (e.g., row address signals, column address signals, and bank address signals) for selecting row lines, column lines, and cell memory blocks of the semiconductor memory. The multiple translation address signals ADDRMS<0:n-1> may include address signals generated by performing an address remapping operation on the row address signals, bank address signals, and column address signals.

[0070] The memory controller 41 may include an address remapping circuit 411. The address remapping circuit 411 can generate multiple translation address signals ADDRMS<0:n-1> by performing an address remapping operation on the target address signal ADDR. The logic configuration of the address remapping circuit 411 can be related to a reference... Figure 6 and Figure 7 The remapping logic of the address remapping circuit 210 described is essentially the same. The memory controller 41 can be configured to send multiple translation address signals ADDRMS<0:n-1> sequentially to the memory module 42 in a preset order.

[0071] Memory module 42 may be a DIMM or a memory module having a 3D structure in which memory dies are stacked. Memory module 42 may include multiple memory chips CHIP0 to CHIPn-1 (421-1 to 421-n) and address control circuitry 422. Memory module 42 may perform data DQ input / output with memory controller 41 by accessing multiple memory chips 421-1 to 421-n in response to command signal CMD and multiple translation address signals ADDRMS<0:n-1>. Multiple memory chips 421-1 to 421-n may have substantially the same configuration. Multiple memory chips 421-1 to 421-n may be configured to access corresponding cell memory regions and corresponding row lines in response to multiple translation address signals ADDRMS<0:n-1>, thereby satisfying a first condition, a second condition, and a third condition.

[0072] Address control circuit 422 can be configured to allocate multiple translation address signals ADDRMS<0:n-1> to multiple memory chips 421-1 to 421-n according to their sequence numbers. Address control circuit 422 can parallelize the multiple translation address signals ADDRMS<0:n-1> and allocate the parallelized signals to the multiple memory chips 421-1 to 421-n according to their sequence numbers. Address control circuit 422 can store and align the multiple translation address signals ADDRMS<0:n-1> provided serially from memory controller 41 to parallelize them into first translation address signals ADDRMS0 to nth translation address signals ADDRMSn-1, and allocate the parallelized first translation address signals ADDRMS0 to nth translation address signals ADDRMSn-1 to the multiple memory chips 421-1 to 421-n respectively. For example, the address control circuit 422 can provide a first translation address signal ADDRMS0 to the first memory chip 421-1, a second translation address signal ADDRMS1 to the second memory chip 421-2, and in this way, provide an nth translation address signal ADDRMSn-1 to the nth memory chip 421-n.

[0073] Figure 10 This is a diagram illustrating the configuration of a memory chip 500 according to an embodiment of the present disclosure.

[0074] Reference Figure 10 The memory chip 500 may include a memory region 501, an address decoder 502, a pin array 503, a data input / output circuit 504, and a control circuit 505.

[0075] Memory region 501 may have the same Figure 3 The memory region 101 has a substantially the same configuration. The memory cells of the memory region 501 can be divided into multiple cell memory regions, for example, multiple memory banks BK0 to BKn-1.

[0076] Address decoder 502 can be connected to control circuit 505 and memory area 501. Address decoder 502 can convert the address signal ADDRMF provided from control circuit 505. Decode the code and access memory area 501 based on the decoding result.

[0077] Pin array 503 may include command and address integrated pins (CA) 503-1. Pin array 503 may have... Figure 3 The pin array 103 has essentially the same configuration.

[0078] Data input / output circuitry 504 can be connected to memory region 501. Data input / output circuitry 504 can have... Figure 3 The data input / output circuit 104 has essentially the same configuration.

[0079] Control circuitry 505 can be connected to memory region 501, address decoder 502, and data input / output circuitry 504. Control circuitry 505 can perform control operations related to read operations, write operations, and address processing of memory chip 500. Control circuitry 505 can receive command signal CMD and target address signal ADDR via command and address integrated pin (CA) 503-1. The target address signal ADDR can be provided from a configuration external to memory chip 500 (e.g., a memory controller). Target address signal ADDR may include address signals (e.g., row address signals, column address signals, and bank address signals) for selecting row lines, column lines, and cell memory blocks in memory region 501.

[0080] Control circuit 505 can generate multiple translation address signals ADDRMF<0:n-1> by remapping the row address signal included in the target address signal ADDR. Control circuit 505 can be configured to provide address decoder 502 with any one of the multiple translation address signals ADDRMF<0:n-1> corresponding to the memory bank's sequence number. The memory bank corresponds to the memory bank address signal included in the target address signal ADDR.

[0081] Control circuit 505 may include address remapping circuit 600 and multiplexing circuit 700. Address remapping circuit 600 can generate multiple translation address signals ADDRMF<0:n-1> by performing address remapping operations on the row address signals included in the target address signal ADDR. The logic configuration of address remapping circuit 600 can be related to a reference... Figure 2 and Figure 4 The remapping logic of the described address remapping circuit 110 is essentially the same. The multiple translation address signals ADDRMF<0:n-1> may include address signals generated by performing an address remapping operation on the row address signal, column address signal, and memory bank address signal. The multiplexing circuit 700 can select one translation address signal ADDRMF from the multiple translation address signals ADDRMF<0:n-1> in response to the memory bank address signal ADDR_BA included in the destination address signal ADDR. The multiplexing circuit 700 selects the selected conversion address signal ADDRMF1 from the multiple conversion address signals ADDRMF<0:n-1> and outputs the selected conversion address signal ADDRMF1. For example, when the memory address signal ADDR_BA has a value corresponding to the second memory BK1 among the multiple memory banks BK0 to BKn-1, the multiplexing circuit 700 can select the conversion address signal ADDRMF1 from the multiple conversion address signals ADDRMF<0:n-1> and output the selected conversion address signal ADDRMF1.

[0082] In the aforementioned memory chip 500, even if the row address signals included in each of the different target address signals ADDR have substantially the same value, different row lines can be accessed for each of the multiple memory banks BK0 to BKn-1. Therefore, in one embodiment, by satisfying a first condition that the sequence numbers of the accessed row lines do not overlap with each other and a second condition that the sequence number of the victim row in the accessed row line does not overlap with the sequence number of the victim row of the adjacent memory chip, data loss caused by row hammers can be minimized.

[0083] Those skilled in the art to which this disclosure pertains will understand that this disclosure can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this disclosure is defined by the claims, which will be described subsequently, rather than by the specific embodiments, and it should be understood that the meaning and scope of the claims, as well as all modifications or variations derived from their equivalents, are included within the scope of this disclosure.

Claims

1. A memory module comprising: J memory chips which input and output data in response to each of a plurality of converted address signals; and an address remapping circuit which generates a plurality of preliminary converted address signals by adding a first correction value to a target address signal supplied from outside of the memory module, and generates the plurality of converted address signals by shifting all bits of each of the plurality of preliminary converted address signals so that K bits included in each bit string of each of the plurality of preliminary converted address signals move to other positions of the bit string; wherein K is determined by Log2[Max(I, J)], and I is determined by a total number of a currently accessed row line and row lines physically adjacent to the currently accessed row line; wherein J represents a number of memory chips in the memory module, and wherein K represents a number; wherein the other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary converted address signals, and the K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary converted address signals.

2. The memory module of claim 1, wherein, The address remapping circuit generates the plurality of preliminary converted address signals by adding the first correction value to a row address signal included in the target address signal.

3. The memory module according to claim 1, wherein I is a value set to ensure reliability of an access operation of the memory chips.

4. The memory module of claim 1, wherein, Data loss of memory cells coupled to the row lines physically adjacent to the currently accessed row line occurs due to activation of the currently accessed row line.

5. A memory module comprising: J memory chips each including a plurality of unit memory areas, and inputting and outputting data by accessing unit memory areas having serial numbers which do not overlap with each other among the plurality of unit memory areas in response to each of a plurality of converted address signals; and an address remapping circuit which generates a plurality of preliminary converted address signals by adding a first correction value to a row address signal included in a target address signal supplied from outside of the memory module, shifts all bits of each of the plurality of preliminary converted address signals so that K bits included in each bit string of each of the plurality of preliminary converted address signals move to other positions of the bit string, and generates the plurality of converted address signals by adding a second correction value to a unit area address included in the target address signal; wherein K is determined by Log2[Max(I, J)], and I is determined by a total number of a currently accessed row line and row lines physically adjacent to the currently accessed row line; wherein J represents a number of memory chips in the memory module, and wherein K represents a number; wherein the other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary converted address signals, and the K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary converted address signals. wherein the other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary translation address signals, and K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary translation address signals.

6. The memory module of claim 5, wherein, The first correction value and the second correction value are set to be equal to each other.

7. The memory module of claim 5, wherein data loss of memory cells coupled to a row line physically adjacent to the currently accessed row line occurs by activation of the currently accessed row line.

8. A memory system, comprising: a memory controller that: generates a plurality of preliminary translation address signals by adding a correction value to a target address signal; and generates a plurality of translation address signals by shifting all bits of each of the plurality of preliminary translation address signals so that K bits included in each bit string of each of the plurality of preliminary translation address signals move to other positions of the bit string; and a memory module that includes J memory chips, receives the plurality of translation address signals, and causes the J memory chips to perform data input and output with the memory controller in response to each of the plurality of translation address signals; wherein K is determined by Log2[Max(I, J)], and I is determined by a total number of a currently accessed row line and a row line physically adjacent to the currently accessed row line; wherein J represents a number of memory chips in the memory module, and wherein K represents a number; wherein the other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary translation address signals, and K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary translation address signals.

9. The memory system of claim 8, wherein, the memory controller includes an address remapping circuit, wherein the address remapping circuit generates the plurality of preliminary translation address signals by adding the correction value to a row address signal included in the target address signal.

10. The memory system of claim 8, wherein, Data loss of memory cells coupled to a row line physically adjacent to the currently accessed row line occurs by activation of the currently accessed row line.

11. The memory system of claim 8, wherein, the memory module includes an address control circuit, wherein the address control circuit allocates the plurality of translation address signals to the J memory chips according to a sequence number of the plurality of translation address signals.

12. A memory system, comprising: a memory controller that: generates a plurality of preliminary translation address signals by adding a first correction value to a row address signal included in a target address signal; shifts all bits of each of the plurality of preliminary translation address signals so that K bits included in each bit string of each of the plurality of preliminary translation address signals move to other positions of the bit string; and generates a plurality of translation address signals by adding a second correction value to a cell region address included in the target address signal; and a memory module that includes J memory chips, receives the plurality of translation address signals, and causes the J memory chips to perform data input and output with the memory controller in response to each of the plurality of translation address signals; A memory module including J memory chips each including a plurality of unit memory areas, the memory module causing the J memory chips to perform data input and output with the memory controller by accessing unit memory areas of the plurality of unit memory areas having serial numbers that do not overlap with each other in response to each of the plurality of conversion address signals; wherein K is determined by Log2[Max(I, J)], and I is determined by a total number of a currently accessed row line and row lines physically adjacent to the currently accessed row line; wherein J represents a number of memory chips in the memory module, and wherein K represents a number; wherein other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary conversion address signals, and K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary conversion address signals.

13. The memory system of claim 12, wherein, Data of memory cells coupled to row lines physically adjacent to the currently accessed row line is lost due to activation of the currently accessed row line.

14. The memory system of claim 12, wherein, The memory module includes an address control circuit, wherein the address control circuit allocates the plurality of conversion address signals to the J memory chips according to serial numbers of the plurality of conversion address signals.

15. A semiconductor memory device, comprising: a memory area including J unit memory areas; a control circuit that generates a plurality of conversion address signals by remapping a target address signal provided from outside of a memory module, and outputs any conversion address signal of the plurality of conversion address signals corresponding to a unit area address included in the target address signal; and an address decoder that decodes the any conversion address signal, and accesses the memory area according to a result of the decoding, wherein the control circuit includes an address remapping circuit that generates a plurality of preliminary conversion address signals by adding a first correction value to a row address signal included in the target address signal, and generates the plurality of conversion address signals by shifting all bits of each of the plurality of preliminary conversion address signals so that K bits of each bit string included in each of the plurality of preliminary conversion address signals move to other positions of the bit string; wherein K is determined by Log2[Max(I, J)], and I is determined by a total number of a currently accessed row line and row lines physically adjacent to the currently accessed row line; wherein J represents a number of memory chips in the memory module, and wherein K represents a number; wherein other positions of each bit string correspond to bits in a right direction from a most significant bit of the bit string of each of the plurality of preliminary conversion address signals, and K bits correspond to bits in a left direction from a least significant bit of the bit string of each of the plurality of preliminary conversion address signals.

16. The semiconductor memory device of claim 15, wherein, The control circuit further includes: A multiplexing circuit that: selects any one of the plurality of translation address signals in response to a bank address signal included in the target address signal; and outputs the selected signal.

17. The semiconductor memory device of claim 16, wherein, Data loss from memory cells coupled to a row line physically adjacent to the currently accessed row line occurs as a result of activation of the currently accessed row line.

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