A magnetic memory and its performance adjustment method

Abstract

The present application discloses a method for adjusting the performance of a magnetic memory, including receiving a performance adjustment instruction; obtaining the parallel-state switching voltage and the anti-parallel-state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with a CMOS circuit; and adjusting the parallel-state switching voltage or the anti-parallel-state switching voltage to adjust the performance of the magnetic tunnel junction. It can be seen that, after receiving the performance adjustment instruction, the method for adjusting the performance of the magnetic memory in the present application obtains the parallel-state switching voltage and the anti-parallel-state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit, and adjusts the performance of the magnetic memory by adjusting the parallel-state switching voltage or the anti-parallel-state switching voltage, so as to optimize the writing difficulty and the number of erasable and rewritable times of the magnetic memory. In addition, the present application also provides a magnetic memory.

Description

Technical Field

[0001] This application relates to the technical field of magnetic memories, and particularly to a magnetic memory and a method for adjusting its performance. Background Art

[0002] Spin Transfer Torque Magnetic Random Access Memory (abbreviated as STT-MRAM) is a new type of memory, which needs to be integrated with a CMOS (Complementary Metal-Oxide-Semiconductor) circuit during use. The integration method of STT-MRAM and the CMOS circuit is to connect the magnetic tunnel junction (MTJ) of the basic storage unit of STT-MRAM in series with one or more source electrodes on one side of the CMOS circuit. The drain electrode is externally connected to the biteline (BL), the gate electrode is connected to the word line (WL), and the source electrode is connected to the source line (SL), as Figure 1 shown.

[0003] The flipping of the MTJ is driven by current. Since the resistance values of the parallel state and the antiparallel state differ greatly, and the flipping currents of the two states are also different, and at the same time affected by the current supply capacity of the CMOS, the flipping voltages of the two states of the MTJ also have a large gap, as Figure 2 shown. In the figure, the abscissa is voltage and the ordinate is resistance. When flipping by applying voltage from the BL, the CMOS voltage division is small, the drain voltage is low, the source electrode is grounded, V gate -V drain is relatively high, the current passing ability of the CMOS is strong, the CMOS resistance is small, and the MTJ voltage division is more; when flipping by applying voltage from the SL, due to the MTJ voltage division, the source-drain voltage of the CMOS is high, V gate -V drianLow, the current-carrying capacity of CMOS is weak, the resistance of CMOS increases, and the voltage division of MTJ is small. When the source line voltage increases to a certain extent, continuing to apply voltage, the voltage across the MTJ remains basically unchanged. Therefore, the voltage division of the MTJ in the two flipping states differs greatly, and it is difficult to write to the MTJ. On the other hand, usually, the number of erasable and rewritable times of the MTJ in one direction is significantly lower than that in the other direction. For example, the number of erasable and rewritable times from the parallel state to the antiparallel state is significantly less than that from the antiparallel state to the parallel state, or the number of erasable and rewritable times from the parallel state to the antiparallel state is significantly greater than that from the antiparallel state to the parallel state, resulting in a low overall number of erasable and rewritable times of the MTJ. However, currently, these two performances of the MTJ cannot be optimized and adjusted.

[0004] Therefore, how to solve the above technical problems should be the key concern of those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a magnetic memory and its performance adjustment method to optimize the performance of the magnetic memory.

[0006] To solve the above technical problems, this application provides a method for adjusting the performance of a magnetic memory, including:

[0007] Receiving a performance adjustment instruction;

[0008] Obtaining the parallel-state flipping voltage and the antiparallel-state flipping voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit;

[0009] Adjusting the parallel-state flipping voltage or the antiparallel-state flipping voltage to adjust the performance of the magnetic tunnel junction.

[0010] Optionally, when the performance adjustment instruction is to reduce the writing difficulty, the adjusting the parallel-state flipping voltage or the antiparallel-state flipping voltage to adjust the performance of the magnetic tunnel junction includes:

[0011] Determining the magnitude relationship between the parallel-state flipping voltage and the antiparallel-state flipping voltage;

[0012] When the antiparallel-state flipping voltage is greater than the parallel-state flipping voltage, increasing the parallel-state flipping voltage or decreasing the antiparallel-state flipping voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the parallel-state flipping voltage and the antiparallel-state flipping voltage;

[0013] When the antiparallel-state flipping voltage is less than the parallel-state flipping voltage, decreasing the parallel-state flipping voltage or increasing the antiparallel-state flipping voltage, and adjusting the magnetic bias field in the negative direction to balance the parallel-state flipping voltage and the antiparallel-state flipping voltage;

[0014] Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is defined as the positive direction when it points in the same direction as the magnetic moment of the reference layer.

[0015] Optionally, when the performance adjustment instruction is to increase the number of erasable writes, adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:

[0016] Obtaining a first number of erasable writes of the magnetic tunnel junction from the parallel state to the anti-parallel state and a second number of erasable writes from the anti-parallel state to the parallel state;

[0017] Determining the magnitude relationship between the first number of erasable writes and the second number of erasable writes;

[0018] When the first number of erasable writes is greater than the second number of erasable writes, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the first number of erasable writes and the second number of erasable writes;

[0019] When the first number of erasable writes is less than the second number of erasable writes, decreasing the parallel state switching voltage or increasing the anti-parallel state switching voltage, and adjusting the magnetic bias field in the negative direction to balance the first number of erasable writes and the second number of erasable writes;

[0020] Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is defined as the positive direction when it points in the same direction as the magnetic moment of the reference layer.

[0021] Optionally, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes:

[0022] Reducing the number of layers of the first ferromagnetic repeating unit in the pinned layer or increasing the number of layers of the second ferromagnetic repeating unit in the reference layer.

[0023] Optionally, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes:

[0024] Reducing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is greater than the thickness of the pinned layer.

[0025] Optionally, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes:

[0026] Adjusting the first material of the first ferromagnetic repeating unit or adjusting the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is less than the saturation magnetization intensity of the second material.

[0027] Optionally, reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes:

[0028] Increasing the number of layers of the first ferromagnetic repeating unit in the pinning layer or reducing the number of layers of the second ferromagnetic repeating unit in the reference layer.

[0029] Optionally, reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes:

[0030] Increasing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.

[0031] Optionally, reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes:

[0032] Adjusting the first material of the first ferromagnetic repeating unit or adjusting the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is greater than that of the second material.

[0033] Optionally, it further includes:

[0034] Thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.

[0035] Optionally, it further includes:

[0036] Increasing the thickness of the first ferromagnetic repeating unit or thinning the thickness of the second ferromagnetic repeating unit.

[0037] Optionally, obtaining the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:

[0038] Measuring the test key of the magnetic tunnel junction connected in series with the CMOS circuit to obtain the parallel state switching voltage and the antiparallel state switching voltage;

[0039] Or, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the antiparallel state switching voltage.

[0040] Optionally, the reference layer is Co x Fe y B z and the coupling structure layer of (CoPt) n , where n≥1; the pinning layer is the magnetic layer of (CoPt) m , where m≥1 and m>n.

[0041] The present application also provides a magnetic memory, which is used to implement the magnetic memory performance adjustment method described in any one of the above.

[0042] A magnetic memory performance adjustment method provided by the present application includes receiving a performance adjustment instruction; obtaining the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with a CMOS circuit; and adjusting the parallel state switching voltage or the antiparallel state switching voltage to adjust the performance of the magnetic tunnel junction.

[0043] It can be seen that after receiving the performance adjustment instruction, the magnetic memory performance adjustment method in the present application obtains the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit, and adjusts the performance of the magnetic memory by adjusting the parallel state switching voltage or the antiparallel state switching voltage, thereby optimizing the writing difficulty and the number of erasable and rewritable times of the magnetic memory.

[0044] In addition, the present application also provides a magnetic memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0046] Figure 1 It is a circuit diagram of a magnetic tunnel junction connected in series with a CMOS circuit;

[0047] Figure 2 It is a schematic diagram of the switching voltages of the parallel state and the antiparallel state of the magnetic tunnel junction;

[0048] Figure 3 It is a flowchart of a magnetic memory performance adjustment method provided by an embodiment of the present application;

[0049] Figure 4 It is a flowchart of another magnetic memory performance adjustment method provided by an embodiment of the present application;

[0050] Figure 5 It is a schematic diagram of the structure of the magnetic tunnel junction;

[0051] Figure 6 It is a schematic diagram of the magnetic bias field;

[0052] Figure 7 It is a schematic diagram of the structure of the magnetic tunnel junction at a small etching angle;

[0053] Figure 8Schematic diagram of the structure of the magnetic tunnel junction at a large etching angle

[0054] Figure 9 Flow chart of another method for adjusting the performance of a magnetic memory provided by an embodiment of the present application;

[0055] Figure 10 Schematic diagram of the adjustment of the magnetic bias field when the first erasable write count is greater than the second erasable write count;

[0056] Figure 11 Schematic diagram of the adjustment of the anti-parallel state flip voltage when the first erasable write count is greater than the second erasable write count. Detailed implementation manners

[0057] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0058] As described in the background art section, when flipping the MTJ by applying pressure from the BL, the CMOS voltage division is small, the drain voltage is low, the source is grounded, V gate -V drain is relatively high, the current-carrying capacity of the CMOS is strong, the CMOS resistance is small, and the MTJ voltage division is large; when flipping by applying pressure from the SL, due to the MTJ voltage division, the source-drain voltage of the CMOS is high, V gate -V drian is low, the current-carrying capacity of the CMOS is weak, the CMOS resistance increases, and the MTJ voltage division is small. When the source line voltage increases to a certain extent, continuing to apply pressure results in basically no change in the voltage on the MTJ. Therefore, the MTJ voltage division in the two flipping states differs significantly, and the writing difficulty of the MTJ is high. On the other hand, usually, the erasable write count of the MTJ in one direction is significantly lower than that in the other direction, resulting in a low overall erasable write count of the MTJ. However, currently, it is not possible to optimize and adjust these two performances of the MTJ.

[0059] In view of this, the present application provides a method for adjusting the performance of a magnetic memory. Please refer to Figure 3 , Figure 3 Flow chart of a method for adjusting the performance of a magnetic memory provided by an embodiment of the present application. The method includes:

[0060] Step S101: Receive a performance adjustment instruction.

[0061] Step S102: Obtain the parallel state flip voltage and the anti-parallel state flip voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

[0062] The magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer, and a free layer. The reference layer and the pinned layer are strongly antiferromagnetically coupled by an antiferromagnetic coupling layer to make their magnetic moments antiparallel. Among them, the parallel state switching voltage is the voltage required to flip the magnetic moment of the free layer from the direction parallel to the magnetic moment of the reference layer to the antiparallel direction; the antiparallel state switching voltage is the voltage required to flip the magnetic moment of the free layer from the direction antiparallel to the magnetic moment of the reference layer to the parallel direction.

[0063] Optionally, obtaining the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:

[0064] Measuring the testkey of the magnetic tunnel junction connected in series with the CMOS circuit to obtain the parallel state switching voltage and the antiparallel state switching voltage.

[0065] Alternatively, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the antiparallel state switching voltage.

[0066] The electrical parameters of the magnetic tunnel junction include but are not limited to the parallel state switching voltage V c-P to AP of the magnetic tunnel junction when it is not connected to the CMOS circuit, the antiparallel state switching voltage V c-AP to P , the parallel state resistance R p , the antiparallel state resistance R ap , the coercivity Hc, and the Hoff value.

[0067] Specifically, the applied gate voltage V WL can be 1.6V.

[0068] The parallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit is denoted as V SL-P to AP , and the antiparallel state switching voltage is denoted as V BL-AP to P .

[0069] Step S103: Adjust the parallel state switching voltage or the antiparallel state switching voltage to adjust the performance of the magnetic tunnel junction.

[0070] After receiving the performance adjustment instruction, the magnetic memory performance adjustment method in this application obtains the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit, and adjusts the performance of the magnetic memory by adjusting the parallel state switching voltage or the antiparallel state switching voltage, optimizing the writing difficulty and the number of erasable and rewritable times of the magnetic memory.

[0071] The following elaborates in detail on the magnetic memory performance adjustment method in this application according to different performance adjustment instructions.

[0072] First, when the performance adjustment instruction is to reduce the writing difficulty, please refer to Figure 4 , Figure 4 which is a flowchart of another magnetic memory performance adjustment method provided by an embodiment of this application. The method includes:

[0073] Step S201: Receive a performance adjustment instruction.

[0074] Step S202: Obtain the parallel-state switching voltage and the anti-parallel-state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

[0075] Step S203: Determine the magnitude relationship between the parallel-state switching voltage and the anti-parallel-state switching voltage.

[0076] Step S204: When the anti-parallel-state switching voltage is greater than the parallel-state switching voltage, increase the parallel-state switching voltage or decrease the anti-parallel-state switching voltage, and adjust the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the parallel-state switching voltage and the anti-parallel-state switching voltage.

[0077] As Figure 5 shown, the magnetic tunnel junction includes a free layer 1, a reference layer 2, and a pinned layer 3. The magnetization directions of the free layer 1, the reference layer 2, and the pinned layer 3 are perpendicular magnetization; the magnetic bias field is the synthesis of the stray fields generated by other magnetic layers outside the free layer of the magnetic tunnel junction, which is equivalent to an external static magnetic field applied to the free layer. Due to the directionality of the magnetic bias field, the MTJ will be more stable in a certain state. Please refer to Figure 6 . The magnetic bias field will affect the electrical switching. When the MTJ magnetic bias field biases towards a certain state, the switching voltage of this state will increase, and vice versa.

[0078] Optionally, there are three ways to increase the parallel-state switching voltage or decrease the anti-parallel-state switching voltage, which are introduced separately below.

[0079] First, reduce the number of layers of the first ferromagnetic repeating unit in the pinned layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer. At this time, the Hoff value is adjusted in the positive direction, and the magnetic bias field is adjusted in the positive direction.

[0080] When the anti-parallel-state switching voltage V BL-AP to P is greater than the parallel-state switching voltage V SL-P to AP , it is necessary to reduce the anti-parallel-state switching voltage V c-AP to P of the magnetic tunnel junction when it is not connected to the CMOS circuit., reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer can reduce the stray field generated by the pinning layer. The direction of the stray field generated by the pinning layer is opposite to the magnetic moment direction of the reference layer, that is, the direction of the stray field generated by the pinning layer is negative. Increasing the number of layers of the second ferromagnetic repeating unit in the reference layer can increase the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the magnetic moment direction of the reference layer, that is, the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted in the positive direction. Therefore, the magnetic bias field is adjusted in the positive direction, and the parallel state switching voltage V SL-P to AP becomes larger, and the antiparallel state switching voltage V BL-AP to P becomes smaller. The difference between V SL-P to AP and V BL-AP to P decreases, so as to make V SL-P to AP and V BL-AP to P basically equal in magnitude.

[0081] Second, reduce the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is greater than the thickness of the pinning layer.

[0082] It can be understood that in this case, other parameter indicators of the reference layer and the pinning layer are the same, and the thickness is the single variable.

[0083] When the antiparallel state switching voltage V BL-AP to P is greater than the parallel state switching voltage V SL-P to AP , under the condition that the thickness of the reference layer in the magnetic tunnel junction is greater than the thickness of the pinning layer, by reducing the etching angle, the schematic structural diagram of the magnetic tunnel junction is as shown in Figure 7 . It can be realized that the volume of the reference layer is greater than the volume of the pinning layer. The direction of the stray field generated by the pinning layer is negative, and the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the positive direction. Therefore, the magnetic bias field is adjusted in the positive direction, and the antiparallel state switching voltage V BL-AP to P becomes smaller, and the parallel state switching voltage V SL-P to AP becomes larger, so as to make V SL-P to AP and V BL-AP to P basically equal in magnitude.

[0084] Third, adjust the first material of the first ferromagnetic repeating unit or adjust the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is less than the saturation magnetization intensity of the second material.

[0085] It should be noted that in this application, the types of the first material and the second material are not specifically limited, as long as the saturation magnetization intensity of the first material is less than the saturation magnetization intensity of the second material is ensured.

[0086] When the antiparallel state switching voltage V BL-AP to P is greater than the parallel state switching voltage V SL-P to APWhen the saturation magnetization of the first material is less than that of the second material, the total magnetic moment of the pinned layer is less than that of the reference layer, the Hoff value is adjusted in the positive direction, so the magnetic bias field is adjusted in the positive direction.

[0087] Optionally, for the above first and second methods, the reference layer is Co x Fe y B z coupled with the (CoPt) n coupling structure layer, where n≥1; the pinned layer is a (CoPt) m magnetic layer, where m≥1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

[0088] Step S205: When the anti-parallel state switching voltage is less than the parallel state switching voltage, reduce the parallel state switching voltage or increase the anti-parallel state switching voltage, and adjust the magnetic bias field in the negative direction to balance the parallel state switching voltage and the anti-parallel state switching voltage; wherein, the magnetic tunnel junction includes at least a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is positive when it points in the same direction as the magnetic moment of the reference layer.

[0089] Optionally, there are three ways to reduce the parallel state switching voltage or increase the anti-parallel state switching voltage, which are introduced below respectively.

[0090] First, increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or reduce the number of layers of the second ferromagnetic repeating unit in the reference layer.

[0091] Increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer can increase the stray field generated by the pinned layer. The direction of the stray field generated by the pinned layer is opposite to the direction of the magnetic moment of the reference layer, that is, the direction of the stray field generated by the pinned layer is negative. Reducing the number of layers of the second ferromagnetic repeating unit in the reference layer can reduce the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, the parallel state switching voltage V SL-P to AP becomes smaller, and the anti-parallel state switching voltage V BL-AP to P becomes larger. The difference between V SL-P to AP and V BL-AP to P decreases, so as to make V SL-P to AP and V BL-AP to P basically equal.

[0092] Second, increase the etching angle of the magnetic tunnel junction, where the thickness of the reference layer is not greater than that of the pinned layer.

[0093] When the anti-parallel state switching voltage VBL-AP to P Less than the parallel state switching voltage V SL-P to AP When the thickness of the reference layer is not greater than that of the pinning layer, increasing the etching angle of the magnetic tunnel junction, the schematic structural diagram of the magnetic tunnel junction is as shown in Figure 8 As shown, the larger the etching angle, the larger the volume difference between the pinning layer and the reference layer. The direction of the stray field generated by the pinning layer is negative, and the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, and the anti-parallel state switching voltage V BL-AP to P becomes larger, and the parallel state switching voltage V SL-P to AP becomes smaller, so as to make V SL-P to AP and V BL-AP to P basically equal in magnitude. [[ID=I15]]

[0094] Thirdly, adjusting the first material of the first ferromagnetic repeating unit or adjusting the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is greater than that of the second material.

[0095] It should be noted that the types of the first material and the second material in this application are not specifically limited, as long as the saturation magnetization intensity of the first material is greater than that of the second material.

[0096] When the anti-parallel state switching voltage V BL-AP to P is less than the parallel state switching voltage V SL-P to AP the saturation magnetization intensity of the first material is greater than that of the second material, so that the total magnetic moment of the pinning layer is greater than that of the reference layer, and the Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction.

[0097] Optionally, for the first and second methods described above, the reference layer is a coupling structure layer of Co x Fe y B z and (CoPt) n where n≥1; the pinning layer is a (CoPt) m magnetic layer, where m≥1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

[0098] In this embodiment, by adjusting the parallel state switching voltage and the anti-parallel state switching voltage, the parallel state switching voltage and the anti-parallel state switching voltage are balanced, the difficulty of flipping between the parallel state and the anti-parallel state is reduced, and the writing difficulty of the magnetic memory is reduced. Among them, the difference between the parallel state switching voltage and the anti-parallel state switching voltage of the adjusted magnetic memory is less than 10%.

[0099] Further, based on the above embodiments, in an embodiment of the present application, when adjusting by reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer or increasing the number of layers of the second ferromagnetic repeating unit in the reference layer, it further includes:

[0100] Thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.

[0101] Further, based on the above embodiments, in an embodiment of the present application, when increasing the number of layers of the first ferromagnetic repeating unit in the pinning layer or reducing the number of layers of the second ferromagnetic repeating unit in the reference layer, it further includes:

[0102] Increasing the thickness of the first ferromagnetic repeating unit or thinning the thickness of the second ferromagnetic repeating unit.

[0103] Since the compositions of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit are fixed, increasing or decreasing the number of layers of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit may cause the adjustment of the Hoff value to be too large, making it impossible to achieve continuous adjustment, and thus impossible to achieve continuous adjustment of the magnetic bias field. By adjusting the thickness of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit, the step size of adjusting the Hoff value can be reduced, and the parallel state switching voltage V SL-P to AP and the antiparallel state switching voltage V BL-AP to P are closer to each other.

[0104] It should be noted that when adjusting the thickness of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit, the thickness adjustment needs to be within a certain range to maintain magnetic stability.

[0105] Second, when the performance adjustment instruction is to improve the number of erasable writes, please refer to Figure 9 , Figure 9 which is the flowchart of another method for adjusting the performance of a magnetic memory provided by an embodiment of the present application. The method includes:

[0106] Step S301: Receive a performance adjustment instruction.

[0107] Step S302: Obtain the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

[0108] Step S303: Obtain the first number of erasable writes of the magnetic tunnel junction from the parallel state to the antiparallel state and the second number of erasable writes from the antiparallel state to the parallel state.

[0109] Step S304: Determine the magnitude relationship between the first number of erasable writes and the second number of erasable writes.

[0110] Step S305: When the first erasable write count is greater than the second erasable write count, increase the parallel state switching voltage or decrease the anti-parallel state switching voltage, and adjust the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the first erasable write count and the second erasable write count.

[0111] Optionally, there are three ways to increase the parallel state switching voltage or decrease the anti-parallel state switching voltage, which are introduced separately below.

[0112] First, reduce the number of layers of the first ferromagnetic repeating unit in the pinned layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer. At this time, the Hoff value is adjusted in the positive direction, and the magnetic bias field is adjusted in the positive direction.

[0113] When the anti-parallel state switching voltage V BL-AP to P is greater than the parallel state switching voltage V SL-P to AP , it is necessary to reduce the anti-parallel state switching voltage V c-AP to P of the magnetic tunnel junction when it is not connected to the CMOS circuit. Reducing the number of layers of the first ferromagnetic repeating unit in the pinned layer can reduce the stray field generated by the pinned layer. The direction of the stray field generated by the pinned layer is opposite to the magnetic moment direction of the reference layer, that is, the direction of the stray field generated by the pinned layer is negative. Increasing the number of layers of the second ferromagnetic repeating unit in the reference layer can increase the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the magnetic moment direction of the reference layer, that is, the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the positive direction, so the magnetic bias field is adjusted in the positive direction, the parallel state switching voltage V SL-P to AP becomes larger, the anti-parallel state switching voltage V BL-AP to P becomes smaller, and the difference between V SL-P to AP and V BL-AP to P decreases, so that the magnitudes of V SL-P to AP and V BL-AP to P are basically equal.

[0114] Second, reduce the etching angle of the magnetic tunnel junction, where the thickness of the reference layer is greater than the thickness of the pinned layer.

[0115] It can be understood that in this case, other parameter indicators of the reference layer and the pinned layer are the same, and the thickness is a single variable.

[0116] When the anti-parallel state switching voltage V BL-AP to P is greater than the parallel state switching voltage V SL-P to AP , under the condition that the thickness of the reference layer in the magnetic tunnel junction is greater than the thickness of the pinned layer, by reducing the etching angle, the structural schematic diagram of the magnetic tunnel junction is as shown in Figure 7As shown, it is possible to achieve that the volume of the reference layer is larger than that of the pinned layer. The direction of the stray field generated by the pinned layer is negative, and the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the positive direction, so the magnetic bias field is adjusted in the positive direction, and the anti-parallel state flip voltage V BL-AP to P becomes smaller, and the parallel state flip voltage V SL-P to AP becomes larger, so as to achieve that V SL-P to AP and V BL-AP to P are substantially equal in magnitude.

[0117] Thirdly, adjust the first material of the first ferromagnetic repeating unit or adjust the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is less than that of the second material.

[0118] It should be noted that in this application, the types of the first material and the second material are not specifically limited, as long as it is ensured that the saturation magnetization intensity of the first material is less than that of the second material. For example, when the first material uses a material with a low saturation magnetization intensity, such as inserting a non-magnetic metal layer or doping a non-magnetic material in CoFeB, the second material uses a material with a high saturation magnetization intensity, such as CoFe alloy or (Co x Fe 1-x ) y B 1-y , where x is between 0.2 and 0.7, and y is between 0.5 and 1.

[0119] When the anti-parallel state flip voltage V BL-AP to P is greater than the parallel state flip voltage V SL-P to AP , the saturation magnetization intensity of the first material is less than that of the second material, so that the total magnetic moment of the pinned layer is less than that of the reference layer, and the Hoff value is adjusted in the positive direction, so the magnetic bias field is adjusted in the positive direction.

[0120] Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co x Fe y B z and (CoPt) n , where n≥1; the pinned layer is a (CoPt) m magnetic layer, where m≥1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

[0121] When the first erasable write count is greater than the second erasable write count, please refer to Figure 10 and Figure 11 respectively for the adjustment schematic diagrams of the magnetic bias field and the anti-parallel state flip voltage.

[0122] Step S306: When the first erasable write count is less than the second erasable write count, decrease the parallel state switching voltage or increase the anti-parallel state switching voltage, and adjust the magnetic bias field in the negative direction to balance the first erasable write count and the second erasable write count; wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the positive direction of the magnetic bias field is the same as the direction of the magnetic moment of the reference layer.

[0123] Optionally, there are three ways to decrease the parallel state switching voltage or increase the anti-parallel state switching voltage, which are introduced separately below.

[0124] First, increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or decrease the number of layers of the second ferromagnetic repeating unit in the reference layer.

[0125] Increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer can increase the stray field generated by the pinned layer. The direction of the stray field generated by the pinned layer is opposite to the direction of the magnetic moment of the reference layer, that is, the direction of the stray field generated by the pinned layer is negative. Decreasing the number of layers of the second ferromagnetic repeating unit in the reference layer can decrease the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, the parallel state switching voltage V SL-P to AP becomes smaller, and the anti-parallel state switching voltage V BL-AP to P becomes larger. The difference between V SL-P to AP and V BL-AP to P decreases, so that V SL-P to AP and V BL-AP to P are basically equal.

[0126] Second, increase the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not greater than the thickness of the pinned layer.

[0127] When the anti-parallel state switching voltage V BL-AP to P is less than the parallel state switching voltage V SL-P to AP , under the condition that the thickness of the reference layer is not greater than the thickness of the pinned layer, increasing the etching angle of the magnetic tunnel junction, the schematic structural diagram of the magnetic tunnel junction is as shown in Figure 8 . The larger the etching angle, the larger the volume difference between the pinned layer and the reference layer. The direction of the stray field generated by the pinned layer is negative, and the direction of the stray field generated by the reference layer is positive. The Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, the anti-parallel state switching voltage V BL-AP to P becomes larger, and the parallel state switching voltage V SL-P to AP becomes smaller, so that V SL-P to AP and V BL-AP to P are basically equal.

[0128] Thirdly, adjust the first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is greater than that of the second material.

[0129] It should be noted that the types of the first material and the second material in this application are not specifically limited, as long as the saturation magnetization intensity of the first material is greater than that of the second material.

[0130] When the anti-parallel state flip voltage V BL-AP to P is less than the parallel state flip voltage V SL-P to AP the saturation magnetization intensity of the first material is greater than that of the second material, so that the total magnetic moment of the pinning layer is greater than that of the reference layer, the Hoff value is adjusted negatively, and thus the magnetic bias field is adjusted negatively.

[0131] Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co x Fe y B z and (CoPt) n where n≥1; the pinning layer is a (CoPt) m magnetic layer, where m≥1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

[0132] In this embodiment, when balancing the first erasable write count and the second erasable write count, the parallel state flip voltage and the anti-parallel state flip voltage are also adjusted. It should be noted that when the first erasable write count and the second erasable write count reach balance, the parallel state flip voltage and the anti-parallel state flip voltage are not close or equal. That is, at this time, for the purpose of balancing the magnitudes of the first erasable write count and the second erasable write count, the magnitude relationship between the parallel state flip voltage and the anti-parallel state flip voltage does not need to be concerned. Balancing the first erasable write count and the second erasable write count can effectively improve the overall erasable write count of the magnetic memory.

[0133] This application also provides a magnetic memory, and the magnetic memory is used for the magnetic memory performance adjustment method described in any of the above embodiments.

[0134] After performing the above adjustment to reduce the writing difficulty on the magnetic memory, the parallel state flip voltage and the anti-parallel state flip voltage of the magnetic memory are balanced, and a common power supply can be shared. The difficulty of flipping between the parallel state and the anti-parallel state is low, and the writing difficulty of the magnetic memory is reduced.

[0135] After performing the above adjustment to increase the erasable write count on the magnetic memory, the overall erasable write count of the magnetic memory is improved.

[0136] In the present specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0137] The above has introduced in detail the magnetic memory and its flip voltage regulation method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only for helping to understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for adjusting the performance of a magnetic memory, characterized in that, Including: Receiving a performance adjustment instruction; Obtaining the parallel state switching voltage and the anti-parallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is in series with the CMOS circuit; Adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction; When the performance adjustment instruction is to reduce the writing difficulty, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes: Determining the magnitude relationship between the parallel state switching voltage and the anti-parallel state switching voltage; When the anti-parallel state switching voltage is greater than the parallel state switching voltage, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the parallel state switching voltage and the anti-parallel state switching voltage; When the anti-parallel state switching voltage is less than the parallel state switching voltage, decreasing the parallel state switching voltage or increasing the anti-parallel state switching voltage, and adjusting the magnetic bias field in the negative direction to balance the parallel state switching voltage and the anti-parallel state switching voltage; Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is positive in the direction same as the magnetic moment of the reference layer.

2. The magnetic memory performance adjustment method according to claim 1, wherein, When the performance adjustment instruction is to improve the number of erasable writes, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes: Obtaining a first number of erasable writes of the magnetic tunnel junction from the parallel state to the anti-parallel state and a second number of erasable writes from the anti-parallel state to the parallel state; Determining the magnitude relationship between the first number of erasable writes and the second number of erasable writes; When the first number of erasable writes is greater than the second number of erasable writes, increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the positive direction to balance the first number of erasable writes and the second number of erasable writes; When the first number of erasable writes is less than the second number of erasable writes, decreasing the parallel state switching voltage or increasing the anti-parallel state switching voltage, and adjusting the magnetic bias field in the negative direction to balance the first number of erasable writes and the second number of erasable writes; Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is positive in the direction same as the magnetic moment of the reference layer.

3. The magnetic memory performance adjustment method according to claim 1 or 2, characterized in that, The increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes: Reducing the number of layers of the first ferromagnetic repeating unit in the pinned layer or increasing the number of layers of the second ferromagnetic repeating unit in the reference layer.

4. The method for adjusting the performance of a magnetic memory according to claim 1 or 2, characterized in that, The increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes: Reducing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is greater than the thickness of the pinned layer.

5. The method for adjusting the performance of a magnetic memory according to claim 1 or 2, characterized in that, The increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage includes: Adjusting the first material of the first ferromagnetic repeating unit or adjusting the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is less than the saturation magnetization intensity of the second material.

6. The method for adjusting the performance of a magnetic memory according to claim 1 or 2, characterized in that, Reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes: Increasing the number of layers of the first ferromagnetic repeating unit in the pinning layer or decreasing the number of layers of the second ferromagnetic repeating unit in the reference layer.

7. The magnetic memory performance adjustment method according to claim 1 or 2, characterized in that Reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes: Increasing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.

8. The magnetic memory performance adjustment method according to claim 1 or 2, characterized in that Reducing the parallel state switching voltage or increasing the antiparallel state switching voltage includes: Adjusting the first material of the first ferromagnetic repeating unit or adjusting the second material of the second ferromagnetic repeating unit so that the saturation magnetization intensity of the first material is greater than that of the second material.

9. The magnetic memory performance adjustment method according to claim 3, wherein Further includes: Thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.

10. The method for adjusting the performance of a magnetic memory according to claim 6, wherein, Further includes: Increasing the thickness of the first ferromagnetic repeating unit or thinning the thickness of the second ferromagnetic repeating unit.

11. The method for adjusting the performance of a magnetic memory according to claim 1, characterized in that, Obtaining the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes: Measuring the testkey of the magnetic tunnel junction connected in series with the CMOS circuit to obtain the parallel state switching voltage and the antiparallel state switching voltage; Alternatively, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the antiparallel state switching voltage.

12. The method for adjusting the performance of a magnetic memory according to claim 1 or 2, characterized in that, The reference layer is Co x Fe y B z and the coupling structure layer with (CoPt) n , where n≥1; the pinning layer is (CoPt) m magnetic layer, where m≥1 and m>n.

13. A magnetic memory, characterized in that, The magnetic memory is used to implement the magnetic memory performance adjustment method according to any one of claims 1 to 12.

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