Data writing method and apparatus and storage medium

Abstract

This disclosure relates to a data writing method and apparatus for NAND flash memory, as well as a storage medium. The method includes: a pairing step for pairing all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs; and a writing step for sequentially writing data to one identical page from a plurality of pages corresponding to the programming mode of each word line of each LUN in the LUN pair for each LUN pair. After completing the data writing to the identical page of the word line of all LUNs in the LUN pair, data is sequentially written to the next identical page from the plurality of pages of the word line of each LUN in the LUN pair, and so on, until the last identical page from the plurality of pages of the word line of each LUN in the LUN pair is sequentially written. This improves the transmission efficiency of the NAND bus, thereby enhancing the data writing performance of the NAND flash memory.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a data writing method, apparatus, and storage medium. Background Technology

[0002] Solid State Drive (SSD) is a hard drive made using an array of solid-state electronic storage chips. An SSD can use NAND flash memory as its storage medium. An SSD can include an SSD controller and multiple NAND flash memory chips, which are placed on a printed circuit board (PCB) and connected together.

[0003] The NAND controller can communicate with several NAND channels. Each channel is connected to one or more CE (Chip Enable) signals, and each CE can correspond to one or more Logic Units (LUNs). Therefore, there may be multiple LUNs on a single channel.

[0004] For channels where the NAND controller is connected to the CE group, all targets and LUNs share the same NAND bus. Therefore, the transmission efficiency of the NAND bus can affect the data write performance of the NAND flash memory. Summary of the Invention

[0005] In view of this, the present disclosure proposes a data writing method, apparatus, and storage medium to improve the transmission efficiency of the NAND bus, thereby improving the data writing performance of NAND flash memory.

[0006] According to a first aspect of this disclosure, a data writing method for NAND flash memory is provided, applied to a NAND controller. The method includes: a pairing step for pairing all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs; and a writing step for writing data to each LUN pair, sequentially writing data to one identical page from a plurality of pages corresponding to a programming mode included in each word line of each LUN in the LUN pair, after completing the data writing to the identical page of the word line of all LUNs in the LUN pair, sequentially writing data to the next identical page from the plurality of pages of the word line of each LUN in the LUN pair, ..., and so on, until the last identical page from the plurality of pages of the word line of each LUN in the LUN pair is sequentially written.

[0007] In one possible implementation, for each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and an UP page. For each word line of each LUN pair, data is written as follows: data is written to the LP page of the first LUN in the LUN pair; data is written to the LP page of the second LUN in the LUN pair; data is written to the MP page of the first LUN in the LUN pair; data is written to the MP page of the second LUN in the LUN pair; data is written to the UP page of the first LUN in the LUN pair; and data is written to the UP page of the second LUN in the LUN pair.

[0008] In one possible implementation, for each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page. For each word line of each LUN pair, data is written as follows: data is written to the LP page of the first LUN in the LUN pair; data is written to the LP page of the second LUN in the LUN pair; data is written to the MP page of the first LUN in the LUN pair; data is written to the MP page of the second LUN in the LUN pair; data is written to the UP page of the first LUN in the LUN pair; data is written to the UP page of the second LUN in the LUN pair; data is written to the TP page of the first LUN in the LUN pair; and data is written to the TP page of the second LUN in the LUN pair.

[0009] In one possible implementation, the pairing step includes: determining the number of LUNs included in a LUN pair for each channel of the NAND flash memory; and pairing all LUNs within the channel such that each LUN pair includes the determined number of LUNs.

[0010] In one possible implementation, determining the number of LUNs included in a LUN pair includes: calculating the ratio of programming cache busy time to data transfer time; if the ratio is less than 1, determining that each LUN pair includes 2 LUNs; if the ratio is equal to M, determining that each LUN pair includes M+1 LUNs, where M is an integer greater than 1.

[0011] According to a second aspect of this disclosure, a data writing apparatus for NAND flash memory is provided, applied to a NAND controller. The apparatus includes: a pairing module for pairing all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs; and a writing module for sequentially writing data to one identical page from a plurality of pages corresponding to a programming mode included in each word line of each LUN in the LUN pair for each LUN pair, wherein after completing the data writing to the identical page of the word line of all LUNs in the LUN pair, data is sequentially written to the next identical page from the plurality of pages of the word line of each LUN in the LUN pair, ..., and so on, until the last identical page from the plurality of pages of the word line of each LUN in the LUN pair is sequentially written.

[0012] In one possible implementation, the pairing module is configured to: pair all LUNs within each channel of the NAND flash memory such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and an UP page; the writing module is configured to: write data to each word line of each LUN pair as follows: write data to the LP page of the first LUN in the LUN pair; write data to the LP page of the second LUN in the LUN pair; write data to the MP page of the first LUN in the LUN pair; write data to the MP page of the second LUN in the LUN pair; write data to the UP page of the first LUN in the LUN pair; and write data to the UP page of the second LUN in the LUN pair.

[0013] In one possible implementation, the pairing module is configured to: pair all LUNs within each channel of the NAND flash memory such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page; the writing module is configured to: write data to each word line of each LUN pair in the following manner: write data to the LP page of the first LUN in the LUN pair; write data to the LP page of the second LUN in the LUN pair; write data to the MP page of the first LUN in the LUN pair; write data to the MP page of the second LUN in the LUN pair; write data to the UP page of the first LUN in the LUN pair; write data to the UP page of the second LUN in the LUN pair; write data to the TP page of the first LUN in the LUN pair; and write data to the TP page of the second LUN in the LUN pair.

[0014] In one possible implementation, the pairing module is configured to: determine the number of LUNs included in a LUN pair for each channel of the NAND flash memory; and pair all LUNs within the channel such that each LUN pair includes the determined number of LUNs.

[0015] In one possible implementation, the pairing module is configured to: calculate the ratio of the programming cache busy time to the data transfer time; if the ratio is less than 1, determine that each LUN pair includes 2 LUNs; if the ratio is equal to M, determine that each LUN pair includes M+1 LUNs, where M is an integer greater than 1.

[0016] According to a third aspect of this disclosure, a data writing apparatus is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing instructions stored in the memory.

[0017] According to a fourth aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0018] According to a fifth aspect of this disclosure, a computer program product is provided, including computer-readable code or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0019] According to the data writing method, apparatus, and storage medium disclosed herein, all LUNs in each channel of the NAND flash memory are first paired, and then data transmission is performed alternately for each LUN pair. In this way, even if the tPCBSY is short, it is not wasted. During the brief busy period of a LUN, data transmission of the remaining LUNs in the LUN pair can be performed. Therefore, the short tPCBSY is effectively utilized for alternating data transmission, thereby improving the transmission efficiency of the NAND bus, thereby improving the data writing performance of the NAND flash memory, and even bringing the data writing performance of the NAND flash memory closer to its limit.

[0020] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0022] Figure 1a This is an example diagram illustrating data writing to an SSD under normal conditions, according to an exemplary embodiment.

[0023] Figure 1b This is an example diagram illustrating data writing to a large-capacity SSD according to an exemplary embodiment.

[0024] Figure 1c This is a flowchart illustrating a data writing method according to an exemplary embodiment.

[0025] Figure 1d This is an example diagram illustrating the data writing process after writing data to a large-capacity SSD using the data writing method of this embodiment, according to an exemplary embodiment.

[0026] Figure 2 This is a flowchart illustrating a data writing method according to an exemplary embodiment.

[0027] Figure 3 This is a flowchart illustrating a data writing method according to an exemplary embodiment.

[0028] Figure 4 This is a flowchart illustrating a data writing method according to an exemplary embodiment.

[0029] Figure 5 This is a block diagram illustrating a data writing device according to an exemplary embodiment.

[0030] Figure 6 This is a block diagram illustrating a data writing device according to an exemplary embodiment.

[0031] Figure 7 This is a system architecture block diagram of a data writing device according to an exemplary embodiment. Detailed Implementation

[0032] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0033] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0034] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0035] It should be understood that each LUN can include one or more planes, each plane can include multiple blocks, each block can include multiple word lines (WLs), and each word line can include one or more pages. For example, each NAND flash memory can include two targets, each target can include one LUN, and this LUN can include two planes, each plane can include 1478 blocks, and each block can include 768 pages. Alternatively, each NAND flash memory can include four targets, each target can include two LUNs, each LUN can include two planes, each plane can include 4096 blocks, and each block can include 256 pages.

[0036] NAND flash memory programming modes can include Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quadruple-Level Cell (QLC). When programming in SLC mode, one page is programmed per cycle; in MLC mode, two pages are programmed per cycle; in TLC mode, the LP (low page), MP (middle page), and UP (upper page) pages are programmed simultaneously per cycle; and in QLC mode, all four pages (LP, MP, UP, and TP) pages are programmed simultaneously per cycle.

[0037] Taking TCL as an example, each word line can include three pages: LP, MP, and UP. Taking QLC as an example, each word line can include four pages: LP, MP, UP, and TP.

[0038] Taking TLC mode programming as an example, after programming the LP page and MP page, there is a Program Cache Busy Time (tPCBSY). tPCBSY is relatively short, generally less than 5 microseconds (us). In contrast, after programming the UP page, there is a Program Operation Time (tPROG). tPROG is relatively long, possibly 2 or 3 milliseconds (ms).

[0039] Since each channel may connect to multiple targets, and each target may include one or more LUNs, a single channel may have multiple targets and multiple LUNs sharing the same NAND bus. For each WL of each LUN, the LP page / MP page / UP page needs to be programmed sequentially.

[0040] In related technologies, it is assumed that each LUN includes WL1, WL2, WL3…WL N-1 WL NFor each LUN, first program the WL1 of a LUN in the order of LP page / MP page / UP page, then program the WL1 of the next LUN in the same order, and so on, until all LUNs have been traversed. Then, program the WL2 of a LUN in the same order, and so on, until all LUNs have been traversed. Then, following the order of LP page / MP page / UP page, program the WL2 of the next LUN until all LUNs have been traversed; then start programming the WL3 of a LUN following the order of LP page / MP page / UP page, then program the WL3 of the next LUN following the order of LP page / MP page / UP page, then program the WL3 of the next LUN following the order of LP page / MP page / UP page, and so on, until all LUNs have been traversed; ..., and so on, until all LUNs have been traversed. N until.

[0041] However, when supporting large-capacity SSDs is required, or when the NAND bus transfer speed is slow, there is a busy period (tPCBSY) between programming the LP page and the MP page, and between programming the MP page and the UP page (or between programming the UP page and the TP page if programming in QLC mode). During this busy period, no data is transferred, meaning the NAND bus is idle.

[0042] If the NAND bus is not a performance bottleneck for NAND flash memory (e.g., the NAND flash memory capacity is relatively small, the number of LUNs is relatively small, or the NAND bus transmission speed is relatively fast), the transmission efficiency of the NAND bus should be sufficient to meet the data write performance requirements of the NAND flash memory, and therefore there may be no need to improve the transmission efficiency of the NAND bus.

[0043] For example, suppose a NAND flash memory channel has four LUNs: LUN0, LUN1, LUN2, and LUN3 (i.e., the number of LUNs is relatively small), then, as Figure 1aAs shown, each word line of these four LUNs is programmed as follows: LUN0's LP page is programmed; LUN0's MP page is programmed; LUN0's UP page is programmed; LUN1's LP page is programmed; LUN1's MP page is programmed; LUN1's UP page is programmed; LUN2's LP page is programmed; LUN2's MP page is programmed; LUN2's UP page is programmed; LUN3's LP page is programmed; LUN3's MP page is programmed; LUN3's UP page is programmed. Therefore, tPCBSY has little impact on NAND flash memory performance. In contrast, tPROG has a greater impact on NAND flash memory performance; that is, tPROG is the performance bottleneck of NAND flash memory. Therefore, it is not a problem if the NAND bus waits for tPCBSY for a short period of time.

[0044] However, when the NAND bus becomes a performance bottleneck for NAND flash memory (e.g., the NAND flash memory capacity is too large, the number of LUNs is too large, and / or the NAND bus transmission speed is too slow), the transmission efficiency of the NAND bus may not meet the data write performance requirements of the NAND flash memory. Therefore, the efficiency of the NAND bus needs to be improved, and the data write performance of the NAND flash memory needs to be enhanced.

[0045] For example, suppose a NAND flash memory channel has eight LUNs: LUN0, LUN1, LUN2, LUN3, LUN4, LUN5, LUN6, and LUN7 (i.e., the number of LUNs is relatively large). Then, if... Figure 1b As shown, each word line of these 8 LUNs is programmed as follows: The LP page of LUN0 is programmed; the MP page of LUN0 is programmed; the UP page of LUN0 is programmed; the LP page of LUN1 is programmed; the MP page of LUN1 is programmed; the UP page of LUN1 is programmed; the LP page of LUN2 is programmed; the MP page of LUN2 is programmed; the UP page of LUN2 is programmed; the LP page of LUN3 is programmed; the MP page of LUN3 is programmed; the L... Program the UP page of LUN3; program the LP page of LUN4; program the MP page of LUN4; program the UP page of LUN4; program the LP page of LUN5; program the MP page of LUN5; program the UP page of LUN5; program the LP page of LUN6; program the MP page of LUN6; program the UP page of LUN6; program the LP page of LUN7; program the MP page of LUN7; program the UP page of LUN7.

[0046] Reference Figure 1b During the busy period between the LP and MP pages, the NAND controller waits for the NAND bus, which is idle and does not transmit data. Meanwhile, due to the large number of LUNs, a word line such as WL... N The time corresponding to the transmitted data of a LUN and the next word line, such as WL N+1 The time interval between the data transmissions of the corresponding LUN is relatively long, exceeding tPROG. The LUN still needs to wait for the NAND bus transmission, meaning that no data writing operation has been performed inside the NAND array.

[0047] Therefore, at different times, the NAND bus and NAND array may wait for each other, that is, the NAND bus is not transmitting data and the NAND array is not performing data writing operations, which may result in the NAND flash memory's data writing performance being less than ideal.

[0048] Therefore, this disclosure proposes a data writing method, apparatus, and storage medium to improve the transmission efficiency of the NAND bus, thereby improving the data writing performance of NAND flash memory.

[0049] Figure 1c A flowchart illustrating a data writing method for NAND flash memory according to an embodiment of the present disclosure is shown. This data writing method can be applied to a NAND controller for NAND flash memory. Figure 1c As shown, the data writing method may include the following steps:

[0050] In step S110, for each channel of the NAND flash memory, all LUNs within that channel are paired so that each LUN pair includes at least two LUNs. This step corresponds to the pairing step.

[0051] In this embodiment, there are multiple LUNs on each channel. All LUNs on each channel can be grouped according to a predetermined pairing method. Each group of LUNs can be called a LUN pair, and each LUN pair can include two or more LUNs.

[0052] In one possible implementation, the predetermined pairing method involves grouping all LUNs on each channel such that each group of LUNs includes 2 LUNs. For example, for Figure 1bFor the NAND flash memory shown, there are 8 LUNs in one channel: LUN0, LUN1, LUN2, LUN3, LUN4, LUN5, LUN6, and LUN7. According to the predetermined pairing method, the 8 LUNs included in this channel can be grouped into 4 LUN pairs. These 4 LUN pairs are: the first LUN pair consisting of LUN0 and LUN1, the second LUN pair consisting of LUN2 and LUN3, the third LUN pair consisting of LUN4 and LUN5, and the fourth LUN pair consisting of LUN6 and LUN7.

[0053] In one possible implementation, the predetermined pairing method includes grouping all LUNs on each channel such that each group of LUNs includes a predetermined number of LUNs, where the predetermined number is related to tPCBSY. For example, for Figure 1b For the NAND flash memory shown, the 8 LUNs included in the channel are grouped according to the predetermined pairing method. These 8 LUNs can be grouped into (8 / predetermined number) LUN pairs. Assuming the predetermined number is 4, these 8 LUNs can be grouped into 2 LUN pairs. These 2 LUN pairs are: the first LUN pair consisting of LUN0, LUN1, LUN2 and LUN3, and the second LUN pair consisting of LUN4, LUN5, LUN6 and LUN7.

[0054] After pairing all LUNs within the channel, perform the following step S130.

[0055] In step S130, for each LUN pair, data is sequentially written to the same page among the multiple pages corresponding to the programming mode included in each word line of each LUN in the LUN pair. After completing the data writing to the same page of the word line of all LUNs in the LUN pair, data is sequentially written to the next same page among the multiple pages of the word line of each LUN in the LUN pair, and so on, until the last same page among the multiple pages of the word line of each LUN in the LUN pair is sequentially written. This step corresponds to the write step.

[0056] In this embodiment, for each LUN pair, data is sequentially written to the first page of the plurality of pages corresponding to the programming mode included in each word line of each LUN in the LUN pair. After the data writing to the first page of the word line of all LUNs in the LUN pair is completed, data is sequentially written to the second page of the plurality of pages of the word line of each LUN in the LUN pair. After the data writing to the second page of the word line of all LUNs in the LUN pair is completed, data is sequentially written to the third page of the plurality of pages of the word line of each LUN in the LUN pair, and so on, until the data writing to the last page of the plurality of pages of the word line of each LUN in the LUN pair is completed.

[0057] The number of pages (i.e., the multiple pages mentioned above) corresponding to the programming mode included in each word line varies depending on the programming mode of the NAND flash memory. For TLC mode, each word line includes 3 pages, namely LP page, MP page, and UP page. For QLC mode, each word line includes 4 pages, namely LP page, MP page, UP page, and TP page.

[0058] In one possible implementation, for each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and an UP page. For each word line of each LUN pair, data is written as follows: data is written to the LP page of the first LUN in the LUN pair; data is written to the LP page of the second LUN in the LUN pair; data is written to the MP page of the first LUN in the LUN pair; data is written to the MP page of the second LUN in the LUN pair; data is written to the UP page of the first LUN in the LUN pair; and data is written to the UP page of the second LUN in the LUN pair.

[0059] See Figure 2In step S210, for each channel of the NAND flash memory, all LUNs in the channel can be paired by grouping them into pairs, such that each group of LUNs includes two LUNs. Each LUN pair includes a first LUN and a second LUN, and is programmed using TLC mode. Therefore, each word line of the first LUN and the second LUN each includes an LP page, an MP page, and an UP page. Correspondingly, in step S230, data can be written to each word line pair of each LUN in the following manner: Data is written sequentially to the LP pages of the first LUN and the second LUN in the LUN pair; data is written sequentially to the MP pages of the first LUN and the second LUN in the LUN pair; and data is written sequentially to the UP pages of the first LUN and the second LUN in the LUN pair.

[0060] Continuing with the example above, for Figure 1b For the NAND flash memory shown, assuming that the eight LUNs (LUN0, LUN1, LUN2, LUN3, LUN4, LUN5, LUN6, and LUN7) on a channel are grouped according to a predetermined pairing method into a first LUN pair consisting of LUN0 and LUN1, a second LUN pair consisting of LUN2 and LUN3, a third LUN pair consisting of LUN4 and LUN5, and a fourth LUN pair consisting of LUN6 and LUN7, and programming is performed using TLC mode, data can be written as follows:

[0061] For each word line of the first LUN pair, data is written to the LP page of LUN0 in the first LUN pair, then data is written to the LP page of LUN1 in the first LUN pair, data is written to the MP page of LUN0 in the first LUN pair, then data is written to the MP page of LUN1 in the first LUN pair, data is written to the UP page of LUN0 in the first LUN pair, and then data is written to the UP page of LUN1 in the first LUN pair.

[0062] For each word line of the second LUN pair, data is written to the LP page of LUN2 in the second LUN pair, then data is written to the LP page of LUN3 in the second LUN pair, data is written to the MP page of LUN2 in the second LUN pair, then data is written to the MP page of LUN3 in the second LUN pair, data is written to the UP page of LUN2 in the second LUN pair, and then data is written to the UP page of LUN3 in the second LUN pair.

[0063] For each word line of the third LUN pair, data is written to the LP page of LUN4 in the third LUN pair, then data is written to the LP page of LUN5 in the third LUN pair, data is written to the MP page of LUN4 in the third LUN pair, then data is written to the MP page of LUN5 in the third LUN pair, data is written to the UP page of LUN4 in the third LUN pair, and then data is written to the UP page of LUN5 in the third LUN pair.

[0064] For each word line of the fourth LUN pair, data is written to the LP page of LUN6 in the fourth LUN pair, then data is written to the LP page of LUN7 in the fourth LUN pair, data is written to the MP page of LUN6 in the fourth LUN pair, then data is written to the MP page of LUN7 in the fourth LUN pair, data is written to the UP page of LUN6 in the fourth LUN pair, and then data is written to the UP page of LUN7 in the fourth LUN pair.

[0065] Therefore, data transmission is performed sequentially and alternately for each word line of the first LUN pair, the second LUN pair, the third LUN pair, and the fourth LUN pair. In this way, during tPCBSY, data transmission can be performed for another LUN in the LUN pair. This effectively utilizes the brief busy time between the LP page and the MP page, as well as the brief busy time between the MP page and the UP page, thereby improving the transmission efficiency of the NAND bus and thus improving the data write performance of the NAND flash memory.

[0066] Compared to data writing using existing technologies (see diagram for data writing diagram), Figure 1b This embodiment uses the data writing method to write data to a large-capacity SSD. See [link / reference]. Figure 1d LUN pairs alternately transmit data, so even though tPCBSY is short, it is not wasted. During a short busy period of a LUN, data of the LUN pair can be transmitted. Therefore, the short tPCBSY is effectively utilized for data transmission, thereby improving the transmission efficiency of the NAND bus and thus improving the data write performance of NAND flash memory.

[0067] In one possible implementation, for each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page. For each word line of each LUN pair, data is written as follows: data is written to the LP page of the first LUN in the LUN pair; data is written to the LP page of the second LUN in the LUN pair; data is written to the MP page of the first LUN in the LUN pair; data is written to the MP page of the second LUN in the LUN pair; data is written to the UP page of the first LUN in the LUN pair; data is written to the UP page of the second LUN in the LUN pair; data is written to the TP page of the first LUN in the LUN pair; and data is written to the TP page of the second LUN in the LUN pair.

[0068] See Figure 3 In step S310, for each channel of the NAND flash memory, all LUNs in the channel can be paired by grouping them into pairs, such that each pair includes a first LUN and a second LUN. Programming is performed using QLC mode, therefore each word line of the first LUN and the second LUN includes an LP page, an MP page, an UP page, and a TP page. Correspondingly, in step S330, data can be written to each word line of each LUN pair as follows: Data is written sequentially to the LP pages of the first and second LUNs in the LUN pair; data is written sequentially to the MP pages of the first and second LUNs in the LUN pair; data is written sequentially to the UP pages of the first and second LUNs in the LUN pair; and data is written sequentially to the TP pages of the first and second LUNs in the LUN pair.

[0069] Continuing the example above, suppose the eight LUNs (LUN0, LUN1, LUN2, LUN3, LUN4, LUN5, LUN6, and LUN7) on a channel are grouped according to a predetermined pairing method into a first LUN pair consisting of LUN0 and LUN1, a second LUN pair consisting of LUN2 and LUN3, a third LUN pair consisting of LUN4 and LUN5, and a fourth LUN pair consisting of LUN6 and LUN7. And if QLC mode is used for programming, data can be written as follows:

[0070] For each word line of the first LUN pair, data is written to the LP page of LUN0 in the first LUN pair, then data is written to the LP page of LUN1 in the first LUN pair, data is written to the MP page of LUN0 in the first LUN pair, then data is written to the MP page of LUN1 in the first LUN pair, data is written to the UP page of LUN0 in the first LUN pair, then data is written to the UP page of LUN1 in the first LUN pair, data is written to the TP page of LUN0 in the first LUN pair, then data is written to the TP page of LUN1 in the first LUN pair.

[0071] For each word line of the second LUN pair, data is written to the LP page of LUN2 in the second LUN pair, then data is written to the LP page of LUN3 in the second LUN pair, data is written to the MP page of LUN2 in the second LUN pair, then data is written to the MP page of LUN3 in the second LUN pair, data is written to the UP page of LUN2 in the second LUN pair, then data is written to the UP page of LUN3 in the second LUN pair, data is written to the TP page of LUN2 in the second LUN pair, then data is written to the TP page of LUN3 in the second LUN pair.

[0072] For each word line of the third LUN pair, data is written to the LP page of LUN4 in the third LUN pair, then data is written to the LP page of LUN5 in the third LUN pair, data is written to the MP page of LUN4 in the third LUN pair, then data is written to the MP page of LUN5 in the third LUN pair, data is written to the UP page of LUN4 in the third LUN pair, then data is written to the UP page of LUN5 in the third LUN pair, data is written to the TP page of LUN4 in the third LUN pair, then data is written to the TP page of LUN5 in the third LUN pair.

[0073] For each word line of the fourth LUN pair, data is written to the LP page of LUN6 in the fourth LUN pair, then data is written to the LP page of LUN7 in the fourth LUN pair, data is written to the MP page of LUN6 in the fourth LUN pair, then data is written to the MP page of LUN7 in the fourth LUN pair, data is written to the UP page of LUN6 in the fourth LUN pair, then data is written to the UP page of LUN7 in the fourth LUN pair, data is written to the TP page of LUN6 in the fourth LUN pair, and then data is written to the TP page of LUN7 in the fourth LUN pair.

[0074] Therefore, data transmission is performed sequentially and alternately on each word line of the first, second, third, and fourth LUN pairs. In this way, during tPCBSY, data transmission can be performed on another LUN in the LUN pair. This effectively utilizes the brief busy times between the LP and MP pages, the brief busy times between the MP and UP pages, and the brief busy times between the UP and TP pages, thereby improving the transmission efficiency of the NAND bus and thus improving the data write performance of the NAND flash memory.

[0075] Therefore, according to the data writing method of this embodiment, all LUNs in each channel of the NAND flash memory are first paired, and then data is transmitted alternately for each word line of each LUN pair. In this way, even if tPCBSY is short, it is not wasted. During the short busy period of a LUN, the data transmission of the remaining LUNs in the LUN pair can be carried out. Therefore, the short tPCBSY is effectively utilized for data transmission, thereby improving the transmission efficiency of the NAND bus, thereby improving the data writing performance of the NAND flash memory, and even making the data writing performance of the NAND flash memory closer to the limit level.

[0076] In one possible implementation, all LUNs within a channel can be paired as follows: for each channel of the NAND flash memory, determine the number of LUNs included in a LUN pair; pair all LUNs within the channel such that each LUN pair includes the determined number of LUNs.

[0077] In this embodiment, the pairing method used for pairing is related to the number of LUNs included in the paired LUN pair. Therefore, the number of LUNs included in the LUN pair can be determined according to the pairing method used for pairing. For example, assuming the pairing method used for pairing is to group all LUNs on each channel so that each group of LUNs includes 2 LUNs, the number of LUNs included in the LUN pair can be determined to be 2 according to this pairing method. Then, this number of adjacent LUNs in the channel can be paired into a LUN pair. Continuing this example, every 2 LUNs in the same channel can be paired. Specific examples of pairing can be found in the previous description of step S110, and will not be repeated here.

[0078] In one possible implementation, the number of LUNs included in a LUN pair can be determined as follows: calculate the ratio of programming cache busy time (tPCBSY) to data transfer time; if the ratio is less than 1, determine that each LUN pair includes 2 LUNs; if the ratio is equal to M, determine that each LUN pair includes M+1 LUNs, where M is an integer greater than 1.

[0079] See Figure 4 The number of LUNs included in a LUN pair can be determined by executing steps S410, S420, and S430. Specifically, the ratio of tPCBSY to the data transmission time can be calculated; it can be determined whether the ratio is less than 1 or greater than 1. If the ratio is less than 1, it means that the data transmission time is greater than tPCBSY, and pairing them up is appropriate. Therefore, the number of LUNs included in a LUN pair is 2. Typically, tPCBSY is short, generally less than 5 microseconds, which is less than the data transmission time, so pairing them up is suitable.

[0080] If the ratio is greater than 1, for example, tPCBSY = M times the data transmission time, then M+1 LUNs are paired, meaning the number of LUNs included in a LUN pair is M+1. Therefore, M LUNs can be transmitted during tPCBSY.

[0081] Figure 5 This is a block diagram illustrating a data writing apparatus according to an exemplary embodiment. The data writing apparatus 500 can be applied to a NAND controller of NAND flash memory. Figure 5 As shown, the data writing device 500 may include a pairing module 510 and a writing module 520.

[0082] The pairing module 510 is used to pair all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs. The writing module 520 is connected to the pairing module 510 and is used to write data to one identical page in the plurality of pages corresponding to the programming mode of each word line of each LUN in the LUN pair for each LUN pair. After completing the data writing of the identical page of the word line of all LUNs in the LUN pair, the next identical page in the plurality of pages of the word line of each LUN in the LUN pair is written data sequentially, and so on, until the last identical page in the plurality of pages of the word line of each LUN in the LUN pair is written data sequentially.

[0083] In one possible implementation, the pairing module 510 can be configured to pair all LUNs within each channel of the NAND flash memory, such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and an UP page. The writing module 520 can be configured to write data to each word line of each LUN pair as follows: write data to the LP page of the first LUN in the LUN pair; write data to the LP page of the second LUN in the LUN pair; write data to the MP page of the first LUN in the LUN pair; write data to the MP page of the second LUN in the LUN pair; write data to the UP page of the first LUN in the LUN pair; and write data to the UP page of the second LUN in the LUN pair.

[0084] In one possible implementation, the pairing module 510 can be configured to pair all LUNs within each channel of the NAND flash memory, such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page. The writing module 520 can be configured to write data to each word line of each LUN pair as follows: write data to the LP page of the first LUN in the LUN pair; write data to the LP page of the second LUN in the LUN pair; write data to the MP page of the first LUN in the LUN pair; write data to the MP page of the second LUN in the LUN pair; write data to the UP page of the first LUN in the LUN pair; write data to the UP page of the second LUN in the LUN pair; write data to the TP page of the first LUN in the LUN pair; and write data to the TP page of the second LUN in the LUN pair.

[0085] In one possible implementation, the pairing module 510 may be configured to: determine the number of LUNs included in a LUN pair for each channel of the NAND flash memory; and pair all LUNs in the channel such that each LUN pair includes the determined number of LUNs.

[0086] In one possible implementation, the pairing module 510 may be configured to: calculate the ratio of programming cache busy time to data transfer time; if the ratio is less than 1, determine that each LUN pair includes 2 LUNs; if the ratio is equal to M, determine that each LUN pair includes M+1 LUNs, where M is an integer greater than 1.

[0087] Figure 6 This is a block diagram illustrating a data writing apparatus according to an exemplary embodiment. (Refer to...) Figure 6 The data writing device 600 may include a processor 601 and a machine-readable storage medium 602 storing machine-executable instructions. The processor 601 and the machine-readable storage medium 602 can communicate via a system bus 603. Furthermore, the processor 601 executes the data writing method described above by reading the machine-executable instructions corresponding to the data writing method of the data writing device from the machine-readable storage medium 602.

[0088] The machine-readable storage medium 602 mentioned herein can be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, etc. For example, a machine-readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid-state drive, any type of storage disk (such as optical disc, DVD, etc.), or similar storage media, or combinations thereof.

[0089] Figure 7 This is a system architecture block diagram illustrating a data writing device according to an exemplary embodiment. Please refer to... Figure 7 The system may include: CPU subsystem 710, DDR_TOP 720, PMU 730, AXI FABRIC 740, NCB 750, BTN760, SRAM 770, PCIe PHY 780, PCIe MAC 790, and NVMe 791.

[0090] The CPU subsystem 710 may include a 4-Cortex R5 711 CPU and peripherals 712. The 4-Cortex R5 711 is an ARM CPU that can run corresponding software. Peripherals 712 can connect to SPI / UART / SMB. SPI (Serial Peripheral Interface) means that the CPU subsystem 710 can connect to an external SPI FLASH via SPI. UART (Universal Asynchronous Receiver / Transmitter) means that the CPU subsystem 710 can connect to a universal asynchronous receiver / transmitter. SMB (System Management Bus) means that the CPU subsystem 710 can be used for debugging.

[0091] The DDR_TOP 720 is a DDR (Double Data Rate) memory controller used to manage DDR memory. The DDR_TOP 720 can connect to and manage external DDR memory via the DDR I / F (interface). The AXI (Advanced eXtensible Interface) FABRIC 740 is an AXI bus used to connect various modules. For example, the DDR_TOP 720 can be connected to the BTN 760 via the AXI FABRIC 740. The BTN (Buffer Table NAND) 760 manages the dtags (data tags) in the SRAM 770, a block of memory that stores programs and data, approximately several megabytes in size. A portion of the SRAM 770 is allocated to store host data, typically around 4KB, with each dtag representing a 4KB storage unit.

[0092] The PMU (Power Management Unit) 730 is a power management unit. When idle, the host triggers the PMU 730, or the PMU 730 triggers itself, to enter a low-power mode, thus achieving low power consumption. The PCIe (Peripheral Component Interconnect Express) PHY (Physical Layer) 780 and PCIe MAC (Media Access Control) 790 are the front-end interface components, connecting to the motherboard slot. The NVMe (Non-Volatile Memory Express) 791 is the front-end NVMe protocol processing component.

[0093] NCB (NAND Control Block) 750 represents the NAND control block, which may include ECCU 751, FICU 752, and NDCU 753. Among them, ECCU (Error Correction & Control Unit) 751 represents the error correction and control unit, which is mainly used to perform ECC error correction when encoding and decoding data. This is because, considering that the data written to NAND flash memory may contain error bits, if ECC parity and cyclic redundancy check (CRC) are performed on the data written to NAND flash memory, then when reading the written data from NAND flash memory, decoding and error detection can be performed. If an error is detected, ECC error correction is performed.

[0094] FICU (Flash Instruction Control Unit) 752 represents the Flash Instruction Control Unit, primarily used for communication between the firmware and NCB hardware. It primarily uses more abstract instructions for this communication. FICU 752 can parse these abstract instructions, and if the parsing is complete, it can notify the firmware that the command has been completed.

[0095] NDCU (NAND Control Unit) 753 represents the NAND control unit. In other words, NDCU 753 can correspond to a NAND controller, and its main functions include configuring the NAND protocol, sending corresponding commands, and performing signal-related configuration processing. Please refer to [link to relevant documentation]. Figure 7 The NCB 750 also has eight channels: Channel 0, Channel 1... Channel 6, and Channel 7. Of course, it should be understood that the NCB 750 can be configured with other numbers of channels, but due to space limitations, this will not be discussed further. For the configuration and description of each channel, please refer to the previous section on channels; it will not be repeated here.

[0096] It should be understood that the data writing method and apparatus of this embodiment can be used for Figure 7 In one possible implementation of the system shown, the data writing method and apparatus can be applied to the NDCU 753 in the system when the system is running, thereby improving the transmission efficiency of the NAND bus and thus improving the data writing performance of the NAND flash memory.

[0097] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0098] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0099] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in the processor of a data writing device, the processor in the data writing device executes the above-described data writing method.

[0100] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for writing data to NAND flash memory, applied to a NAND controller, characterized in that, include: The pairing step is used to pair all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs. as well as The write step is used to, for each LUN pair, sequentially write data to one identical page from the plurality of pages corresponding to the programming mode of each word line of each LUN in the LUN pair. After completing the data writing of the identical page of the word line of all LUNs in the LUN pair, the next identical page from the plurality of pages of the word line of each LUN in the LUN pair is sequentially written, and so on, until the last identical page from the plurality of pages of the word line of each LUN in the LUN pair is sequentially written. The pairing step includes: For each channel of the NAND flash memory, determine the number of LUNs included in the LUN pair; Pair all LUNs within the channel such that each LUN pair includes the defined number of LUNs. Determining the number of LUNs included in a LUN pair includes: Calculate the ratio of programming cache busy time to data transfer time; If the ratio is less than 1, each LUN pair is determined to consist of 2 LUNs; When the ratio is equal to M, each LUN pair is determined to include M+1 LUNs, where M is an integer greater than 1.

2. The data writing method according to claim 1, characterized in that, For each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and a UP page. For each word line of each LUN pair, data is written as follows: Write data to the LP page of the first LUN in the LUN pair; Write data to the LP page of the second LUN in the LUN pair; Write data to the MP page of the first LUN in the LUN pair; Write data to the MP page of the second LUN in the LUN pair; Write data to the UP page of the first LUN in the LUN pair; Write data to the UP page of the second LUN in the LUN pair.

3. The data writing method according to claim 1, characterized in that, For each channel of the NAND flash memory, all LUNs within that channel are paired such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page. For each word line of each LUN pair, data is written as follows: Write data to the LP page of the first LUN in the LUN pair; Write data to the LP page of the second LUN in the LUN pair; Write data to the MP page of the first LUN in the LUN pair; Write data to the MP page of the second LUN in the LUN pair; Write data to the UP page of the first LUN in the LUN pair; Write data to the UP page of the second LUN in the LUN pair; Write data to the TP page of the first LUN in the LUN pair; Write data to the TP page of the second LUN in the LUN pair.

4. A data writing device for NAND flash memory, applied to a NAND controller, characterized in that, include: The pairing module is used to pair all logical units (LUNs) within each channel of the NAND flash memory, such that each LUN pair includes at least two LUNs. as well as The write module is used to write data to one identical page from multiple pages corresponding to the programming mode of each word line of each LUN in the LUN pair, sequentially for each LUN in the LUN pair. After completing the data writing to the identical page of the word line of all LUNs in the LUN pair, the module sequentially writes data to the next identical page from the multiple pages of the word line of each LUN in the LUN pair, and so on, until the last identical page from the multiple pages of the word line of each LUN in the LUN pair is written. The pairing module is configured as follows: For each channel of the NAND flash memory, determine the number of LUNs included in the LUN pair; Pair all LUNs within the channel such that each LUN pair includes the defined number of LUNs. The pairing module determines the number of LUNs included in a LUN pair in the following manner: Calculate the ratio of programming cache busy time to data transfer time; If the ratio is less than 1, each LUN pair is determined to consist of 2 LUNs; When the ratio is equal to M, each LUN pair is determined to include M+1 LUNs, where M is an integer greater than 1.

5. The data writing device according to claim 4, characterized in that, The pairing module is configured to pair all LUNs within each channel of the NAND flash memory, such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, and a UP page. The write module is configured to write data for each word line of each LUN pair in the following manner: Write data to the LP page of the first LUN in the LUN pair; Write data to the LP page of the second LUN in the LUN pair; Write data to the MP page of the first LUN in the LUN pair; Write data to the MP page of the second LUN in the LUN pair; Write data to the UP page of the first LUN in the LUN pair; Write data to the UP page of the second LUN in the LUN pair.

6. The data writing device according to claim 4, characterized in that, The pairing module is configured to pair all LUNs within each channel of the NAND flash memory, such that each LUN pair includes a first LUN and a second LUN, wherein each word line of the first LUN and the second LUN each includes an LP page, an MP page, an UP page, and a TP page. The write module is configured to write data for each word line of each LUN pair in the following manner: Write data to the LP page of the first LUN in the LUN pair; Write data to the LP page of the second LUN in the LUN pair; Write data to the MP page of the first LUN in the LUN pair; Write data to the MP page of the second LUN in the LUN pair; Write data to the UP page of the first LUN in the LUN pair; Write data to the UP page of the second LUN in the LUN pair; Write data to the TP page of the first LUN in the LUN pair; Write data to the TP page of the second LUN in the LUN pair.

7. A data writing device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the data writing method according to any one of claims 1-3 when executing instructions stored in the memory.

8. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the data writing method according to any one of claims 1-3.

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