A method for forming landing pads and DRAM

Abstract

This invention relates to a method for forming landing pads and DRAM, belonging to the field of semiconductor technology, and solves the problems of complex, time-consuming, and costly existing landing pad formation processes for connecting SN and SNC. The method includes: providing a semiconductor substrate on which a bit line structure and memory node contacts are formed; sequentially forming a barrier metal layer, a landing pad layer, a bottom mask layer, and a pad pattern mask layer above the bit line structure; forming the pad pattern mask layer into a pad pattern mask by an etching process, including multiple first bumps and a first opening between any two adjacent first bumps, wherein the multiple first bumps correspond to the landing pads to be formed; continuing to etch the bottom mask layer, landing pad layer, and barrier metal layer downwards within the multiple first openings to expose the top surface of the bit line structure; and removing the remaining multiple first bumps and the bottom mask layer to form the landing pads. This simplifies the landing pad formation process by omitting several process steps.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming landing pads and DRAM. Background Technology

[0002] Memory is a device or component in a digital system used to store large amounts of information, and it is an important part of computers and digital devices. Memory can be divided into two main categories: Random Access Memory (RAM) and Read-Only Memory (ROM). RAM includes DRAM, PRAM, MRAM, etc. Transistors and capacitors are the key components in the manufacture of these RAMs.

[0003] Landing pad (LP) technology is part of the capacitor formation process. Optimizing existing landing pad technologies addresses the design margin limitations resulting from the shrinking size of current DRAM devices. In current DRAM designs, directly connecting the capacitor (SN, memory node) to the shallow trench isolation (STI) on the SNC (memory node contact) suffers from space constraints. Therefore, a pad is needed to connect the SN and SNC; the process for forming this pad is called SNC2 or LP. Current LP technologies are very complex, with the final stage being the ACP (Accelerated Conversion Process) technology, which also comprises many steps. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a method for forming landing pads and DRAM, in order to solve the problems of complex, time-consuming and costly existing landing pad formation processes for connecting SN and SNC.

[0005] On one hand, embodiments of the present invention provide a method for forming a landing pad, comprising: providing a semiconductor substrate on which bit line structures and memory node contacts located between adjacent bit line structures are formed; sequentially forming a barrier metal layer, a landing pad layer, a bottom mask layer, and a pad pattern mask layer above the bit line structures; forming the pad pattern mask layer into a pad pattern mask by an etching process, wherein the pad pattern mask includes a plurality of first protrusions and a first opening located between any two adjacent first protrusions, wherein the plurality of first protrusions correspond to the landing pad to be formed; continuing to etch the bottom mask layer, the landing pad layer, and the barrier metal layer downward in the plurality of first openings to expose the top surface of the bit line structures; and removing the remaining plurality of first protrusions and the bottom mask layer to form the landing pad.

[0006] The beneficial effects of the above technical solution are as follows: converting ACP (Array Close Photo) lithography into ACP etching process omits the back etching and cleaning process of the pad pattern mask layer and the sidewall cleaning process, thereby simplifying the landing pad formation process connecting SN and SNC.

[0007] Based on further improvements to the above method, in-situ etching processes are performed on the barrier metal layer, the landing pad layer, the bottom mask layer, and the pad pattern mask layer in the same process chamber.

[0008] Based on a further improvement of the above method, the method for forming the bit line structure includes: sequentially forming a nitride layer, a barrier layer, a metal layer, and a capping layer above a semiconductor substrate; sequentially etching the capping layer, the metal layer, the barrier layer, and the nitride layer to form a plurality of bit lines; depositing an insulating material layer above the plurality of bit lines; and etching the insulating material layer into bit line sidewalls located on opposite sidewalls of the plurality of bit lines to form the bit line structure, wherein the bit line structure includes the plurality of bit lines and the bit line sidewalls.

[0009] Based on a further improvement of the above method, before forming the barrier layer, the method further includes: forming an insulating material layer between the plurality of bit line structures; and forming the insulating material layer as an STI to space the plurality of bit line structures apart by the STI.

[0010] Based on a further improvement of the above method, the bottom mask layer includes an amorphous carbon hard mask layer and a silicon oxynitride mask layer located above the amorphous carbon hard mask layer.

[0011] A further improvement to the above method, forming a pad pattern mask layer further includes: forming a first spin-coated hard mask layer over the silicon oxynitride mask layer; forming the first spin-coated hard mask layer into a plurality of second protrusions, wherein the plurality of second protrusions correspond in the vertical direction to a plurality of landing pads to be formed; depositing an oxide layer on the sidewalls of the plurality of second protrusions; and forming a second spin-coated hard mask layer with fluidity over the oxide layer to automatically fill the gaps in the oxide layer.

[0012] Based on a further improvement of the above method, forming the pad pattern mask layer into a pad pattern mask by etching further includes: etching the second spin-coated hard mask layer by a first etching process and over-etching the oxide layer below the second spin-coated hard mask layer; etching the exposed oxide layer by a second etching process and over-etching the first spin-coated hard mask layer below the oxide layer, while keeping the unexposed oxide layer unetched, to form the plurality of first openings and the plurality of first protrusions located on opposite sides of each first opening, wherein the first protrusion includes a combination of the first spin-coated hard mask layer and the oxide mask, or the first spin-coated hard mask layer.

[0013] Based on further improvements to the above method, in the first etching process, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 400 V, the process time is 48 s to 72 s, the over-etching is 16% to 24%, the O2 is 32 sccm to 48 sccm, and the Ar is 120 sccm to 180 sccm.

[0014] Based on further improvements to the above method, in the second etching process, the atmospheric pressure is 8 mtorr to 12 mtorr, the RF power is 550W, the bias RF voltage is 100V, the process time is 18.4s to 27.6s, the over-etching is 24% to 36%, and the CF4 is 80sccm to 120sccm.

[0015] Based on a further improvement of the above method, etching the bottom mask layer downward in the plurality of first openings further includes: continuing to etch the silicon oxynitride mask layer downward in the plurality of first openings; and continuing to etch the amorphous carbon hard mask layer downward in the plurality of first openings.

[0016] Based on further improvements to the above method, during the etching process of the silicon oxynitride mask layer, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 400 W, the bias RF voltage is 600 V, the process time is 44.8 s to 67.2 s, the over-etching time is 4.8 s to 7.2 s, the O2 etching time is 4 sccm to 6 sccm, the Ar etching time is 120 sccm to 180 sccm, the C4F8 etching time is 5.6 sccm to 8.4 sccm, and the C4F6 etching time is 6.4 sccm to 9.6 sccm.

[0017] Based on further improvements to the above method, during the etching process of the amorphous carbon hard mask layer, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 300 V, the process time is 40 s to 60 s, the over-etching time is 8 s to 12 s, the over-etching percentage is 16% to 24%, the O2 is 32 sccm to 48 sccm, the N2 is 64 sccm to 96 sccm, the Ar is 120 sccm to 180 sccm, and the CF4 is 12 sccm to 18 sccm.

[0018] Based on further improvements to the above method, during the etching process of the landing pad layer, the atmospheric pressure is 24 mtorr to 36 mtorr, the RF power is 1150 W, the over-etch RF power is 600 W, the bias RF voltage is 300 V, the over-etch bias RF voltage is 100 V, the process time is 18.4 s to 27.6 s, the over-etch time is 4.8 s to 7.2 s, the O2 is 40 sccm to 60 sccm, the SF6 is 320 sccm to 480 sccm, the over-etch SF6 is 128 sccm to 192 sccm, and the Ar is 72 sccm to 108 sccm.

[0019] Based on further improvements to the above method, during the etching process of the barrier metal layer, the atmospheric pressure is 5.6 mtorr to 8.4 mtorr, the RF power is 400 W, the bias RF voltage is 100 V, the process time is 11.2 s to 16.8 s, the over-etching time is 7.2 s to 10.8 s, the Cl2 etching depth is 22.4 sccm to 33.6 sccm, the over-etched Cl2 etching depth is 19.2 sccm to 28.8 sccm, the Ar etching depth is 128 sccm to 192 sccm, and the over-etched Ar etching depth is 136 sccm to 204 sccm.

[0020] Based on a further improvement of the above method, the method for forming the landing pad further includes: removing residues in the process chamber by a dry cleaning process.

[0021] Based on further improvements to the above method, the residue includes: TiN particles, W particles, C,F,CFx polymers, C,F,SixFy polymers, and coatings.

[0022] Based on further improvements to the above method, TiN particles in the process chamber are removed by Cl2; W particles in the process chamber are removed by SF6; C, F, and CFx polymers in the process chamber are removed by NF3; C, F, and SixFy polymers in the process chamber are removed by O2; and the coating in the process chamber is removed by SiCl4.

[0023] On the other hand, embodiments of the present invention provide a method for forming DRAM, comprising: forming a landing pad using the landing pad forming method described above, wherein the landing pad is used to connect a memory node and an STI.

[0024] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0025] 1. Converting ACP (Array Close Photo) lithography to ACP etching process omits the back etching and cleaning processes of the pad pattern mask layer and the sidewall cleaning process, thereby simplifying the landing pad formation process for connecting SN and SNC.

[0026] 2. In-situ etching of the barrier metal layer, landing pad layer, bottom mask layer, and pad pattern mask layer is performed in the same process chamber, avoiding the need to perform six different process steps in different process chambers, such as pattern mask layer back etching, pattern mask layer cleaning, sidewall cleaning, mask etching, tungsten etching, and barrier metal etching. This saves transfer time and device loading / unloading time in different process chambers, and uses only a single process chamber, which significantly shortens the process time and reduces the process cost.

[0027] 3. During etching, a lot of polymers are formed in the process chamber. After the landing pads are formed, a variety of etching gases are supplied to the process chamber to remove these polymers in order to keep the process chamber clean.

[0028] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0029] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0030] Figure 1 This is a cross-sectional view of an intermediate stage of a method for forming a landing pad according to an embodiment of the present invention.

[0031] Figure 2 This is a cross-sectional view of an intermediate stage of a method for forming a landing pad according to an embodiment of the present invention.

[0032] Figure 3 A cross-sectional view of the landing pad has been formed according to the method for forming the landing pad according to an embodiment of the present invention.

[0033] Figure 4 A diagram showing the specific parameter settings during the etching process of the method for forming landing pads according to an embodiment of the present invention.

[0034] Figure 5 A diagram showing the specific parameter settings in the dry cleaning process according to an embodiment of the present invention. Detailed Implementation

[0035] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the disclosure. Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can further design regions / layers with different shapes, sizes, and relative positions as needed.

[0036] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0037] One specific embodiment of the present invention discloses a method for forming a landing pad. Hereinafter, reference will be made to... Figure 1 The method for forming the landing pad is described in detail.

[0038] refer to Figure 1 A semiconductor substrate 102 is provided.

[0039] A bit line structure 108 and memory node contacts located between adjacent bit line structures 108 are formed on a semiconductor substrate 102. Specifically, forming the bit line structure 108 may include sequentially forming a nitride layer 114, a barrier layer 116, a metal layer 118, and a capping layer 120 above the semiconductor substrate 102. Then, the capping layer 120, the metal layer 118, the barrier layer 116, and the nitride layer 114 are sequentially etched from top to bottom to form a plurality of bit lines 112, wherein each bit line 112 includes a bit line nitride layer 114, a bit line barrier layer 116, a bit line metal layer 118, and a bit line capping layer 120 from bottom to top. Finally, an insulating material layer is deposited above the plurality of bit lines; the insulating material layer is etched into bit line sidewalls 110 located on the opposite sidewalls of the plurality of bit lines 112 to form the bit line structure 108, wherein the bit line structure 108 includes a plurality of bit lines 112 and bit line sidewalls 110. In one embodiment, the bit line sidewall 110 may employ a nitride-oxide-nitride (NON) structure.

[0040] refer to Figure 1 After forming bit line structures 108 above semiconductor substrate 102, an STI 104 is formed above semiconductor substrate 102. Specifically, an insulating material layer is formed between the plurality of bit line structures 108. The insulating material layer is then etched to form the STI 104, thereby spacing the plurality of bit line structures 108 apart. The top surface of the STI 104 may be located between the top and bottom surfaces of the bit line capping layer 120. In an alternative embodiment, the top surface of the STI 104 is located at half the height of the bit line structure 108.

[0041] refer to Figure 1 After forming STI 104 over semiconductor substrate 102, barrier metal layers 122 and 106, landing pad layer 124, bottom mask layer, and pad pattern mask layer are sequentially formed from bottom to top over bit line structures 108 and STI 104. Specifically, this further includes forming barrier metal layers 122 and 106 over multiple bit line structures 112 and STI 104; forming landing pad layer 124 over barrier metal layers 122 and 106; and forming a bottom mask layer over landing pad layer 124, wherein the bottom mask layer includes an amorphous carbon hard mask layer 126 and a silicon oxynitride mask layer 128 located above the amorphous carbon hard mask layer 126. (Reference) Figure 1Specifically, forming the pad pattern mask layer further includes: forming a first spin-on hard mask (SOH) layer over a silicon oxynitride mask layer 128; forming the first spin-on hard mask layer into a plurality of second protrusions 130, wherein the plurality of second protrusions 130 correspond in the vertical direction to a plurality of landing pads to be formed; depositing an oxide layer 132 over the plurality of second protrusions 130, wherein a portion of the oxide material fills the trenches between adjacent second protrusions 130 to form oxide sidewalls; and forming a second spin-on hard mask layer 134 with fluidity over the oxide layer 132 to automatically fill gaps in the oxide layer.

[0042] refer to Figure 2After forming barrier metal layers 112 and 106, landing pad layer 124, bottom mask layer, and pad pattern mask layer sequentially from bottom to top above bit line structure 108, the pad pattern mask layer is formed into a pad pattern mask by an etching process. The pad pattern mask includes a plurality of first protrusions 136, 138 and a first opening 140 located between any two adjacent first protrusions among the plurality of first protrusions 136, 138. The plurality of first protrusions 136, 138 correspond to the landing pads to be formed. Specifically, forming the pad pattern mask layer into a pad pattern mask by the etching process further includes: etching the second spin-coated hard mask layer 134 by a first etching process and over-etching the oxide layer 132 beneath the second spin-coated hard mask layer. In the first etching process, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 400 V, the process time is 48 s to 72 s, the over-etching is 16% to 24%, the O2 is 32 sccm to 48 sccm, and the Ar is 120 sccm to 180 sccm. In a preferred embodiment, the atmospheric pressure is 5 mtorr, the RF power is 440 W, the bias RF voltage is 400 V, the process time is 60 s, the over-etching is 20%, the O2 is 40 sccm, and the Ar is 150 sccm. The exposed oxide layer 132 is etched using a second etching process, and the first spin-coated hard mask layer beneath the oxide layer 132 is over-etched, while the unexposed oxide layer remains unetched, to form a plurality of first openings 140 and a plurality of first protrusions 136, 138 located on opposite sides of each first opening 140. The first protrusion 138 may include a combination of the first spin-coated hard mask 142 and the oxide mask 144, or the first protrusion 136 may include only the first spin-coated hard mask. In the second etching process, the atmospheric pressure is 8 mtorr to 12 mtorr, the RF power is 550 W, the bias RF voltage is 100 V, the process time is 18.4 s to 27.6 s, the over-etching is 24% to 36%, and the CF4 is 80 sccm to 120 sccm. In a preferred embodiment, the atmospheric pressure is 10 mtorr, the RF power is 550 W, the bias RF voltage is 100 V, the process time is 23 s, the over-etching is 30%, and the CF4 is 100 sccm.

[0043] refer to Figure 2 The bottom mask layer, landing pad layer 124, and barrier metal layer 122 are etched downwards through multiple first openings 140 to expose the top surface of the bitline structure. In-situ etching is then performed on the barrier metal layer 122, landing pad layer 124, bottom mask layer, and pad pattern mask layer in the same process chamber. Referring below... Figure 2 The etching process for the bottom mask layer, landing pad layer 124 and barrier metal layer 122 will be described in detail.

[0044] refer to Figure 2 The etching of a bottom mask layer downwards within a plurality of first openings 140 to form a bottom mask further includes: continuing to etch a silicon oxynitride mask layer 128 downwards within the plurality of first openings 140. During the etching of the silicon oxynitride mask layer, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 400 W, the bias RF voltage is 600 V, the process time is 44.8 s to 67.2 s, the over-etch time is 4.8 s to 7.2 s, the O2 etching time is 4 sccm to 6 sccm, the Ar etching time is 120 sccm to 180 sccm, the C4F8 etching time is 5.6 sccm to 8.4 sccm, and the C4F6 etching time is 6.4 sccm to 9.6 sccm. In a preferred embodiment, the atmospheric pressure is 5 mtorr, the RF power is 400 W, the bias RF voltage is 600 V, the process time is 56 s, the over-etch time is 6 s, the O2 is 5 sccm, the Ar is 150 sccm, the C4F8 is 7 sccm, and the C4F6 is 8 sccm. Then, the amorphous carbon (ALC) hard mask layer 128 is etched downwards through the plurality of first openings 140. During the etching of the amorphous carbon hard mask layer, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 300 V, the process time is 40 s to 60 s, the over-etch time is 8 s to 12 s, the over-etch is 16% to 24%, the O2 is 32 sccm to 48 sccm, the N2 is 64 sccm to 96 sccm, the Ar is 120 sccm to 180 sccm, and the CF4 is 12 sccm to 18 sccm. In a preferred embodiment, the atmospheric pressure is 5 mtorr, the RF power is 440 W, the bias RF voltage is 300 V, the process time is 50 s, the over-etching time is 10 s, the over-etching is 20%, the O2 is 40 sccm, the N2 is 80 sccm, the Ar is 150 sccm, and the CF4 is 15 sccm.

[0045] Refer again Figure 2During the etching process of the landing pad layer, the atmospheric pressure was 24 mtorr to 36 mtorr, the RF power was 1150 W, the over-etch RF power was 600 W, the bias RF voltage was 300 V, the over-etch bias RF voltage was 100 V, the process time was 18.4 s to 27.6 s, the over-etch time was 4.8 s to 7.2 s, the O2 was 40 sccm to 60 sccm, the SF6 was 320 sccm to 480 sccm, the over-etch SF6 was 128 sccm to 192 sccm, and the Ar was 72 sccm to 108 sccm. In a preferred embodiment, the atmospheric pressure is 30 mtorr, the RF power is 1150 W, the over-etch RF power is 600 W, the bias RF voltage is 300 V, the over-etch bias RF voltage is 100 V, the process time is 23 s, the over-etch time is 6 s, the O2 is 50 sccm, the SF6 is 400 sccm, the over-etch SF6 is 160 sccm, and the Ar is 90 sccm. During the etching of the barrier metal layer, the atmospheric pressure is 5.6 mtorr to 8.4 mtorr, the RF power is 400 W, the bias RF voltage is 100 V, the process time is 11.2 s to 16.8 s, the over-etch time is 7.2 s to 10.8 s, the Cl2 is 22.4 sccm to 33.6 sccm, the over-etch Cl2 is 19.2 sccm to 28.8 sccm, the Ar is 128 sccm to 192 sccm, and the over-etch Ar is 136 sccm to 204 sccm. In a preferred embodiment, the atmospheric pressure is 7 mtorr, the RF power is 400 W, the bias RF voltage is 100 V, the process time is 14 s, the over-etching time is 9 s, the Cl2 etching time is 28 sccm, the over-etched Cl2 time is 24 sccm, the Ar etching time is 160 sccm, and the over-etched Ar time is 170 sccm. In a preferred embodiment, Figure 4 The specific parameter settings are shown.

[0046] refer to Figure 3 After etching down through the multiple first openings 140, the bottom mask layer, landing pad layer, and barrier metal layer are etched, the remaining multiple first bumps 136, 138 and the bottom mask are removed to form multiple landing pads 146 and openings 148 between adjacent landing pads 146. The landing pads 146 are formed directly on the STI 104 to connect the STI 104 to the memory nodes above via the landing pads 146.

[0047] Compared with the prior art, the landing pad formation method provided in this embodiment converts ACP (Array Close Photo) lithography into ACP etching process, omitting the back etching and cleaning process of the pad pattern mask layer and the sidewall cleaning process, thereby simplifying the landing pad formation process connecting SN and SNC.

[0048] After the landing pad 146 is formed, residues in the process chamber are removed by a dry cleaning process. Residues may include TiN particles, W particles, C,F,CFx polymers, C,F,SixFy polymers, and coatings. Specifically, TiN particles are removed from the process chamber by Cl2, W particles by SF6, C,F,CFx polymers by NF3, C,F,SixFy polymers by O2, and coatings by SiCl4. In a preferred embodiment, Figure 5 The specific parameter settings are shown.

[0049] Compared with the prior art, the landing pad formation method provided in this embodiment forms a lot of polymers in the process chamber during the etching process. After the landing pad is formed, a variety of etching gases are provided to the process chamber to remove these polymers, so as to maintain the cleanliness of the process chamber.

[0050] A specific embodiment of the present invention discloses a method for forming a DRAM, comprising: forming a landing pad using the landing pad forming method described above, wherein the landing pad is used to connect an upper memory node and a lower STI.

[0051] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0052] 1. Converting ACP (Array Close Photo) lithography to ACP etching process omits the back etching and cleaning processes of the pad pattern mask layer and the sidewall cleaning process, thereby simplifying the landing pad formation process for connecting SN and SNC.

[0053] 2. In-situ etching of the barrier metal layer, landing pad layer, bottom mask layer, and pad pattern mask layer is performed in the same process chamber, avoiding the need to perform six different process steps in different process chambers, such as pattern mask layer back etching, pattern mask layer cleaning, sidewall cleaning, mask etching, tungsten etching, and barrier metal etching. This saves transfer time and device loading / unloading time in different process chambers, and uses only a single process chamber, which significantly shortens the process time and reduces the process cost.

[0054] 3. During etching, a lot of polymers are formed in the process chamber. After the landing pads are formed, a variety of etching gases are supplied to the process chamber to remove these polymers in order to keep the process chamber clean.

[0055] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0056] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for forming a landing pad, characterized in that, include: A semiconductor substrate is provided, on which bit line structures and memory node contacts are formed between adjacent bit line structures; An insulating material layer is formed between the plurality of bit line structures; And the insulating material layer is formed as an STI to space the plurality of bit line structures apart by the STI; A barrier metal layer, a landing pad layer, a bottom mask layer, and a pad pattern mask layer are sequentially formed above the bit line structure and the STI. The formation of the pad pattern mask layer further includes: forming a first spin-coated hard mask layer above the bottom mask layer; forming the first spin-coated hard mask layer into a plurality of second protrusions, wherein the plurality of second protrusions correspond in the vertical direction to a plurality of landing pads to be formed; depositing an oxide layer on the sidewalls of the plurality of second protrusions; and forming a second spin-coated hard mask layer with fluidity above the oxide layer to automatically fill gaps in the oxide layer. The pad pattern mask layer is formed into a pad pattern mask by an etching process. The pad pattern mask includes a plurality of first protrusions and a first opening located between any two adjacent first protrusions. The plurality of first protrusions correspond to the landing pads to be formed. The bottom mask layer, the landing pad layer, and the barrier metal layer are etched downwards through multiple first openings to expose the top surface of the bit line structure; and Remove the remaining plurality of first protrusions and the bottom mask layer to form landing pads. In this process, the barrier metal layer, the landing pad layer, the bottom mask layer, and the pad pattern mask layer are subjected to in-situ etching in the same process chamber.

2. The method for forming the landing pad according to claim 1, characterized in that, The method for forming the bit line structure includes: A nitride layer, a barrier layer, a metal layer, and a capping layer are sequentially formed on a semiconductor substrate; The capping layer, the metal layer, the barrier layer, and the nitride layer are sequentially etched to form multiple bit lines; An insulating material layer is deposited above the multiple bit lines; The insulating material layer is etched into bit line sidewalls located on opposite sidewalls of the plurality of bit lines to form the bit line structure, wherein the bit line structure includes the plurality of bit lines and the bit line sidewalls.

3. The method for forming the landing pad according to claim 2, characterized in that, The bottom mask layer includes an amorphous carbon hard mask layer and a silicon oxynitride mask layer located above the amorphous carbon hard mask layer.

4. The method for forming the landing pad according to claim 3, characterized in that, Forming the pad pattern mask layer into a pad pattern mask through an etching process further includes: The second spin-coated hard mask layer is etched by a first etching process, and the oxide layer beneath the second spin-coated hard mask layer is over-etched. The exposed oxide layer is etched by a second etching process and the first spin-coated hard mask layer beneath the oxide layer is over-etched, while the unexposed oxide layer remains unetched to form the plurality of first openings and the plurality of first protrusions located on opposite sides of each first opening, wherein the first protrusion comprises a combination of the first spin-coated hard mask layer and an oxide mask, or the first spin-coated hard mask layer.

5. The method for forming the landing pad according to claim 4, characterized in that, In the first etching process, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 400 V, the process time is 48 s to 72 s, the over-etching is 16% to 24%, the O2 is 32 sccm to 48 sccm, and the Ar is 120 sccm to 180 sccm.

6. The method for forming a landing pad according to claim 4, characterized in that, In the second etching process, the atmospheric pressure is 8 mtorr to 12 mtorr, the RF power is 550 W, the bias RF voltage is 100 V, the process time is 18.4 s to 27.6 s, the over-etching is 24% to 36%, and the CF4 is 80 sccm to 120 sccm.

7. The method for forming a landing pad according to claim 3, characterized in that, Etching the bottom mask layer downwards through the plurality of first openings further includes: The silicon oxynitride mask layer is etched downwards through multiple first openings; and The amorphous carbon hard mask layer continues to be etched downwards through multiple first openings.

8. The method for forming a landing pad according to claim 7, characterized in that, During the etching process of the silicon oxynitride mask layer, the atmospheric pressure was 4 mtorr to 6 mtorr, the RF power was 400 W, the bias RF voltage was 600 V, the process time was 44.8 s to 67.2 s, the over-etching time was 4.8 s to 7.2 s, the O2 etching time was 4 sccm to 6 sccm, the Ar etching time was 120 sccm to 180 sccm, the C4F8 etching time was 5.6 sccm to 8.4 sccm, and the C4F6 etching time was 6.4 sccm to 9.6 sccm.

9. The method for forming a landing pad according to claim 7, characterized in that, During the etching process of the amorphous carbon hard mask layer, the atmospheric pressure is 4 mtorr to 6 mtorr, the RF power is 440 W, the bias RF voltage is 300 V, the process time is 40 s to 60 s, the over-etching time is 8 s to 12 s, the over-etching percentage is 16% to 24%, the O2 is 32 sccm to 48 sccm, the N2 is 64 sccm to 96 sccm, the Ar is 120 sccm to 180 sccm, and the CF4 is 12 sccm to 18 sccm.

10. The method for forming a landing pad according to claim 1, characterized in that, During the etching process of the landing pad layer, the atmospheric pressure was 24 mtorr to 36 mtorr, the RF power was 1150 W, the over-etch RF power was 600 W, the bias RF voltage was 300 V, the over-etch bias RF voltage was 100 V, the process time was 18.4 s to 27.6 s, the over-etch time was 4.8 s to 7.2 s, the O2 was 40 sccm to 60 sccm, the SF6 was 320 sccm to 480 sccm, the over-etch SF6 was 128 sccm to 192 sccm, and the Ar was 72 sccm to 108 sccm.

11. The method for forming a landing pad according to claim 1, characterized in that, During the etching process of the barrier metal layer, the atmospheric pressure was 5.6 mtorr to 8.4 mtorr, the RF power was 400 W, the bias RF voltage was 100 V, the process time was 11.2 s to 16.8 s, the over-etching time was 7.2 s to 10.8 s, the Cl2 etching depth was 22.4 sccm to 33.6 sccm, the over-etched Cl2 etching depth was 19.2 sccm to 28.8 sccm, the Ar etching depth was 128 sccm to 192 sccm, and the over-etched Ar etching depth was 136 sccm to 204 sccm.

12. The method for forming a landing pad according to claim 1, characterized in that, Further includes: Residues in the process chamber are removed using a dry cleaning process.

13. The method for forming a landing pad according to claim 12, characterized in that, The residues include: TiN particles, W particles, C,F,CFx polymers, C,F,SixFy polymers, and coatings.

14. The method for forming a landing pad according to claim 13, characterized in that, TiN particles in the process chamber are removed by Cl2; W particles in the process chamber are removed by SF6; The C, F, CFx polymers in the process chamber are removed by NF3; The C, F, SixFy polymers in the process chamber are removed by O2; and The coating in the process chamber is removed by SiCl4.

15. A method for forming DRAM, characterized in that, include: The landing pad is formed using the method of forming the landing pad according to any one of claims 1 to 14, wherein the landing pad is used to connect the storage node and the STI.

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