Insulating substrate, semiconductor packaging structure and method for preparing insulating substrate

Abstract

The present application provides an insulating substrate, a semiconductor packaging structure, and a method for preparing an insulating substrate. The insulating substrate includes a heat dissipation layer, an insulating layer, and a wiring layer stacked in sequence along the thickness direction, and the materials of the wiring layer and the heat dissipation layer are both metals. The insulating substrate also includes: a plurality of crack prevention bodies spaced apart in the insulating layer; wherein the plane where each of the crack prevention bodies is located forms an angle with the plane where the insulating layer is located, and the angle is greater than 0 degrees and less than 180 degrees. The semiconductor packaging structure includes the insulating substrate, and a chip arranged on the insulating substrate. The preparation method is used to prepare the insulating substrate. The present application can greatly improve the thermal conductivity of the insulating layer and reduce the risk of tearing the insulating layer by spaced apart obliquely or longitudinally arranging a plurality of the crack prevention bodies in the insulating layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an insulating substrate, a semiconductor packaging structure, and a method for preparing the insulating substrate. Background Art

[0002] In the prior art, metal insulating substrates are generally used for high-power module packaging, and high molecular polymers are used as the base material of the insulating layer. Most insulating layers have the disadvantages of being easily torn at high temperatures and having low thermal conductivity.

[0003] like Figure 1 As shown in the figure, it is a schematic diagram of the structure of a metal insulating substrate in the prior art. The metal insulating substrate includes a heat dissipation metal layer 10', an insulating layer 20' and a wiring copper layer 30' which are stacked in sequence. The chip is mounted on the wiring copper layer 30'. The insulating layer 20' includes a thermal conductive additive 21' and a high molecular polymer 22'. The glass fiber cloth 40' is horizontally laid in the insulating layer 20'. The heat generated by the chip during operation is conducted in the direction of the arrow P' and finally released through the heat dissipation metal layer 10'.

[0004] Since the insulation layer conducts heat mainly through heat conduction between thermally conductive additives, the glass fiber cloth laid horizontally in the insulation layer can reduce the possibility of tearing of the insulation layer to a certain extent. However, the thermal conductivity of the glass fiber cloth itself is very low. In addition, the gap size of the glass fiber cloth is much smaller than the size of the thermally conductive additive, resulting in the thermally conductive additive being completely separated by the glass fiber cloth. These two reasons lead to the overall thermal conductivity of the metal insulation substrate being unable to meet the heat dissipation requirements.

[0005] Therefore, how to improve the overall thermal conductivity of the metal insulation substrate while reducing the risk of insulation layer tearing is a difficult problem to be solved in the field. Summary of the invention

[0006] One aspect of the present application provides an insulating substrate, the insulating substrate comprising a heat dissipation layer, an insulating layer and a wiring layer stacked in sequence along a thickness direction, the wiring layer and the heat dissipation layer are made of metal, and the insulating substrate further comprises:

[0007] A plurality of crack prevention bodies, wherein the plurality of crack prevention bodies are arranged in the insulating layer at intervals;

[0008] Wherein, the plane where each of the crack prevention bodies is located forms an angle with the plane where the insulating layer is located, and the angle is greater than 0 degrees and less than 180 degrees.

[0009] Optionally, each of the crack prevention bodies includes a first end close to the heat dissipation layer and a second end close to the wiring layer, and both the first end and the second end are located in the insulating layer.

[0010] Optionally, the angles formed by the plane where each of the crack prevention bodies is located and the plane where the insulating layer is located are the same; or,

[0011] The multiple angles formed by the planes where the multiple crack prevention bodies are located and the plane where the insulating layer is located are at least partially different.

[0012] Optionally, the angles formed by the plane where each of the crack prevention bodies is located and the plane where the insulating layer is located are the same, and the angles are all 90 degrees; or,

[0013] The angle is not equal to 90 degrees.

[0014] Optionally, the anti-crack body is a fabric structure; and / or,

[0015] The material of the crack-preventing body is insulating oxide.

[0016] Optionally, the anti-crack body has a thickness of 20 μm-35 μm.

[0017] Optionally, the insulating layer includes a high molecular polymer layer and a heat dissipation additive dispersed in the high molecular polymer layer, and the heat dissipation additive is distributed at least between two adjacent crack prevention bodies.

[0018] A second aspect of the present application provides a semiconductor packaging structure, which includes the insulating substrate as described above, and a chip disposed on the insulating substrate.

[0019] A second aspect of the present application provides a method for preparing an insulating substrate, the method for preparing the insulating substrate as described above, the method comprising the following steps:

[0020] Providing the heat dissipation layer;

[0021] forming the insulating layer on the heat dissipation layer, and arranging a plurality of the crack preventing bodies in the insulating layer before the insulating layer is cured;

[0022] The wiring layer is formed on the cured insulating layer.

[0023] Optionally, before forming the insulating layer on the heat dissipation layer, the method further includes:

[0024] The surface of the heat dissipation layer which will form the insulating layer is subjected to surface treatment.

[0025] The above-mentioned insulating substrate, semiconductor packaging structure and method for preparing an insulating substrate provided in the embodiments of the present application can greatly improve the thermal conductivity of the insulating layer and reduce the risk of tearing of the insulating layer by arranging a plurality of the anti-crack bodies at intervals in the insulating layer, and by arranging the plane where each of the anti-crack bodies is located to form an angle greater than 0 degree and less than or equal to 90 degrees with the plane where the insulating layer is located (that is, the plane where the anti-crack body is located is not parallel to the plane where the insulating layer is located, and the anti-crack body is arranged obliquely or longitudinally).

[0026] It should be noted that, based on long-term experience, the tearing of the insulation layer is mostly in the transverse extension mode. This application improves the transverse tensile strength of the insulation layer by designing a technical solution for arranging the longitudinal and oblique crack-proof bodies. In addition, the technical solution of this application can ensure that the heat dissipation filler directly contacts and penetrates the entire insulation layer in the longitudinal direction, which can achieve the highest thermal conductivity of the insulation layer and improve the heat dissipation capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a cross-sectional view of an insulating substrate in the prior art.

[0028] Figure 2 It is a cross-sectional view of the insulating substrate proposed in Example 1 of the present application.

[0029] Figure 3 It is a flow chart of the semiconductor packaging method proposed according to the first embodiment of the present application.

[0030] Figure 4(a)-Figure 4(d) It is a process flow chart of the semiconductor packaging method proposed in Example 1 of the present application.

[0031] Figure 5 It is a schematic diagram of the structure of the insulating substrate proposed in Example 2 of the present application.

[0032] Figure 6 It is a schematic diagram of the structure of the insulating substrate proposed in Example 3 of the present application. DETAILED DESCRIPTION

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0035] Example 1

[0036] Please combine Figure 2 It is understood that this embodiment provides an insulating substrate 1. The insulating substrate 1 includes a heat dissipation layer 10, an insulating layer 20 and a wiring layer 30 which are sequentially stacked along a thickness direction T, and the wiring layer 30 and the heat dissipation layer 10 are made of metal. The thickness direction refers to the thickness direction of the insulating substrate 1.

[0037] The insulating substrate 1 further includes: a plurality of crack prevention bodies 40, which are arranged at intervals in the insulating layer 20; wherein a plane C where each crack prevention body 40 is located forms an angle α with a plane where the insulating layer 20 is located, and the angle α formed by the plane where each crack prevention body 40 is located and the plane where the insulating layer 20 is located is the same, and the angle α is equal to 90 degrees. In other words, the plane C where the crack prevention body 40 is located is not parallel to the plane where the insulating layer 20 is located, and the plane C where the crack prevention body 40 is located is perpendicular to the plane where the insulating layer 20 is located, that is, the crack prevention body 40 is arranged longitudinally (arranged along the thickness direction T). The crack-preventing body 40 has a tear-resistant effect. By arranging the crack-preventing body 40 in the longitudinal direction, the transverse tensile strength of the insulating layer 20 can be improved, thereby having a restraining effect on transverse tearing, thereby reducing the risk of tearing of the insulating layer 20; and, since the plurality of crack-preventing bodies 40 are arranged at intervals, it is ensured that the heat dissipation filler is in direct contact with and penetrates the entire insulating layer 20 in the longitudinal direction, and the highest thermal conductivity of the insulating layer 20 can be achieved, thereby improving the heat dissipation capacity. Specifically, the crack-preventing body 40 arranged in the longitudinal direction does not affect the direct contact of the conductive heat dissipation filler with the wiring layer 30 and the heat dissipation layer 10 in the longitudinal direction, and the longitudinal arrangement of the crack-preventing body 40 avoids the disadvantage of low thermal conductivity in the longitudinally conductive insulating substrate 1, thereby greatly improving the thermal conductivity of the metal insulating substrate 1.

[0038] like Figure 2 As shown in FIG. 1 , for better understanding, the plane C where the crack preventing body 40 is located is drawn with a dotted line, but in actual results, there is no structure in the dotted line part.

[0039] In this embodiment, the number of the crack prevention bodies 40 is four, but is not limited thereto and can be set to other numbers according to design requirements.

[0040] Each crack prevention body 40 includes a first end 40a close to the heat dissipation layer 10 and a second end 40b close to the wiring layer 30. The first end 40a and the second end 40b are both located in the insulating layer 20 to avoid different materials from intersecting to form a tear point. In other words, the crack prevention body 40 is not in contact with the wiring layer 30 and the heat dissipation layer 10, thereby avoiding unnecessary tear points; the first end 40a of the crack prevention body 40 is at a distance d1 from the heat dissipation layer 10, and the second end 40b of the crack prevention body 40 is at a distance d2 from the wiring layer 30. The numerical range of the specific distance is not limited here.

[0041] In this embodiment, the anti-crack body 40 is a fabric structure, and the material of the anti-crack body 40 is an insulating oxide. Specifically, the anti-crack body 40 is a glass fiber cloth, which has a better tear resistance. The shape of the anti-crack body 40 is a plate.

[0042] In this embodiment, the thickness t of the crack prevention body 40 is 20 μm-35 μm. Thus, by setting a certain thickness, the crack prevention body 40 can be guaranteed to have a certain strength, thereby improving the transverse tensile strength of the insulating layer 20 while ensuring a better overall size of the insulating substrate 1 .

[0043] The insulating layer 20 includes a polymer layer 21 and a heat dissipation additive 22 dispersed in the polymer layer 21. The heat dissipation additive 22 is distributed at least between two adjacent anti-crack bodies 40. In this way, it is ensured that the heat dissipation filler directly contacts and penetrates the entire insulating layer 20 in the longitudinal direction, and the highest thermal conductivity of the insulating layer 20 can be achieved, thereby improving the heat dissipation capacity. Specifically, the material of the heat dissipation additive 22 is aluminum oxide, aluminum nitride, magnesium oxide, silicon carbide, etc.; the material of the polymer layer 21 is various epoxy resins. The mass proportion of the heat dissipation additive 22 in the insulating layer 20 is less than 10%.

[0044] This embodiment further provides a semiconductor packaging structure, which includes the insulating substrate 1 as described above, and a chip disposed on the insulating substrate 1 .

[0045] The semiconductor packaging structure provided in the embodiment of the present application can significantly improve the thermal conductivity of the insulating layer 20 and reduce the risk of tearing of the insulating layer 20 by arranging a plurality of anti-crack bodies 40 at intervals in the insulating layer 20, and by arranging the angle α formed by the plane where each anti-crack body 40 is located and the plane where the insulating layer 20 is located to be equal to 90 degrees.

[0046] Figure 3 FIG. 1 is a flow chart of the method for preparing the insulating substrate proposed in this embodiment. Figure 3 As shown, the method for preparing the insulating substrate comprises the following steps:

[0047] Step 100: providing the heat dissipation layer;

[0048] Step 200: forming an insulating layer on the heat dissipation layer, and arranging a plurality of the crack prevention bodies in the insulating layer before the insulating layer is solidified;

[0049] Step 300: forming the wiring layer on the cured insulating layer.

[0050] Specifically, Figure 4(a)-Figure 4(d) As shown, the semiconductor packaging method of this embodiment includes:

[0051] In step 100, as shown in Fig. 4(a), a heat dissipation layer 10 is provided. The material of the heat dissipation layer 10 is metal.

[0052] Before entering step 200, that is, before forming the insulating layer 20 on the heat dissipation layer 10, the process further includes: performing surface treatment on the surface of the heat dissipation layer 10 where the insulating layer 20 is to be formed, so as to enhance the contact strength with the insulating layer 20. Specifically, anodizing surface treatment and micro-arc oxidation surface treatment may be used.

[0053] In step 200, as shown in FIG. 4(b) and FIG. 4(c), an insulating layer 20 is formed on the heat dissipation layer 10, and before the insulating layer 20 is cured, a plurality of crack prevention bodies 40 are arranged in the insulating layer 20. The technical features of the crack prevention bodies 40 and the technical features of the insulating layer 20 can be found in the specific contents of the above-mentioned insulating substrate, which will not be repeated here.

[0054] In step 300, as shown in Fig. 4(d), the wiring layer 30 is formed on the cured insulating layer 20. The wiring layer 30 is made of metal.

[0055] The preparation method of the above-mentioned insulating substrate provided in the embodiment of the present application can improve the transverse tensile strength of the insulating layer by longitudinally arranging the anti-crack bodies, thereby reducing the risk of tearing of the insulating layer; and because the plurality of anti-crack bodies are arranged at intervals, it is ensured that the heat dissipation filler is in direct contact with and penetrates the entire insulating layer in the longitudinal direction, thereby achieving the highest thermal conductivity of the insulating layer and improving the heat dissipation capacity.

[0056] Example 2

[0057] like Figure 5 As shown, the contents of the insulating substrate of this embodiment are basically the same as the structure of the insulating substrate in Example 1, the difference being that, in the insulating substrate 1 of this embodiment, the angle α formed by the plane C where each of the anti-crack bodies 40 is located and the plane where the insulating layer 20 is located is the same, and the angle α is greater than 0 degrees and less than 180 degrees, and is not equal to 90 degrees, that is, the plane C where the anti-crack body 40 is located is neither parallel nor perpendicular to the plane where the insulating layer 20 is located, that is, the anti-crack body 40 is obliquely arranged, and all of the anti-crack bodies 40 are obliquely arranged at the same angle.

[0058] As described above, the anti-crack body 40 has an anti-tear effect. By arranging the anti-crack body 40 obliquely, the transverse and longitudinal tensile strength of the insulating layer 20 can be improved, thereby having a certain restraining effect on transverse and longitudinal tearing, thereby reducing the risk of tearing of the insulating layer 20; and, since the plurality of anti-crack bodies 40 are arranged at intervals, it is ensured that the heat dissipation filler is in direct contact with and penetrates the entire insulating layer 20 in the longitudinal direction, so that the highest thermal conductivity of the insulating layer 20 can be achieved, thereby improving the heat dissipation capacity.

[0059] Preferably, the angle α is greater than 60 degrees and less than 120 degrees. In this way, the crack prevention body 40 can provide the insulating layer 20 with better tensile strength in the lateral direction.

[0060] This embodiment also provides a semiconductor packaging structure, which includes the insulating substrate 1 as described above, and a chip disposed on the insulating substrate 1 .

[0061] The method for preparing the insulating substrate in this embodiment is the same as that in Embodiment 1 and will not be described again here.

[0062] Example 3

[0063] The contents of the insulating substrate 1 of this embodiment are substantially the same as the structure of the insulating substrate 1 in Embodiment 2, except that, in the insulating substrate of this embodiment, the multiple angles formed by the planes where the multiple anti-crack bodies are located and the plane where the insulating layer is located are not completely the same.

[0064] like Figure 6 As shown, the insulating substrate 1 includes Figure 6 The four crack prevention bodies from left to right are recorded as the first crack prevention body 41, the second crack prevention body 42, the third crack prevention body 43 and the fourth crack prevention body 44. The angle formed by the plane where the first crack prevention body 41 is located and the plane where the insulating layer 20 is located is the first angle α1, the angle formed by the plane where the second crack prevention body 42 is located and the plane where the insulating layer 20 is located is the second angle α2, the angle formed by the plane where the third crack prevention body 43 is located and the plane where the insulating layer 20 is located is the third angle α3, and the angle formed by the plane where the fourth crack prevention body 44 is located and the plane where the insulating layer 20 is located is the fourth angle α4. The first angle α1 and the third angle α3 are the same, both of which are 60 degrees; the second angle α2 and the fourth angle α4 are the same, both of which are 45 degrees.

[0065] But not limited to this, in other embodiments, the angles formed by the plane where each of the crack prevention bodies 40 is located and the plane where the insulating layer 20 is located may be different, that is, the first angle α1, the second angle α2, the third angle α3 and the fourth angle α4 are not equal.

[0066] It should be noted that the specific numerical range of the interval between two adjacent anti-crack bodies 40 is not limited here, as long as the two adjacent anti-crack bodies 40 are arranged at an interval, that is, the two adjacent anti-crack bodies 40 will not form an intersection in the insulating layer 20, thereby affecting the direct contact of the thermal conductive filler with the wiring layer 30 and the heat dissipation layer 10 in the longitudinal direction.

[0067] This embodiment also provides a semiconductor packaging structure, which includes the insulating substrate 1 as described above, and a chip disposed on the insulating substrate 1 .

[0068] The method for preparing the insulating substrate in this embodiment is the same as that in Embodiment 1, and will not be described again here.

[0069] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0070] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An insulating substrate, characterized in that: The insulating substrate comprises a heat dissipation layer, an insulating layer and a wiring layer which are sequentially stacked in a thickness direction, wherein the wiring layer and the heat dissipation layer are made of metal, and the insulating substrate further comprises: A plurality of crack prevention bodies, wherein the plurality of crack prevention bodies are arranged in the insulating layer at intervals; Wherein, the plane where each of the crack prevention bodies is located forms an angle with the plane where the insulating layer is located, and the angle is greater than 0 degrees and less than 180 degrees; Each of the crack prevention bodies comprises a first end close to the heat dissipation layer and a second end close to the wiring layer, wherein the first end and the second end are both located in the insulating layer; The insulating layer includes a high molecular polymer layer and a heat dissipation additive dispersed in the high molecular polymer layer, and the heat dissipation additive is distributed at least between two adjacent crack prevention bodies.

2. The insulating substrate according to claim 1, wherein The angles formed by the plane where each of the crack prevention bodies is located and the plane where the insulating layer is located are the same; or, The multiple angles formed by the planes where the multiple crack prevention bodies are located and the plane where the insulating layer is located are at least partially different.

3. The insulating substrate according to claim 1, wherein The angles formed by the plane where each of the crack prevention bodies is located and the plane where the insulating layer is located are the same, and the angles are all 90 degrees; or, The angles are not equal to 90 degrees.

4. The insulating substrate according to claim 1, wherein The anti-crack body is a fabric structure; and / or, The material of the crack prevention body is insulating oxide.

5. The insulating substrate according to claim 1, wherein The crack preventing body has a thickness of 20 μm to 35 μm.

6. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises the insulating substrate as claimed in any one of claims 1 to 5, and a chip arranged on the insulating substrate.

7. A method for preparing an insulating substrate, characterized in that: The preparation method is used to prepare the insulating substrate according to any one of claims 1 to 5, and the preparation method comprises the following steps: Providing the heat dissipation layer; forming the insulating layer on the heat dissipation layer, and arranging a plurality of the crack preventing bodies in the insulating layer before the insulating layer is cured; The wiring layer is formed on the cured insulating layer.

8. The method for preparing an insulating substrate according to claim 7, wherein: Before forming the insulating layer on the heat dissipation layer, the method further includes: The surface of the heat dissipation layer which will form the insulating layer is subjected to surface treatment.

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