Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, which belong to the field of display technology. The display panel includes a crack detection line, an electrostatic release line, a charge release circuit and a connecting component. Among them, the connecting component can control the on-off between the charge release circuit and the electrostatic release line. When the charge release circuit is connected to the electrostatic release line, the charge release circuit can release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line. In this way, the on-off of the charge release circuit and the electrostatic release line can be flexibly controlled by the connecting component to ensure that the charge on the crack detection line is effectively released, so as to avoid the short circuit between the crack detection line and the electrostatic release line caused by the breakdown of the charge release circuit, thereby ensuring the reliability of crack detection.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, in order to ensure the factory yield of display substrates, a panel crack detect (PCD) line is often arranged at the edge of the display substrate to detect whether cracks occur in the display substrate. Summary of the invention

[0003] The present disclosure provides a display panel and a display device, which can solve the problem in the related art that the crack detection line and the static electricity release line are short-circuited due to the breakdown failure of the charge release circuit, resulting in poor crack detection reliability. The technical solution is as follows:

[0004] In one aspect, a display panel is provided, the display panel comprising:

[0005] A substrate having a non-display area;

[0006] a crack detection line, located in the non-display area, the crack detection line having a first line segment and a second line segment connected to each other, the first line segment is also connected to the signal output unit, the second line segment is also connected to the signal receiving unit, the crack detection line is used to transmit a second signal for crack detection to the signal receiving unit through the second line segment based on a first signal provided by the signal output unit to the first line segment;

[0007] The charge release circuit, the electrostatic release line and the connecting component are all located in the non-display area. The connecting component is respectively connected to the charge release circuit and the electrostatic release line, and the charge release circuit is also respectively connected to the first line segment and the second line segment. The connecting component is used to control the on-off of the charge release circuit and the electrostatic release line. The charge release circuit is used to release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line when connected to the electrostatic release line.

[0008] Optionally, the connecting component includes: a switch circuit;

[0009] The switch circuit is respectively connected to the first line segment, the electrostatic release line and the charge release circuit, and is used to control the on / off of the charge release circuit and the electrostatic release line in response to a first signal provided by the signal transmission unit to the first line segment.

[0010] Optionally, the switch circuit includes: a switch transistor;

[0011] The gate of the switch transistor is connected to the first line segment, the first electrode of the switch transistor is connected to the charge release circuit, and the second electrode of the switch transistor is connected to the static electricity release line.

[0012] Optionally, the switch transistor is a dual-gate transistor, and the charge release circuit and the switch transistor both include:

[0013] An active layer and a first gate metal layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first gate metal layer on the substrate overlaps with an orthographic projection of the active layer on the substrate;

[0014] Among them, the overlapping area of ​​the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the active layer on the substrate in the charge release circuit is smaller than the overlapping area of ​​the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the active layer on the substrate in the switching transistor.

[0015] Optionally, the connecting component is connected to the charge release circuit via a connecting lead, and both the connecting lead and the electrostatic release line include: a first metal layer located on one side of the substrate, and the connecting lead and the electrostatic release line are spaced apart from each other;

[0016] The display panel further comprises: an insulating layer located in the non-display area and located on a side of the first metal layer away from the substrate, and two via holes located in the insulating layer and spaced apart from each other;

[0017] The connecting component includes: a second metal layer located on the side of the first metal layer away from the substrate, the second metal layer is overlapped with the connecting lead and the electrostatic release line respectively through the two vias to connect the charge release circuit with the electrostatic release line; and the second metal layer has at least one cutting hole on the side away from the substrate, and the at least one cutting hole is used to cut off the second metal layer to disconnect the charge release circuit from the electrostatic release line.

[0018] Optionally, the insulating layer includes: a first insulating layer and a second insulating layer stacked in sequence in a direction away from the substrate;

[0019] The two via holes penetrate the first insulating layer;

[0020] Furthermore, the second metal layer is located between the first insulating layer and the second insulating layer.

[0021] Optionally, the insulating layer includes: a first insulating layer and a second insulating layer stacked in sequence in a direction away from the substrate;

[0022] The two via holes penetrate the first insulating layer and the second insulating layer;

[0023] Furthermore, the second metal layer is located on a side of the second insulating layer away from the substrate.

[0024] Optionally, the substrate further has a display area, and the non-display area at least partially surrounds the display area; the display panel further includes:

[0025] A first source-drain metal layer, a passivation layer, a second source-drain metal layer, a planarization layer, and an anode layer are located in the display area and sequentially stacked in a direction away from the substrate;

[0026] Wherein, the first metal layer and the first source-drain metal layer are located in the same layer, the first insulating layer and the passivation layer are located in the same layer, and the second insulating layer and the planarization layer are located in the same layer;

[0027] If the second metal layer is located between the first insulating layer and the second insulating layer, the second metal layer and the second source-drain metal layer are located in the same layer;

[0028] If the second metal layer is located on the side of the second insulating layer away from the substrate, the second metal layer and the anode layer are located on the same layer, or, in the second metal layer, the portion located on the side of the second insulating layer away from the substrate and the portion located in the via hole passing through the second insulating layer are both located on the same layer as the anode layer, and the portion located in the via hole passing through the first insulating layer is located on the same layer as the second source and drain metal layer.

[0029] Optionally, a side of the second metal layer away from the substrate has a plurality of cutting holes connected in series.

[0030] In another aspect, a display device is provided, the display device comprising: a crack detection circuit, and the display panel as described in the above aspect;

[0031] The crack detection circuit is connected to a signal output portion in the display panel and is used to provide a first signal to the signal output portion for performing crack detection through a crack detection line in the display panel.

[0032] In summary, the beneficial effects brought about by the technical solution provided by the embodiments of the present disclosure may at least include:

[0033] A display panel and a display device are provided. The display panel includes a crack detection line, an electrostatic release line, a charge release circuit and a connecting component. The connecting component can control the on-off between the charge release circuit and the electrostatic release line. When the charge release circuit is connected to the electrostatic release line, the charge release circuit can release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line. In this way, the on-off of the charge release circuit and the electrostatic release line can be flexibly controlled by the connecting component, so as to avoid the short circuit between the crack detection line and the electrostatic release line due to the breakdown of the charge release circuit under the premise of ensuring the effective release of the charge on the crack detection line, thereby ensuring the reliability of crack detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0036] Figure 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0037] Figure 3 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0038] Figure 4 yes Figure 3 An equivalent circuit diagram of the structure shown;

[0039] Figure 5 yes Figure 3 A structural layout of the structure shown;

[0040] Figure 6 yes Figure 5 A structural layout of the active layer in the structure shown;

[0041] Figure 7 yes Figure 5 A structural layout of an active layer and a first gate metal layer in the structure shown;

[0042] Figure 8 yes Figure 5 A structural layout of an active layer, a first gate metal layer and a second gate metal layer in the structure shown;

[0043] Fig. 9 yes Figure 5A structural layout of an active layer, a first gate metal layer, a second gate metal layer and an interlayer dielectric layer in the structure shown;

[0044] Fig.10 is a structural diagram of another display panel provided by an embodiment of the present disclosure;

[0045] Fig.11 yes Fig.10 A cross-sectional view of the structure shown in the NN' direction;

[0046] Fig.12 yes Fig.10 Another cross-sectional view of the structure shown in the NN' direction;

[0047] Fig.13 yes Fig.10 Another cross-sectional view of the structure shown in the NN' direction;

[0048] Fig.14 yes Fig.10 Another cross-sectional view of the structure shown in the NN' direction;

[0049] Fig.15 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0051] At present, the material of the PCD routing used for crack detection is generally metal material, which can also be called metal routing. The PCD routing usually needs to be distributed to the pre-inspection area where crack detection is required, which makes a large amount of metal material, that is, a large area of ​​metal exposed in the process. For example, in dry etching, plasma enhanced chemical vapor deposition (PECVD), plasma or glass generates friction with equipment components during the process. This will further cause a large amount of charge to accumulate on the surface of the PCD routing. The accumulated charge will not only affect the reliability of crack detection, but also cause irreversible damage to the display substrate.

[0052] Based on this, an electrostatic discharge (ESD) circuit is often introduced to release the accumulated charge to improve the reliability of crack detection and ensure a good factory yield of the display substrate. For example, an electrostatic discharge line can be set, and an ESD circuit can be set to be connected to the PCD line and the electrostatic discharge line respectively. The ESD circuit can release the charge accumulated on the surface of the PCD line based on the signal provided by the electrostatic discharge line. Among them, the electrostatic discharge line is generally a pull-down power line that can provide a low-level signal, that is, a VSS signal line, and the voltage of the low-level signal is usually -3 volts (V).

[0053] However, after testing, it was found that the set ESD circuit was easily broken down, resulting in a short circuit (short) between the VSS signal line and the PCD line, that is, the two were shorted. Since the VSS line is usually located on the same layer as the source & drain (SD) metal layer in the display substrate, and the PCD line is usually located on the same layer as the gate metal layer, the short circuit between the VSS line and the PCD line can also be understood as: there is a short between the gate metal layer and the SD metal layer in the display substrate. The short between the two will also affect the reliability of crack detection.

[0054] Among them, the method of using PCD routing for crack detection includes: image quality detection and resistance detection. For image quality detection, one end of the PCD routing is connected to a pin (also called a Pin foot) in the crack detection circuit to receive a high-level signal from the Pin foot, and the other end is connected to a data line connected to a pixel in the display substrate to light up the pixel through the data line, and perform crack detection based on the lighting result. When the PCD routing is short-circuited with the VSS routing, the signal on the PCD routing will be pulled down by the low-level signal (such as -3V) provided by the VSS routing, the pixel will emit light abnormally, and the display substrate will produce a vertical bright line, making it impossible to identify the real crack. For resistance detection, one end and the other end of the PCD routing are respectively connected to different Pin feet on the crack detection circuit, so as to indicate an electrical signal of the resistance value to another Pin foot based on a signal from one Pin foot, and perform crack detection based on the electrical signal. When the PCD line is short-circuited with the VSS line, the electrical signal will be abnormal, thereby affecting the accuracy of crack detection and interfering with the yield grading result of the display substrate, thereby causing yield loss of the display substrate, that is, affecting the production capacity and yield of the display substrate.

[0055] The embodiment of the present application provides a display panel, in which the electrostatic release line and the ESD circuit are movably connected through a connecting component, that is, not fixedly connected. In this way, when the ESD circuit is broken down, the connection between the electrostatic release line and the ESD circuit can be cut off by the connecting component, thereby avoiding a short circuit between the electrostatic release line and the PCD line connected to the ESD circuit. Under the premise of releasing the charge, the crack detection accuracy is ensured to be good.

[0056] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1 As shown, the display panel includes: a substrate 01, the substrate 01 having a non-display area B1. On this basis, the display panel also includes: a crack detection line (i.e., PCD line) located in the non-display area B1, a charge release circuit (i.e., ESD circuit) 02, an electrostatic release line (e.g., a pull-down power line VSS line), and a connecting component 03.

[0057] The crack detection line PCD has a first line segment PCD1 and a second line segment PCD2 connected to each other, and the first line segment PCD1 is also connected to the signal output unit, and the second line segment PCD2 is also connected to the signal receiving unit. The crack detection line PCD is used to transmit a second signal for crack detection to the signal receiving unit based on the first signal provided by the signal output unit to the first line segment PCD1.

[0058] For example, in combination with the above embodiments, it can be seen that Figure 1 In the image quality detection mode, the signal output unit can be connected to the crack detection circuit, such as being bound to the Pin of the crack detection circuit. The signal receiving unit can be a data line Data connected to the pixel. Accordingly, the first signal can be a high-level signal VGH from the Pin, and the second signal can be a data signal for lighting the pixel. If the pixel is lit normally, it can be determined that there is no crack on the display panel; if the pixel is lit abnormally, it can be determined that there is a crack on the display panel. In the resistance detection mode, the signal output unit and the signal receiving unit can be respectively bound to two different Pins of the crack detection circuit. Accordingly, the first signal can be a high-level signal VGH from the Pin, and the second signal can be an electrical signal that can indicate the resistance value on the crack detection line PCD. If the resistance value is normal, it can be determined that there is no crack on the display panel; if the resistance value is abnormal, it can be determined that there is a crack on the display panel.

[0059] Continue to refer Figure 1, the connecting component 03 is respectively connected to the charge release circuit 02 and the electrostatic release line VSS, and the charge release circuit 02 is also respectively connected to the first line segment PCD1 and the second line segment PCD2. Among them, the connecting component 03 is used to control the on-off of the charge release circuit 02 and the electrostatic release line VSS. That is, in the embodiment of the present disclosure, the charge release circuit 02 and the electrostatic release line VSS can be movably connected through the connecting component 03, rather than fixedly connected. The charge release circuit 02 is used to release the charge (i.e., static electricity) accumulated on the crack detection line PCD based on the electrical signal provided by the electrostatic release line VSS when connected to the electrostatic release line VSS.

[0060] Thus, it can be known that in the disclosed embodiment, when crack detection is performed and / or when the charge release circuit 02 is broken down, the connection between the charge release circuit 02 and the electrostatic release line VSS can be cut off by the connection component 03, that is, the charge release circuit 02 is controlled to be disconnected from the electrostatic release line VSS to avoid the crack detection line PCD and the electrostatic release line VSS being short-circuited and affecting the crack detection result. And, when crack detection is not performed and / or the charge release circuit 02 is not broken down, the charge release circuit 02 can be controlled to be reliably connected to the electrostatic release line VSS by the connection component 03, so that the charge release circuit 02 can reliably release the charge accumulated on the crack detection line PCD based on the electrical signal provided by the electrostatic release line VSS, further avoiding affecting the crack detection.

[0061] In summary, an embodiment of the present disclosure provides a display panel, which includes a crack detection line, an electrostatic release line, a charge release circuit and a connecting component. Among them, the connecting component can control the on-off between the charge release circuit and the electrostatic release line. When the charge release circuit is connected to the electrostatic release line, the charge release circuit can release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line. In this way, the on-off of the charge release circuit and the electrostatic release line can be flexibly controlled by the connecting component to ensure that the charge on the crack detection line is effectively released, thereby avoiding the short circuit between the crack detection line and the electrostatic release line due to the breakdown of the charge release circuit, thereby ensuring the reliability of crack detection.

[0062] As an optional implementation: refer to Figure 2 It can be seen from the other display panel shown that the connecting component 03 described in the embodiment of the present disclosure may include: a switch circuit 031.

[0063] The switch circuit 031 can be connected to the first line segment PCD1, the static discharge line VSS and the charge discharge circuit 02 respectively. The switch circuit 031 can be used to control the connection between the charge discharge circuit 02 and the static discharge line VSS in response to the first signal provided by the signal output unit to the first line segment PCD1.

[0064] For example, the switch circuit 031 can control the charge release circuit 02 to be connected to the electrostatic release line VSS when the potential of the first signal is a first potential, and can control the charge release circuit 02 to be disconnected from the electrostatic release line VSS when the potential of the first signal is a second potential.

[0065] Among them, for the switch circuit 031, the first potential can be an effective potential, the second potential can be an invalid potential, and the first potential can be a high potential relative to the second potential. Because when crack detection is performed, the first signal provided by the signal output unit is generally a high-level signal VGH, that is, a high-potential signal; when crack detection is not performed, the signal output unit is generally in a floating state, and the first signal is a low potential at this time. Therefore, for this implementation method, the switch circuit 031 can control the charge release circuit 02 to disconnect from the electrostatic release line VSS when crack detection is performed, to prevent the electrostatic release line VSS from being short-circuited with the crack detection line PCD due to the breakdown of the charge release circuit 02, thereby avoiding over-detection. And when crack detection is not performed, the charge release circuit 02 can be controlled to be turned on with the electrostatic release line VSS, so that the charge release circuit 02 can reliably release the charge accumulated on the crack detection line PCD based on the signal provided by the electrostatic release line VSS.

[0066] Optional, with Figure 2 Take the structure shown as an example, Figure 3 A schematic diagram of the structure of another display panel is shown. Figure 3 It can be seen that the switch circuit 031 described in the above embodiment may include: a switch transistor T1.

[0067] The gate of the switch transistor T1 may be connected to the first line segment PCD1 , the first electrode of the switch transistor T1 may be connected to the charge release circuit 02 , and the second electrode of the switch transistor T1 may be connected to the static electricity release line VSS.

[0068] Optionally, the switch transistor T1 may be a thin film transistor, a field effect transistor or other devices with the same characteristics, and the switch transistor T1 may be an N-type transistor that is turned on in response to an effective potential of a high potential. In addition, because the source and drain of the switch transistor are symmetrical, the source and drain are interchangeable. Accordingly, in the embodiment of the present disclosure, the source may be referred to as the first pole, and the drain may be referred to as the second pole. Alternatively, the drain may be referred to as the first pole, and the source may be referred to as the second pole. Of course, in some other embodiments, the switch transistor T1 may also be a P-type transistor, in which case the first potential may be a low potential relative to the second potential. Accordingly, the first signal during crack detection may be a low potential.

[0069] For example, taking the switch transistor T1 as an N-type transistor, when the first signal provided by the signal output unit to the first line segment PCD1 is a high potential, the switch transistor T1 can be turned on, at which time, the first electrode and the second electrode of the switch transistor T1 are connected, and then the charge release circuit 02 is connected to the electrostatic release line VSS. When the first signal provided by the signal output unit to the first line segment PCD1 is a low potential, the switch transistor T1 can be turned off, at which time, the first electrode and the second electrode of the switch transistor T1 are disconnected, and then the charge release circuit 02 is disconnected from the electrostatic release line VSS.

[0070] Optionally, the gate of the switch transistor T1 may also be connected to other power supply terminals that can provide low potential and high potential at different times, instead of being connected to the first line segment PCD1.

[0071] Optional, with Figure 3 Take the structure shown as an example, Figure 4 A schematic structural diagram of another display panel is shown. Figure 4 , the equivalent circuit diagram of the charge release circuit 02 and the equivalent circuit diagram of the switch transistor T1 are specifically shown. Figure 4 It can be seen that the switch transistor T1 can be equivalent to a single-pole single-throw switch. The charge release circuit 02 can be equivalent to a plurality of switch tubes T0, and four switch tubes T0 are shown in the figure. The gate of each switch tube T0 can be connected to the first electrode of the switch transistor T1, and the first electrode and the second electrode of each switch tube T0 can be connected to the crack detection line PCD. When the switch transistor T1 controls the electrostatic release line VSS to be connected to the switch tube T0, the switch tube T0 can reliably release the charge accumulated on the crack detection line PCD based on the electrical signal provided by the electrostatic release line VSS.

[0072] by Figure 3 and Figure 4 Take the structure shown as an example, Figure 5 FIG. 2 shows a schematic diagram of the structure of another display panel. Figure 5 As shown, the charge release circuit 02 and the switch transistor T1 may include: an active (poly) layer P1 and a first gate metal layer Gate1 stacked in sequence in a direction away from the substrate 01. The orthographic projection of the first gate metal layer Gate1 on the substrate 01 overlaps with the orthographic projection of the active layer P1 on the substrate 01.

[0073] Among them, the overlapping area of ​​the orthographic projection of the first gate metal layer Gate1 on the substrate 01 and the orthographic projection of the active layer P1 on the substrate 01 in the charge release circuit 02 can be smaller than the overlapping area of ​​the orthographic projection of the first gate metal layer Gate1 on the substrate 01 and the orthographic projection of the active layer P1 on the substrate 01 in the switch transistor T1, and the switch transistor T1 can be a dual-gate transistor. And the switch transistor T1 can be a dual-gate transistor. A dual-gate transistor refers to a transistor with two gates (i.e., two parts of the first gate metal layer Gate1 shown in the figure).

[0074] Because for the charge release circuit 02 and the switch transistor T1, the overlapping part of its active layer P1 and the first gate metal layer Gate1 can form a capacitor, the area of ​​the capacitor (i.e., the overlapping area) is positively correlated with its antistatic ability, that is, the larger the overlapping area, the stronger the antistatic ability. Therefore, by setting the overlapping area of ​​the first gate metal layer Gate1 and the active layer P1 in the charge release circuit 02 to be smaller than the overlapping area of ​​the first gate metal layer Gate1 and the active layer P1 in the switch transistor T1, the antistatic ability of the switch transistor T1 can be increased and the antistatic ability of the charge release circuit 02 can be reduced. In this way, the static electricity accumulated on the crack detection line PCD can be fully discharged through the charge release circuit 02, preventing the static electricity from being unable to be released and causing the devices at other positions (such as the switch transistor T1) to be damaged. That is, the switch transistor T1 can be effectively protected to ensure its working safety.

[0075] Optional, still reference Figure 4 It can be seen that the charge release circuit 02 and the switch transistor T1 may also include: a second gate metal layer Gate2, an inner layer dielectric (ILD) layer and a first source-drain metal layer SD1, which are located on the side of the first gate metal layer Gate1 away from the substrate 01 and are stacked in sequence. The ILD layer may also be called a connection (CNT) layer. Of course, an insulating layer is also required between the first gate metal layer Gate1 and the second gate metal layer Gate2 to insulate the two gate metal layers.

[0076] The crack detection line PCD may be located in the same layer as the second gate metal layer Gate2. The line segment connecting the first line segment PCD1 and the switch transistor T1 may be located in the same layer as the first source-drain metal layer SD1. The interlayer dielectric layer ILD may be used to form a via K0, so that the first source-drain metal layer SD1 is connected to the first gate metal layer Gate1 and the second gate metal layer Gate2 through the via K0. Since the layout structure of the charge release circuit 02 is ring-shaped, the charge release circuit 02 may also be called an ESD ring.

[0077] It should be noted that being located in the same layer may refer to: using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. In this way, the manufacturing process can be simplified and manufacturing costs can be saved.

[0078] Optional, with Figure 5 Take the structure shown as an example, Figures 6 to 9 The structure layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2 and the interlayer dielectric layer ILD are shown respectively. Figure 7 It can be seen that the switch transistor T1 includes two first gate metal layers Gate1 and is a dual-gate transistor.

[0079] In combination with the above embodiments, it can be known that for the first implementation method, it can be considered to change the backplane (BP) module of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD and the first source and drain metal layer SD1, and add a switch transistor T1 to the connection line between the ESD ring and the electrostatic release line VSS, and use the signal on the first line segment as the gate signal of the switch transistor T1, so as to achieve the purpose of isolating the electrostatic release line VSS from the charge release circuit 02 during crack detection. In the crack detection process, it can prevent the crack detection line PCD and the electrostatic release line VSS from crosstalking each other after the charge release circuit 02 fails due to breakdown, that is, effectively shield the signal provided by the electrostatic release line VSS. In other words, by adding the switch transistor T1, it is possible to effectively release the static electricity on the crack detection line PCD while avoiding interference with crack detection, reduce the defective inspection rate, and improve the yield of the display panel.

[0080] As another optional implementation: refer to Fig.10 As shown in the structural diagram of another display panel, the connection component 03 described in the embodiment of the present disclosure can be connected to the charge release circuit 02 through the connection lead L1. Fig.10 For example, Fig.11 A cross-sectional view of a display panel along the NN′ direction is shown.

[0081] refer to Fig.10 and Fig.11It can be seen that the connecting lead L1 and the electrostatic release line VSS may include: a first metal layer M1 located on one side of the substrate 01, and the connecting lead L1 and the electrostatic release line VSS are spaced apart from each other. That is, the first metal layer M1 included in the connecting lead L1 is spaced apart from the first metal layer M1 included in the electrostatic release line VSS.

[0082] On this basis, combined with Fig.10 and Fig.11 It can also be seen that the display panel recorded in the embodiment of the present disclosure may also include: an insulating layer J1 located in the non-display area B1 and located on the side of the first metal layer M1 away from the substrate 01, and two vias K1 and K2 located in the insulating layer J1 and spaced apart from each other.

[0083] The connection component 03 may include: a second metal layer M2 located on the side of the first metal layer M1 away from the substrate 01. The second metal layer M2 may be connected to the connection lead L1 and the electrostatic release line VSS through the two vias K1 and K2, respectively, to connect the charge release circuit 02 and the electrostatic release line VSS.

[0084] That is, Fig.11 As shown, the second metal layer M2 can overlap with the first metal layer M1 included in the connecting lead L1 through a via K1, and can overlap with the first metal layer M1 included in the electrostatic release line VSS through another via K2. In this way, the cross-layer bridge between the connecting lead L1 and the electrostatic release line VSS can be realized through the second metal layer M2. Since the connecting lead L1 is a line segment used to connect the charge release circuit 02 and the connecting component 03, the cross-layer bridge between the charge release circuit 02 and the electrostatic release line VSS can be realized through the second metal layer M2. On this basis, refer to Fig.11 It can also be seen that the orthographic projection of the via K1 on the substrate 01 can overlap with the orthographic projection of the first metal layer M1 included in the connection lead L1 on the substrate 01. The orthographic projection of the via K2 on the substrate 01 can overlap with the orthographic projection of the first metal layer M1 included in the electrostatic release line VSS on the substrate 01.

[0085] And reference Fig.10 It can be seen that the second metal layer M2 may also have at least one cutting hole Q0 on the side away from the substrate 01, and the at least one cutting hole Q0 is used to cut the second metal layer M2 to disconnect the charge release circuit 02 from the electrostatic release line VSS. That is, a cutting position may be reserved on the second metal layer M2.

[0086] For example, the second metal layer M2 may have a plurality of cutting holes Q0 connected in series on one side away from the substrate 01. On this basis, the second metal layer M2 may be cut multiple times along the plurality of cutting holes Q0 to ensure the cutting effect and ensure that the second metal layer M2 can be completely cut off, thereby further ensuring that the charge release circuit 02 and the electrostatic release line VSS can be reliably disconnected.

[0087] In the disclosed embodiment, if breakdown failure of the charge release circuit 02 is detected, the second metal layer M2 can be cut along the cutting hole Q0, i.e., the connecting component 03 can be cut, such as by laser cutting. After the second metal layer M2 is cut off, the connecting lead L1 used to connect the charge release circuit 02 and the connecting component 03 is disconnected from the electrostatic release line VSS, and then the charge release circuit 02 is disconnected from the electrostatic release line VSS. Accordingly, the cutting hole Q0 can also be referred to as a laser cutting hole. In addition, the second metal layer M2 is provided as the connecting component 03 to bridge the charge release circuit 02 and the electrostatic release line VSS across the layer, and the impedance on the electrostatic release line VSS can also be increased to enhance the anti-static ability of the electrostatic release line VSS.

[0088] Optional, Fig.12 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure along the NN′ direction. Fig.13 FIG. 2 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure along the NN′ direction. Fig.12 and Fig.13 It can be seen that the insulating layer J1 described in the above embodiment may include: a first insulating layer J11 and a second insulating layer J12 sequentially stacked in a direction away from the substrate 01 .

[0089] Furthermore, the two via holes K1 and K2 located in the insulating layer J1 may only penetrate the first insulating layer J11 to expose the first metal layer M1. Fig.12 As shown, the second metal layer M2 may be located between the first insulating layer J11 and the second insulating layer J12, that is, located on the side of the first insulating layer J11 away from the substrate 01. The second metal layer M2 may be effectively overlapped with the first metal layer M1 through two vias K1 and K2 penetrating the first insulating layer J11.

[0090] Alternatively, refer to Fig.13 In another display panel shown, two via holes K1 and K2 in the insulating layer J1 can penetrate both the first insulating layer J11 and the second insulating layer J12 to expose the first metal layer M1. On this basis, the second metal layer M2 can be located on the side of the second insulating layer J12 away from the substrate 01. The second metal layer M2 can be effectively overlapped with the first metal layer M1 through the two via holes K1 and K2 that penetrate the first insulating layer J11 and the second insulating layer J12.

[0091] Optionally, the substrate 01 described in the embodiment of the present disclosure may also have a display area (not shown in the figure), and the non-display area B1 may at least partially surround the display area. For example, the non-display area B1 may surround the display area A1. The display panel may also include: a first source-drain metal layer SD1, a passivation layer PVX1, a second source-drain metal layer SD2, a planarization layer PLN1, and an anode layer Anode, which are located in the display area A1 and are sequentially stacked in a direction away from the substrate 01.

[0092] On this basis, reference Fig.12 and Fig.13 It can be seen that the first metal layer M1 recorded in the above embodiment can be located in the same layer as the first source and drain metal layer SD1, the first insulating layer J11 can be located in the same layer as the passivation layer PVX1, and the second insulating layer J12 can be located in the same layer as the planarization layer PLN1.

[0093] Furthermore, if the second metal layer M2 is located between the first insulating layer J11 and the second insulating layer J12, that is, Fig.12 As shown in the structure, the second metal layer M2 can be located in the same layer as the second source-drain metal layer SD2.

[0094] In this way, the cutting hole position can be reserved after the process of the first source-drain metal layer SD1 included in the BP module. Then in the BP factory, in the process of the passivation layer PVX1, a new mask is introduced to realize the opening, where the opening means: opening vias K1 and K2 that penetrate the passivation layer PVX1. Finally, in the process of the second source-drain metal layer SD2 included in the BP module, the second source-drain metal layer SD2 is filled in the vias K1 and K2 to realize the cross-layer bridge between the charge release circuit 02 and the electrostatic release line VSS.

[0095] If the second metal layer M2 is located on the side of the second insulating layer J12 away from the substrate 01, that is, Fig.13 As shown in the structure, the second metal layer M2 and the anode layer Anode can be located in the same layer.

[0096] In this way, the cutting hole position can be reserved after the process of the first source-drain metal layer SD1 included in the BP module. Then in the BP factory, in the process of the passivation layer PVX1 and the flat layer PLN1, a new mask is introduced to realize the opening. The opening here means: opening vias K1 and K2 that penetrate the passivation layer PVX1 and the flat layer PLN1. Finally, in the process of the anode layer Anode included in the BP module, the anode layer Anode is filled in the vias K1 and K2 to realize the cross-layer bridge between the charge release circuit 02 and the electrostatic release line VSS.

[0097] Alternatively, refer to Fig.14 As shown in the other display panel, Fig.13 Based on the structure, in the second metal layer M2, the portion located on the side of the second insulating layer J12 away from the substrate 01 and the portion located at the vias K1 and K2 passing through the second insulating layer J12 can both be located on the same layer as the anode layer Anode, and the portion located at the vias K1 and K2 passing through the first insulating layer J11 can be located on the same layer as the second source and drain metal layer SD2.

[0098] In this way, the cutting hole position can be reserved after the process of the first source-drain metal layer SD1 included in the BP module. Then in the BP factory, in the process of the passivation layer PVX1 and the flat layer PLN1, a new mask plate is introduced to realize the opening, and the opening here means: opening vias K1 and K2 that penetrate the passivation layer PVX1 and the flat layer PLN1. Finally, in the process of the second source-drain metal layer SD2 and the anode layer Anode included in the BP module, the second source-drain metal layer SD2 is filled in the part where the via K1 and the via K2 penetrate the passivation layer PVX1, and the anode layer Anode is filled in the part where the via K1 and the via K2 penetrate the passivation layer PVX1, so as to realize the cross-layer bridge between the charge release circuit 02 and the electrostatic release line VSS.

[0099] Optionally, in the embodiment of the present disclosure, the non-display area B1 may include a barrier dam located farthest from the display area. Figures 10 to 14 The connection component 03 (i.e., the second metal layer M2) of the implementation shown can be located on the side of Dam away from the display area. This area can also be called the PNL PAD area. In this way, it can be avoided that when the second metal layer M2 is cut to disconnect the charge release circuit 02 from the static discharge line VSS, part of the film layer close to the display area is cut by mistake, thereby ensuring the safety of the circuit operation in the display area.

[0100] Optional, reference Figures 11 to 14 It can also be seen that, in addition to the above film layers, the display panel may also include: a multilayer insulating layer J0 located in the non-display area B1 and between the substrate 01 and the first metal layer M1, the multilayer insulating layer J0 may include: a protection (barrier) layer, a gate insulator (GI) layer and / or an inter-level dielectric (ILD) layer. And, an encapsulation (EN) layer and / or a touch screen TSP located on the side of the second insulating layer J12 away from the substrate 01.

[0101] It should be noted that in the embodiment of the present disclosure, the number and arrangement of the insulating layers can be appropriately adjusted according to actual needs. The EN layer, the touch screen TSP and the insulating layer J1 on the side of the second metal layer M2 away from the substrate 01 are generally made of transparent materials, so the position of the cutting hole Q0 can be observed through the layers on the side of the second metal layer M2 away from the substrate 01 through a microscope or other equipment, so as to achieve reliable cutting of the second metal layer M2. In addition, the process of cutting the second metal layer can be performed at any time after the substrate (Array) process of the display panel and before the touch (Touch) process.

[0102] Combined with the above records, it can be known that in the embodiment of the present disclosure, by setting the second metal layer M2 and setting a cutting hole on one side of the second metal layer M2, a maintenance channel can be provided for the BP module and the back-end process (which can also be understood as the back-end factory, including EV, EN or TSP), so that after the charge release circuit 02 is broken down, the second metal layer M2 is cut by laser to disconnect the connection between the charge release circuit 02 and the electrostatic release line VSS, thereby avoiding the short circuit between the electrostatic release line VSS and the crack detection line PCD. That is, while effectively releasing the charge, the reliability of crack detection can be ensured, thereby improving the yield of the display panel.

[0103] Optionally, in the embodiment of the present disclosure, the substrate 01 may be a flexible substrate. Of course, in some other embodiments, the substrate 01 may also be a glass substrate or a substrate of other materials.

[0104] In summary, an embodiment of the present disclosure provides a display panel, which includes a crack detection line, an electrostatic release line, a charge release circuit and a connecting component. Among them, the connecting component can control the on-off between the charge release circuit and the electrostatic release line. When the charge release circuit is connected to the electrostatic release line, the charge release circuit can release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line. In this way, the on-off of the charge release circuit and the electrostatic release line can be flexibly controlled by the connecting component to ensure that the charge on the crack detection line is effectively released, thereby avoiding the short circuit between the crack detection line and the electrostatic release line due to the breakdown of the charge release circuit, thereby ensuring the reliability of crack detection.

[0105] Fig.15 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. Fig.15 As shown, the display device comprises: a crack detection circuit 10, and a display panel 00 as shown in the above figures. The crack detection circuit 10 may be an integrated circuit (IC).

[0106] The crack detection circuit 10 can be connected to a signal output unit in the display panel 00 and used to provide a first signal to the signal output unit for performing crack detection through a crack detection line PCD in the display panel. For example, the signal output unit can be bound to a pin of the crack detection circuit 10.

[0107] For example, Fig.15 The display panel 00 also includes a display area A1 and a non-display area B1 of the substrate 01. Also, the crack detection line PCD, the charge release circuit 02, the connection component 03 and the static electricity release line VSS located in the non-display area B1 are shown. Fig.15 It can be seen that the first line segment PCD1 of the crack detection line PCD can be connected to the pin of the crack detection circuit 10, and the second line segment PCD2 can be connected to the data line Data in the display area A1. Alternatively, in some other embodiments, the second line segment PCD2 can be connected to another pin of the crack detection circuit 10.

[0108] Optionally, the display device can be: an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a liquid crystal display (LCD) device, a sub-millimeter mini-LED display device, a micro-LED display device, a mobile phone, a tablet computer, a television, a monitor, or any other product or component with a display function.

[0109] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0110] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0111] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0112] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0113] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0114] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0115] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: A substrate having a non-display area; a crack detection line, located in the non-display area, the crack detection line having a first line segment and a second line segment connected to each other, the first line segment is also connected to the signal output unit, the second line segment is also connected to the signal receiving unit, the crack detection line is used to transmit a second signal for crack detection to the signal receiving unit through the second line segment based on a first signal provided by the signal output unit to the first line segment; The charge release circuit, the electrostatic release line and the connecting component are all located in the non-display area. The connecting component is respectively connected to the charge release circuit and the electrostatic release line, and the charge release circuit is also respectively connected to the first line segment and the second line segment. The connecting component is used to control the on-off of the charge release circuit and the electrostatic release line. The charge release circuit is used to release the charge on the crack detection line based on the electrical signal provided by the electrostatic release line when connected to the electrostatic release line.

2. The display panel according to claim 1, characterized in that: The connecting component includes: a switch circuit; The switch circuit is respectively connected to the first line segment, the electrostatic release line and the charge release circuit, and is used to control the on and off of the charge release circuit and the electrostatic release line in response to a first signal provided by the signal output unit to the first line segment.

3. The display panel according to claim 2, characterized in that: The switch circuit comprises: a switch transistor; The gate of the switch transistor is connected to the first line segment, the first electrode of the switch transistor is connected to the charge release circuit, and the second electrode of the switch transistor is connected to the static electricity release line.

4. The display panel according to claim 3, characterized in that: The switch transistor is a dual-gate transistor, and the charge release circuit and the switch transistor both include: An active layer and a first gate metal layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first gate metal layer on the substrate overlaps with an orthographic projection of the active layer on the substrate; Among them, the overlapping area of ​​the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the active layer on the substrate in the charge release circuit is smaller than the overlapping area of ​​the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the active layer on the substrate in the switching transistor.

5. The display panel according to claim 1, characterized in that: The connecting component is connected to the charge release circuit via a connecting lead, and both the connecting lead and the electrostatic release line include: a first metal layer located on one side of the substrate, and the connecting lead and the electrostatic release line are spaced apart from each other; The display panel further comprises: an insulating layer located in the non-display area and located on a side of the first metal layer away from the substrate, and two via holes located in the insulating layer and spaced apart from each other; The connecting component includes: a second metal layer located on the side of the first metal layer away from the substrate, the second metal layer is overlapped with the connecting lead and the electrostatic release line respectively through the two vias to connect the charge release circuit with the electrostatic release line; and the second metal layer has at least one cutting hole on the side away from the substrate, and the at least one cutting hole is used to cut off the second metal layer to disconnect the charge release circuit from the electrostatic release line.

6. The display panel according to claim 5, characterized in that: The insulating layer comprises: a first insulating layer and a second insulating layer sequentially stacked in a direction away from the substrate; The two via holes penetrate the first insulating layer; Furthermore, the second metal layer is located between the first insulating layer and the second insulating layer.

7. The display panel according to claim 5, characterized in that: The insulating layer comprises: a first insulating layer and a second insulating layer sequentially stacked in a direction away from the substrate; The two via holes penetrate the first insulating layer and the second insulating layer; Furthermore, the second metal layer is located on a side of the second insulating layer away from the substrate.

8. The display panel according to claim 6 or 7, characterized in that: The substrate further has a display area, and the non-display area at least partially surrounds the display area; the display panel further includes: A first source-drain metal layer, a passivation layer, a second source-drain metal layer, a planarization layer, and an anode layer are located in the display area and sequentially stacked in a direction away from the substrate; Wherein, the first metal layer and the first source-drain metal layer are located in the same layer, the first insulating layer and the passivation layer are located in the same layer, and the second insulating layer and the planarization layer are located in the same layer; If the second metal layer is located between the first insulating layer and the second insulating layer, the second metal layer and the second source-drain metal layer are located in the same layer; If the second metal layer is located on the side of the second insulating layer away from the substrate, the second metal layer and the anode layer are located on the same layer, or, in the second metal layer, the portion located on the side of the second insulating layer away from the substrate and the portion located in the via hole passing through the second insulating layer are both located on the same layer as the anode layer, and the portion located in the via hole passing through the first insulating layer is located on the same layer as the second source and drain metal layer.

9. The display panel according to any one of claims 5 to 7, characterized in that: The second metal layer has a plurality of cutting holes connected in series on a side away from the substrate.

10. A display device, characterized in that: The display device comprises: a crack detection circuit, and a display panel according to any one of claims 1 to 9; The crack detection circuit is connected to a signal output portion in the display panel and is used to provide a first signal to the signal output portion for performing crack detection through a crack detection line in the display panel.

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