Display substrate

Abstract

The present invention provides a display substrate comprising a first buffer layer, a first gate insulating layer, a second gate insulating layer, and a second buffer layer. The first buffer layer is used to dispose the polysilicon in a polysilicon thin-film transistor. The first gate insulating layer is disposed on the first buffer layer and covers the polysilicon disposed on the first buffer layer. The second gate insulating layer is disposed on the first gate insulating layer. The second buffer layer is disposed on the second gate insulating layer. The oxide in an oxide thin-film transistor is disposed on the second buffer layer. The display substrate provided by the present invention can reduce the degree of substrate warping and deformation, improve product production efficiency, and reduce the complexity and cost of the manufacturing process.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate. Background Art

[0002] Low-Temperature Polycrystalline Oxide (LTPO) semiconductor products combine the advantages of high mobility and fast charging of Low-Temperature Poly-Silicon (LTPS) with the low leakage current and low power consumption of Metal Oxide, greatly improving the user experience of display products.

[0003] An existing low-temperature polycrystalline oxide organic light-emitting diode (OLED) array substrate includes a glass substrate (Glass), a first buffer layer (Buffer), a first gate insulating layer (Gate Insulator, abbreviated as GI), a second gate insulating layer, an inter-level dielectric layer (ILD) and a second buffer layer, wherein the first buffer layer is arranged on the glass substrate, polycrystalline silicon (p-Si) of a low-temperature polycrystalline silicon thin-film transistor (TFT) is arranged on the first buffer layer, the first gate insulating layer is arranged on the first buffer layer and covers the polycrystalline silicon, the second gate insulating layer is arranged on the first gate insulating layer, the inter-level dielectric layer is arranged on the second gate insulating layer, the second buffer layer is arranged on the inter-level dielectric layer, and the metal oxide of the metal oxide thin-film transistor is arranged on the second buffer layer.

[0004] However, the existing low-temperature polycrystalline oxide organic light-emitting diode array substrate has a large number of film layers, which may cause the glass substrate to warp and deform due to the stress of each film layer, affecting the production efficiency of the low-temperature polycrystalline oxide product, and also resulting in a complex preparation process and high cost. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art and proposes a display substrate that can reduce the degree of substrate warping and deformation, improve product production efficiency, and reduce the complexity and cost of the preparation process.

[0006] To achieve the above-mentioned objectives, the present invention provides a display substrate, comprising a first buffer layer, a first gate insulating layer, a second gate insulating layer and a second buffer layer, wherein the first buffer layer is used to set the polysilicon in the polysilicon thin film transistor, the first gate insulating layer is set on the first buffer layer and covers the polysilicon set on the first buffer layer, the second gate insulating layer is set on the first gate insulating layer, the second buffer layer is set on the second gate insulating layer, and the second buffer layer is used to set the oxide in the oxide thin film transistor.

[0007] Optionally, the second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is arranged on the first gate insulating layer, the second sub-insulating layer is arranged on the first sub-insulating layer, the second buffer layer is arranged on the second sub-insulating layer, and the hydrogen content in the second sub-insulating layer is less than the hydrogen content in the first sub-insulating layer.

[0008] Optionally, the content of silicon-hydrogen bonds in the second sub-insulating layer is less than the content of silicon-hydrogen bonds in the first sub-insulating layer.

[0009] Optionally, the content of Si-H bonds in the first sub-insulating layer is in a range of 3%-10%, and / or the content of Si-H bonds in the second sub-insulating layer is in a range of 0.5%-3%.

[0010] Optionally, the content of silicon-hydrogen bonds in the second sub-insulating layer is in a range of 0.5%-1.5%.

[0011] Optionally, the density of the second sub-insulating layer is greater than the density of the first sub-insulating layer.

[0012] Optionally, a ratio of silicon to nitrogen in the second sub-insulating layer is greater than a ratio of silicon to nitrogen in the first sub-insulating layer.

[0013] Optionally, the ratio of silicon to nitrogen in the first sub-insulating layer is in the range of 0.7-0.8, and / or the ratio of silicon to nitrogen in the second sub-insulating layer is in the range of 0.8-1.5.

[0014] Optionally, the ratio of silicon to nitrogen in the second sub-insulating layer is in the range of 1-1.5.

[0015] Optionally, the thickness of the first sub-insulating layer is in a range of 50 nm to 150 nm, and / or the thickness of the second sub-insulating layer is in a range of 10 nm to 100 nm.

[0016] The present invention has the following beneficial effects:

[0017] Compared with an existing low-temperature polycrystalline oxide organic light-emitting diode array substrate, the display substrate provided by the present invention does not first provide an interlayer dielectric layer on the second gate insulating layer and then provide a second buffer layer on the interlayer dielectric layer. Instead, the second buffer layer is directly provided on the second gate insulating layer. In other words, compared with an existing low-temperature polycrystalline oxide organic light-emitting diode array substrate, the display substrate provided by the present invention eliminates the interlayer dielectric layer provided between the second gate insulating layer and the second buffer layer, thereby reducing the number of film layers provided on the substrate of the display substrate and reducing the stress of each film layer on the substrate. This can further reduce the degree of warping and deformation of the substrate, improve the production efficiency of the product, and reduce the complexity and cost of the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic structural diagram of a display substrate provided by the present invention;

[0019] Figure 2 Another structural schematic diagram of the display substrate provided by the present invention;

[0020] Description of reference numerals:

[0021] 1-display substrate; 11-substrate; 12-first flexible film layer; 13-first barrier layer; 14-second flexible film layer; 15-second barrier layer; 16-first buffer layer; 17-first gate insulating layer; 18-second gate insulating layer; 181-first sub-insulating layer; 182-second sub-insulating layer; 19-second buffer layer; 21-third gate insulating layer; 22-interlayer dielectric layer; 23-polysilicon; 24-first gate; 25-second gate; 26-oxide; 27-third gate; 28-drain metal connection line; 100-polysilicon thin-film transistor; 200-oxide thin-film transistor. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical aspects of the present invention, the display substrate provided by the present invention is described in detail below with reference to the accompanying drawings.

[0023] like Figure 1 and Figure 2As shown, an embodiment of the present invention provides a display substrate 1, including a first buffer layer 16, a first gate insulating layer 17, a second gate insulating layer 18 and a second buffer layer 19. The first buffer layer 16 is used to set the polysilicon 23 in the polysilicon thin film transistor 100. The first gate insulating layer 17 is set on the first buffer layer 16 and covers the polysilicon 23 set on the first buffer layer 16. The second gate insulating layer 18 is set on the first gate insulating layer 17. The second buffer layer 19 is set on the second gate insulating layer 18. The second buffer layer 19 is used to set the oxide 26 in the oxide thin film transistor 200.

[0024] Compared with an existing low-temperature polycrystalline oxide 26 organic light-emitting diode array substrate, the display substrate 1 provided by the embodiment of the present invention does not first set the interlayer dielectric layer 22 on the second gate insulating layer 18 and then set the second buffer layer 19 on the interlayer dielectric layer 22. Instead, the second buffer layer 19 is directly set on the second gate insulating layer 18. That is, compared with an existing low-temperature polycrystalline oxide 26 organic light-emitting diode array substrate, the display substrate 1 provided by the embodiment of the present invention removes the interlayer dielectric layer 22 set between the second gate insulating layer 18 and the second buffer layer 19, thereby reducing the number of film layers set on the substrate 11 of the display substrate 1, reducing the stress of each film layer on the substrate 11, and further reducing the degree of warping and deformation of the substrate 11, thereby improving the production efficiency of the product and reducing the complexity and cost of the preparation process.

[0025] Optionally, the polysilicon thin film transistor 100 may include a low-temperature polysilicon thin film transistor.

[0026] Optionally, the polysilicon 23 in the low-temperature polysilicon thin film transistor may include low-temperature polysilicon.

[0027] Optionally, the oxide thin film transistor 200 may include a metal oxide thin film transistor.

[0028] Optionally, the oxide 26 in the metal oxide thin film transistor may include indium gallium zinc oxide 26 (Indium Gallium Zinc Oxide, abbreviated as IGZO).

[0029] like Figure 2 As shown, in a preferred embodiment of the present invention, the second gate insulating layer 18 may include a first sub-insulating layer 181 and a second sub-insulating layer 182, the first sub-insulating layer 181 is arranged on the first gate insulating layer 17, the second sub-insulating layer 182 is arranged on the first sub-insulating layer 181, and the second buffer layer 19 is arranged on the second sub-insulating layer 182, and the hydrogen content in the second sub-insulating layer 182 is less than the hydrogen content in the first sub-insulating layer 181.

[0030] This design is due to the fact that the polysilicon thin film transistor 100 has the characteristic of "liking hydrogen (H)". Hydrogen can remove dangling bonds at the interface between the polysilicon 23 and the first gate insulating layer 17 in the polysilicon thin film transistor 100, thereby improving the characteristics of the polysilicon thin film transistor 100. However, the oxide thin film transistor 200 has the characteristic of "disliking hydrogen". Hydrogen will make the characteristics of the oxide thin film transistor 200 unstable. Therefore, on the one hand, by providing the first sub-insulating layer 181 on the first gate insulating layer 17, the first sub-insulating layer 181 is closer to the polysilicon 23 relative to the second sub-insulating layer 182. Since the hydrogen content in the first sub-insulating layer 181 is greater than the hydrogen content in the second sub-insulating layer 182, the hydrogen in the first sub-insulating layer 181 can be more easily freed and diffused to the interface between the polysilicon 23 and the first gate insulating layer 17, so that the hydrogen in the first sub-insulating layer 181 can be used to remove the dangling bonds at the interface between the polysilicon 23 and the first gate insulating layer 17, thereby improving the characteristics of the polysilicon thin film transistor 100. On the other hand, by setting the second sub-insulating layer 182 on the first sub-insulating layer 181 and the second buffer layer 19 on the second sub-insulating layer 182, the second sub-insulating layer 182 is made closer to the oxide 26 set on the second buffer layer 19 relative to the first sub-insulating layer 181. Since the hydrogen content in the second sub-insulating layer 182 is less than the hydrogen content in the first sub-insulating layer 181, the hydrogen freely diffused into the channel of the oxide 26 can be reduced, thereby reducing the influence of hydrogen on the characteristics of the oxide thin film transistor 200, so that the characteristics of the oxide thin film transistor 200 can be kept stable. Furthermore, while reducing the number of film layers set on the substrate 11 of the display substrate 1, reducing the stress of each film layer on the substrate 11, reducing the degree of warping and deformation of the substrate 11, improving the production efficiency of the product, and reducing the complexity and cost of the preparation process, it can also reduce the influence on the characteristics of the oxide thin film transistor 200, so that the characteristics of the oxide thin film transistor 200 can be kept stable.

[0031] Alternatively, the first sub-insulating layer 181 may include a silicon nitride (SiN) film.

[0032] Optionally, the second sub-insulating layer 182 may include a silicon nitride film.

[0033] In a preferred embodiment of the present invention, the content of Si-H bonds in the second sub-insulating layer 182 may be less than the content of Si-H bonds in the first sub-insulating layer 181 .

[0034] This is because in the first sub-insulating layer 181 and the second sub-insulating layer 182 of the silicon nitride film, there will be silicon-nitrogen bonds (Si-N), and there may be residual silicon-hydrogen bonds (Si-H), wherein the bond energy of the silicon-hydrogen bonds is low. When the display substrate 1 is subjected to a high-temperature annealing process, for example, the silicon-hydrogen bonds are more easily broken and separated into silicon (Si) and hydrogen (H). Under the action of high-temperature annealing, hydrogen will be free and diffused to the interface between the polysilicon 23 and the first gate insulating layer 17, removing the dangling bonds at the interface between the polysilicon 23 and the first gate insulating layer 17. Therefore, the first sub-insulating layer 181 and The content of silicon-hydrogen bonds in the second sub-insulating layer 182 can represent the content of hydrogen in the first sub-insulating layer 181 and the second sub-insulating layer 182. Therefore, by making the content of silicon-hydrogen bonds in the second sub-insulating layer 182 smaller than the content of silicon-hydrogen bonds in the first sub-insulating layer 181, the content of hydrogen in the second sub-insulating layer 182 can be smaller than the content of hydrogen in the first sub-insulating layer 181. The bond energy of silicon-nitrogen bonds is relatively high. When the display substrate 1 undergoes a high-temperature annealing process, for example, the silicon-nitrogen bonds are relatively high. When the display substrate 1 undergoes a high-temperature annealing process, for example, the silicon-nitrogen bonds are relatively stable and not easy to break.

[0035] In a preferred embodiment of the present invention, the content of SiH bonds in the first sub-insulating layer 181 may be in the range of 3%-10%, and / or the content of SiH bonds in the second sub-insulating layer 182 may be in the range of 0.5%-3%.

[0036] In a preferred embodiment of the present invention, the content of Si-H bonds in the second sub-insulating layer 182 may be in the range of 0.5%-1.5%.

[0037] In a preferred embodiment of the present invention, the density of the second sub-insulating layer 182 may be greater than the density of the first sub-insulating layer 181 .

[0038] By making the density of the second sub-insulating layer 182 greater than the density of the first sub-insulating layer 181, the second sub-insulating layer 182 can be used to block the hydrogen in the first sub-insulating layer 181 and the second sub-insulating layer 182 from diffusing upward to the channel of the oxide 26, thereby further reducing the influence of hydrogen on the characteristics of the oxide thin film transistor 200, so that the characteristics of the oxide thin film transistor 200 can be further maintained stable, thereby reducing the number of film layers provided on the display substrate 1, reducing the stress of each film layer on the substrate 11 of the display substrate 1, reducing the degree of warping and deformation of the substrate 11, improving the production efficiency of the product, and reducing the complexity and cost of the preparation process, and further reducing the influence on the characteristics of the oxide thin film transistor 200, so that the characteristics of the oxide thin film transistor 200 can be further maintained stable.

[0039] In a preferred embodiment of the present invention, the ratio of silicon to nitrogen in the second sub-insulating layer 182 may be greater than the ratio of silicon to nitrogen in the first sub-insulating layer 181 .

[0040] By making the ratio of silicon to nitrogen in the second sub-insulating layer 182 greater than the ratio of silicon to nitrogen in the first sub-insulating layer 181 , the density of the second sub-insulating layer 182 can be greater than the density in the first sub-insulating layer 181 .

[0041] In a preferred embodiment of the present invention, the ratio of silicon to nitrogen in the first sub-insulating layer 181 may be in the range of 0.7-0.8, and / or the ratio of silicon to nitrogen in the second sub-insulating layer 182 may be in the range of 0.8-1.5.

[0042] In a preferred embodiment of the present invention, the ratio of silicon to nitrogen in the second sub-insulating layer 182 may be in the range of 1-1.5.

[0043] In a preferred embodiment of the present invention, the thickness of the first sub-insulating layer 181 may be in a range of 50 nm to 150 nm, and / or the thickness of the second sub-insulating layer 182 may be in a range of 10 nm to 100 nm.

[0044] Optionally, the display substrate 1 may further include a substrate 11 (optionally a glass substrate 11 (Glass)), a first flexible film layer 12 (the material of which may be polyimide (abbreviated as PI)), a first barrier layer 13 (Barrier), a second flexible film layer 14 (the material of which may be polyimide), a second barrier layer 15, a third gate insulating layer 21, an interlayer dielectric layer 22, a first gate 24 (Gate), a second gate 25, a third gate 27 and a source-drain metal connection line 28 (SD).

[0045] Among them, the first flexible film layer 12, the first barrier layer 13, the second flexible film layer 14 and the second barrier layer 15 are stacked on the substrate 11 from bottom to top, the first buffer layer 16 is stacked on the second barrier layer 15, the first gate 24 is arranged on the first gate insulating layer 17, the second gate insulating layer 18 is arranged on the first gate insulating layer 17 and covers the first gate 24, the second gate 25 is arranged on the second gate insulating layer 18 and is covered by the second buffer layer 19 arranged on the second gate insulating layer 18 (as shown in FIG. Figure 1As shown), when the second gate insulating layer 18 includes a first sub-insulating layer 181 and a second sub-insulating layer 182, the first sub-insulating layer 181 is provided on the first gate insulating layer 17 and covers the first gate 24, the second sub-insulating layer 182 is provided on the first sub-insulating layer 181, and the second gate 25 is provided on the second sub-insulating layer 182 and is covered by the second buffer layer 19 provided on the second sub-insulating layer 182 (as shown). Figure 2 As shown), a third gate insulating layer 21 is arranged on the second buffer layer 19 and covers the oxide 26 arranged on the second buffer layer 19, a third gate 27 is arranged on the third gate insulating layer 21, an interlayer dielectric layer 22 is arranged on the third gate insulating layer 21 and covers the third gate 27, the polycrystalline silicon thin film transistor 100 may include polycrystalline silicon 23, a first gate 24 and a second gate 25 located above the polycrystalline silicon 23, the oxide thin film transistor 200 may include an oxide 26, a second gate 25 located below the oxide 26 and a third gate 27 located above the oxide 26, the source-drain metal connection line 28 passes through a part of the film layer to be connected to the two ends of the polycrystalline silicon 23 for forming the source and the drain, and passes through a part of the film layer to be connected to the two ends of the oxide 26 for forming the source and the drain.

[0046] Furthermore, the display substrate 1 may further include a protective layer (PVX) not shown in the figures. The protective layer may be disposed on the interlayer dielectric layer 22 and cover a portion of the source-drain metal connection line 28 located on the interlayer dielectric layer 22 .

[0047] In summary, the display substrate 1 provided by the embodiment of the present invention can reduce the degree of warping and deformation of the substrate 11 , improve the production efficiency of the product, and reduce the complexity and cost of the manufacturing process.

[0048] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The present invention comprises a first buffer layer, a first gate insulating layer, a second gate insulating layer, and a second buffer layer, wherein the first buffer layer is used to arrange polysilicon in a polysilicon thin film transistor, the first gate insulating layer is arranged on the first buffer layer and covers the polysilicon arranged on the first buffer layer, the second gate insulating layer is arranged on the first gate insulating layer, the second buffer layer is arranged on the second gate insulating layer, and the oxide in the oxide thin film transistor is arranged on the second buffer layer; The second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is disposed on the first gate insulating layer, the second sub-insulating layer is disposed on the first sub-insulating layer, and the second buffer layer is disposed on the second sub-insulating layer; The ratio of silicon to nitrogen in the second sub-insulating layer is greater than the ratio of silicon to nitrogen in the first sub-insulating layer; A content of Si-H bonds in the second sub-insulating layer is less than a content of Si-H bonds in the first sub-insulating layer.

2. The display substrate according to claim 1, wherein A content of hydrogen in the second sub-insulating layer is less than a content of hydrogen in the first sub-insulating layer.

3. The display substrate according to claim 1, wherein The content of Si-H bonds in the first sub-insulating layer is in a range of 3%-10%, and / or the content of Si-H bonds in the second sub-insulating layer is in a range of 0.5%-3%.

4. The display substrate according to claim 3, wherein: The content of silicon-hydrogen bonds in the second sub-insulating layer is in a range of 0.5% to 1.5%.

5. The display substrate according to claim 1 or 2, characterized in that: The density of the second sub-insulating layer is greater than that of the first sub-insulating layer.

6. The display substrate according to claim 5, wherein: The ratio of silicon to nitrogen in the first sub-insulating layer is in a range of 0.7-0.8, and / or the ratio of silicon to nitrogen in the second sub-insulating layer is in a range of 0.8-1.

5.

7. The display substrate according to claim 6, wherein: The ratio of silicon to nitrogen in the second sub-insulating layer is in the range of 1-1.

5.

8. The display substrate according to claim 2, wherein: The thickness of the first sub-insulating layer is in a range of 50 nm to 150 nm, and / or the thickness of the second sub-insulating layer is in a range of 10 nm to 100 nm.

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