Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. An object is to provide a technique capable of realizing an appropriate channel region. The semiconductor device includes: a first contact layer connected to a lower portion of a first trench contact portion; and a second contact layer connected to a lower portion of a second trench contact portion. When viewed from above, a distance between a first side portion of the first trench and the first trench contact portion is larger than a distance between a second side portion of the first trench and the second trench contact portion. When viewed in cross section, the first contact layer is separated from the first side portion, and the second contact layer is connected to the second side portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] In recent years, a technique for manufacturing a semiconductor device using self-aligned implantation in which the shape of a contact layer corresponds to the shape of a trench contact has been proposed. According to such a technique, since a dedicated mask for forming the contact layer is not required, the manufacturing cost can be reduced.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-256628

[0004] However, in the case of a semiconductor device using self-aligned implantation, there is a problem that an appropriate channel region cannot be achieved because the distance between a trench in which an active portion connected to a gate electrode is disposed and the trench contact is inappropriate. Summary of the Invention

[0005] Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of achieving an appropriate channel region.

[0006] The semiconductor device according to the present invention includes: a semiconductor substrate provided with an emitter electrode and a gate electrode; a base layer of a first conductivity type disposed on the upper surface side of the semiconductor substrate; a source layer of a second conductivity type disposed on the upper surface side of the base layer; an active portion disposed on an insulating film on an inner surface of a first trench penetrating the base layer and the source layer and connected to the gate electrode; a first trench contact portion and a second trench contact portion respectively disposed opposite to a first side portion and a second side portion of the first trench in a plan view, and the emitter electrode is disposed inside the first trench contact portion and the second trench contact portion; a first contact layer of a first conductivity type connected to a lower portion of the first trench contact portion and having a higher concentration of impurities of the first conductivity type than the base layer; a second contact layer of a first conductivity type connected to a lower portion of the second trench contact portion and having a higher concentration of impurities of the first conductivity type than the base layer; and a collector electrode disposed on the lower surface of the semiconductor substrate. In a plan view, the distance between the first side portion and the first trench contact portion is larger than the distance between the second side portion and the second trench contact portion, and in a cross-sectional view, the first contact layer is separated from the first side portion, and the second contact layer is connected to the second side portion.

[0007] Advantages of the Invention

[0008] According to the present invention, when viewed from above, the distance between the first side portion of the first trench and the first trench contact portion is larger than the distance between the second side portion of the first trench and the second trench contact portion. When viewed in cross-section, the first contact layer is separated from the first side portion, and the second contact layer is connected to the second side portion. With such a structure, an appropriate channel region can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 6 is a cross-sectional view taken along line Z1-Z1 showing the structure of the semiconductor device according to Embodiment 1.

[0010] Figure 2 FIG. 10 is a cross-sectional view taken along line Z2-Z2 showing the structure of the semiconductor device according to Embodiment 1.

[0011] Figure 3 FIG. 14 is a top view taken along line Y1-Y1 showing the structure of the semiconductor device according to Embodiment 1.

[0012] Figure 4 FIG. 18 is a top view taken along line Y2-Y2 showing the structure of the semiconductor device according to Embodiment 1.

[0013] Figure 5 FIG. 22 is a cross-sectional view taken along line Z1-Z1 for explaining the manufacturing method of the semiconductor device according to Embodiment 1.

[0014] Figure 6 FIG. 26 is a cross-sectional view taken along line Z1-Z1 for explaining the manufacturing method of the semiconductor device according to Embodiment 1.

[0015] Figure 7 FIG. 30 is a cross-sectional view taken along line Z1-Z1 for explaining the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 8 FIG. 34 is a graph showing the relationship between the distance between the first trench and the trench contact and the threshold voltage.

[0017] Figure 9 FIG. 38 is a top view showing the structure of the semiconductor device according to Modification 1-1.

[0018] Figure 10 FIG. 42 is a cross-sectional view taken along line Z1-Z1 showing the structure of the semiconductor device according to Modification 1-1.

[0019] Figure 11 FIG. 46 is a cross-sectional view taken along line Z2-Z2 showing the structure of the semiconductor device according to Modification 1-1.

[0020] Figure 12 FIG. 50 is a top view showing the structure of the semiconductor device according to Modification 1-2.

[0021] Figure 13 It is a top view showing the structure of the semiconductor device related to Modifications 1-3.

[0022] Figure 14 It is a cross-sectional view taken along line Z3-Z3 showing the structure of the semiconductor device related to Modifications 1-3.

[0023] Figure 15 It is a top view showing the structure of the semiconductor device related to Modifications 1-4.

[0024] Figure 16 It is a top view showing the structure of the semiconductor device related to Embodiment 2.

[0025] Figure 17 It is a top view showing the structure of the semiconductor device related to Modification 2-1.

[0026] Figure 18 It is a top view showing the structure of the semiconductor device related to Modification 2-2.

[0027] Figure 19 It is a top view showing the structure of the semiconductor device related to Modification 2-2.

[0028] Figure 20 It is a top view taken along line Y1-Y1 showing the structure of the semiconductor device related to Modification 2-3.

[0029] Figure 21 It is a top view taken along line Y2-Y2 showing the structure of the semiconductor device related to Modification 2-3.

[0030] Figure 22 It is a cross-sectional view taken along line Z1-Z1 showing the structure of the semiconductor device related to Modification 2-3.

[0031] Figure 23 It is a cross-sectional view taken along line Z2-Z2 showing the structure of the semiconductor device related to Modification 2-3.

[0032] Figure 24 It is a top view showing the structure of the semiconductor device related to Modification 2-4.

[0033] Figure 25 It is a top view showing the structure of the semiconductor device related to Modification 2-4.

[0034] Figure 26 It is a top view taken along line Y1-Y1 showing the structure of the semiconductor device related to Embodiment 3.

[0035] Figure 27 It is a cross-sectional view taken along line Z1-Z1 showing the structure of the semiconductor device related to Embodiment 3.

[0036] Figure 28 It is a cross-sectional view taken along the line Z2-Z2 showing the structure of the semiconductor device according to Embodiment 3.

[0037] Figure 29 It is a plan view taken along the line Y1-Y1 showing the structure of the semiconductor device according to Modification 3-1.

[0038] Figure 30 It is a cross-sectional view taken along the line Z1-Z1 showing the structure of the semiconductor device according to Modification 3-1.

[0039] Figure 31 It is a cross-sectional view taken along the line Z2-Z2 showing the structure of the semiconductor device according to Modification 3-1.

[0040] Figure 32 It is a cross-sectional view taken along the line Z2-Z2 for explaining the manufacturing method of the semiconductor device according to Modification 3-1.

[0041] Figure 33 It is a plan view taken along the line Y1-Y1 showing the structure of the semiconductor device according to Modification 3-2.

[0042] Figure 34 It is a cross-sectional view taken along the line Z1-Z1 showing the structure of the semiconductor device according to Modification 3-2.

[0043] Figure 35 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Modification 3-3.

[0044] Figure 36 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Modification 3-3.

[0045] Figure 37 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Modification 3-3.

[0046] Figure 38 It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Modification 3-3.

[0047] Figure 39 It is a plan view taken along the line Y1-Y1 showing the structure of the semiconductor device according to Modification 3-4.

[0048] Figure 40 It is a cross-sectional view taken along the line Z1-Z1 showing the structure of the semiconductor device according to Modification 3-4.

[0049] Figure 41 It is a plan view showing the structure of the semiconductor device according to Embodiment 5.

[0050] Figure 42 It is a top view showing the structure of the semiconductor device according to Embodiment 6. Detailed implementation

[0051] Hereinafter, the embodiments will be described with reference to the drawings. The features described in the following embodiments are examples, and not all features are essential. In addition, in the following descriptions, the same or similar reference numerals are assigned to the same structural elements in multiple embodiments, and mainly different structural elements will be described. In addition, in the descriptions recorded below, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily coincide with the directions during actual implementation.

[0052] In addition, for example, a certain part having a higher concentration than other parts means that the average value of the concentration of a certain part is higher than the average value of the concentration of other parts. On the contrary, for example, a certain part having a lower concentration than other parts means that the average value of the concentration of a certain part is lower than the average value of the concentration of other parts. In addition, hereinafter, the first conductivity type will be described as p-type and the second conductivity type as n-type, but the first conductivity type can also be n-type and the second conductivity type can be p-type. In addition, n - represents that the impurity concentration is lower than n, n + represents that the impurity concentration is higher than n. Similarly, p - represents that the impurity concentration is lower than p, p + represents that the impurity concentration is higher than p.

[0053] <Embodiment 1>

[0054] Figure 1 and Figure 2 are cross-sectional views showing the structure of the semiconductor device according to Embodiment 1, i.e., the semiconductor element 100, Figure 3 and Figure 4 are top views showing the structure of the semiconductor element 100. Specifically, Figure 1 is Figure 3 a cross-sectional view taken along line Z1-Z1 of Figure 2 is Figure 3 a cross-sectional view taken along line Z2-Z2 of Figure 3 is Figure 1 a top view taken along line Y1-Y1 of Figure 4 is Figure 1 a top view taken along line Y2-Y2 of

[0055] First, the outline will be described. As Figures 1 to 4As shown, the semiconductor element 100 has a semiconductor substrate provided with an emitter electrode 1 and a gate electrode 15, and an active trench A and a dummy trench D are provided in the semiconductor substrate. The semiconductor substrate may be composed of a normal semiconductor wafer or an epitaxial growth layer. In addition, Figure 3 the illustrations showing G of the gate electrode 15 and E of the emitter electrode 1 may sometimes be appropriately omitted in Figure 5 the drawings hereinafter.

[0056] As Figure 1 and Figure 2 shown, the active trench A is formed by disposing an active portion 14 on the inner surface of the first trench 7 in the semiconductor substrate, i.e., on the gate oxide film (insulating film) 8. The dummy trench D is formed by disposing a dummy portion 24 on the inner surface of the second trench 27 in the semiconductor substrate, i.e., on the oxide film 28.

[0057] As Figure 3 shown, the active trench A and the dummy trench D are arranged in a strip shape. The active portion 14 of the active trench A is electrically connected to the gate electrode 15. The dummy portion 24 of the dummy trench D is electrically connected to the emitter electrode 1 disposed on the first main surface (upper surface) of the semiconductor substrate.

[0058] In the case of the semiconductor device according to the first embodiment, a structure is adopted in which the active trench A and the dummy trench D are alternately arranged side by side. The number of each of the active trench A and the dummy trench D arranged side by side may be 1, may be 3, or may be other numbers. In addition, the number of the dummy trenches D may also be 0. That is, the dummy trench D may not be provided and one or more active trenches A may be provided.

[0059] As Figure 1 and Figure 2 shown, a p-type base layer 5 is disposed on the upper surface side of the semiconductor substrate, and an n + -type source layer 4 is disposed on the upper surface side of the p-type base layer 5. The n + -type source layer 4 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 to 1.0E+20 / cm 3 . By making the first trench 7 penetrate the p-type base layer 5 and the n + -type source layer 4, the p-type base layer 5 and the n + -type source layer 4 are provided in connection with the active trench A.

[0060] As Figure 1 and Figure 2 shown, the semiconductor element 100 has an n-type drift layer 9 formed of a semiconductor substrate. In Figure 1 and Figure 2 the example, the semiconductor substrate is from n+ Range from the p-type source layer 4 to the p-type collector layer 11. The n-type drift layer 9 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+15 / cm 3 . In Figure 1 , the upper end of the n + -type source layer 4 on the paper surface is referred to as the upper surface of the semiconductor substrate, and the lower end of the p-type collector layer 11 on the paper surface is referred to as the lower surface (second main surface) of the semiconductor substrate. The upper surface of the semiconductor substrate is the main surface on the upper surface (front side) of the semiconductor element 100, and the lower surface of the semiconductor substrate is the main surface on the lower surface (back side) of the semiconductor element 100. The semiconductor element 100 has an n-type drift layer 9 between the upper surface and the lower surface.

[0061] As Figure 1 and Figure 2 shown, an n-type carrier accumulation layer 6 having a higher concentration of n-type impurities than the n-type drift layer 9 is disposed on the upper surface side of the n-type drift layer 9. The n-type carrier accumulation layer 6 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 . In addition, the semiconductor element 100 may be a structure in which the n-type carrier accumulation layer 6 is not disposed, and the n-type drift layer 9 is also disposed in the region of the n-type carrier accumulation layer 6 as Figure 1 and Figure 2 shown. In the structure in which the n-type carrier accumulation layer 6 is disposed, the conduction loss when current flows can be reduced. The n-type carrier accumulation layer 6 and the n-type drift layer 9 may also be collectively referred to as the drift layer.

[0062] The n-type carrier accumulation layer 6 is formed by ion-implanting an n-type impurity into the semiconductor substrate constituting the n-type drift layer 9, and then diffusing the implanted n-type impurity in the semiconductor substrate by annealing.

[0063] On the upper surface (upper surface) side of the n-type carrier accumulation layer 6, a p-type base layer 5 is provided. The p-type base layer 5 is a semiconductor layer having, for example, boron or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 . The p-type base layer 5 is connected to the gate oxide film 8 of the active trench A.

[0064] On the upper surface (upper surface) side of the p-type base layer 5, an n + -type source layer 4 is provided. The n + -type source layer 4 is connected to the gate oxide film 8 of the active trench A. In addition, n+ The type source layer 4 constitutes the upper surface of the semiconductor substrate.

[0065] As Figures 1 to 4 shown, when viewed from above, the trench contact TC is disposed opposite to the first trench 7. As Figure 1 and Figure 2 shown, the emitter electrode 1 is disposed inside the trench contact TC.

[0066] As Figure 3 and Figure 4 shown, when viewed from above, the second trench 27 is provided along the first trench 7, and the trench contact TC is sandwiched between the second trench 27 and the first trench 7. In the present Embodiment 1, the second trench 27 is a dummy trench D, but it may also be an active trench A.

[0067] The trench contact TC includes Figure 1 the first trench contact portion TCa and Figure 2 the second trench contact portion TCb. As will be described later, the first trench contact portion TCa is disposed opposite to the first side portion of the first trench 7 when viewed from above, and the first trench contact portion TCa and the first side portion correspond to Figure 3 the channel region C. On the other hand, the second trench contact portion TCb is disposed opposite to the second side portion of the first trench 7 when viewed from above, and the second trench contact portion TCb and the second side portion correspond to Figure 3 the non-channel region N. In addition, the first side portion and the second side portion of the first trench 7 may be included in one end portion of the first trench 7, or may be included in two different end portions. Similarly, the first trench contact portion TCa and the second trench contact portion TCb may be included in one trench contact TC, or may be included in two different trench contacts TC.

[0068] p + type contact layer 3 includes a first p + type contact layer 3a as the first contact layer and a second p + type contact layer 3b as the second contact layer. The first p + type contact layer 3a is a semiconductor layer that is connected to the lower portion of the first trench contact portion and has a higher concentration of p-type impurities than the p-type base layer 5. The second p + type contact layer 3b is a semiconductor layer that is connected to the lower portion of the second trench contact portion and has a higher concentration of p-type impurities than the p-type base layer 5. The concentrations of p-type impurities in the first and second p + type contact layers 3a and 3b are, for example, 1.0E+15 / cm 3 to 1.0E+20 / cm 3 .

[0069] As Figure 1 and Figure 2As shown, the semiconductor element 100 is provided with an n-type buffer layer 10 having a higher concentration of n-type impurities than the n-type drift layer 9 on the lower surface (second main surface) side of the n-type drift layer 9. The n-type buffer layer 10 is provided to suppress the depletion layer punch-through extending from the p-type base layer 5 toward the lower surface side when the semiconductor element 100 is in the off state. The n-type buffer layer 10 can be formed, for example, by implantation of phosphorus (P) or protons (H + ), or can be formed by implantation of both phosphorus (P) and protons (H + ). In addition, the semiconductor element 100 may be structured such that the n-type buffer layer 10 is not provided, and the n-type drift layer 9 is also provided in the region of the n-type buffer layer 10 at Figure 1 and Figure 2 . The n-type buffer layer 10 and the n-type drift layer 9 may be collectively referred to as the drift layer.

[0070] The semiconductor element 100 is provided with a p-type collector layer 11 on the lower surface side of the n-type buffer layer 10. That is, the p-type collector layer 11 is provided between the n-type drift layer 9 and the lower surface of the semiconductor substrate.

[0071] As Figure 1 and Figure 2 shown, the semiconductor element 100 is provided with a first trench 7 that penetrates the p-type base layer 5 from the upper surface of the semiconductor substrate and reaches the n-type drift layer 9. Specifically, the first trench 7 penetrates the n + type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6. The active trench A is configured such that the active part 14 is provided in the first trench 7 with a gate oxide film 8 therebetween.

[0072] As Figure 1 and Figure 2 shown, an interlayer insulating film 2 is provided above the active part 14. A contact hole is provided in the interlayer insulating film 2 to expose the trench contact TC. An emitter electrode 1 is provided inside the trench contact TC, above the region of the upper surface of the semiconductor substrate where the interlayer insulating film 2 is not provided, and above the interlayer insulating film 2.

[0073] The emitter electrode 1 makes an ohmic contact with the n + type source layer 4, the p + type contact layer 3, and the dummy part 24, and is electrically connected to the n + type source layer 4, the p + type contact layer 3, and the dummy part 24. In addition, in Figure 1 and Figure 2 or in a cross section different from Figure 1 and Figure 2 , the emitter electrode 1 may contact the dummy part 24, or the emitter electrode 1 may contact the dummy part 24 via a contact hole (not shown) provided in the interlayer insulating film 2.

[0074] The emitter electrode 1 can be composed of, for example, an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be composed of a multi-layer metal film having a coating film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The coating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) coating film. In addition, when there is a minute area between adjacent interlayer insulating films 2 or the like that cannot be well filled by the emitter electrode 1, a tungsten film having better filling properties than the emitter electrode 1 can be disposed in the minute area, and the emitter electrode 1 can be provided on the tungsten film.

[0075] In addition, a barrier metal can be provided between the interlayer insulating film 2 and the emitter electrode 1. The barrier metal can be, for example, a conductor containing titanium (Ti) such as titanium nitride, or can be TiSi obtained by alloying titanium and silicon (Si). In addition, a barrier metal can be provided only on an n-type semiconductor layer such as the n-type source layer 4. The barrier metal and the emitter electrode 1 can also be collectively referred to as the emitter electrode. + A collector electrode 12 is provided on the lower surface side of the p-type collector layer 11. Similar to the emitter electrode 1, the collector electrode 12 can be composed of an aluminum alloy, can be composed of an aluminum alloy and a coating film, or can have a structure different from that of the emitter electrode 1. The collector electrode 12 makes an ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0076] Therefore, as shown, the emitter electrode 1 is disposed inside the first and second trench contact portions TCa and TCb that are shallower and narrower in width than the first trench 7. The first and second p-type contact layers 3a and 3b are connected to the lower portions of the first and second trench contact portions TCa and TCb.

[0077] So, as Figures 1 to 4 shown, the emitter electrode 1 is disposed inside the first and second trench contact portions TCa and TCb that are shallower and narrower in width than the first trench 7. The first and second p + -type contact layers 3a and 3b are connected to the lower portions of the first and second trench contact portions TCa and TCb.

[0078] As Figure 3 shown, when viewed from above, the distance Lc between the first side portion of the first trench 7 and the first trench contact portion TCa is larger than the distance Ln between the second side portion of the first trench 7 and the second trench contact portion TCb. In addition, the distance described here is the distance in a direction intersecting the extending direction of the first trench 7 (hereinafter sometimes described as the "extension intersecting direction"). In the first embodiment, by making the width at the first side portion of the first trench 7 smaller than the width at the second side portion of the first trench 7 when viewed from above, that is, by locally reducing the width of the first trench 7, the distance Lc and the distance Ln are set.

[0079] As Figure 1 shown, when viewed in cross-section, the first p-type contact layer 3a connected to the lower portion of the first trench contact portion TCa +The p-type contact layer 3a is separated from the first side portion of the first trench 7. Specifically, the p-type base layer 5 and the n + type source layer 4 adjacent to the first side portion of the first trench 7 are connected to each other. This region becomes the channel region C where a channel is formed corresponding to the voltage of the active portion 14.

[0080] On the other hand, as Figure 2 shown, when observed in cross section, the second p + type contact layer 3b connected to the lower portion of the second trench contact portion TCb is connected to the second side portion of the first trench 7. Specifically, the p-type base layer 5 and the n + type source layer 4 adjacent to the second side portion of the first trench 7 are separated by the second p + type contact layer 3b. This region becomes the non-channel region N where a channel is not formed corresponding to the voltage of the active portion 14.

[0081] That is, by changing the width in the extending crossing direction of the first trench 7, the non-channel region N is provided in the shorter region between the first trench 7 and the trench contact TC, and the channel region C is provided in the longer region between the first trench 7 and the trench contact TC. According to such a structure, regardless of the pattern of the n + type source layer 4, the channel region C and the non-channel region N can be adjusted by making the p + type contact layer 3 contact or not contact with the first trench 7.

[0082] In addition, according to the above structure, by disposing the p + type contact layer 3 at the lower portion of the trench contact TC, the latch-up tolerance can be improved. In addition, in the channel region C, since the distance between the first trench 7 and the trench contact TC becomes larger, a channel region C in which the adverse effect of the p + type contact layer 3 on the turn-on characteristics is suppressed can be realized. Therefore, at least one of a reduction in manufacturing cost due to self-aligned implantation of the p + type contact layer 3 and a reduction in turn-on voltage due to narrowing of the mesa width can be realized.

[0083] In addition, in the first embodiment 1, Figure 2 the depth at the second side portion of the first trench 7 is deeper than Figure 1 the depth at the first side portion of the first trench 7. According to such a structure, since the p + type contact layer 3 (the second p + type contact layer 3b) is connected to the deeper first trench 7, the amount of hole discharge in the non-channel region N can be increased, and the latch-up tolerance can be improved. In addition, Figure 2 and Figure 1 and Figure 2Such a difference in the depth of the first trench 7 can be formed using the microloading effect, or it can be a structure in which no depth difference is formed by adjusting the etching conditions and the trench width.

[0084] Here, for example, assume a structure in which the width of the trench contact TC is locally changed. In such a structure, it is necessary to increase the width between the first trench 7 and the second trench 27 and it cannot be miniaturized. In addition, when the trench contact TC is bent, it is also necessary to increase the width between the first trench 7 and the second trench 27, so miniaturization cannot be achieved.

[0085] In contrast, in the first embodiment, the width of the first trench 7 is locally changed. Generally, when viewed from above, the width of the active trench A is wider than that of the trench contact TC, so there is a large margin for adjusting the width. Even if the width is changed significantly, the impact on miniaturization is small. Therefore, both width adjustment and miniaturization can be achieved.

[0086] In addition, as Figure 3 shown, the width difference between the width of the first side portion and the width of the second side portion of the first trench 7, that is, the width W1 after the width of the first trench 7 is narrowed, is larger than the width W2 of the trench contact TC (the first and second trench contact portions TCa, TCb). According to such a structure, it is easy to increase the distance Lc while miniaturizing. This holds when the width of the first trench 7 is larger than the width of the trench contact TC.

[0087] In addition, although not shown in Figure 3 and Figure 4 , the n + type source layer 4 can also be arranged intermittently in a strip shape along the extending direction of the first trench 7 as in the prior art, or can be arranged continuously along the extending direction as Figure 4 shown.

[0088] <Manufacturing Method>

[0089] Next, an example of the manufacturing method of the semiconductor element according to the first embodiment will be described. In addition, in the following description, mainly the manufacturing method of the structure in the Figure 1 cross-section will be described, but the manufacturing method of the structure in the Figure 2 cross-section is also the same as the following. In addition, in the following description, mainly the manufacturing method of the structure of the Figure 1 first trench 7 will be described, but the manufacturing method of the structure of the second trench 27 is also substantially the same as the following.

[0090] First, prepare a semiconductor substrate that constitutes the n-type drift layer 9. As the semiconductor substrate, an n-type wafer containing an n-type impurity such as an FZ wafer manufactured by the FZ (Floating Zone) method or an MCZ wafer manufactured by the MCZ (Magnetic-field applied CZochralki) method can be used.

[0091] The concentration of the n-type impurity contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the manufactured semiconductor device. For example, for a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurity is adjusted so that the resistivity of the n-type drift layer 9 that constitutes the semiconductor substrate becomes about 40 to 120 Ω·cm. In the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes the n-type drift layer 9. From the upper surface side or the lower surface side of such a semiconductor substrate, p-type or n-type impurity ions described below are implanted, and then diffused in the semiconductor substrate by heat treatment or the like, whereby a p-type or n-type semiconductor layer is formed on the semiconductor substrate, and the semiconductor element 100 is manufactured.

[0092] In addition, although not shown, a region that becomes an end region is disposed around the cell region in which the semiconductor element 100 is disposed. Hereinafter, mainly the manufacturing method of the structure of the cell region of the semiconductor element 100 will be described, but the end region of the semiconductor element 100 can also be manufactured by a known manufacturing method. For example, an FLR (Field Limiting Ring) having a p-type end well layer can be formed in the end region as a breakdown voltage holding structure. In this case, p-type impurity ions can be implanted into the end region to form the FLR before processing the cell region of the semiconductor element 100, or p-type impurity ions can be implanted into the end region simultaneously with the ion implantation of the p-type impurity into the cell region of the semiconductor element 100 to form the FLR.

[0093] Next, as shown in Figure 5 (a), n-type impurity such as arsenic (As) or phosphorus (P) is implanted from the upper surface side of the semiconductor substrate to form an n-type carrier accumulation layer 6. In addition, as shown in Figure 5As shown in Fig. (b), a p-type base layer 5 is formed by implanting p-type impurities such as boron (B) or aluminum (Al) from the upper surface side of the semiconductor substrate. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the n-type impurities and the p-type impurities are implanted after a mask treatment is performed on the upper surface of the semiconductor substrate, the n-type carrier accumulation layer 6 and the p-type base layer 5 are selectively formed on the upper surface side of the semiconductor substrate. Specifically, the n-type carrier accumulation layer 6 and the p-type base layer 5 are formed in the cell region and are connected to the p-type end well layer in the end region. In addition, the mask treatment means coating a resist layer on the semiconductor substrate, using photolithography technology to form an opening in a specified region of the resist layer, and thus forming a mask on the semiconductor substrate for performing ion implantation or etching on a specified region of the semiconductor substrate via the opening.

[0094] Next, as Figure 5 shown in Fig. (c), n-type impurities are selectively implanted from the upper surface side of the p-type base layer 5 in the cell region through a mask treatment to form an n + type source layer 4. The implanted n-type impurities can be, for example, arsenic (As) or phosphorus (P). In addition, by using the same mask in the formation of the p-type base layer 5 and the formation of the n + type source layer 4, the number of masks can be reduced and the manufacturing cost can be lowered.

[0095] Then, as Figure 6 shown in Fig. (a), a first trench 7 is formed that penetrates the n + type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 from the upper surface side of the semiconductor substrate and reaches the n-type drift layer 9. In the cell region, the side wall of the first trench 7 that penetrates the n + type source layer 4 is connected to a part of the n + type source layer 4. For example, after depositing an oxide film such as SiO2 that becomes a mask on the semiconductor substrate, an opening is formed in the part of the oxide film where the first trench 7 is to be formed through a mask treatment, and the semiconductor substrate is etched using the oxide film with the opening as a mask, thereby forming the first trench 7.

[0096] Then, the semiconductor substrate is heated in an oxygen-containing atmosphere to form a gate oxide film 8 on the inner wall of the first trench 7 and the upper surface of the semiconductor substrate. The gate oxide film 8 formed on the upper surface of the semiconductor substrate is removed in subsequent processes.

[0097] Next, in the first trench 7 in which the gate oxide film 8 is formed, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like. Since this polysilicon becomes the active part 14 and the dummy part 24, in Figure 6 (a) and the like, the labels of the active part 14 and the dummy part 24 are marked on this polysilicon.

[0098] Next, as Figure 6 (b) shows, an interlayer insulating film 2 is formed on the polysilicon in the cell region. The interlayer insulating film 2 can be, for example, SiO2. Then, as Figure 6 (c) shows, after contact holes are formed in the interlayer insulating film 2 deposited by mask processing, the semiconductor substrate exposed from the contact holes is etched to form trench contacts TC.

[0099] Next, as Figure 7 (a) shows, p-type impurities such as boron (B) or aluminum (Al) are implanted through the same mask as the trench contact TC to form a p + -type contact layer 3. The p + -type contact layer 3 is formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. Thus, in the first embodiment, the p + -type contact layer 3 is formed by performing self-aligned implantation on the trench contact TC. Since ion implantation is performed through the same mask as the trench contact TC, the p + -type contact layer 3 is formed under the trench contact TC.

[0100] In addition, after the trench contact TC and the p + -type contact layer 3 are formed, the contact holes of the interlayer insulating film 2 can be laterally expanded by wet etching or the like. Thus, an emitter electrode 1 is formed on the n + -type source layer 4 exposed from the interlayer insulating film 2. According to such a structure, the contact area between the n + -type source layer 4 and the emitter electrode 1 can be increased, and the contact resistance can be reduced.

[0101] Next, as Figure 7 (b) shows, on the p +An emitter electrode 1 is formed on the upper surface of the semiconductor substrate and on the interlayer insulating film 2 inside the trench contact TC above the type contact layer 3. The emitter electrode 1 can also be formed, for example, by depositing an aluminum-silicon alloy (Al-Si-based alloy) through PVD (physical vapor deposition) such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be further formed on the formed aluminum-silicon alloy through electroless plating or electroplating to form the emitter electrode 1. If the emitter electrode 1 is formed by plating, a thick metal film can be easily formed as the emitter electrode 1, and thus the heat resistance can be improved by increasing the heat capacity of the emitter electrode 1. In addition, when a nickel alloy is further formed by plating after the emitter electrode 1 made of an aluminum-silicon alloy is formed by PVD, the plating process for forming the nickel alloy can also be performed after the processing on the lower surface side of the semiconductor substrate.

[0102] Next, the lower surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a designed specified thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0103] Then, an n-type impurity is implanted from the lower surface side of the semiconductor substrate to form Figure 1 and Figure 2 the n-type buffer layer 10. Then, a p-type impurity is implanted from the lower surface side of the semiconductor substrate to form Figure 1 and Figure 2 the p-type collector layer 11.

[0104] The n-type buffer layer 10 can be formed, for example, by implanting phosphorus (P) ions, or by implanting protons (H + ), or by implanting both protons and phosphorus. Protons can be implanted to a deep position from the lower surface of the semiconductor substrate with a lower acceleration energy. In addition, the implantation depth of protons can be easily changed by changing the acceleration energy. Therefore, when the n-type buffer layer 10 is formed by protons, as long as the acceleration energy is changed and multiple implantations are performed, an n-type buffer layer 10 thicker in the thickness direction of the semiconductor substrate than in the case of forming by phosphorus can be formed.

[0105] In addition, as the n-type impurity, phosphorus has a higher activation rate than protons. Therefore, even for the thinned semiconductor substrate, if the n-type buffer layer 10 is formed by phosphorus, the punch-through of the depletion layer can be suppressed. In order to further thin the semiconductor substrate, it is preferable to implant both protons and phosphorus so that protons are implanted to a deeper position from the lower surface than phosphorus to form the n-type buffer layer 10.

[0106] The p-type collector layer 11 can be formed, for example, by implanting boron (B). After ion-implanting boron from the lower surface side of the semiconductor substrate, a laser is irradiated onto the lower surface for laser annealing, thereby activating the implanted boron to form the p-type collector layer 11. At this time, the phosphorus in the n-type buffer layer 10 implanted from the lower surface of the semiconductor substrate to a shallower position is also activated simultaneously.

[0107] In addition, protons in the n-type buffer layer 10 are activated at a relatively low annealing temperature such as 380°C to 500°C. Therefore, it is necessary to pay attention that after proton implantation, the entire semiconductor substrate does not become a temperature higher than 380°C to 500°C except for the process for activating protons. The above-mentioned laser annealing can make only the vicinity of the lower surface of the semiconductor substrate become high temperature. Therefore, it can be used for activating n-type impurities and p-type impurities after proton implantation.

[0108] Next, a Figure 1 and Figure 2 collector electrode 12 is formed on the lower surface of the semiconductor substrate. The collector electrode 12 can be formed by depositing an aluminum-silicon alloy (Al-Si based alloy) or titanium (Ti) etc. through PVD such as sputtering or evaporation, or can be formed by laminating multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. In addition, the collector electrode 12 can also be formed by the following method, that is, a chemical plating or electroplating metal film is further formed on the metal film formed by PVD.

[0109] Through the above processes, a plurality of semiconductor elements 100 are fabricated in a matrix on one n-type wafer. The semiconductor elements 100 are cut into individual ones by laser cutting or die cutting to complete the semiconductor elements 100.

[0110] <Action>

[0111] Figure 8 is a graph showing the relationship between the distance between the first trench 7 and the trench contact TC and the threshold voltage (Vth). If the trench contact TC is close to the first trench 7, the ratio of the p + -type contact layer 3 under the trench contact TC in the channel region C becomes higher. Therefore, the threshold voltage (Vth) becomes larger and the turn-on voltage becomes larger. In particular, when the above distance is 0.2 μm, the p + -type contact layer 3 is connected to the first trench 7, and the threshold voltage is higher than the normal gate drive voltage of 15 V, and no current flows at this gate drive voltage.

[0112] Based on the above tendency, the inventor believes that in order to form a suppression of the p +For the channel where the p-type contact layer 3 has an adverse effect on the turn-on characteristics, the following method is effective, that is, in the channel region C, the distance between the first trench 7 and the trench contact TC is increased, and in the non-channel region N, the distance between the first trench 7 and the trench contact TC is decreased. More specifically, the following structure is considered, that is, when viewed from above, it is configured such that the width at the first side portion of the first trench 7 is smaller than the width at the second side portion of the first trench 7, so that the channel region C is provided at the first side portion and the non-channel region N is provided at the second side portion.

[0113] According to such a structure, for the non-channel region N, the distance between the trench contact TC and the first trench 7 is small, and the gate oxide film 8 of the active trench A is connected to the p-type base layer 5, the n + -type source layer 4 and the p + -type contact layer 3. Therefore, even if a gate drive voltage is applied to the active portion 14, since the high-concentration p + -type contact layer 3 is connected to the gate oxide film 8 of the active trench A, no channel is formed or it is difficult to form a channel in the non-channel region N.

[0114] On the other hand, for the channel region C, the distance between the trench contact TC and the first trench 7 is large, and the gate oxide film 8 of the active trench A is connected to the p-type base layer 5 and the n + -type source layer 4, but not connected to the p + -type contact layer 3. Therefore, if a gate drive voltage is applied to the active portion 14, a channel is formed in the p-type base layer 5 in contact with the gate oxide film 8 of the active trench A.

[0115] That is, the region where the p + -type contact layer 3 is not connected to the first trench 7 becomes the channel region C where a channel is formed, and the region where the p + -type contact layer 3 is connected to the first trench 7 becomes the non-channel region N where substantially no channel is formed.

[0116] As described above, the channel region C can be adjusted by whether the p + -type contact layer 3 is connected to the first trench 7. Therefore, as shown in Figure 4 , the n + -type source layer 4 can be provided over the entire surface of the cell region by self-aligned implantation using the p-type base layer 5 as a mask. In this case, reduction of the mask can be achieved. In addition, in order to suppress a short circuit between the n + -type source layer 4 and the n-type drift layer 9, the end portion of the n + -type source layer 4 can also be formed to be covered by the p-type base layer 5 larger than the n + -type source layer 4.

[0117] <Summary of Embodiment 1>

[0118] In the first embodiment 1, by locally reducing the width of the first trench 7 and locally increasing the distance between the first trench 7 and the trench contact TC, it is possible to realize a channel region C in which the adverse effect of the p + -type contact layer 3 on the conduction characteristics is suppressed. Thus, it is possible to achieve at least one of a reduction in manufacturing cost due to self-aligned implantation of the p + -type contact layer 3 and a reduction in conduction voltage due to narrowing of the mesa width.

[0119] In addition, the channel region C can be adjusted by whether the p + -type contact layer 3 is connected to the first trench 7. Therefore, even if the n + -type source layer 4 is provided over the entire surface of the cell region by self-aligned implantation using the mask of the p-type base layer 5, the saturation current can be controlled by adjusting the channel density, and thus a reduction in the short-circuit time can be suppressed. As a result, the manufacturing cost of the n + -type source layer 4 can be reduced.

[0120] In addition, as shown Figure 2 , the upper ends of the p + -type contact layer 3 (the first and second p + -type contact layers 3a, 3b) can be connected to the lower ends of the n + -type source layer 4, or they can be made not to be connected by providing a p-type base layer 5 therebetween. At the portion where the upper end of the p + -type contact layer 3 is connected to the lower end of the n + -type source layer 4, electron injection from the n + -type source layer 4 is suppressed by the p + -type contact layer 3. Therefore, the saturation current can be controlled and a reduction in the short-circuit time can be suppressed. At the portion where the upper end of the p + -type contact layer 3 is not connected to the lower end of the n + -type source layer 4, the component of electrons flowing downward from the n + -type source layer 4 through the p-type base layer 5 can be suppressed by the p + -type contact layer 3. However, the component of electrons flowing through the p-type base layer 5 from the n + -type source layer 4 in the extending direction of the first trench 7 rather than downward is not suppressed, and the electrons flow into the n-type drift layer 9 through the channel region C where the p + -type contact layer 3 is not connected to the first trench 7. Therefore, the saturation current may not be adjusted sometimes.

[0121] <Modification 1-1>

[0122] In Embodiment 1, the width of the first trench 7 is locally reduced by alternately providing first side portions on one side and the other side of the first trench 7, but it is not limited thereto. For example, as Figure 9 shown, first side portions may be provided at opposite portions on one side and the other side of the first trench 7 to reduce the width of the first trench 7 from both sides.

[0123] According to such a structure, the width of the first trench 7 in the extending crossing direction becomes narrower. If the width of the first trench 7 becomes narrower, due to the microloading effect, the etching rate becomes slower at the portion where the width of the first trench 7 is narrow. Therefore, as Figure 10 shown, the difference in depth between the first trench 7 in the channel region C and the first trench 7 in the non-channel region N as Figure 11 shown is larger than that in Embodiment 1. In addition, it may also be a structure in which no depth difference is formed by adjusting the etching conditions and the trench width.

[0124] In addition, in order to improve the latch-up tolerance, it is only necessary to suppress the potential rise below the n + -type source layer 4 caused by holes. To achieve this goal, the following method is effective, that is, the hole discharge amount is increased in the region where the p + -type contact layer 3 exists under the n + -type source layer 4, and the hole discharge amount is reduced in the region where the p + -type contact layer 3 does not exist under the n + -type source layer 4. In addition, at the time of cutoff, holes are discharged through the inversion layer formed on the side surface of the active trench A in contact with the n-type drift layer 9. For the deep first trench 7, compared with the shallow first trench 7, since the distance between the side surface of the first trench 7 and the discharged holes becomes smaller, the holes are preferentially discharged along the side surface of the deep first trench 7.

[0125] In the region where the p + -type contact layer 3 exists under the n + -type source layer 4 adjacent to the deep first trench 7 becomes a region with high latch-up tolerance. In the region where the p + -type contact layer 3 does not exist under the n + -type source layer 4 adjacent to the shallow first trench 7 becomes a region with low latch-up tolerance. In the non-channel region N, since the p + -type contact layer 3 exists under the n + -type source layer 4 and the first trench 7 in the non-channel region N is deeper than the first trench 7 in the channel region C, the amount of holes discharged along the side surface of the first trench 7 is larger.

[0126] <Summary of Modification 1-1>

[0127] As described above, in the first modification 1-1, by reducing the width of the opposing portions on both sides of the first groove 7, due to the microloading effect, the first groove 7 becomes deeper at the portion where the width of the first groove 7 is not reduced. Thus, the amount of holes discharged from the trenchless region N of the p-type contact layer 3 existing under the n-type source layer 4 is increased, and therefore, the latch-up tolerance can be improved. + type source layer 4 to the p + type contact layer 3 increases the hole discharge amount of the trenchless region N, and thus, the latch-up tolerance can be improved.

[0128] <Modification 1-2>

[0129] In the first embodiment, the width of the first groove 7 is narrowed, but it is not limited thereto. For example, as Figure 12 shown, in a plan view, the first groove 7 is bent and recessed at the first side portion. Specifically, the first groove 7 has a concave shape at the first side portion and a convex shape at the side portion opposite to the first side portion. Preferably, the first groove 7 may be bent in such a manner that the width of the first groove 7 is constant. More preferably, in a plan view, the corners of the concave shape and the convex shape of the first groove 7 may have a gentle curvature.

[0130] <Summary of Modification 1-2>

[0131] In a plan view, the first groove 7 is recessed at the first side portion by being bent, so that the width of the first groove 7 can be made substantially constant. Thus, the microloading effect does not occur, and the depth of the first groove 7 can be made uniform. For a structure in which there is a difference in the depth of the first groove 7, the electric field tends to concentrate at the corner portion at the bottom of the deeper first groove 7, but in the first modification 1-2 like this, according to the structure in which the depth of the first groove 7 is made uniform, such concentration of the electric field can be alleviated. In addition, in a plan view, as long as the corners of the concave shape and the convex shape of the first groove 7 are configured to have a gentle curvature, the electric field at the corner portion at the bottom of the first groove 7 can be alleviated.

[0132] <Modification 1-3>

[0133] Figure 13 is a plan view showing the structure of the semiconductor device of the first modification 1-3, Figure 14 is showing Figure 13 the cross-sectional view of the structure taken along the line Z3-Z3.

[0134] In the first embodiment, the trench contact TC is disposed opposite to all of the first grooves 7, but it is not limited thereto. For example, as Figure 13 and Figure 14 shown, the first and second trench contact portions TCa, TCb may also be configured not to be opposite to the third side portion of the first groove 7 in a plan view. That is, the trench contact TC may be disposed not opposite to all of the first grooves 7 but with a partial interval removed. More preferably, as Figure 13and Figure 14 As shown, the mesa width Lmd of the region where the trench contact TC is excluded at intervals is made narrower than the width Lmn of the region where the trench contact TC is provided. More preferably, an n-type drift layer 9 may be provided instead of the p-type base layer 5 in the region where the trench contact TC is excluded at intervals.

[0135] <Summary of Modification Examples 1-3>

[0136] It is possible to narrow the mesa width of the region where the trench contact TC is excluded at intervals. Therefore, the carrier accumulation amount can be increased, and the on-voltage can be further reduced. In addition, as long as the p-type base layer 5 is not provided in the region where the trench contact TC is excluded at intervals, the amount of hole discharge through the p-type base layer 5 can be reduced, and thus the on-voltage can be further reduced.

[0137] <Modification Example 1-4>

[0138] In Embodiment 1, when viewed from above, the outer contour line at the first side portion of the first trench 7 has one concave shape, but it is not limited thereto. For example, it may also be as Figure 15 shown, the outer contour line at the first side portion of the first trench 7 has a plurality of concave shapes. Alternatively, the outer contour line at the first side portion of the first trench 7 may have one or more convex shapes, or may have a combination of one or more concave shapes and one or more convex shapes. In addition, in Figure 15 , the outer contour line of the first trench 7 along the extending direction has a concave shape, but the outer contour line of the first trench 7 along the extending cross direction may also have at least one of one or more concave shapes and convex shapes.

[0139] <Summary of Modification Example 1-4>

[0140] According to the above structure, the channel width in the channel region C can be increased, and thus the current density can be improved.

[0141] <Embodiment 2>

[0142] In Embodiment 1 and the modification examples of Embodiment 1, the distance between the first trench 7 and the trench contact TC is locally increased by locally changing the width of the first trench 7 or locally bending the first trench 7. In contrast, in this Embodiment 2, as Figure 16 shown, when viewed from above, the trench contact TC including the first trench contact portion TCa is bent toward the side opposite to the first side portion of the first trench 7. That is, the trench contact TC is locally bent.

[0143] <Summary of Embodiment 2>

[0144] By bending the trench contact TC, the distance between the first trench 7 (first side portion) and the trench contact TC (first trench contact portion TCa) can be locally increased in the same manner as in Embodiment 1. Thus, in the same manner as in Embodiment 1, a channel region C can be realized that suppresses the adverse effects of the p + type contact layer 3 on the conduction characteristics. Therefore, it is possible to simultaneously achieve a reduction in manufacturing cost due to the self-aligned implantation of the p + type contact layer 3 and a reduction in conduction voltage due to the narrowing of the mesa width.

[0145] Although such an effect can also be achieved by locally changing the width of the trench contact TC, the fillability of the emitter electrode 1 into the portion where the width of the trench contact TC is changed is poor. Therefore, there is a limit to locally changing the width of the trench contact TC to increase the distance between the first side portion of the first trench 7 and the first trench contact portion TCa of the trench contact TC, and sometimes it is not possible to sufficiently suppress the adverse effects on the conduction characteristics. In contrast, in the structure where the trench contact TC is bent as in Embodiment 2, the limitation caused by the fillability of the emitter electrode 1 is alleviated, so that the distance between the first trench 7 and the trench contact TC can be made sufficiently far, and the adverse effects on the conduction characteristics can be suppressed.

[0146] <Deformation Example 2-1>

[0147] As Figure 17 shown, the second trench 27 may include a first portion 27a opposite to the first trench contact portion TCa in the trench contact TC and a second portion 27b opposite to the portion other than the first trench contact portion TCa in the trench contact TC. And the width of the second portion 27b may be larger than the width of the first portion 27a. That is, the width of the second trench 27 adjacent to the portion of the trench contact TC that is not bent toward the second trench 27 side can be made wider. In addition, in Figure 17 the second trench 27 whose width is widened is a dummy trench D, but it may also be an active trench A.

[0148] <Summary of Deformation Example 2-1>

[0149] According to the above structure, the mesa width can be narrowed, so that the conduction voltage can be reduced.

[0150] <Deformation Example 2-2>

[0151] In Embodiment 2, the number of trench contacts TC in the mesa region is 1, but it is not limited thereto. For example, as Figure 18 shown, the number of trench contacts TC in the mesa region can be 2, and as Figure 19As shown, the number of trench contacts TC in the tabletop region is greater than or equal to two. That is, the trench contact TC can include a third trench contact part TCc that is arranged side by side in the width direction with the first trench contact part TCa or the second trench contact part TCb between the first trench 7 and the second trench 27. In addition, the number of trench contacts TC adjacent to the non-channel region N can also be larger than the number of trench contacts TC adjacent to the channel region C.

[0152] <Summary of Modification Example 2-2>

[0153] By providing a plurality of trench contacts TC, the area of the p-type contact layer 3 under the trench contacts TC can be increased, and thus the discharge of holes and the latch-up tolerance can be improved. + type contact layer 3, and thus the discharge of holes and the latch-up tolerance can be improved.

[0154] <Modification Example 2-3>

[0155] Figure 20 It represents Figure 23 A top view of the structure of the semiconductor device of this Modification Example 2-3 along the Y1-Y1 line, Figure 21 It represents Figure 23 A top view of the structure along the Y2-Y2 line of this. Figure 22 It is Figure 20 and Figure 21 A cross-sectional view along the Z1-Z1 line of, and it is a cross-sectional view of the channel region C. Figure 23 It is Figure 20 and Figure 21 A cross-sectional view along the Z2-Z2 line of, and it is a cross-sectional view of the non-channel region N.

[0156] In Embodiment 2, the trench contact TC adjacent to the channel region C is bent, but it is not limited thereto. For example, as Figures 20 to 23 shown, the trench contact TC can be spaced out in the channel region C. That is, the p-type base layer 5 and the n + type source layer 4 adjacent to the third side portion of the first trench 7 can also be connected to each other. The third side portion of the first trench 7 mentioned here is the side portion of the first trench 7 that does not face the trench contact TC by spacing out the trench contact TC as described in Modification Example 1-3. More preferably, as Figure 22 shown, the n Figure 21 and Figure 23 shown, the n + type source layer 4 is provided in the non-channel region N. Further preferably, as Figure 20 and Figure 23 shown, the p + type contact layer 3 is connected to the first trench 7 in the non-channel region N.

[0157] <Summary of Modification Example 2-3>

[0158] According to the above structure, the TC in contact with the trench can be selectively removed at intervals, and accordingly, the mesa width can be further reduced. Additionally, when the n + -type source layer 4 is also provided in the channel-less region N, as shown in Figure 21 and Figure 23 , contact with the n + -type source layer 4 can be obtained from the trench contact TC adjacent to the channel-less region N.

[0159] <Variant Example 2-4>

[0160] The structure of Embodiment 1 and the structure of Embodiment 2 can also be combined. That is, as shown in Figure 24 , in a plan view, it is configured such that the width at the first side portion of the first trench 7 is smaller than the width at the second side portion of the first trench 7, and the trench contact TC is configured to bend toward the side opposite to the first side portion of the first trench 7. Preferably, as shown in Figure 25 , the second trench 27 is also configured to bend toward the side opposite to the first side portion of the first trench 7, similarly to the trench contact TC.

[0161] <Summary of Variant Example 2-4>

[0162] According to the above structure, the distance between the first side portion of the first trench 7 and the trench contact TC can be further increased, and thus the adverse effect of the p + -type contact layer 3 on the turn-on characteristics can be further suppressed. Additionally, as shown in Figure 25 , when the second trench 27 bends toward the side opposite to the first side portion of the first trench 7, similarly to the trench contact TC, the adverse effect of the p + -type contact layer 3 on the turn-on characteristics can be further suppressed.

[0163] <Embodiment 3>

[0164] In Embodiments 1 and 2, the trench contact TC is provided in the mesa region between the first trench 7 and the second trench 27. In contrast, in this Embodiment 3, as shown in Figures 26 to 28 , the inside of the second trench 27 is connected to the trench contact TC (the first trench contact portion TCa and the second trench contact portion TCb). That is, the trench contact TC is provided so as to straddle the mesa region and the second trench 27. In addition, in Figures 26 to 28 , the second trench 27 is a dummy trench D, but it can also be an active trench A. When the second trench 27 is an active trench A, an insulating film such as an oxide film can be provided between the trench contact TC and the active portion so that the trench contact TC is not electrically connected to the active portion of the second trench 27.

[0165] <Summary of Embodiment 3>

[0166] Since it is configured in such a way that the trench contact TC is internally connected to the second trench 27, even if the distance between the first trench 7 and the second trench 27 is not increased, the distance between the first trench 7 and the trench contact TC can be increased. Thus, it is possible to further suppress the adverse effect on the conduction characteristics caused by the p + -type contact layer 3 in the channel region C. In addition, the mesa width can be made narrower, and thus, the conduction voltage can be reduced.

[0167] <Example of Variation 3-1>

[0168] In Embodiment 3, the trench contact TC is provided so as to straddle the mesa region and the second trench 27, but it is not limited thereto. As Figures 29 to 31 shown, in a plan view, the trench contact TC (the first trench contact portion TCa and the second trench contact portion TCb) is provided in the second trench 27. That is, as Figure 30 and Figure 31 shown, both ends of the trench contact TC are aligned with both ends of the second trench 27. In addition, as Figure 32 shown, the p + -type contact layer 3 is formed on the side wall and the lower part of the trench contact TC by inclined ion implantation. For example, by providing a tapered portion that tapers downward in the first trench 7, the p + -type contact layer 3 can be formed even for ion implantation substantially perpendicular to the semiconductor substrate.

[0169] <Summary of Example of Variation 3-1>

[0170] In a plan view, since the trench contact TC is provided in the second trench 27, the distance between the first trench 7 and the trench contact TC can be further increased. Thus, it is possible to further suppress the adverse effect on the conduction characteristics caused by the p + -type contact layer 3 in the channel region C. In addition, the mesa width can be further narrowed, and thus the conduction voltage can be further reduced.

[0171] <Example of Variation 3-2>

[0172] As Figure 33 and Figure 34 shown, the trench contact TC may include a part that is not connected to the p + -type contact layer 3 (the first p + -type contact layer 3a and the second p + -type contact layer 3a) but is connected to the n +The third trench contact portion TCd that internally connects the type source layer 4 and the second trench 27. That is, by bending the trench contact TC, the portion of the trench contact TC adjacent to the channel region C can be disposed within the second trench 27. Alternatively, the portion of the trench contact TC adjacent to the channel region C can also be disposed to straddle the mesa region and the second trench 27.

[0173] <Summary of Modification 3-2>

[0174] According to the above structure, in the channel region C, no p + type contact layer 3 is provided under the trench contact TC. Therefore, it is possible to suppress the adverse effect of the p + type contact layer 3 on the conduction characteristics.

[0175] <Modification 3-3>

[0176] In Embodiment 1, the p + type contact layer 3 was formed by performing normal self-aligned implantation on the trench contact TC. In contrast, it can also be as in Figure 33 and Figure 34 shown in Modification 3-2, where the n + type source layer 4 is formed by self-aligned implantation including inclined ion implantation from the trench contact TC (the third trench contact portion TCd) connected to the n + type source layer 4. Similarly, the p-type base layer 5 can also be formed by self-aligned implantation including inclined ion implantation. Similarly, the n-type carrier accumulation layer 6 can also be formed by self-aligned implantation including inclined ion implantation. Hereinafter, this will be described using Figures 35 to 38 this.

[0177] First, as shown in Figure 35 (a) and Figure 35 (b), the gate oxide film 8 and the polysilicon that become the active portion 14 and the dummy portion 24 are etched by dry etching or wet etching to form the trench contact TC.

[0178] Next, as shown in Figure 36 (a) and Figure 36 (b), the p-type base layer 5 is formed by self-aligned implantation including inclined ion implantation from the trench contact TC. Next, as shown in Figure 37 (a) and Figure 37 (b), the n + type source layer 4 is formed by self-aligned implantation including inclined ion implantation from the trench contact TC. Then, as shown in Figure 38 (a) and Figure 38 (b), p is formed under the trench contact TC in the mesa region by self-aligned implantation from the trench contact TC+ Type contact layer 3.

[0179] In addition, the description of the formation of the n-type carrier accumulation layer 6 is omitted above, but similar to the formation of the n-type source layer 4 and the p-type base layer 5, it can be formed by self-aligned implantation including inclined ion implantation from the trench contact TC. + Similar to the formation of the n-type source layer 4 and the p-type base layer 5, it can be formed by self-aligned implantation including inclined ion implantation from the trench contact TC.

[0180] <Summary of Modification Example 3-3>

[0181] The n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 are formed by self-aligned implantation including inclined ion implantation from the trench contact TC. Thus, the photolithography process for the n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 can be reduced. As a result, the manufacturing cost can be reduced. + The n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 are formed by self-aligned implantation including inclined ion implantation from the trench contact TC. Thus, the photolithography process for the n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 can be reduced. As a result, the manufacturing cost can be reduced. + The n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 are formed by self-aligned implantation including inclined ion implantation from the trench contact TC. Thus, the photolithography process for the n-type source layer 4, the p-type base layer 5, and the n-type carrier accumulation layer 6 can be reduced. As a result, the manufacturing cost can be reduced.

[0182] Here, it is assumed that the manufacturing method of this Modification Example 3-3 is applied to the structure of Modification Example 3-2 in which the second trench 27 exists under the trench contact TC, and the case where ions for forming the p-type contact layer 3 are implanted substantially perpendicular to the semiconductor substrate. In this case, the formation of the p-type contact layer 3 in the channel region C adjacent to the second trench 27 is suppressed. Thus, a channel region C in which the adverse effect of the p-type contact layer 3 on the conduction characteristics is suppressed can be realized. Figure 33 and Figure 34 of the structure, and the case where ions for forming the p-type contact layer 3 are implanted substantially perpendicular to the semiconductor substrate. In this case, the formation of the p-type contact layer 3 in the channel region C adjacent to the second trench 27 is suppressed. Thus, a channel region C in which the adverse effect of the p-type contact layer 3 on the conduction characteristics is suppressed can be realized. + type contact layer 3 + type contact layer 3 + type contact layer 3 on the conduction characteristics is suppressed can be realized.

[0183] In addition, here, the case where the manufacturing method of this Modification Example 3-3 is applied to the structure of Modification Example 3-2 to suppress the adverse effect of the p-type contact layer 3 on the conduction characteristics is described, but it is not limited thereto. For example, the manufacturing method of this Modification Example 3-3 can also be applied to the structure of Embodiment 1 in which the width of the first trench 7 is locally different ( + type contact layer 3 on the conduction characteristics is suppressed can be realized. Figure 33 and Figure 34 of the structure, but it is not limited thereto. For example, the manufacturing method of this Modification Example 3-3 can also be applied to the structure of Embodiment 1 in which the width of the first trench 7 is locally different ( Figures 1 to 4 ), and can also be applied to the structure of Embodiment 2 in which the trench contact TC is bent ( Figure 16 ).

[0184] <Modification Example 3-4>

[0185] As Figure 39 shown, the second trench 27 may include a first part 27c separated from the third trench contact portion TCd and a second part 27d connected to the third trench contact portion TCd. The third trench contact portion TCd here is the same as that in Modification Example 3-2. As Figure 40 shown, it is the part in the trench contact TC that does not contact the p-+ The type contact layer 3 is connected not to but to the part that is connected to the n + type source layer 4 and the inside of the second trench 27.

[0186] In such a structure, as Figure 39 shown, the width of the second part 27d can be larger than the width of the first part 27c. That is, it can also be that the second trench 27 bulges in the width direction, and the trench contact TC is locally arranged in the bulging part.

[0187] <Summary of Modification Example 3-4>

[0188] According to the structure in which the second trench 27 bulges as in this Modification Example 3-4, the distance between the trench contact TC and the active trench A can be reduced. Therefore, it is possible to facilitate the formation of a structure in which the n + type source layer 4 is in contact with the active trench A by self-aligned implantation including inclined ion implantation.

[0189] <Embodiment 4>

[0190] In addition to the main unit, the semiconductor device may also have a sensing unit that has a function of detecting an abnormality during a short circuit and protecting the main unit. In this case, from the viewpoint of preventing malfunction, it is preferable that the threshold voltage Vth of the sensing unit is higher than the threshold voltage Vth of the main unit. Therefore, in this Embodiment 4, regarding the distance between the first side portion of the first trench 7 and the first trench contact portion TCa of the trench contact TC, it is configured such that this distance of the sensing unit is shorter than this distance of the main unit.

[0191] <Summary of Embodiment 4>

[0192] According to the above structure, it is possible to make the threshold voltage Vth of the sensing unit higher than the threshold voltage Vth of the main unit. Therefore, malfunction of the semiconductor device can be suppressed.

[0193] <Embodiment 5>

[0194] Figure 41 It is a top view showing the structure of the semiconductor element 100 included in the semiconductor device according to this Embodiment 5. In this Embodiment 5, similar to Embodiment 1, by providing multiple sets of first side portions and first p + type contact layers 3a for one first trench 7, multiple channel regions such as channel regions C and C2 are provided.

[0195] And, the distance Lc between one set of first side portions and the first p + type contact layer 3a is different from the distance Lc2 between another set of first side portions and the first p + type contact layer 3a. InFigure 41 In the example, the distance Lc2 of the channel region C2 is shorter than the distance Lc of the channel region C, and is longer than the distance Ln between the second side of the non-channel region N and the second p + -type contact layer 3b.

[0196] <Summary of Embodiment 5>

[0197] According to Embodiment 5 as described above, the threshold voltage Vth of the channel region C2 can be made higher than the threshold voltage Vth of the channel region C. Thus, at cutoff, the channel region C2 having a high threshold voltage Vth cuts off before the channel region C, reducing the electron injection amount. Therefore, the carrier density inside the n-type drift layer 9 can be reduced. As a result, the on-off time when the channel region C having a low threshold voltage Vth cuts off can be shortened, and the cutoff loss can be reduced.

[0198] <Embodiment 6>

[0199] Figure 42 FIG. is a plan view showing the structure of a semiconductor element 100 included in the semiconductor device according to Embodiment 6. In Embodiment 6, a plurality of active trenches, i.e., a plurality of first trenches 7 such as active trenches A and A2, are provided. Further, the active portion 14 of the active trench A is connected to the gate electrode 15, and the active portion 14 of the active trench A2 is connected to the gate electrode 20.

[0200] Here, as a dual-gate drive for turning on and off two gate electrodes 15 and 20 at different timings, a drive is performed in which the gate electrode 20 is turned off first and the gate electrode 15 is turned off later. In such a dual-gate drive, during the on-off time, i.e., the control period, when the gate electrode 20 is cut off, only the channel of the active trench A connected to the gate electrode 15 is energized, so the on-state voltage increases. Therefore, it is preferable that the control period is short. For this purpose, it is preferable that the threshold voltage Vth of the active trench A2 is high so that the electron injection amount of the active trench A2 connected to the gate electrode 20 becomes small.

[0201] In view of this, in Embodiment 6, the distance Lc between the first side of one active trench A (first trench 7) and the first p + -type contact layer 3a and the distance Lc3 between the first side of the other active trench A2 (first trench 7) and the first p + -type contact layer 3a are different. In Figure 42 the example, the distance Lc3 of the channel region C3 at the active trench A2 is shorter than the distance Lc of the channel region C at the active trench A. More preferably, the area of the channel region C3 at the active trench A2 is smaller than the area of the channel region C at the active trench A.

[0202] <Summary of Embodiment 6>

[0203] According to Embodiment 6 described above, the threshold voltage Vth of the active trench A2 connected to the gate electrode 20 is higher than the threshold voltage Vth of the active trench A connected to the gate electrode 15. Therefore, the control period during double-gate driving can be shortened, and the turn-off loss can be reduced.

[0204] <Other Modification Example 1>

[0205] The active portion 14 described in Embodiments 1 to 6 can also be used for the gate of an RC-IGBT. That is, the semiconductor element 100 of Embodiments 1 to 6 can also be an RC-IGBT (Reverse Conducting IGBT).

[0206] In addition, the area of the p + -type contact layer 3 under the trench contact TC in the diode region of the RC-IGBT can also be smaller than the area of the p + -type contact layer 3 under the trench contact TC in the IGBT region of the RC-IGBT. The p + -type contact layer 3 mentioned here includes a first p + -type contact layer 3a and a second p + -type contact layer 3b.

[0207] In addition, regarding the ratio of the trench contact TC disposed in the second trench 27 with respect to the entire trench contact TC when viewed from above, the ratio of the diode region can be made larger than the ratio of the IGBT region.

[0208] According to the above structure, by disposing the trench contact TC in the second trench 27, the area of the p + -type contact layer 3 in the diode region can be reduced, and the contact area of the emitter electrode 1 can be increased. As a result, the amount of hole injection is reduced and the amount of electron emission is increased, so that the recovery loss can be reduced.

[0209] <Other Modification Example 2>

[0210] The active portion 14 described in Embodiments 1 to 6 can also be used for the gate of a MOSFET (Metal Oxcide Semiconductor Field Effect Transistor). That is, the semiconductor element 100 of Embodiments 1 to 6 can also be a MOSFET.

[0211] <Other Modification Example 3>

[0212] In Embodiments 1 to 6, the semiconductor used for a semiconductor substrate or the like is not described, but the semiconductor may be silicon (Si) or a wide-bandgap semiconductor. The wide-bandgap semiconductor includes, for example, silicon carbide (SiC), gallium nitride-based materials, gallium oxide, or diamond. With such a structure, the breakdown voltage of the semiconductor device can be increased. In addition, ions implanted into the SiC substrate are less likely to thermally diffuse than ions implanted into the Si substrate. Therefore, the width of the p-type contact layer opposite to the trench contact in the SiC substrate is smaller than that in the Si substrate. Therefore, the distance between the first side portion of the first trench in the SiC substrate and the p-type contact layer at the bottom in contact with the trench is larger than that in the Si substrate. That is, for the SiC substrate, the likelihood that the distance of the p-type contact layer having an adverse effect on the threshold voltage Vth becomes large. As a result, for the SiC substrate, the distance between the first side portion and the trench contact can be further shortened without affecting the threshold voltage Vth, thereby reducing the mesa width, and thus the on-state voltage can be further reduced. + The width of the p-type contact layer in the SiC substrate in contact with the bottom of the trench on the first side of the first trench is smaller than that in the Si substrate. Therefore, the distance between the first side portion of the first trench in the SiC substrate and the p-type contact layer at the bottom in contact with the trench is larger than that in the Si substrate. That is, for the SiC substrate, the likelihood that the distance of the p-type contact layer having an adverse effect on the threshold voltage Vth becomes large. + type contact layer between the first side of the first trench and the bottom of the trench contact is larger than that of the Si substrate. That is, for the SiC substrate, the likelihood that the distance of the p-type contact layer having an adverse effect on the threshold voltage Vth becomes large. + As a result, for the SiC substrate, the distance between the first side portion and the trench contact can be further shortened without affecting the threshold voltage Vth, thereby reducing the mesa width, and thus the on-state voltage can be further reduced.

[0213] In addition, the embodiments and the modified examples can be freely combined, or the embodiments and the modified examples can be appropriately modified or omitted.

[0214] Description of reference numerals

[0215] 1 Emitter electrode, 3a First p + type contact layer, 3b Second p + type contact layer, 4n + type source layer, 5p-type base layer, 7 First trench, 8 Gate oxide film, 14 Active portion, 15, 20 Gate electrode, 27 Second trench, 27a, 27c First part, 27b, 27d Second part, TC Trench contact, TCa First trench contact portion, TCb Second trench contact portion, TCc, TCd Third trench contact portion.

Claims

1. A semiconductor device having: A semiconductor substrate provided with an emitter electrode and a gate electrode; A base layer of a first conductivity type disposed on the upper surface side of the semiconductor substrate; A source layer of a second conductivity type disposed on the upper surface side of the base layer; An active portion disposed on an insulating film on an inner surface of a first trench that penetrates the base layer and the source layer and is connected to the gate electrode; A first trench contact portion and a second trench contact portion respectively disposed opposite to a first side portion and a second side portion of the first trench in a plan view, and the emitter electrode is disposed inside the first trench contact portion and the second trench contact portion; A first contact layer of a first conductivity type connected to a lower portion of the first trench contact portion and having a higher concentration of impurities of the first conductivity type than the base layer; A second contact layer of a first conductivity type connected to a lower portion of the second trench contact portion and having a higher concentration of impurities of the first conductivity type than the base layer; And A collector electrode disposed on a lower surface of the semiconductor substrate, In a plan view, a distance between the first side portion and the first trench contact portion is larger than a distance between the second side portion and the second trench contact portion, In a cross-sectional view, the first contact layer is separated from the first side portion, and the second contact layer is connected to the second side portion, In a plan view, an outer contour line at the first side portion of the first trench has at least one of a concave shape and a convex shape greater than or equal to 1.

2. The semiconductor device according to claim 1, wherein, In a plan view, a width at the first side portion of the first trench is smaller than a width at the second side portion of the first trench.

3. The semiconductor device according to claim 2, wherein, A difference between the width at the first side portion and the width at the second side portion is larger than widths of the first trench contact portion and the second trench contact portion respectively.

4. The semiconductor device according to claim 1, wherein, In a plan view, the first trench bends and is recessed at the first side portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein, In a plan view, a trench contact including the first trench contact portion bends toward a side opposite to the first side portion of the first trench.

6. The semiconductor device according to any one of claims 1 to 4, wherein, The base layer and the source layer adjacent to the second side portion of the first trench are separated by the second contact layer.

7. The semiconductor device according to any one of claims 1 to 4, wherein, The base layer and the source layer adjacent to the first side portion of the first trench are connected to each other.

8. The semiconductor device according to claim 1, wherein, Upper ends of the first contact layer and the second contact layer are connected to a lower end of the source layer.

9. The semiconductor device according to claim 2 or 3, wherein, A depth at the second side portion of the first trench is deeper than a depth at the first side portion of the first trench.

10. The semiconductor device according to any one of claims 1 to 4, wherein, the first trench contact portion and the second trench contact portion do not oppose the third side portion of the first trench when viewed from above.

11. The semiconductor device according to claim 5, wherein, the semiconductor device is provided with a second trench sandwiching the trench contact between the first trenches when viewed from above, the second trench includes: a first portion opposing the first trench contact portion of the trench contact; and a second portion opposing a portion other than the first trench contact portion of the trench contact, the width being larger than that of the first portion.

12. The semiconductor device according to claim 1, wherein, when viewed from above, a second trench is provided along the first trench, the semiconductor device further has a third trench contact portion arranged side by side with the first trench contact portion or the second trench contact portion in the width direction between the first trench and the second trench.

13. The semiconductor device according to claim 10, wherein, the base layer and the source layer adjacent to the third side portion of the first trench are connected to each other.

14. The semiconductor device according to claim 1, wherein, when viewed from above, a second trench is provided along the first trench, the first trench contact portion and the second trench contact portion are connected to the inside of the second trench.

15. The semiconductor device according to claim 14, wherein, when viewed from above, the first trench contact portion and the second trench contact portion are provided inside the second trench.

16. The semiconductor device according to claim 1, wherein, when viewed from above, a second trench is provided along the first trench, the semiconductor device further has a third trench contact portion that is not connected to the first contact layer and the second contact layer but is connected to the source layer and the inside of the second trench.

17. The semiconductor device according to claim 16, wherein, the second trench includes: a first portion separated from the third trench contact portion; a second portion connected to the third trench contact portion, the width being larger than that of the first portion.

18. The semiconductor device according to claim 1, wherein, multiple sets of the first side portion and the first contact layer are provided for one first trench, the distance between the first side portion and the first contact layer of one set is different from the distance between the first side portion and the first contact layer of another set.

19. The semiconductor device according to claim 1, wherein, a plurality of the first trenches are provided, the distance between the first side portion and the first contact layer of one first trench is different from the distance between the first side portion and the first contact layer of another first trench.

20. The semiconductor device according to any one of claims 1 to 4, wherein, the active portion is for the gate of an RC-IGBT.

21. The semiconductor device according to claim 20, wherein, The area of the contact layer including the first contact layer and the second contact layer at the diode region of the RC-IGBT is smaller than the area of the contact layer including the first contact layer and the second contact layer at the IGBT region of the RC-IGBT.

22. The semiconductor device according to any one of claims 1 to 4, wherein The active portion is for the gate of the MOSFET.

23. The semiconductor device according to any one of claims 1 to 4, wherein The semiconductor substrate includes a wide-bandgap semiconductor.

24. A method of manufacturing a semiconductor device, which is the method of manufacturing the semiconductor device according to claim 16, wherein The source layer is formed by self-aligned implantation including inclined ion implantation performed from the third trench contact portion connected to the source layer.

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