A high-speed low-power high-voltage drive circuit

Abstract

The application discloses a high-speed low-power high-voltage drive circuit, comprising an N-type DMOS tube N1, a P-type DMOS tube P1, a voltage stabilizing tube D1, an inverter drive circuit (X1, X2, X3), low-voltage NMOS tubes (N2, N3, N5, N7, N8), high-voltage NMOS tubes (N4, N6), low-voltage PMOS tubes (P2, P3, P4, P5), resistors (R1, R2, R3) and capacitors (C1, C2), the source end of the low-voltage PMOS tube P4 is connected with the source end of the high-voltage NMOS tube N4, the drain end of the low-voltage PMOS tube P4 is connected with the drain end of the low-voltage NMOS tube N7, the source end of the low-voltage PMOS tube P5 is connected with the source end of the high-voltage NMOS tube N6, and the drain end of the low-voltage PMOS tube P5 is connected with the drain end of the low-voltage NMOS tube N8; compared with the commonly used high-voltage drive circuit, the application only increases very few devices, and the application cost is low.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, specifically relating to a high-speed, low-power, high-voltage drive circuit. Background Technology

[0002] In the process of integrated circuit design, we often encounter various high-voltage drive circuits. In order to meet the requirements of high voltage and high current, the power output transistors of high-voltage drive circuits are usually selected as high-voltage LDMOS or high-voltage VDMOS. The drain-source breakdown voltage of these two types of DMOS transistors is generally relatively high, and their breakdown voltage can be tens of volts or hundreds of volts. However, their gate-source breakdown voltage is very low, generally below 10V.

[0003] For the reasons mentioned above, DMOS (LDMOS or VDMOS) transistors cannot be directly driven by the power supply voltage. Currently, common solutions include... Figure 1 As shown in the diagram: N1 is an N-type DMOS transistor in the power output stage, with a drain-source breakdown voltage higher than the high-voltage power supply VDD and a gate-source breakdown voltage lower than 10V; P1 is a P-type DMOS transistor in the power output stage, with a drain-source breakdown voltage higher than the high-voltage power supply VDD and a gate-source breakdown voltage lower than 10V; X1, X2, and X3 are inverter drive circuits, which operate on a low-voltage power supply (typically 5V) generated by the high-voltage power supply VDD, meaning the N-type DMOS transistors are directly driven by the low-voltage power supply; N2, N3, and N5 are low-voltage NMOS transistors, with current bias Ibias flowing through N2, and N3 and N5 mirroring the current flowing through N2; N4 and N6 are high-voltage NMOS transistors, with their drain-source breakdown voltage higher than the high-voltage power supply VDD and a gate-source breakdown voltage lower than 10V; P2 and P3 are low-voltage PMOS transistors; R1 is a resistor; D1 is a Zener diode with a reverse breakdown voltage of approximately 6V.

[0004] The working principle of this circuit is as follows:

[0005] When the input signal IN goes high, the signal Ngate goes low, and the output stage power transistor N1 is turned off; when the signal INB goes low, N3, N4, P2, and P3 are all turned off; when the signal INE goes high, N5 and N6 are turned on. The conduction current depends on the Ibias current value and the mirror ratio of N5 and N2. This current reverse-breaks down D1, pulling the signal Pgate voltage down to VDD-6V. Therefore, the output stage power transistor P1 is turned on, and the output voltage OUT goes high. At the same time, the gate-source voltage of the output stage power transistor P1 is clamped at 6V, and P1 operates within a safe voltage range.

[0006] When the input signal IN becomes low, the signal INE is low, N5 and N6 are all turned off; the signal INB is high, N3, N4 and P2, P3 are turned on, the current is determined by the Ibias current value and the mirror ratio of N3 and N2 and P3 and P2, the current pulls up the signal Pgate voltage to the voltage of VDD, the output stage power tube P1 is turned off, the resistor R1 continuously provides pull-up current to the signal Pgate when the signal Pgate voltage is close to the voltage of VDD and P3 works in the linear region; the signal Ngate signal becomes high, the output stage power tube N1 is turned on, the output voltage OUT becomes low, the gate-source voltage of N1 is 5V low voltage power supply, and N1 works in the safe voltage range.

[0007] According to the working principle of the circuit, the following conclusions are drawn: the mirror current of N3 and N5 determines the voltage variation speed of the signal Pgate, if the circuit is applied to high-frequency signal driving, the mirror current flowing through N3 and N5 needs to be very large, if the input signal IN is a 1MHz signal, the mirror current flowing through N3 and N5 may reach tens of milliamperes or even hundreds of milliamperes, which will cause the power consumption current of the entire circuit to be very large, causing the circuit to heat up or even be damaged, and at the same time, it does not meet the main theme of green and low power consumption. SUMMARY

[0008] In order to achieve the above purpose, the technical scheme of the present application is as follows: a high-speed low-power high-voltage drive circuit, the present application meets the application of high-frequency high-voltage signals while controlling the power consumption of the circuit at a very low level, the circuit comprises N-type DMOS tube N1, P-type DMOS tube P1, voltage stabilizing tube D1, inverter drive circuit (X1, X2, X3), low-voltage NMOS tube (N2, N3, N5, N7, N8), high-voltage NMOS tube (N4, N6), low-voltage PMOS tube (P2, P3, P4, P5), resistor (R1, R2, R3) and capacitor (C1, C2).

[0009] One end of the resistor R1 is connected to the source end of the PMOS tube P3, the other end of the resistor R1 is connected to the drain end of the PMOS tube P3, the anode of the voltage stabilizing tube D1 is connected to the gate end of the P-type DMOS tube P1, and the cathode of the voltage stabilizing tube D1 is connected to the source end of the P-type DMOS tube P1.

[0010] The drain end of the N-type DMOS tube N1 and the drain end of the P-type DMOS tube P1 are connected, the gate end of the P-type DMOS tube P1 is connected between the drain end of the PMOS tube P3 and the drain end of the NMOS tube N6, the source end of the N-type DMOS tube N1 is grounded, the source end of the P-type DMOS tube P1 is connected to VDD, and the connection point of the N-type DMOS tube N1 and the P-type DMOS tube P1 is connected to the output signal OUT.

[0011] The gate end of the low-voltage PMOS tube P4 is connected to the resistance R2, the source end of the low-voltage PMOS tube P4 is connected to the source end of the high-voltage NMOS tube N4, and the drain end of the low-voltage PMOS tube P4 is connected to the drain end of the low-voltage NMOS tube N7.

[0012] The gate end of the low-voltage PMOS tube P5 is connected to the resistance R3, the source end of the low-voltage PMOS tube P5 is connected to the source end of the high-voltage NMOS tube N6, and the drain end of the low-voltage PMOS tube P5 is connected to the drain end of the low-voltage NMOS tube N8.

[0013] As an improvement of the present application, the gate end of the high-voltage NMOS tube N4 is connected to the INB signal, the other end of the resistance R2 is connected to the gate end of the high-voltage NMOS tube N4, the source end of the high-voltage NMOS tube N4 is connected to the drain end of the low-voltage NMOS tube N3, the gate end of the high-voltage NMOS tube N6 is connected to the INE signal, the other end of the resistance R3 is connected to the gate end of the high-voltage NMOS tube N6, and the source end of the high-voltage NMOS tube N6 is connected to the drain end of the low-voltage NMOS tube N5.

[0014] As an improvement of the present application, the drain end of the high-voltage NMOS tube N4 is connected to the drain end of the low-voltage PMOS tube P2, the gate end of the low-voltage PMOS tube P2 is connected to the drain end, the drain end of the high-voltage NMOS tube N6 is connected to the drain end of the low-voltage PMOS tube P3, the gate end of the low-voltage PMOS tube P2 is connected to the gate end of the low-voltage PMOS tube P3, and the source end of the low-voltage PMOS tube P2 is connected to the source end of the low-voltage PMOS tube P3.

[0015] As an improvement of the present application, one end of the capacitor C1 is connected to the gate end of the PMOS tube P4 and the connection point of the resistance R2, and the other end is grounded. One end of the capacitor C2 is connected to the gate end of the PMOS tube P5 and the connection point of the resistance R3, and the other end is grounded. When the signal INE is high, the high-level signal of INE charges the capacitor C2 through the resistance R3. The values of the resistance R3 and the capacitor C2 satisfy R3*C2=5n.

[0016] As an improvement of the present application, when the signal INB is high, the high-level signal of INB charges the capacitor C1 through the resistance R2. The values of the resistance R2 and the capacitor C1 satisfy R2*C1=5n.

[0017] As an improvement of the present application, when the parasitic gate capacitance of the P-type DMOS tube P1 is 10pF, the voltage flip time of Pgate is less than 1nS.

[0018] As an improvement of the present application, the low-voltage NMOS tube N3 is connected to the gate end of the low-voltage NMOS tube N2, the connection point of the low-voltage NMOS tube N3 and the low-voltage NMOS tube N2 is connected to the gate end of the low-voltage NMOS tube N7, the gate end of the low-voltage NMOS tube N5 and the gate end of the low-voltage NMOS tube N8, the source end of the low-voltage NMOS tube N2 is grounded, the drain end of the low-voltage NMOS tube N2 is connected to the current source Ibias, and the drain end and the gate end of the low-voltage NMOS tube N2 are connected.

[0019] As an improvement of the present application, the inverter circuit is connected to the IN signal, the inverters X1, X2 and X3 are connected in sequence, the output end of the inverter X1 is connected to the input end of the inverter X2, the output end of the inverter X2 is connected to the input end of the inverter X3, the output end of the inverter X3 is connected to the gate end of the N-type DMOS tube N1, the input end of the inverter X1 is connected to the signal IN, the inverter X1 outputs the signal INB, and the inverter X2 outputs the signal INE.

[0020] Compared with the prior art, the present application has the following advantages:

[0021] 1) The circuit structure of the present application is simple, and only a few devices are added compared with the commonly used high-voltage drive circuit, so the application cost is low.

[0022] 2) In the present application, the 100mA large current and the 10uA small current are used to drive the power tube, which ensures the high-speed operation of the drive circuit and has very low power consumption current. The resistance is used to charge the capacitor to control the on-time of the large current, and the power consumption current of the drive circuit is greatly reduced. Under the application frequency of 1HMz, the power consumption current is reduced from 100mA of the commonly used circuit to 1mA.

[0023] 3) The highest working frequency of the drive circuit in the present application can reach more than 10MHz. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of the high-voltage drive circuit in the prior art.

[0025] Figure 2 It is a schematic diagram of the high-voltage drive circuit in the present application.

[0026] Figure 3 It is a schematic diagram of the related waveforms in the present embodiment. DETAILED DESCRIPTION

[0027] The present application will be further illustrated in conjunction with the drawings and specific embodiments, and it should be understood that the following specific embodiments are only used to illustrate the present application and not to limit the scope of the present application.

[0028] Embodiment: refer to Figure 2A high-speed low-power high-voltage drive circuit, the circuit comprises N-type DMOS tube N1, P-type DMOS tube P1, voltage stabilizing tube D1, inverter drive circuit (X1, X2, X3), low-voltage NMOS tube (N2, N3, N5, N7, N8), high-voltage NMOS tube (N4, N6), low-voltage PMOS tube (P2, P3, P4, P5), resistance (R1, R2, R3) and capacitor (C1, C2).

[0029] Wherein N1 is the power output stage N-type DMOS tube, the breakdown voltage of its drain-source is higher than the high-voltage power supply VDD, and the gate-source breakdown voltage is lower than 10V, P1 is the power output stage P-type DMOS tube, the breakdown voltage of its drain-source is higher than the high-voltage power supply VDD, and the gate-source breakdown voltage is lower than 10V, the inverter drive circuit X1 / X2 / X3 works at the low-voltage power supply generated by the high-voltage power supply VDD, generally 5V power supply, that is, the N-type DMOS tube N1 is directly driven by the low-voltage power supply, the current bias Ibias flows through the low-voltage NMOS tube N2, the low-voltage NMOS tube N3, the low-voltage NMOS tube N5, the low-voltage NMOS tube N7, the low-voltage NMOS tube N8 mirrors the current flowing through the low-voltage NMOS tube N2, the breakdown voltage of the drain-source of the high-voltage NMOS tube (N4, N6) is higher than the high-voltage power supply VDD, and the gate-source breakdown voltage is lower than 10V, the reverse breakdown voltage of the voltage stabilizing tube D1 is about 6V.

[0030] Further, the gate end of the low-voltage PMOS tube P4 is connected to the resistance R2, the source end of the low-voltage PMOS tube P4 is connected to the source end of the high-voltage NMOS tube N4, and the drain end of the low-voltage PMOS tube P4 is connected to the drain end of the low-voltage NMOS tube N7.

[0031] Further, the gate end of the low-voltage PMOS tube P5 is connected to the resistance R3, the source end of the low-voltage PMOS tube P5 is connected to the source end of the high-voltage NMOS tube N6, and the drain end of the low-voltage PMOS tube P5 is connected to the drain end of the low-voltage NMOS tube N8.

[0032] Further, the gate end of the low-voltage PMOS tube P4 is connected to the resistance R2, the source end of the low-voltage PMOS tube P4 is connected to the source end of the high-voltage NMOS tube N4, and the drain end of the low-voltage PMOS tube P4 is connected to the drain end of the low-voltage NMOS tube N7.

[0033] Further, the gate end of the low-voltage PMOS tube P5 is connected to the resistance R3, the source end of the low-voltage PMOS tube P5 is connected to the source end of the high-voltage NMOS tube N6, and the drain end of the low-voltage PMOS tube P5 is connected to the drain end of the low-voltage NMOS tube N8.

[0034] Further, the gate terminals of the low-voltage NMOS transistor N3, the low-voltage NMOS transistor N7, the low-voltage NMOS transistor N5, the low-voltage NMOS transistor N8 and the low-voltage NMOS transistor N2 are connected, and the source terminals of the low-voltage NMOS transistor N3, the low-voltage NMOS transistor N7, the low-voltage NMOS transistor N5, the low-voltage NMOS transistor N8 and the low-voltage NMOS transistor N2 are grounded.

[0035] Further, the inverter circuit is connected to the IN signal, the inverters X1, X2 and X3 are connected in sequence and connected to the gate terminal of the N-type DMOS transistor N1, and the N-type DMOS transistor N1 is connected to the P-type DMOS transistor P1.

[0036] In the circuit, when the input signal IN becomes high, the signal Ngate becomes low, and the output stage power transistor N1 is turned off; the signal INB is low, and the low-voltage NMOS transistors N3, N4, N7 and the low-voltage PMOS transistors P2, P3 and P4 are all turned off; the signal INE is high, the high-voltage transistor N6 is turned on, the initial value of the gate voltage of P5 is 0V, P5 and N8 are turned on, the conduction current is the mirror current of N8 (N8 and N2 form a current mirror, and the size ratio of the two transistors determines the mirror current ratio), the design value of the pulse conduction current is 100mA, this current will reverse breakdown D1, and the signal Pgate voltage will be quickly pulled down to VDD-6V, so the output stage power transistor P1 is turned on, and the output voltage OUT becomes high, at the same time the gate-source voltage of the output stage power transistor P1 is clamped at 6V, and P1 works in a safe voltage range; the high-level signal of INE charges the capacitor C2 through the resistor R3, and the values of the resistor R3 and the capacitor C2 are reasonably designed to make:

[0037] R3*C2=5n

[0038] Wherein, n represents the order of magnitude, such as m, u, n. It can also be described as 1E-9. After the resistor R3 charges the capacitor C2 for about 10nS, the gate voltage of P5 rises to the same voltage as INE, P5 and N8 are turned off, N5 is always turned on after INE becomes high, and the mirror current of N5 is designed to be 10uA, so that the current flowing through N6 is switched from 100mA to 10uA after 10nS, and the voltage of Pgate continues to be VDD-6V.

[0039] When the input signal IN becomes low, the signal INE is low, the signal INB is high, N5, N6, N8 and P5 are all turned off; the high voltage tube N4 is turned on, the initial value of the gate voltage of P4 is 0V, P4 and N7 are turned on, the conduction current is the mirror current of N7, the design value is 100mA, the current is mirrored through P2 and P3, and the signal Pgate voltage is quickly pulled up to the VDD voltage, the output stage power tube P1 is turned off, the resistor R1 continuously provides the pull-up current to the signal Pgate when the signal Pgate voltage is close to the VDD voltage and P3 works in the linear region; the high level signal of INB charges the capacitor C1 through the resistor R2, and the values of the resistor R2 and the capacitor C1 are reasonably designed so that:

[0040] R2*C1=5n

[0041] Wherein, n represents the order of magnitude, such as m, u, n. It can also be described as 1E-9. After the resistor R2 charges the capacitor C1 for about 10nS, the gate voltage of P4 rises to the same voltage as INB, P4 and N7 are turned off, N3 is always turned on after INB becomes high, the mirror current of N3 is designed to be 10uA, then the current flowing through N4 is switched from 100mA to 10uA after 10nS, and the voltage of Pgate continues to be VDD; the signal IN is low, the signal Ngate signal becomes high, the output stage power tube N1 is turned on, N1 is turned on, the output is pulled low, the output voltage OUT becomes low, the gate-source voltage of N1 is 5V low voltage power supply, and N1 works in the safe voltage range.

[0042] The waveform diagram of the related signals is shown in Figure 3 .

[0043] Because the 100mA power consumption current only works for 10nS, the power consumption current of the application is greatly reduced, and under the application condition of 1MHz input signal IN, the power consumption current of the application is reduced from 100mA to 1mA. At the same time, under the condition that the parasitic gate capacitance of the power output tube P1 is 10pF, the voltage of Pgate is less than 1nS, and the highest working frequency of the application can reach more than 10MHz.

[0044] It should be noted that the above content only illustrates the technical idea of the application, and cannot limit the protection scope of the application. For ordinary skilled persons in the technical field, some improvements and refinements can be made without departing from the principles of the application, and these improvements and refinements all fall within the protection scope of the claims of the application.

Claims

1. A high-speed, low-power, high-voltage drive circuit, characterized in that, The circuit includes an N-type DMOS transistor N1, a P-type DMOS transistor P1, a Zener diode D1, an inverter drive circuit composed of inverters X1, X2, and X3, low-voltage NMOS transistors N2, N3, N5, N7, and N8, high-voltage NMOS transistors N4 and N6, low-voltage PMOS transistors P2, P3, P4, and P5, resistors R1, R2, and R3, capacitors C1 and C2, and the Zener diode D1 and resistor R1 are connected to the gate terminal of the P-type DMOS transistor P1. The gate terminal of the low-voltage PMOS transistor P4 is connected to the resistor R2, the source terminal of the low-voltage PMOS transistor P4 is connected to the source terminal of the high-voltage NMOS transistor N4, and the drain terminal of the low-voltage PMOS transistor P4 is connected to the drain terminal of the low-voltage NMOS transistor N7. The gate of the low-voltage PMOS transistor P5 is connected to the resistor R3, the source of the low-voltage PMOS transistor P5 is connected to the source of the high-voltage NMOS transistor N6, and the drain of the low-voltage PMOS transistor P5 is connected to the drain of the low-voltage NMOS transistor N8. The inverter driver circuit is connected to the IN signal, the INB signal is the inverted version of the IN signal, and the INE signal is the inverted version of the INB signal. The gate terminal of the high-voltage NMOS transistor N4 is connected to the INB signal, and the resistor R2 is connected to the gate terminal of the high-voltage NMOS transistor N4. The source terminal of the high-voltage NMOS transistor N4 is connected to the low-voltage NMOS transistor N3. The gate terminal of the high-voltage NMOS transistor N6 is connected to the INE signal, and the resistor R3 is connected to the gate terminal of the high-voltage NMOS transistor N6. The source terminal of the high-voltage NMOS transistor N6 is connected to the low-voltage NMOS transistor N5. The drain of the high-voltage NMOS transistor N4 is connected to the low-voltage PMOS transistor P2, the drain of the high-voltage NMOS transistor N6 is connected to the low-voltage PMOS transistor P3, and the gates of the low-voltage PMOS transistors P2 and P3 are connected. When signal INE is high, the high-level signal of INE charges capacitor C2 through resistor R3. The values ​​of resistor R3 and capacitor C2 satisfy: R3 * C2 = 5n, where n is 1E. -9 , When signal INB is high, the high-level signal of INB charges capacitor C1 through resistor R2. The values ​​of resistor R2 and capacitor C1 satisfy R2*C1=5n, where n is 1E. -9 , When the parasitic gate capacitance of the P-type DMOS transistor P1 is 10pF, the voltage switching time of Pgate is less than 1ns.

2. The high-speed, low-power, high-voltage drive circuit according to claim 1, characterized in that, The gate terminals of the low-voltage NMOS transistors N3, N7, N5, N8, and N2 are connected.

3. The high-speed, low-power, high-voltage drive circuit according to claim 1, characterized in that, The inverters X1, X2 and X3 are sequentially connected to the gate of the N-type DMOS transistor N1, and the N-type DMOS transistor N1 is connected to the P-type DMOS transistor P1.

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