Efficient scheduling of tasks for resolution enhancement techniques

Abstract

Systems and methods for scheduling Optical Proximity Correction (OPC) operations or other Resolution Enhancement Techniques (RET) operations on a layout design are disclosed. The layout design is divided into multiple regions, such as multiple tiles. OPC is performed on the multiple tiles to generate a modified layout design. Performing OPC on multiple tiles is time-consuming. To allocate OPC processing more efficiently, the OPC processing time for multiple tiles is estimated. The estimation of the OPC processing time for a given tile can be based on one or both of the following analyses: analysis of the given tile; or analysis of one or more tiles adjacent to the given tile. Based on this estimation, tiles with longer estimated processing times are scheduled before tiles with shorter estimated processing times, which may result in more efficient OPC processing.

Description

Technical Field

[0001] This disclosure relates to the fields of circuit design and circuit fabrication, and more specifically, to resolution enhancement techniques for layout design, such as optical proximity correction (OPC) operations. Background Art

[0002] Electronic circuits, such as integrated microcircuits, are used in a wide variety of products, from automobiles to microwaves to personal computers. Designing and manufacturing integrated circuit devices typically involves many steps, sometimes referred to as the "design flow." The specific steps in the design flow generally depend on the type of integrated circuit, its complexity, the design team, and the integrated circuit manufacturer or foundry that will fabricate the microcircuit. Typically, software "tools" and hardware "tools" validate the design at various stages of the design flow by running software simulators and / or hardware simulators. These steps help identify errors in the design and allow designers and engineers to correct or otherwise improve it.

[0003] For example, a layout design can be derived from an electronic circuit design. This layout design can include integrated circuit (IC) layout, IC mask layout, or mask design. Specifically, the layout design can be a representation of the integrated circuit in terms of planar geometry, which corresponds to a pattern of metal, oxide, or semiconductor layers of the components constituting the integrated circuit. The layout design can be for the entire chip or for a portion of a full-chip layout design.

[0004] For analytical purposes, the layout design can be divided into regions or computational units, which are used interchangeably. These regions can be arrays of rectangular or square regions. Alternatively, the regions can include different shapes. The size can be a few micrometers (μm) or 10 μm. These regions or computational units can be referred to as tiles or windows. In practice, the number of tiles can be in the hundreds of thousands or even millions.

[0005] As designers and manufacturers continue to shrink the size of circuit components, the shapes reproduced on the substrate by photolithography become smaller and are placed closer together. This reduction in feature size and spacing increases the difficulty of faithfully reproducing the image intended for the layout design onto the substrate and can introduce defects in the manufactured devices. To address this issue, one or more resolution enhancement techniques are typically employed to improve the resolution of the image formed on the substrate by the photomask during the photolithography circuit fabrication process.

[0006] In this regard, various resolution enhancement techniques can be used to analyze a wide range of patches. One such resolution enhancement technique (optical proximity correction, or optical process correction (OPC)) seeks to compensate for optical diffraction effects. When light illuminates a photomask, the transmitted light diffracts, with light from regions having higher specific frequencies diffracting at higher angles. The resolution limit of a lens in a photolithography system makes it effectively used as a low-pass filter for a wide range of spatial frequencies in a two-dimensional layout. This can lead to optical proximity effects, such as line ends being pulled back from their desired locations, corner rounding, and deviations between isolated and dense structures. Optical proximity correction adjusts the amplitude of light transmitted through the photomask by modifying the layout design data used to create the photomask. For example, the edges in the layout design can be adjusted based on how much additional exposure (or underexposure) is needed at certain points on the substrate, making certain portions of the geometry larger or smaller. When these adjustments are properly calibrated, the overall pattern fidelity is greatly improved, thereby reducing optical proximity effects. Therefore, using OPC or other types of resolution enhancement techniques to analyze potentially millions of patches is computationally very expensive. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of the invention and, together with the description, serve to explain its principles. For convenience, the same reference numerals are used throughout the drawings to denote the same or similar elements.

[0008] Figure 1 Examples of computing systems that can be used to implement various embodiments of the disclosed technology are shown.

[0009] Figure 2 Examples of multi-core processor units that can be used to implement various embodiments of the disclosed technology are shown.

[0010] Figure 3A A flowchart is shown for scheduling multiple tiles in a layout design and implementing resolution enhancement techniques.

[0011] Figure 3B A flowchart is shown for ranking tiles based on tile analysis in order to schedule resolution enhancement techniques to be performed on the tiles.

[0012] Figure 3C A flowchart is shown for classifying tiles based on analysis of neighboring tiles in order to schedule the execution of resolution enhancement techniques on the tiles.

[0013] Figure 4 A flowchart is shown to iteratively estimate the processing time of a given tile based on the actual processing time of tiles in the neighboring regions of that tile.

[0014] Figure 5 An exemplary layout for tile coloring using OPC is shown. Detailed Implementation

[0015] Overall considerations

[0016] Various aspects of the currently disclosed technology relate to techniques for scheduling resolution enhancement techniques (e.g., performing OPC operations) associated with semiconductor manufacturing processes. Numerous details are set forth in the following description for purposes of explanation. However, those skilled in the art will recognize that the disclosed techniques can be implemented without using these specific details. In other instances, known features have not been described in detail to avoid obscuring the currently disclosed technology.

[0017] Some of the techniques described herein can be implemented as software instructions stored on one or more non-transitory computer-readable media, as software instructions executable on a computer, or some combination of both. For example, some of the disclosed techniques can be implemented as part of electronic design automation (EDA) tools. This approach can be performed on a single computer or on a networked computer.

[0018] While the operations of the disclosed methods are described in a specific order for ease of presentation, it should be understood that this descriptive approach includes rearrangement unless the specific language described below requires a particular order. For example, in some cases, the sequentially described operations may be rearranged or performed simultaneously. Furthermore, for simplicity, the disclosed flowcharts and block diagrams typically do not show the various ways in which a particular method can be combined with other methods. Additionally, the detailed description sometimes uses terms such as "execute," "generate," "acquire," and "determine" to describe the disclosed methods. These terms are high-level abstractions of the actual operations performed. The actual operations corresponding to these terms will vary depending on the specific implementation, and these actual operations are readily recognizable to those skilled in the art.

[0019] Furthermore, as used herein, the term "design" is intended to encompass data describing the entire integrated circuit device. The term is also intended to encompass smaller sets of data describing one or more components of the entire device (however, a portion of the integrated circuit device, for example). Additionally, the term "design" is intended to encompass data describing more than one microdevice, such as data used to form multiple microdevices on a single wafer.

[0020] Explanatory operating environment

[0021] Various electronic design automation processes according to embodiments of the disclosed technology can be implemented using computer-executable software instructions executed by one or more programmable computing devices. Because these embodiments of the disclosed technology can be implemented using software instructions, the components and operation of a general-purpose programmable computer system on which various embodiments of the disclosed technology can be employed will be described first. Furthermore, due to the complexity of some electronic design automation processes and the large size of many circuit designs, various electronic design automation tools are configured to operate on computing systems capable of running multiple processing threads simultaneously. Therefore, reference will be made to… Figure 1 This describes the components and operations of a computer network having a host or master computer and one or more remote or slave computers. However, this operating environment is merely an example of a suitable operating environment and is not intended to imply any limitation on the scope or functionality of the disclosed technology.

[0022] exist Figure 1 In this example, computer network 101 includes a host computer 103. In the illustrated example, host computer 103 is a multiprocessor computer including multiple input / output devices 105 and memory 107. Input / output devices 105 may include any device for receiving input data from a user or providing output data to a user. Input devices may include, for example, a keyboard, microphone, scanner, or pointing device for receiving input from a user. Output devices may then include a display monitor, speaker, printer, or haptic feedback device. These devices and their connections are known in the art and will not be discussed in detail here.

[0023] The memory 107 can be implemented using any combination of computer-readable media accessible by the host computer 103. Computer-readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash memory microcircuit devices, CD-ROM discs, digital video discs (DVDs), or other optical storage devices. Computer-readable media may also include magnetic tape cassettes, magnetic tape, disks or other magnetic storage devices, perforated media, holographic storage devices, or any other media that can be used to store the desired information.

[0024] As will be discussed in detail below, the host computer 103 runs a software application for performing one or more operations according to various examples of the disclosed technology. Therefore, memory 107 stores software instructions 109A, which, when executed, implement the software application for performing one or more operations (such as those disclosed herein). Memory 107 also stores data 109B used with the software application. In the illustrated embodiment, data 109B contains processing data used by the software application to perform operations, at least some of which may be parallel.

[0025] The host computer 103 also includes multiple processor units 111 and interface devices 113. The processor units 111 can be any type of processor device that can be programmed to execute software instructions 109A, but are typically microprocessor devices. For example, one or more of the processor units 111 can be commercially available programmable microprocessors, such as… (Intel) or Xeon TM Microprocessors, Athlon from Advanced Micro Devices (AMD) TM Microprocessor, or Motorola's 68K / Microprocessor. Alternatively or additionally, one or more of the processor units 111 may be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Interface device 113, processor unit 111, memory 107, and input / output device 105 are connected together via bus 115.

[0026] In some implementations of the disclosed technology, the host computer 103 may employ one or more processing units 111 having more than one processor core. Therefore, Figure 2 An example of a multi-core processor unit 111 that can be used with various embodiments of the disclosed technology is shown. As shown in the figure, the processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As is known to those skilled in the art, the computing engine includes logic devices for performing various computational functions (e.g., fetching software instructions) and then executing actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers; performing logical operations such as AND, OR, NOR, and XOR; and retrieving data. Each computing engine 203 can then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0027] Each processor core 201 is connected to an interconnect 207. The specific architecture of the interconnect 207 can vary depending on the architecture of the processor unit 111. For some processor cores 201, such as unit microprocessors created by Sony, Toshiba, and IBM, the interconnect 207 can be implemented as an interconnect bus. However, for other processor units 111, such as the Opteron available from Advanced Micro Devices in Sunnyvale, California... TM and Athlon TM The dual-core processor interconnect 207 can be implemented as a system request interface device. In any case, the processor core 201 communicates with the input / output interface 209 and the memory controller 210 via the interconnect 207. The input / output interface 209 provides a communication interface between the processor unit 111 and the bus 115. Similarly, the memory controller 210 controls the exchange of information between the processor unit 111 and the system memory 107. For some embodiments of the disclosed technology, the processor unit 111 may include additional components, such as a high-level cache memory accessible by the processor core 201.

[0028] Although Figure 2 A diagram is shown of a processor unit 111 that may be employed by some embodiments of the disclosed technology; however, it should be understood that this diagram is merely representative and not limiting. Furthermore, for some implementations, a multi-core processor unit 111 may be used instead of multiple individual processor units 111. For example, alternative implementations of the disclosed technology may employ a single processor unit 111 with six cores, two multi-core processor units each with three cores, a multi-core processor unit 111 with four cores, and two individual single-core processor units 111, etc., instead of six individual processor units 111.

[0029] Now back Figure 1 Interface device 113 allows host computer 103 to communicate with slave computers 117A, 117B, 117C...117x via a communication interface. The communication interface can be any suitable type of interface, including, for example, a conventional wired network connection or a wired network connection using optical transmission. The communication interface can also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. Interface device 113 converts data and control signals from the autonomous computer 103 and each slave computer 117 into network messages according to one or more communication protocols (e.g., Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and Internet Protocol (IP)). These and other conventional communication protocols are known in the art and will not be discussed in detail here.

[0030] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and one or more optional input / output devices 125 connected together via a system bus 127. Similar to the host computer 103, the optional input / output devices 125 for the slave computer 117 may include any conventional input or output devices, such as a keyboard, pointing device, microphone, display monitor, speakers, and printer. Similarly, the processor unit 121 may be any type of conventional or custom-made programmable processor device. For example, one or more of the processor units 121 may be commercially available programmable microprocessors, such as… of or Xeon TM Microprocessors, Advanced MicroDevices' Athlon TM Microprocessor, or Motorola's 68K / Microprocessor. Alternatively, one or more of the processor units 121 may be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Furthermore, one or more of the processor units 121 may have more than one core, as referenced above. Figure 2 As described. For example, in some embodiments of the disclosed technology, one or more of the processor units 121 may be unit processors. The memory 119 may then be implemented using any combination of the computer-readable media discussed above. Similar to interface device 113, interface device 123 allows slave computer 117 to communicate with host computer 103 via a communication interface.

[0031] In the example shown, the host computer 103 is a multiprocessor unit computer with multiple processor units 111, while each slave computer 117 has a single processor unit 121. However, it should be noted that alternative implementations of the disclosed technology may employ a host computer with a single processor unit 111. Furthermore, one or more of the slave computers 117 may have multiple processor units 121, depending on their intended use, as discussed previously. Moreover, although only a single interface device 113 or 123 is shown for both the host computer 103 and the slave computers, it should be noted that for alternative implementations of the disclosed technology, one or more of the computer 103, slave computers 117, or some combination of both, may use two or more different interface devices 113 or 123 to communicate through multiple communication interfaces.

[0032] For various examples of the disclosed technology, host computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of computer-readable media accessible by host computer 103. Computer-readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash memory microcircuit devices, CD-ROM discs, digital video discs (DVDs), or other optical storage devices. Computer-readable media may also include magnetic tape cassettes, magnetic tape, disks or other magnetic storage devices, perforated media, holographic storage devices, or any other media that can be used to store desired information. According to some embodiments of the disclosed technology, one or more of the slave computers 117 may alternatively or additionally be connected to one or more external data storage devices. Typically, these external data storage devices will include data storage devices also connected to host computer 103, but they may also differ from any data storage devices accessible by host computer 103.

[0033] It should also be understood that, Figure 1 and Figure 2 The description of the computer networks shown is provided by way of example only and is not intended to imply any limitation on the scope or functionality of alternative embodiments of the disclosed technology.

[0034] Circuit Design Flow and OPC

[0035] As discussed above, software and hardware tools validate designs at various stages of the design flow by running software simulators and / or hardware simulators. For most design flows, several steps are common. Initially, the specification for the new circuit is translated into a logic design, sometimes referred to as the circuit's register transfer level (RTL) description. This logic design describes the circuit according to the signal exchanges between hardware registers and the logical operations performed on those signals. The logic design is typically done using a hardware design language (HDL), such as the Very High Speed ​​Integrated Circuit Hardware Design Language (VHDL). The circuit's logic is then analyzed to confirm that it will precisely perform the functions required by the circuit. This analysis is sometimes called "functional verification."

[0036] After confirming the accuracy of the logic design, it is converted into a device design using synthesis software. The device design, typically in the form of a schematic or netlist, describes the specific electronic components (e.g., transistors, resistors, and capacitors) and their interconnections that will be used in the circuit. This device design generally corresponds to the level of representation shown in a conventional circuit diagram. The relationships between the electronic components are then analyzed to confirm that the circuit described by the device design will correctly perform the required functions. This analysis is sometimes referred to as "formal verification." Additionally, at this stage, preliminary timing estimates of portions of the circuit are typically made using assumed characteristic speeds for each device and incorporated into the verification process.

[0037] Once the components and their interconnections are established, the design is transformed again, this time into a physical design describing specific geometric elements. This type of design is often referred to as a "layout" design. Typically, polygonal geometric elements define the shapes that will be created in various material layers to fabricate the circuit. Automated placement and routing tools are typically used to define the physical layout, specifically defining the wires that will be used to interconnect the circuit devices. In a layout design, each layer of the microcircuit will have a corresponding layer representation, and the geometry described in the layer representation will define the relative positions of the circuit elements that make up the circuit devices. For example, the shapes in the layer representation of a metal layer will define the positions of the metal wires used to connect the circuit devices. Custom layout editors such as Mentor Graphics' ICstation or Cadence's Virtuoso allow designers to customize design layouts, primarily for analog, mixed-signal, RF, and standard cell designs.

[0038] Integrated circuit layout descriptions can be provided in many different formats. The Graphic DataSystem II (GDSII) format is a popular format for transmitting and archiving two-dimensional graphic IC layout data. Among its other features is a hierarchy of structures, each containing layout elements (e.g., polygons, paths or multilines, circles, and text boxes). Other formats include the open-source format Open Access, Milkyway provided by Synopsys, Inc., EDDM provided by Mentor, and the Open Artwork System Interchange Standard (OASIS) recently proposed by Semiconductor Devices and Materials International (SEMI). These various industry formats are used to define the geometric information in IC layout designs used to manufacture integrated circuits. Once a microcircuit device design is complete, the layout portion of that design can be used by manufacturing tools to fabricate the device using a photolithography process.

[0039] Typically, designers will perform multiple verification processes on the layout design. For example, the layout design can be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. In this process, the layout versus schematic (LVS) tool extracts the netlist from the layout design and compares it with the netlist taken from the circuit schematic. LVS can be enhanced by a formal equivalence check, which checks whether two circuits perform exactly the same function without needing to be isomorphic.

[0040] The layout design can also be analyzed to confirm compliance with various design requirements, such as minimum spacing between geometric elements and minimum linewidth of geometric elements. In this process, the design rule checking (DRC) tool takes as input a layout design in GDSII standard format and a list of rules specific to the semiconductor process selected for manufacturing. A set of rules for a particular process is called a run group, a deck, or simply a set. An example of a rule set format is Mentor's Standard Verification Rule Format (SVRF).

[0041] There are many different manufacturing processes used to fabricate circuits, but most involve a series of steps that deposit different material layers onto a substrate, expose specific portions of each layer to radiation, and then etch away the exposed (or unexposed) portions of the layer. A simple semiconductor device component can be fabricated by following these steps, just as an example. First, a positive epitaxial layer is grown on a silicon substrate by chemical vapor deposition. Next, a nitride layer is deposited on the epitaxial layer. Then, specific regions of the nitride layer are exposed to radiation, and the exposed regions are etched away to leave exposed regions on the epitaxial layer (i.e., regions no longer covered by the nitride layer). The exposed regions are then subjected to a diffusion or ion implantation process to allow a dopant (such as phosphorus) to enter the exposed epitaxial layer and form a charged trap. This process of depositing material layers on a substrate or subsequent material layers, then exposing specific patterns to radiation, etching, and doping or other diffusing materials is repeated multiple times, allowing the fabrication of different physical layers of a circuit.

[0042] Each time a material layer is exposed to radiation, a mask is created to expose only the desired areas to the radiation while protecting other areas from exposure. The mask is created based on circuit layout data. That is, the geometry described in the layout design defines the relative positions or areas of the circuitry that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based on the layout design, after which the mask can be used in the photolithography process.

[0043] As discussed previously, one or more resolution enhancement techniques (RETs) can be employed to improve the resolution of the image formed by the mask on the substrate during the photolithography process. One such technique is OPC, which can be rule-based, model-based, or a combination of both. In rule-based OPC, proximity effects are characterized, and a specific solution is designed for a particular geometric configuration. DRC tools or a geometry-based software engine are then used to search for layout designs to find these geometric configurations. Once the geometric configuration is found, the specific solution is applied.

[0044] In addition to OPC, RETs are also considered in this paper. In this respect, any discussion about OPC can be consistently applied to other RETs.

[0045] For simple cases, rule-based OPC methods work well. However, for complex layout features, model-based OPC methods are employed to obtain the desired results. Model-based OPC performs simulations to predict the printed image, which guides layout modifications. At this point, OPC can include performing simulations to predict the printed image and performing any corrections or changes based on the guarantees provided by the performed simulations, as discussed further below. In a typical model-based OPC process, polygons in the layout design are divided into edge segments to allow for the desired fine-grained movement of these edge segments. An example of this is illustrated in U.S. Patent Application Publication No. 2019 / 0155143A1, the entire contents of which are incorporated herein by reference.

[0046] Specifically, the size of the edge segments and which specific edges will be fragmented in a given layout design depend on the OPC process parameters (often referred to as the OPC recipe). A simulation is performed to obtain a predicted printed image for the layout features. This simulated image can be compared to the target image (e.g., at each edge segment). The distance between the target image and the simulated image is often referred to as the edge placement error (EPE). Next, the edge segments can be moved or adjusted individually so that the simulated image used for the resulting mask reproduces the target image as closely as possible. Subsequently, the image generated by the mask using the shifted edge segments is simulated, and the newly simulated image is compared to the target image, calculating the edge placement error for each edge segment.

[0047] This process of moving edge segments, simulating the image generated using the moved edge segments, and comparing the simulated image with the target image can be repeated multiple times. Each cycle of moving edge segments and comparing the newly simulated image with the target image is called an iteration of the OPC process. Typically, the edge segment moved during a given iteration and the distance the edge segment is shifted are determined based on the edge placement error.

[0048] The movement value for each edge segment (often referred to as the edge adjustment value or edge displacement value) can be the edge placement error multiplied by a constant factor (feedback factor). This feedback factor can be location-dependent or edge-type-dependent, based on the OPC recipe. Alternatively, the movement value can be derived using a method that considers the correlation between neighboring edge segments (a method based on cross-MEEF (mask error enhancement factor)).

[0049] The OPC iterative process continues until the simulated image is sufficiently similar to the target image, or until the displacement of the edge segments has converged to the point where further movement of the edge segments will not improve the position of the simulated image. Once the final position of the edge segments is determined in the layout design data, modified mask features can be created based on the corrected layout design data.

[0050] OPC Scheduling

[0051] Multiple computer processing units can be used (e.g., such as...) Figures 1 to 2 The CPU cores shown process OPC or other RET tasks for layout design in a distributed manner. Specifically, the task can be divided into many independent subtasks. Therefore, the overall utilization of computing resources spent processing the entire task can depend on how the subtasks are scheduled in the process of sorting and allocating them to available cores, where each subtask may take a different amount of time to complete. Thus, the layout design can be divided into multiple M regions (e.g., M tiles), where M subtasks correspond to OPC or other RET simulations associated with the M regions, and the M subtasks can be processed in a distributed manner across multiple computer processing units.

[0052] As an extreme example, if there are N cores executing M subtasks, where M >> N, and assuming each subtask takes the same amount of time T, then it will take "(M / N) rounded up × T" (ceil(M / N)*T) time units. Even with a fully parallelizable problem, the remainder M mod N (M mod N, or M%N in C language) will determine the utilization of computational resources during the execution of the tail (also simply called the tail). If M%N is 0, there is 100% utilization, where all subtasks complete simultaneously and no core's processing power is wasted. On the other hand, if M%N is 1, only one core is used to process the last subtask, while N-1 cores are idle, waiting for the only remaining subtask to complete. If T and N are large, the waste will be significant. To further complicate the given example, consider that each of the M subtasks does not take the same amount of time. Depending on which subtask is executed first, the tail span (e.g., the time when utilization is below 100% at the end of the simulation process) can vary greatly.

[0053] In practice, OPC and other RET operations can involve simulating the geometric features of a semiconductor manufacturing process using a specific set of models (e.g., optical models and resist models). OPC operations can additionally involve iterative modifications to the geometry involved to produce a “corrected” result. As discussed above, these are typically accomplished by dividing the entire chip area into millions of small regions called tiles, where each tile on a computing cluster typically takes tens of minutes to an hour or two, consisting of hundreds to tens of thousands of cores (or composed of hundreds to tens of thousands of cores). Therefore, given the scheduling problems described above, the unused resources in the execution tail of OPC operations will be significant.

[0054] In a scenario involving scheduling M subtasks, one or more types of scheduling can improve core utilization. As an example, scheduling can be based on estimated times for completing the respective subtasks (e.g., relative estimated times and / or actual estimated times). Specifically, if the amount of computation time for each subtask is known a priori, scheduling in the order of longest-running subtasks (e.g., tasks with relatively long simulated execution times are executed before tasks with shorter simulated execution times) may yield improved or optimal results in terms of core utilization. In this regard, subtasks can be tiered using their estimated times for completion (e.g., tiering the M subtasks), where the tiers are used sequentially to schedule the execution of the M subtasks. This contrasts with scheduling the M subtasks randomly and independently of any estimated completion times.

[0055] In some embodiments, estimates are generated for performing OPC or other RET operations on one, some, or all of the M subtasks. The estimate for the corresponding subtask (e.g., for performing OPC on a specific tile) may be based on one or both of the following: analysis of the specific tile itself (e.g., analysis of one or more aspects of the specific tile to determine a relative time estimate for performing the corresponding subtask for the specific tile); and / or analysis of adjacent, boundary, or nearby tiles (e.g., analysis of the processing times of adjacent tiles to estimate the time for performing the corresponding subtask for the specific tile). As discussed in more detail below, the estimate may include a time estimate of the specific tile relative to other tiles, which can be used to classify the specific tile among the other tiles.

[0056] Analysis of a specific subtask (e.g., analysis of a particular tile) can estimate the complexity required to perform that subtask (e.g., the complexity of the layout design within that tile) in order to subsequently estimate the relative time required to perform that subtask (e.g., a higher complexity in the layout design within a particular tile may be associated with a longer relative time required to perform OPC or other RET operations on that tile). Tiles with higher estimated complexity can then be scheduled to undergo OPC or other RET operations before tiles with lower estimated complexity. One or more factors may contribute to estimating the complexity of performing a specific subtask. Exemplary factors include any or both of the following: the location of the particular tile; or the layout design within the particular tile.

[0057] For example, the position of a particular tile can be relative to a predetermined location (e.g., the geometric center of the layout or the nearest edge of the layout). Specifically, empirically, layouts towards their centers may tend to be more complex than those at their edges. Therefore, one indicator of the complexity of a particular tile (and subsequently its relative OPC processing time) can be its position, such as its position relative to the geometric center of the layout or its position relative to the nearest edge. This position indicator can include the absolute position or the difference between the tile's position and the predetermined location (e.g., the geometric center or the nearest edge of the layout).

[0058] As another example, the analysis of the layout design within a specific tile can also demonstrate its complexity, and then the relative time required to perform OPC or other RET operations on the layout design within the specific tile can be demonstrated. One or more types of analysis can be performed on the corresponding tile to determine the complexity of the corresponding tile, which includes one or both of the following: (1) counting specific metrics within the specific tile; or (2) analyzing the shape within the specific tile.

[0059] Various metrics can be counted, including the number of vertices in the layout design within a particular tile. For example, a tile with a higher number of vertices in its region may indicate a greater estimated density or complexity than another tile with a lower number of vertices in its layout design. At this point, the number of vertices can indicate the density within a particular tile, and therefore its complexity. Other metrics indicating density (separate from vertex density) are also considered. For example, the number of short edges (e.g., edges less than a predetermined length) within a corresponding tile can be counted to indicate the short edge density within that tile. This short edge density can then be used to determine the relative processing time (e.g., a higher short edge density is associated with a longer processing time compared to a lower short edge density). While density may not be strictly monotonically related to the time required to process a particular tile, density can demonstrate the relative time required to process a particular tile.

[0060] Furthermore, analysis of various types of shapes within a specific tile is considered. In some embodiments, the analysis may include identifying certain types of shapes, where the identified shapes indicate the complexity or lack thereof within a specific tile. For example, some shapes may be more difficult to print, resulting in longer OPC processing times. In this respect, identifying specific shapes within a specific tile that are more difficult to print can justify the estimated OPC processing time. Alternatively or additionally, the analysis may include identifying shapes that are related to other shapes, such as identifying the distances between shapes within a specific tile (e.g., the proximity of one shape to another). For example, the analysis may identify critical distances between shapes or sub-features within a specific tile. OPC operations may involve moving one or more shapes within a specific tile while maintaining at least a predetermined distance between the shapes or sub-features. Smaller distances between shapes or sub-features may complicate OPC operations (including complicating the mobility of shapes or sub-features) and may consequently lead to longer OPC operation execution times.

[0061] Alternatively or additionally, tiles adjacent to, bordering, or near a specific tile can be analyzed to estimate the time required for an OPC or other RET operation on that specific tile. As an example, one or more attributes associated with one or more tiles adjacent to, bordering, or near one or more specific tiles can be analyzed to estimate the time required for an OPC or other RET operation on that specific tile. Specifically, either or both of the following attributes can be used: (1) the actual processing time for an OPC or other RET operation on one or more tiles adjacent to, bordering, or near a specific tile; or (2) the complexity of one or more tiles adjacent to, bordering, or near a specific tile.

[0062] Layout design processing can be performed hierarchically, with some blocks being processed before others. As just one example, blocks can have category designations (e.g., "1", "2", "3", "4"), where the order of OPC or other RET processing is based on that category designation (e.g., in a neighboring area, blocks designated "1" are processed first; then blocks in the neighboring area designated "2" are processed; and so on). Assuming that one or more blocks adjacent, bordering, or near a particular block have already been processed, the processing time for those adjacent, bordering, or near the particular block can help estimate the processing time for the particular block. In one instance, a particular block can be designated "2," meaning that one or more blocks bordering the particular block and designated "1" will be processed before that particular block. Therefore, the processing time for one or more blocks bordering the particular block and designated "1" can be used to estimate the processing time for the particular block. In another example, a specific tile can be designated "3," meaning that one or more tiles designated "1" and "2" that intersect with the specific tile will be processed before processing that specific tile. Therefore, the processing time for one or more corresponding tiles designated "1" and "2" that intersect with the specific tile can be used to estimate the processing time for the specific tile designated "3." In yet another example, a specific tile can be designated "4," meaning that one or more tiles designated "1," "2," and "3" that intersect with the specific tile will be processed before processing that specific tile. Therefore, the processing time for one or more corresponding tiles designated "1," "2," and "3" that intersect with the specific tile can be used to estimate the processing time for the specific tile designated "4." In this way, the estimation of processing time can be iteratively based on different categories of tiles that have already been processed.

[0063] Furthermore, as discussed above, one or more factors can be used to estimate the complexity of a given tile. Therefore, the estimated complexity of tiles adjacent to, bordering, or close to a particular tile can also be used to estimate the processing time for that particular tile.

[0064] Return to the attached diagram for reference. Figure 3AA flowchart 300 is shown for scheduling and performing resolution enhancement techniques on multiple tiles in a layout design. As discussed above, the system may include N cores for processing M tiles, where M >> N. Therefore, at 302, the system schedules an initial set of tiles (e.g., N tiles for N cores) using an initial heuristic algorithm to process them using resolution enhancement techniques. As an example, the initial heuristic algorithm may randomly select the initial set of tiles from the entire set of tiles to be processed. As another example, the initial heuristic algorithm may select the initial set of tiles based on a category specification (e.g., based on whether a tile is specified as "1"). Then, at 304, the resolution enhancement techniques are performed on the initial set of tiles.

[0065] At 306, determine if there are any additional tiles to be processed. If not, flowchart 300 ends at 308. If there are additional tiles to be processed, at 310, classify some or all of the tiles that still need to be processed. As discussed above, the classification of a corresponding tile can be based on an analysis of the corresponding tile itself. For example, the complexity of the corresponding tile can be used to classify the tile relative to the complexity of other tiles that still need to be processed. Alternatively or additionally, the classification of a corresponding tile can be based on an analysis of neighboring tiles. For example, tiles adjacent to the corresponding tile may have already been processed. The processing time for neighboring tiles can be averaged (e.g., a neighbor average) so that the corresponding tile can be classified relative to the neighbor average of other tiles.

[0066] In step 312, one or more subsequent tiles are selected for processing based on tile hierarchy. For example, tiles can be hierarchically ranked from longest estimated processing time to shortest estimated processing time, where the tile with the longest estimated processing time is selected (e.g., selecting the N highest-ranking tiles to be processed by N cores). In step 314, resolution enhancement techniques are performed on the selected subsequent tiles. Afterward, flowchart 300 loops back to step 306. In this way, the scheduling of tile processing can be dynamic. Specifically, scheduling priorities can be periodically re-evaluated, where the highest-priority tiles are selected for subsequent processing.

[0067] Figure 3BA flowchart 320 is shown, which is used to estimate the relative processing time of tiles in a layout design based on the analysis of the corresponding tiles. As discussed above, various factors can be considered in classifying the processing time of tiles, including any one, any combination of, or all of the following: the position of the tile in the layout; the density of shapes in the tile; the identified shapes and / or the distances between shapes; or machine learning used to analyze the complexity of the tiles. Therefore, at 322, a determined distance of the corresponding tile relative to a predetermined position (e.g., relative to the geometric center of the layout design or relative to the nearest edge of the layout design) is obtained. Specifically, a location of the corresponding tile closer to the geometric center / farther from the edge of the layout design may indicate a more complex layout within the corresponding tile (and thus an increased estimated simulation time), while a location of the corresponding tile farther from the geometric center / closer to the edge of the layout design may indicate a less complex layout within the corresponding tile (and thus a smaller estimated simulation time compared to a more complex layout).

[0068] As another example, the relative processing time can be graded using the density of certain geometric properties of the layout devices within the corresponding tile (e.g., the density of corner vertices clustered together), where higher density is associated with longer estimated simulation time (e.g., directly or indirectly). Specifically, at 324, an estimate of the shape density of the corresponding tile is obtained.

[0069] As yet another example, the distance between a particular identified shape and / or between shapes can indicate the complexity within the corresponding tile, and subsequently, the higher the simulation processing time. Therefore, in 326, the distance between one or more identified shapes and / or between shapes within the corresponding tile can be obtained.

[0070] As another example, machine learning can be used to determine the complexity of a corresponding tile. Therefore, at 328, machine learning can be accessed to generate outputs indicating the complexity of the corresponding tile. Generally, machine learning builds a mathematical model based on training data to make predictions. Currently, machine learning can use training data to train a mathematical model configured to output estimates of simulation time. Various inputs to machine learning can be considered, such as any, any combination, or all of the factors disclosed herein, including: parts of the layout design associated with the corresponding tile; the location of the corresponding tile; the estimated density within the corresponding tile; or the identified shapes and / or distances between shapes within the corresponding tile. Other factors are also considered. Machine learning can also output a metric of the complexity of the corresponding tile, which can be used to rank the corresponding tile relative to other tiles, as discussed further below. Furthermore, various types of machine learning are considered, including: supervised learning; unsupervised learning; reinforcement learning; or feature learning.

[0071] At 330, the corresponding tiles are graded relative to each other to schedule RET processing of the tiles. The grading can be based on one, some, or all of the following: determining distance; estimating density; the distance between identified shapes and / or shapes; or machine learning. As an example, for each of the following grading methods—determining distance (e.g., farther from the center results in a lower grade), estimating density (e.g., lower density results in a lower grade), estimating the distance between identified shapes and / or shapes (e.g., closer distances between certain identified shapes or between identified shapes result in a higher grade), and machine learning (e.g., machine learning model output grading)—the tiles can be organized as separate gradings. The gradings can then be combined (e.g., averaged or weighted) to generate an overall grading of the tiles. Specifically, a particular tile may have the following gradings: determining distance: #5005; estimating density: #2101; distance between identified shapes and / or shapes: #902; machine learning: #1404, resulting in an average grading: #2353, which can be used to select a particular tile for processing. As another example, tiles can be ranked based solely on one of the following: determined distance, estimated density, identified shapes and / or distances between shapes, and machine learning. In this way, tiles can be ranked based on relative processing time, such as the highest rank based on the longest relative estimate. This rank can then be used to determine the scheduling / execution priority of the tiles.

[0072] Figure 3C A flowchart 340 is shown for classifying tiles based on analysis of neighboring tiles in order to schedule the execution of resolution enhancement techniques on the tiles. As discussed above, one or more aspects associated with one or more neighboring tiles can be used to classify the corresponding tiles relative to other tiles. Various aspects can be considered, including one or both of the following: Figure 3BThis refers to any part or all of the analysis disclosed in the report; or one or more actual processing times for one or more adjacent tiles that have already been processed. Therefore, at 342, one or more processing times for one or more adjacent tiles that have already been processed are obtained. As discussed above, a tile may be adjacent to a corresponding tile if it is a boundary, contact, or proximity to the corresponding tile (e.g., a nearby tile, within one tile of the corresponding tile, etc.). At 344, the corresponding tile is classified using one or more of the obtained simulation times for one or more adjacent tiles. In the example discussed above where the tile has a category designation (e.g., "1", "2", "3", "4"), the category designated as associated with the corresponding tile can be obtained first. Subsequently, simulation times for tiles adjacent to the corresponding tile with a specific designation (e.g., less than the designated number of the corresponding tile) can be obtained. One, some, or all of the obtained simulation times for the tiles can then be used to determine the estimated simulation time for the corresponding tile. As discussed below... Figures 4 to 5 The acquired simulation times can be mathematically combined to generate estimated simulation times for corresponding tiles. Examples of mathematical combinations include, but are not limited to: normalization; weighting; averaging; or other methods. Furthermore, other mathematical combinations of the acquired simulation times are considered. For example, in a specific neighborhood region, a tile designated as "1" is processed before a tile designated as "2". In classifying the "2" tile in a specific neighborhood region, the processing time for the tile designated as "1" in the neighborhood region of the tile designated as "2" can be used to classify the tile designated as "2", as discussed further below.

[0073] Figure 4 A flowchart 400 is shown, which is used to iteratively classify the estimated time for a tile based on the actual simulation time for tiles in the tile's neighboring region. Figure 5 An exemplary layout 500 for tile coloring using OPC is shown, where the tile coloring is specified as "1", "2", "3", "4". Although Figure 5 The tiles are shown as designated "1", "2", "3", and "4", but other names can also be considered. In this regard, different orders of processing the tiles should also be considered.

[0074] At 402, select the corresponding tile for the second category. As discussed above, tiles can be assigned categories, for example, designated as "1" for the first category and "2" for the second category. As an example, the corresponding tile could be at 510, such as... Figure 5As shown. At 404, one or more actual simulation times for first-category tiles adjacent to the corresponding tiles of the second category can be obtained. For example, simulation times for one or both of tiles "1" at 520 and 522 can be obtained. At 406, estimated simulation times for the corresponding tiles of the second category are generated using the obtained one or more actual simulation times for the one or more first-category tiles. As an example, the simulation times for the two tiles "1" at 520 and 522 can be averaged. As another example, the simulation times for the two tiles "1" at 520 and 522 can be weighted unevenly (e.g., tile "1" closer to the geometric center (at 522) can be weighted more than tile "1" farther from the geometric center (at 520), or vice versa).

[0075] At 408, determine if there are other tiles in the second category. If yes, flowchart 400 loops back to 402 to select the next tile of that category as the appropriate tile. If no, flowchart loops to 410, where it is determined if there are additional categories in the neighboring region of the appropriate tile. If no, flowchart 400 ends at 412. If yes (e.g., if there are tiles of category "3" or category "4"), flowchart 400 moves to 414. At 414, select the next category as the current category. For example, the next category could be a tile designated as "3", such as tile 530. At 416, a tile with the current category can be selected as the appropriate tile. At 418, obtain one or more simulation times for one or more tiles in the neighboring region of the appropriate tile. For example, simulation times can be acquired for one or both of tile "1" at locations 520 and 544, and simulation times can be acquired for one, some, or all of tile "2" at locations 510, 540, 542, and 546. At 420, an estimated simulation time for the corresponding tile is generated using one or more of the acquired simulation times. As an example, all acquired simulation times can be averaged. As another example, the acquired simulation times can be weighted, for example, based on the amounts of neighboring tiles that intersect with the corresponding tile. Figure 5 As shown, tile 530 has tiles 510, 520, 540, 542, 544, and 546 that intersect with it and in which simulations have been performed. Furthermore, as... Figure 5As shown, tiles 520 and 544, designated as "1", share a common edge with tile 530, while tiles 510, 540, 542, and 546, designated as "2", share a common corner. In this respect, tiles 520 and 544, designated as "1", share a larger common perimeter than tiles 510, 540, 542, and 546, designated as "2". Therefore, in one embodiment, the simulation time obtained for tiles sharing a larger common perimeter can be given a higher weight than the simulation time obtained for tiles sharing a smaller common area. Similar to the simulation of the tile designated as "3", the estimation of the tile designated as "4" (e.g., tile 550) can be performed in the same way by using the simulation time of neighboring tiles (e.g., tiles designated as "1" at 520, 522, 544, 554, tiles designated as "2" at 510, 546, and tiles designated as "3" at 530, 552).

[0076] At 422, determine if there are other tiles of the current category. If yes, flowchart 400 loops back to 416 to select the next tile of that category as the appropriate tile. If no, flowchart loops back to 410, where it is determined whether there are any additional categories in the neighboring area of ​​the appropriate tile.

[0077] As discussed above, Figure 5 The specified tiles are shown, such that the tiles will be processed in 4 separate batches. Any division of processing into two or more categories or batches (e.g., dividing tiles into 2, 3, 5 or more categories) allows the use of previous simulation times to estimate subsequent simulation times.

[0078] The following exemplary embodiments of the present invention are also disclosed:

[0079] Example 1:

[0080] A method executed by at least one processor of a computer, comprising:

[0081] Receive layout design, which is divided into regions;

[0082] Estimate the response time for performing resolution enhancement techniques (RET) on multiple regions;

[0083] The RET is scheduled for the multiple regions based on the estimated response time; and

[0084] The RET is executed on the multiple regions based on the scheduling.

[0085] Example 2:

[0086] According to the method described in Example 1,

[0087] The estimation of the response time for performing RET on multiple regions includes: classifying the multiple regions; and

[0088] The RET for scheduling the multiple regions is based on the hierarchical classification of the multiple regions.

[0089] Example 3:

[0090] According to the method of any one of Examples 1 and 2,

[0091] The region with a longer estimated time for executing the RET is scheduled before the region with a shorter estimated time for executing the RET.

[0092] Example 4:

[0093] According to the method of any one of Examples 1 to 3,

[0094] The plurality of regions include a plurality of map tiles;

[0095] Among them, each of the plurality of blocks has a corresponding estimated time;

[0096] Wherein, the corresponding estimated time is based on the estimated complexity associated with the corresponding tile; and

[0097] Among them, tiles with higher estimation complexity are scheduled to be processed before tiles with lower estimation complexity.

[0098] Example 5:

[0099] According to the method of any one of Examples 1 to 4,

[0100] The plurality of regions include a plurality of map tiles; and

[0101] The estimated complexity associated with the corresponding tile is based on the position of the corresponding tile within the layout design.

[0102] Example 6:

[0103] According to the method of any one of Examples 1 to 5,

[0104] The estimated complexity is based on the difference between the position of the corresponding tile and the predetermined position within the layout design.

[0105] Example 7:

[0106] According to the method described in any one of Examples 1 to 6,

[0107] The predetermined location includes the geometric center of the layout design.

[0108] Example 8:

[0109] According to the method described in any one of Examples 1 to 6,

[0110] The predetermined position includes the nearest edge of the layout design.

[0111] Example 9:

[0112] According to the method of any one of Examples 1 to 8,

[0113] The estimated complexity associated with the corresponding tile is based on the analysis of the layout design within the corresponding tile.

[0114] Example 10:

[0115] According to the method of any one of Examples 1 to 9,

[0116] The analysis of the corresponding blocks includes: the analysis of the estimated density of the layout design within the corresponding blocks.

[0117] Example 11:

[0118] According to the method of any one of Examples 1 to 10,

[0119] The analysis of the estimated density of the layout design within the corresponding tile includes: determining the number of vertices within the corresponding tile used for the layout design; and

[0120] The higher vertex number determined for the layout design within the corresponding tile indicates that the corresponding tile has a greater estimated density compared to another corresponding tile with a lower vertex number.

[0121] Example 12:

[0122] According to the method of any one of Examples 1 to 11,

[0123] The analysis of the estimated density of the layout design within the corresponding tile includes: analyzing one or more shapes of the layout design within the corresponding tile.

[0124] Example 13:

[0125] According to the method of any one of Examples 1 to 12,

[0126] The analysis of one or more shapes of the layout design within the corresponding tile includes: analyzing the proximity between the one or more shapes of the layout design within the corresponding tile.

[0127] Example 14:

[0128] According to the method of any one of Examples 1 to 13,

[0129] The analysis of one or more shapes of the layout design within the corresponding block includes: analyzing the mobility of one or more shapes of the layout design within the corresponding block.

[0130] Example 15:

[0131] According to the method described in any one of Examples 1 to 14,

[0132] The estimated response time for performing RET on the multiple regions is based on machine learning.

[0133] Example 16:

[0134] According to the method of any one of Examples 1 to 15,

[0135] The machine learning includes:

[0136] Identify one or more shapes of the layout design within the corresponding area; and

[0137] The machine learning is used based on one or more shapes of the layout design within the identified corresponding region in order to determine the estimated time for performing the RET on the corresponding region.

[0138] Example 17:

[0139] According to the method of any one of Examples 1 to 16,

[0140] The estimated time for performing RET for the corresponding region is based on the analysis of one or more regions adjacent to the corresponding region.

[0141] Example 18:

[0142] According to the method of any one of Examples 1 to 17,

[0143] The one or more regions adjacent to the corresponding region include the regions that intersect with the corresponding region.

[0144] Example 19:

[0145] According to the method of any one of Examples 1 to 18,

[0146] Specifically, the RET is performed on the region that borders the corresponding region before the RET is performed on the corresponding region; and

[0147] The actual time used to perform the RET on the region that borders the corresponding region is used to estimate the time to perform the RET on the corresponding region.

[0148] Example 20:

[0149] According to the method of any one of Examples 1 to 19,

[0150] The actual time for the region that intersects with the corresponding region is normalized in order to estimate the time for performing the RET on the corresponding region.

[0151] Example 21:

[0152] The method described in any one of Examples 1 to 20,

[0153] The actual time for the regions that intersect with the corresponding regions is averaged to estimate the time required to perform the RET on the corresponding regions.

[0154] Example 22:

[0155] One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform the method according to any one of embodiments 1 to 21.

[0156] Example 23:

[0157] A system comprising one or more processors, said one or more processors being programmed to perform the method according to any one of embodiments 1 to 21.

[0158] The subject matter disclosed above is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of this description. Therefore, to the fullest extent permitted by law, the scope shall be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be construed or limited by the foregoing detailed description.

Claims

1. A method for assigning resolution enhancement technology tasks to a plurality of computer processing units, the method being performed by at least one processor (111, 121) of a computer, comprising: Receive layout design (500), the layout design (500) is divided into regions; Estimate the response time for applying resolution enhancement techniques to multiple regions; The resolution enhancement technology is scheduled for the multiple regions based on the estimated response time. The plurality of regions include a plurality of map tiles; Among these, each of the plurality of blocks has an estimated corresponding time; Wherein, the estimated corresponding time is based on the estimated complexity associated with the corresponding tile; and Among these, tiles with higher estimation complexity are scheduled to be processed before tiles with lower estimation complexity; and Based on the scheduling, the resolution enhancement technology is executed on the multiple regions by the multiple computer processing units.

2. The method according to claim 1, wherein, The multiple regions include multiple map tiles; and The estimated complexity associated with the corresponding tile is based on the position of the corresponding tile within the layout design.

3. The method according to claim 2, wherein, The estimated complexity is based on the difference between the position of the corresponding tile and the predetermined position within the layout design.

4. The method according to claim 3, wherein, The predetermined location includes the geometric center of the layout design.

5. The method according to claim 3, wherein, The predetermined position includes the nearest edge of the layout design.

6. The method according to claim 1, wherein, The estimated complexity associated with the corresponding tile is based on the analysis of the layout design within the corresponding tile.

7. The method according to claim 6, wherein, The analysis of the corresponding blocks includes: the analysis of the estimated density of the layout design within the corresponding blocks.

8. The method according to claim 7, wherein, The analysis of the estimated density of the layout design within the corresponding tile includes: determining the number of vertices used for the layout design within the corresponding tile; and The higher vertex number determined for the layout design within the corresponding tile indicates that the corresponding tile has a greater estimated density compared to another corresponding tile with a lower vertex number.

9. The method according to claim 7, wherein, The analysis of the estimated density of the layout design within the corresponding tile includes: analyzing one or more shapes of the layout design within the corresponding tile.

10. The method according to claim 9, wherein, The analysis of one or more shapes of the layout design within the corresponding tile includes: analyzing the proximity between the one or more shapes of the layout design within the corresponding tile.

11. One or more non-transitory computer-readable media (107, 119) storing computer-executable instructions for causing one or more processors (111, 121) to perform the method according to any one of claims 1 to 10.

12. A system for assigning resolution enhancement technology tasks to a plurality of computer processing units, comprising one or more processors (111, 121) programmed to perform the method according to any one of claims 1 to 10.

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