Data recovery management for memory

Abstract

This application relates to data recovery management for memory. A memory device and operating method are described. The memory device may include NAND memory. The memory device may be configured with a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with an attempt to write data to a memory page in a memory block, the memory device may indicate the error to the host device. The host device may, based on the received error indication, transfer backup copies of the data and other affected data from a circular buffer to the memory device. The memory device may configure the host-side buffer to have at least a specific size based on one or more structural or operational aspects of the memory device.

Description

[0001] Cross-referencing

[0002] This patent application is the national phase application of International Patent Application No. PCT / CN2019 / 113306, filed by Wu on October 25, 2019, entitled “DATA RECOVERY MANAGEMENT FOR MEMORY”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to data recovery management for memory. Background Technology

[0004] The following text generally relates to a system comprising at least one memory device, and more specifically, to data recovery management for the memory.

[0005] The system may include various memory devices and controllers coupled via one or more buses to manage information in various electronic devices, such as computers, wireless communication devices, Internet of Things (IoT) devices, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of memory cells. For example, a binary memory cell can store one of two states, typically indicated by a logic "1" or logic "0". Some memory cells can store more than one of more than two states. To access the stored information, the memory device can read or sense the stored states in the memory cell. To store information, the memory device can write or program states into the memory cell.

[0006] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D Xpoint memory, and flash memory (e.g., floating gate flash devices and charge trap flash devices, which can be used in NOR (NOR) or NAND (NAND) memory devices). Memory devices can be volatile or non-volatile. For example, a non-volatile flash memory cell can maintain its stored logic state for a long time even without an external power supply. A volatile DRAM cell, for example, may lose its stored state over time unless it is periodically refreshed by an external power supply. Flash-based memory devices can offer improved performance compared to some non-volatile and volatile memory devices. Summary of the Invention

[0007] A method is described. The method may include: writing first data to a first memory cell page within a first set of memory cell pages at a memory device; receiving a write command for second data from a host device; attempting to write the second data to a second memory cell page within the first set of pages; identifying an error associated with the attempt to write the second data to the second page within the first set of pages; indicating the error to the host device; after indicating the error, receiving a copy of the first data and a copy of the second data from the host device; and writing the copy of the first data to the first memory cell page within the second set of memory cell pages at the memory device, and writing the copy of the second data to the second memory cell page within the second set of pages.

[0008] Another method is described. The method may include: transferring a first data to a memory device; transferring a second data to the memory device; receiving an indication of an error associated with the second data from the memory device; obtaining a copy of the second data and a copy of the first data from a buffer outside the memory device, at least in part based on the indication of the error; and transferring the copy of the first data and the copy of the second data to the memory device, at least in part based on receiving the indication of the error.

[0009] Describe an apparatus. The apparatus may include: a first set of memory cells; a second set of memory cells; and a controller coupled to the first set of memory cells and the second set of memory cells, the controller being configured to cause the apparatus to: identify an error associated with an attempt to write new data to the first set of memory cells; indicate the error to a host device; receive, at least in part, a copy of the new data and a copy of other data previously written to the first set of memory cells from the host device based on the indication of the error; and write the copy of the new data and the copy of the other data to the second set of memory cells. Attached Figure Description

[0010] Figure 1 This document describes instances of memory devices that support data recovery management for memory, based on the examples disclosed herein.

[0011] Figure 2 This document describes an example of a NAND memory circuit that supports data recovery management for memory, based on the examples disclosed herein.

[0012] Figure 3A and 3B This document describes an example of a system that supports data recovery management for memory, based on the examples disclosed herein.

[0013] Figure 4 This document describes an example of a system that supports data recovery management for memory, based on the examples disclosed herein.

[0014] Figure 5 This document describes an example of a process flow for data recovery management of storage devices, based on the examples disclosed herein.

[0015] Figure 6 This document describes an example of a system that supports data recovery management for memory, based on the examples disclosed herein.

[0016] Figure 7 This document illustrates an example of a block diagram supporting data recovery management for storage, based on the examples disclosed herein.

[0017] Figure 8 This document illustrates an example of a block diagram supporting data recovery management for storage, based on the examples disclosed herein.

[0018] Figure 9 and 10 The flowchart illustrates one or more methods for data recovery management of memory, based on the examples disclosed herein. Detailed Implementation

[0019] Some memory cells can each store one of two or more logical states. For example, a single-level memory cell (SLC) can store one of two logical states, and a multi-level memory cell can store one of three or more logical states. In some cases, each SLC can store a single bit of information that can be contained in a single page of data. In other cases, each multi-level cell can store multiple bits of information, and each bit can be contained in different data pages. For example, the first bit of information stored in a multi-level cell can be contained in a lower data page, and the second bit of information stored in the same multi-level cell can be contained in an upper data page.

[0020] For example, some memory cells, such as flash memory cells, can store logical states by storing amounts of charge that represent logical states. For instance, SLC can be programmed by storing amounts of charge above or below a threshold indicating a first or second logical state. In some memory architectures, such as 3D NAND flash memory, a failed write operation on an SLC cell can corrupt data stored by one or more other SLC cells in the same block, thereby increasing the severity of the failure.

[0021] Some multilevel flash memory cells can be programmed (e.g., written) to appropriate logic states using multiple "passes," where each pass adds an amount of charge stored in some of the memory cells (depending on the logic state to be stored in each memory cell) until the amount of stored charge reaches a level representing the desired logic state. For a multilevel cell, the first pass places a first amount of charge on a memory cell having a first bit included in the lower page, and the second pass places additional charge on a memory cell having a second bit included in the upper page.

[0022] In some cases, a failed write operation to one page of data (e.g., the top page) can corrupt data stored on another page (e.g., the bottom page). For example, a failed second write operation to a multi-level cell in the top page can corrupt data previously stored in the first pass in a bottom page containing the same cell.

[0023] Write failures to memory cells can be particularly problematic in high-reliability systems, such as automotive or other safety-critical systems. Therefore, in some cases, memory systems can maintain a local backup copy of the stored information in the event of a write failure (e.g., by keeping a copy of the data in random access memory (RAM) within the memory device or in another storage bank of SLC memory). In this case, the memory device may be able to restore the correct logical state to the affected memory cell. This approach can have disadvantages, such as higher cost, slower write speeds, and higher write amplification (e.g., additional unnecessary writes that can reduce the lifetime of the memory device). Furthermore, the internal RAM within the memory device can be extremely limited, at least relative to the amount that can be allocated to maintain a backup copy of the data.

[0024] To address these or other drawbacks, as described herein, a memory device may be configured to (e.g., an external microprocessor) maintain a circular buffer (at the host device) to retain a copy of recently written data in the event of a write failure at the memory device. In this case, the memory device may notify the host device of a write failure in a memory block, receive backup data from the circular buffer maintained by the host device, and rewrite the received backup data to a different memory block. In some cases, the memory device may determine the size of the circular buffer based on the maximum amount of data that may be corrupted by a failed write operation, and possibly other factors, and may indicate the size of the circular buffer to the host device.

[0025] Initially, as referenced Figure 1 and 2 Features of this disclosure are described in the context of the memory devices and memory circuits described herein. Further details are provided by reference to [reference needed]. Figure 3A-10 The system diagrams, process flows, and flowcharts described herein illustrate and describe these and other features of this disclosure with reference to the system diagrams, process flows, and flowcharts for data recovery management of memory.

[0026] Figure 1 This describes an example of a memory device 100 according to the examples disclosed herein. In some cases, the memory device 100 may be referred to as a memory chip, a memory die, or an electronic memory device. The memory device 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells not labeled). Memory cell 105 may be, for example, a flash memory cell (e.g., in...). Figure 1 (as shown in the enlarged view of memory cell 105-a), DRAM memory cell, FeRAM memory cell, PCM memory cell, or another type of memory cell.

[0027] Each memory cell 105 can be programmed to store logical states representing one or more information bits. In some cases, memory cell 105 can store one information bit at a time (e.g., logical state 0 or logical state 1), for example, in a memory cell of an SLC memory block that may be referred to as an SLC memory cell. In some cases, a single memory cell 105 can store more than one bit of information at a time, for example, in a multilevel cell (MLC), three-level cell (TLC), or four-level cell (QLC). For example, a single MLC memory cell 105 can store two information bits at a time by storing one of four logical states: logical state 00, logical state 01, logical state 10, or logical state 11. For example, a single TLC memory cell 105 can store three information bits at a time by storing one of eight logical states: 000, 001, 010, 011, 100, 101, 110, 111. Furthermore, as another example, a single QLC memory cell 105 can store four information bits at a time by storing one of sixteen logic states.

[0028] In some cases, the multilevel memory cell 105 (e.g., MLC memory cell, TLC memory cell, or QLC memory cell) may be physically different from the SLC cell. For example, the multilevel memory cell 105 may use different cell geometries or be manufactured using different materials. In some cases, the multilevel memory cell 105 may be physically identical or similar to the SLC cell, and other circuitry in the memory block (e.g., controller circuitry, sense amplifiers, drivers, etc.) may be configured to operate (e.g., read and write) the memory cell as an SLC cell, MLC cell, TLC cell, etc.

[0029] Different memory cell architectures can store logical states in different ways. In a FeRAM architecture, for example, each memory cell 105 may include a capacitor containing ferroelectric material for storing charges and / or polarizations representing programmable states. In a DRAM architecture, each memory cell 105 may include a capacitor containing dielectric material (e.g., an insulator) to store charges representing programmable states.

[0030] In a flash memory architecture, each memory cell 105 may include a transistor having a floating gate and / or dielectric material for storing charges representing logic states. For example, Figure 1An enlarged view of memory cell 105-a shows a flash memory cell containing a transistor 110 (e.g., a metal-oxide-semiconductor (MOS) transistor) for storing logic states. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric materials 125. Transistor 110 includes a first node 130 (e.g., a source or drain) and a second node 135 (e.g., a drain or source). Logic states can be stored in transistor 110 by placing (e.g., writing, storing) a certain number of electrons (e.g., charge) on the floating gate 120. The amount of charge to be stored on the floating gate 120 may depend on the logic state to be stored. The charge stored on the floating gate 120 can affect the threshold voltage of transistor 110, and consequently affect the amount of current that can flow through transistor 110 when transistor 110 is activated. The logic state stored in the transistor 110 can be read by applying a voltage to the control gate 115 (e.g., at the control node 140) to activate the transistor 110 and measuring (e.g., detecting, sensing) the resulting amount of current flowing between the first node 130 and the second node 135.

[0031] For example, sensing component 170 can determine whether an SLC memory cell stores logic state 0 or logic state 1 in binary form; for example, based on the presence or absence of current from the memory cell, or based on whether the current is above or below a threshold current. However, for multi-level cells, sensing component 170 can determine the logic state stored in the memory cell based on various intermediate current levels. For example, sensing component 170 can determine the logic state of a TLC cell based on eight different current levels (or current ranges) that define eight possible logic states that can be stored by a TLC cell. The spacing between such current levels can be quite small (in terms of magnitude), thus providing a lower error tolerance compared to the SLC case.

[0032] Similarly, flash SLC memory cells can be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) charge representing one of two possible logic states on the floating gate. In contrast, writing to flash multilevel cells requires applying voltage at a finer granularity (and possibly in multiple passes) to more precisely control the amount of charge stored on the floating gate, thereby enabling the representation of a larger set of logic states.

[0033] A charge-trapping flash memory cell can operate similarly to a floating-gate flash memory cell, but instead of storing charge on the floating gate 120, the charge-trapping flash memory cell can store state-indicating charge in a dielectric material below the control gate 115. Therefore, a charge-trapping flash memory cell may or may not include the floating gate 120.

[0034] In some instances, each row of memory cells 105 may be connected to word lines 160, and each column of memory cells 105 may be connected to digital lines 165. Therefore, a memory cell 105 may be located at the intersection of word lines 160 and digital lines 165. This intersection may be referred to as the address of the memory cell. Digital lines are sometimes referred to as bit lines. In some cases, word lines 160 and digital lines 165 may be substantially perpendicular to each other and may create a memory cell array 105. In some cases, word lines 160 and digital lines 165 may generally be referred to as access lines or select lines.

[0035] In some cases, memory device 100 may include a three-dimensional (3D) memory array, wherein two-dimensional (2D) memory arrays are formed one on top of the other. Compared to a 2D array, this can increase the number of memory cells that can be placed or generated on a single die or substrate, which in turn can reduce manufacturing costs, or increase the performance of the memory array, or both. Figure 1 In some instances, memory device 100 comprises a multi-level memory array. In some instances, the levels may be separated by an electrically insulating material. Each level may be aligned or positioned such that memory cells 105 are aligned (precisely, overlapping, or approximately) with each other on each level, thereby forming a memory cell stack 175. In some cases, the memory cell stack 175 may be referred to as a memory cell string, see reference... Figure 2 A more detailed discussion follows.

[0036] Access to memory cell 105 can be controlled via row decoder 145 and column decoder 150. For example, row decoder 145 receives a row address from memory controller 155 and activates the appropriate word line 160 based on the received row address. Similarly, column decoder 150 receives a column address from memory controller 155 and activates the appropriate digital line 165. Thus, a memory cell 105 can be accessed by activating one word line 160 and one digital line 165.

[0037] After access, memory cell 105 can be read or sensed by sensing component 170. For example, sensing component 170 can be configured to determine the stored logic state of memory cell 105 based on a signal generated by accessing memory cell 105. The signal can include voltage or current or both, and sensing component 170 can include a voltage-sensing amplifier, a current-sensing amplifier, or both. For example, current or voltage can be applied to memory cell 105 (using corresponding word line 160 and / or digital line 165), and the magnitude of the resulting current or voltage on digital line 165 can depend on the logic state stored by memory cell 105. For example, for flash memory cells, the amount of charge stored on the floating gate or in the insulating layer of the transistors in memory cell 105 can affect the threshold voltage of the transistors, thereby affecting the amount of current flowing through the transistors in memory cell 105 when memory cell 105 is accessed. Such differences in current can be used to determine the logic state stored in memory cell 105.

[0038] Sensing component 170 may include various transistors or amplifiers to detect and amplify signals (e.g., current or voltage) on digital line 165. The detected logic state of memory cell 105 may then be output via input / output block 180. In some cases, sensing component 170 may be part of column decoder 150 or row decoder 145, or sensing component 170 may be otherwise connected to or in electronic communication with column decoder 150 or row decoder 145.

[0039] Memory cell 105 can be set or written by similarly activating the associated word line 160 and digital line 165, enabling the storage of logical states (e.g., representing one or more information bits) in memory cell 105. Column decoder 150 or row decoder 145 can, for example, accept data to be written to memory cell 105 from input / output block 180. As previously discussed, in the case of flash memory (e.g., flash memory used in NAND and 3D NAND memory devices), memory cell 105 is written by storing electrons in a floating gate or insulating layer.

[0040] The memory controller 155 can control the operation of the memory cell 105 (e.g., read, write, rewrite, refresh, etc.) through various components such as the row decoder 145, column decoder 150, and sensing component 170. In some cases, one or more of the row decoder 145, column decoder 150, and sensing component 170 may co-address with the memory controller 155. The memory controller 155 can generate row address signals and column address signals to activate the desired word line 160 and digital line 165. The memory controller 155 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0041] In some cases, the memory controller 155 may write first data to a first memory cell page within a first set of memory cell pages at the memory device. The memory controller 155 may receive a write command for second data from the host device and attempt to write the second data to a second memory cell page within the first set of pages. The memory controller 155 may identify an error associated with the attempt to write the second data to the second page within the first set of pages and indicate the error to the host device. After indicating the error, the memory controller 155 may receive a copy of the first data and a copy of the second data from the host device, and write the copy of the first data to the first memory cell page within the second set of memory cell pages at the memory device, and write the copy of the second data to the second memory cell page within the second set of pages.

[0042] Figure 2 This description illustrates an example of a NAND memory circuit 200 supporting data recovery management for memory, according to an embodiment of this disclosure. The NAND memory circuit 200 may be an example of a portion of a memory device (e.g., memory device 100). Although Figure 2 Some of the elements included are labeled with reference numerals, while other corresponding elements are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features.

[0043] NAND memory circuitry 200 includes a plurality of flash memory cells 205 connected in a NAND configuration (which may be, for example, referenced to...). Figure 1 (The described flash memory cell). In a NAND memory configuration (referred to as NAND memory), multiple flash memory cells 205 are connected in series to form a string 210 of memory cells 205, wherein the drain of each flash memory cell 205 in the string 210 is coupled to the source of another flash memory cell 205 in the string. In some cases, flash memory cells connected in a NAND configuration to form NAND memory may be referred to as NAND memory cells.

[0044] Each string 210 of memory cells 205 may be associated with a corresponding digital line 215 shared by the memory cells 205 in the string 210. Each memory cell 205 in the string 210 may be associated with a separate word line 230 (e.g., word lines 230-a, 230-i, 230-n) such that the number of word lines 230 may be equal to the number of memory cells 205 in the string 210.

[0045] Generally, NAND flash memory can be hierarchically organized into strings 210 containing multiple memory cells 205, pages containing multiple strings 210, and blocks containing multiple pages. In some cases, NAND flash memory can be written to and read at the page granularity level, but cannot be erased at the page granularity level. For example, NAND flash memory can actually be erased at a higher granularity level, such as the block granularity level. In some cases, NAND flash memory cells may need to be erased before they can be rewritten. Different memory devices may have different read / write / erase characteristics.

[0046] In some cases, a single memory cell 205 may be contained within a single page. In other cases, a single memory cell 205 may be contained within two or more pages. For example, a multi-level cell configured to store two bits may be contained within two pages, with each bit contained in a different page.

[0047] Each string 210 of memory cells 205 in the NAND memory circuit 200 is coupled at one end to a drain-side selected gate (SGD) transistor 220 and at the other end to a source-side selected gate (SGS) transistor 225. The SGD transistor 220 and the SGS transistor 225 can be used to couple the string 210 of memory cells 205 to bitline 215 and / or source node 250 by applying voltages at the gate 245 of the SGD transistor 225 and / or the gate 240 of the SGS transistor 225, respectively.

[0048] During NAND memory operation, various voltage levels associated with source node 250, gate 240 of SGS transistor 225 associated with source node 250, word line 230, drain node 235, gate 245 of SGD transistor 220 associated with drain node 235, and bit line 215 may be applied to perform one or more operations (e.g., programming, erasing, or reading) on ​​at least some of the NAND memory cells in string 210.

[0049] In some cases, during a first operation (e.g., a read operation), a positive voltage may be applied to bit line 215 connected to drain node 235, while source node 250 may be connected to ground or dummy ground (e.g., approximately 0V). For example, the voltage applied to drain node 235 may be 1V. Simultaneously, the voltage applied to gates 245 and 240 may be increased to a threshold voltage higher than one or more SGS 225s associated with source node 250 and one or more SGD 220s associated with drain node 235, such that the channel associated with memory string 210 is electrically connected to drain node 235 and source node 250. The channel may be an electrical path through memory cells 205 in string 210 (e.g., through transistors in memory cells 205), which may conduct current under certain operating conditions.

[0050] Simultaneously, multiple word lines 160 (e.g., in some cases all word lines 160) other than the selected word line (i.e., the word line associated with the unselected cell in string 210) can be connected to a voltage (e.g., VREAD) higher than the highest threshold voltage (VT) of the memory cell in string 210. VREAD can "turn on" all unselected memory cells in string 210, allowing each unselected memory cell to maintain high conductivity in its associated channel. In some instances, the word line 160 associated with the selected cell can be connected to a voltage VTarget. VTarget can be selected as a value between the VT of the erased memory cell and the VT of the programmed memory cell in string 210. When the selected memory cell exhibits an erased VT (e.g., VTarget > VT of the selected memory cell), the selected memory cell 205 can be "turned on" in response to the application of VTarget, and thus allow current to flow from bit line 215 to source 250 in the channel of string 210. When the selected memory cell exhibits a programmed VT (e.g., therefore VTarget < VT of the selected memory cell), the selected memory cell can be "disconnected" in response to VTarget, and thus current is prevented from flowing from bit line 215 to source 250 in the channel of memory string 210. The current amount (or lack thereof) can be determined by reference... Figure 1 The described sensing component 170 senses to read the stored information in the selected memory cell 205 within the string 210.

[0051] Figure 3A and 3BThis document describes an example of a system 300 supporting data recovery management for memory, based on the examples disclosed herein, and depicts the data flow of the system 300 associated with two consecutive write operations (shown as 300-a and 300-b). The system 300 includes a host device 305 and a memory device 310 that can communicate with each other via a bus 315. The memory device 310 may be a reference. Figure 1 Examples of the described memory device 100. In some cases, memory device 310 may be a managed memory device containing flash memory cells. For example, memory device 310 may be a managed NAND memory device containing flash memory cells arranged in a NAND configuration, such as... Figure 2 The memory circuit 200 is depicted. In some cases, the flash memory cells in the memory device 310 may include SLC memory cells and / or multi-level memory cells, such as MLC memory cells, TLC memory cells, or QLC memory cells.

[0052] Memory device 310 includes an internal buffer 320, which may be a local buffer at memory device 310 (e.g., a buffer located in the same package and / or on the same die as the memory cell of memory device 310). In some cases, internal buffer 320 may represent a portion of a larger internal buffer at memory device 310, and internal buffer 320 may be a portion allocated by memory device 310 for buffering data received from host device 305 for writing to memory block 325. In some cases, internal buffer 320 may include RAM cells (e.g., static RAM (SRAM) cells); that is, internal buffer 320 may be a RAM buffer (or a portion of a RAM buffer).

[0053] Before writing data to memory block 325, for example, by transferring data on bus 335, memory device 310 may temporarily store (e.g., buffer) data received from host device 305 in internal buffer 320. In some cases, internal buffer 320 may operate as a reciprocating buffer during write operations to memory device 310. The reciprocating buffer may function similarly to a two-entry circular buffer, wherein new entries are written to internal buffer 320 in alternating positions. Internal buffer 320 may be used by memory device 310 to overlap or pipelining input / output (I / O) operations and memory access operations to improve the speed of memory device 310, since an entry can be read from internal buffer 320 while an entry is being written to internal buffer 320.

[0054] Memory device 310 includes a plurality of memory blocks 325-a and 325-b. In some cases, memory block 325 may contain flash memory cells arranged in a NAND configuration, which may be referred to as a NAND memory block. Each memory block 325 may contain a set of pages of memory (e.g., pages 330-a, 330-b, 330-c, 330-d).

[0055] In some cases, page 330 may contain a single-level memory cell, a multi-level memory cell, or both. As previously described, a single multi-level flash memory cell (e.g., a multi-level flash memory cell) may be contained in multiple pages 330, for example, when each bit of the multi-level flash memory cell is contained in different pages. That is, page 330 may represent a logical partition rather than a physical partition. In some cases, because NAND memory can be written to at the page granularity, an error in a single memory cell of a page can lead to the need to rewrite the entire page.

[0056] In some cases, memory device 310 may write first data to a first page of memory and second data to a second page of memory, wherein one or more memory cells in the first page are also contained in the second page. In some cases, a double-pass write operation for writing data to a multi-level flash memory cell may write two pages of data, namely a lower page (which may be written during the first pass) and an upper page (which may be written after the first pass, during the second pass). Therefore, the multi-level cell can be programmed in two (or more) passes.

[0057] In some cases, host device 305 may recognize data 340 to be written to memory device 310 (e.g., Data1 340-a, Data2 340-b, etc.) and may send (e.g., transfer) a write command to memory device 310 to write data 340 to memory cells of memory device 310. As described in more detail herein, in some cases, host device 305 may also store a temporary backup copy of data 340 in a circular buffer 345 of host device 305.

[0058] For example, as depicted in system 300-a, host device 305 can recognize Data1 340-a for writing to memory device 310. Host device 305 can save (e.g., write) a backup copy of Data1 340-a to the first entry of circular buffer 345, and can (e.g., simultaneously) transmit a write command containing Data1 340-a (e.g., via bus 315) to memory device 310. In response to receiving the write command, memory device 310 can write Data1 to block 325-a by saving Data1 340-a in the first entry of internal buffer 320 and subsequently writing Data1 340-a (e.g., from the first entry of internal buffer 320) to the first page 330-a of block 325-a. In some cases, after the initialization of the memory device 310 (e.g., the start of a new power cycle for the memory device 310), the memory device 310 may write the data associated with the first write command only to completely empty blocks 325, and may prevent any additional data from being written to any blocks 325 that were partially programmed during a transient power cycle, so as to avoid affecting any data programmed during the last power cycle.

[0059] Similarly, as depicted in system 300-b, host device 305 may subsequently identify Data2 340-b for writing to memory device 310. Host device 305 may save (e.g., write) a backup copy of Data2 340-b in a second entry of circular buffer 345 (which may be, for example, an entry consecutive to the entry that saved Data1). Host device 305 may transmit a write command containing Data2 340-b to memory device 310. In response to receiving the write command, memory device 310 may write Data2 340-b to block 325-a by saving Data2 340-b in a second entry of internal buffer 320 and subsequently writing Data2 340-b to the second page 330-b of block 325-a.

[0060] In some cases, if memory device 310 determines that a write error has occurred while memory device 310 is attempting to write data 340 to memory cell page 330 in block 325, memory device 310 may indicate the error to host device 305, for example, by sending an error indication to host device 305 via bus 315. Host device 305 may, based on the received error indication, send some or all of the data from circular buffer 345 (e.g., copies of Data1 340-a, Data2 340-b, and / or other data) to memory device 310, for example, by sending a write command for some or all of the data from circular buffer 345. Memory device 310 may then write (e.g., rewrite) a copy of the data received from host device 305 to another block 325 of memory (e.g., memory block 325-b).

[0061] In some cases, the size of the loop buffer 345 (e.g., the number of entries in the loop buffer 345) may be determined by the memory device 310 and indicated by the memory device 310 to the host device 305.

[0062] In some cases, memory device 310 may determine the size of circular buffer 345 based at least in part on the maximum amount of data (e.g., the maximum number of pages) that could potentially be corrupted during a write operation and therefore need to be rewritten by memory device 310. For example, for a two-pass write operation of a memory cell, if a write error occurs during the first pass (e.g., when memory device 310 is attempting to write the lower page), the upper page may not be corrupted. However, if a write error occurs during the second pass (e.g., when memory device 310 is attempting to write the upper page), both the upper and lower pages may be corrupted because the same memory cell may be contained in two pages. Therefore, the size may be based on the maximum number (quantity) of pages that may be affected by a write error, or on the capacity of several memory cells (e.g., the memory cells contained in the potentially affected pages).

[0063] Additionally, during or after a write error, memory device 310 may continue to receive new data from host device 305, which is stored in internal buffer 320 when it is ready to be written to memory block 325. If memory device 310 is unable to write the data in internal buffer 320 to memory block 325 after a write error, the data stored in internal buffer 320 may be lost. Therefore, in some cases, memory device 310 may include the size of internal buffer 320 (e.g., capacity in terms of pages or bytes) when determining the size of circular buffer 345. That is, memory device 310 may also determine the size of circular buffer 345 at least in part based on the size of internal buffer 320, for example, such that the size of circular buffer 345 is not less than the number of pages that can be corrupted (e.g., affected) by a write error in page 330 multiplied by the page size and added to the size of internal buffer 320.

[0064] In some cases, if the host device 305 receives an error indication from the memory device 310, the host device 305 may send all data from the circular buffer 345 to the memory device 310, and the memory device 310 may write (e.g., rewrite) all data received from the host device 305 to another block 325 of the memory.

[0065] However, in some cases, it may not be necessary to rewrite all data in the circular buffer 345 to the memory device 310, for example, when some data in the circular buffer 345 is written to a page of the memory device 310 that may not be affected by a write error. In this case, resending and rewriting all data from the circular buffer 345 could introduce unnecessary overhead.

[0066] Furthermore, flash memory cells can support a limited number of write cycles during their lifetime, after which they can no longer reliably store logical states. Therefore, it may be necessary to reduce the amount of unnecessary write operations performed on memory cells and avoid rewriting all data in the circular buffer 345 if only some data may be corrupted.

[0067] To minimize unnecessary data rewriting, in some cases, memory device 310 may include in the error indication an indication of the address (e.g., logical block address (LBA)) of the page associated with the write error and an indication of the size of the write error (e.g., error size). For example, memory device 310 may include the address of the page where the write error occurred, and an indication of the number of pages that may need to be rewritten to memory device 305 due to the write error (or an indication of the cumulative size of the data written to the pages). Host device 305 may then send a portion (e.g., a subset) of the data stored in circular buffer 345 to memory device 310 for rewriting based on the address and size indication. Therefore, in some cases, depending on the error size indicated by memory device 305, host device 305 may or may not send all data in circular buffer 345 to memory device 305 for rewriting.

[0068] In some cases, a page that is affected or may be affected by a subsequent write error occurring on another page (e.g., a page whose operation may be affected by a subsequent write error on another page) may contain a page that shares one or more memory units with the page where the write error occurred, or an intermediate page between the page where the write error occurred and other pages that may have been corrupted by the write error.

[0069] refer to Figure 4 and 5 Examples of the operation of memory device 310 and host device 305 when a write error occurs are described in more detail.

[0070] Figure 4 This document describes an instance of system 400 that supports data recovery management for storage, based on the examples disclosed herein. System 400 may be used as a reference. Figure 3A and 3B Examples of system 300 discussed (e.g., as shown in systems 300-a and 300-b) and the operation of system 400 may be described after a write error is detected.

[0071] In system 400, host device 305 may have written Data1 340-a, Data2 340-b, Data3 340-c, and Data4 340-d to circular buffer 345, and may have transmitted a write command to memory device 310, causing memory device 310 to write the same data to block 325-a. Memory device 310 may have successfully written Data1 340-a, Data2 340-b, and Data3 340-c to pages 330-a, 330-b, and 330-c, respectively, but may have encountered a write error when attempting to write Data4 340-d to page 330-d. In this example, the write error associated with page 330-d may also involve corrupted pages 330-a and 330-b, but not page 330-c.

[0072] After determining that a write error has occurred at page 330-d, the memory device may indicate the error to the host device 305 (e.g., by sending an error indication). The error indication may include the address of page 330-d and the size of the error. The size of the error may include, for example, the cumulative size of the pages affected by the error (e.g., pages 330-b, 330-c, and 330-d) and any intermediate pages (e.g., page 330-c). That is, the memory device 310 may determine the size of the error based on the span of pages from the page where the write error occurred (page 330-d) to the earliest corrupted page (page 330-a). Alternatively or additionally, the error indication may include the address of each page for which data needs to be replaced (e.g., the addresses of pages 330-a, 330-b, 330-c, and 330-d), and may or may not include the size of each such page.

[0073] The host device 305 can receive an error indication and can transfer copies of Data1 340-a, Data2 340-b, Data3 340-c, and Data4 340-d to the memory device 310 based on the error indication (e.g., based on address and size). For example, the host device 305 can send one or more write commands containing one or more of Data1 340-a, Data2 340-b, Data3 340-c, and Data4 340-d to the memory device 310.

[0074] Memory device 310 can rewrite Data1 340-a, Data2 340-b, Data3 340-c, and Data4 340-d to pages 330-e, 330-f, 330-g, and 330-h of block 325-b, respectively. In some cases, memory device 310 can rewrite data by using internal buffer 320 as a reciprocating buffer, and rewrite each of Data1 340-a, Data2 340-b, Data3 340-c, and Data4 340-d from internal buffer 320 to block 325-b. In some cases, block 325-b can be a memory block previously erased by memory device 310 and therefore available for writing.

[0075] Figure 5 This document describes a process flow 500 supporting data recovery management for memory, based on examples disclosed herein. Process flow 500 can be executed by a host device 505 and a memory device 510, which may be referenced... Figure 3A , 3B Examples of host device 305 and memory device 310 described in section 4.

[0076] At 515, memory device 510 may determine the size of the buffer that host device 505 will maintain. In some cases, memory device 510 may determine the buffer size based on the maximum number of pages whose operation can be affected by write operations of memory device 510. In some cases, memory device 510 may further determine the buffer size based on internal buffers of memory device 510 (e.g., reference...). Figure 3A and Figure 3B The size of the buffer is determined by the size of the internal buffer 320 described.

[0077] At 520, memory device 510 may transmit an indication of the buffer size to host device 505. In some cases, memory device 510 may transmit the indication of the buffer size during an initialization procedure (e.g., in response to receiving an initialization command or in response to power-on). In some cases, host device 505 may then initialize (e.g., configure, set) a circular buffer having the indicated buffer size.

[0078] At 525, the host device 505 can identify data to be written to the memory device 510, and can transfer the data to the memory device 510, for example, by transmitting a write command containing the data.

[0079] At 530, host device 505 can store a copy of the data in a circular buffer.

[0080] At 535, memory device 510 may store data in an internal buffer (e.g., a reciprocating buffer) of memory device 510 in preparation for writing data to a memory page.

[0081] At 540, memory device 510 can write data to a page of memory device 510.

[0082] Operations 525, 530, 535, and 540 can be repeated as host device 505 continues to identify new data to be written to memory device 510.

[0083] At 545, memory device 510 may attempt to write data to a page and may determine that a write error has occurred.

[0084] At 550, memory device 510 can identify the address and size associated with the write error and can transmit the address and size indication to host device 505. For example, the address may be the address of a page in the block where the write error occurred, and the size may be, for example, the number of pages, the cumulative size of several pages, or the amount of data that may need to be rewritten due to (e.g., based on) the write error.

[0085] At 555, the host device can receive the address and size, and can send some or all of the data in the circular buffer to the memory device 510.

[0086] At 560, memory device 510 can write data received from host device 505 to one or more pages of different blocks of memory device 510.

[0087] Figure 6 A diagram illustrating a system 600 supporting data recovery management for memory according to an embodiment of the present disclosure is shown. System 600 may include a device 605, which may include a processor 610, a system memory controller 615, and a memory device 620. For example, memory device 620 may be an instance of memory device 100. Processor 610 may be configured to coordinate operation with system memory controller 615 via bus 625. System memory controller 615 may be configured to operate together with processor 610 and memory device 620 via buses 625 and 630.

[0088] In some instances, memory device 620 may include one or more memory arrays 640, each of which may be coupled to a corresponding local memory controller 645. For example, in some cases, memory array 640 may be a NAND memory cell array. In some cases, refer to Figure 3A , 3BThe operations described in points 4 and 5 can be performed by the local memory controller 645 and / or the system memory controller 615. In some cases, the device 605 may be coupled to an external host device 650, such as an external memory controller.

[0089] Local memory controller 645 can be configured to control the operation of memory array 640. Furthermore, local memory controller 645 can be configured to communicate with system memory controller 615 (e.g., to receive and transmit data and / or commands). Local memory controller 645 can support system memory controller 615 in controlling the operation of memory device 620 as described herein. In some cases, memory device 620 does not include system memory controller 615 and local memory controller 645, and host device 650 can perform the various functions described herein. Therefore, local memory controller 645 can be configured to communicate with system memory controller 615, with other local memory controllers 645, or directly with host device 650.

[0090] In some instances, memory device 620 may attempt to write data to a page in a block of memory array 640 and may determine that a write error has occurred. Memory device 620 may indicate the error to host device 650. Host device 650 may, based on the error indication, send a backup copy of the data previously written to one or more pages in a block of memory array 640. Memory device 620 may write copies of the data to one or more pages in different blocks of memory array 640. Host device 650 may maintain a circular buffer for holding backup copies of the data transferred to memory device 620. In some cases, the size of the circular buffer may be indicated to host device 650 by memory device 620.

[0091] Figure 7 A block diagram 700 illustrates a memory device 705 supporting data recovery management for memory according to various aspects of this disclosure. The memory device 705 may be an example of an aspect of the memory device 100 described herein. The memory device 705 may include a write component 710, a command component 715, an error identification component 720, an error indication component 725, and a buffer management component 730. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0092] The write component 710 can write first data to a first memory cell page within a first set of memory cell pages at the memory device. The command component 715 can receive a write command for second data from the host device. In some instances, the write component 710 can attempt to write the second data to a second memory cell page within the first set of pages. The error identification component 720 can identify errors associated with the attempt to write the second data to the second page within the first set of pages. The error indication component 725 can indicate errors to the host device.

[0093] In some instances, command component 715 may receive copies of the first data and the second data from the host device after an error is indicated. In some instances, write component 710 may write a copy of the first data to a first memory page within a second set of memory page units at the memory device, and write a copy of the second data to a second memory page within the second set of page units.

[0094] In some instances, instructing the host device to indicate an error includes specifying the address of the second page and indicating the error size, which represents the number of pages to be rewritten based on the identified error.

[0095] In some instances, the error identification component 720 can determine that the first page is affected by an error. In some instances, the error indication component 725 can determine the size of the error based on the determination that the first page is affected by an error.

[0096] In some instances, the write component 710 may write third data to a third memory cell page within a first set of memory cell pages after writing the first data and before attempting to write the second data, wherein the pages to be rewritten include the first page, the second page, and the third page. In some instances, the write component 710 may receive a copy of the third data from the host device after an error is indicated. In some instances, the write component 710 may write a copy of the third data to a third memory cell page within a second set of pages. In some cases, the third memory cell page is unaffected by an error.

[0097] In some instances, the buffer management component 730 may determine the size of the buffer that the host device should maintain, at least in part, based on the maximum number of pages whose operations within the first set of pages could be affected by a write error of one page in the first set of pages. In some instances, the buffer management component 730 may instruct the host device on the size of the buffer that the host device should maintain.

[0098] In some instances, the write component 710 may write the first data to a portion of an internal buffer at the memory device before writing the first data to the first page, wherein said portion of the internal buffer at the memory device is configured to buffer data received from the host device, and may write the second data to said portion of the internal buffer at the memory device before attempting to write the second data to the second page within the first set of pages. In some instances, the size of the buffer to be maintained by the host device is at least partially based on the capacity of said portion of the internal buffer.

[0099] In some instances, command component 715 may receive an initialization command for a memory device, wherein the size of the buffer to be maintained by the host device is based on the received initialization command.

[0100] In some instances, the write component 710 may allocate a first page for the first data based on the received initialization command, wherein the first set of pages is empty during the time between allocating the first page and writing the first data to the first page.

[0101] In some cases, the memory device includes NAND memory cells. In some cases, the first set of pages is a first block of NAND memory cells. In some cases, the second set of pages is a second block of NAND memory cells.

[0102] Figure 8 A block diagram 800 illustrates a host device 805 supporting data recovery management for memory according to various aspects of this disclosure. Host device 805 may be an example of, for example, a aspect of host device 305. Host device 805 may include a data transmission component 810, an error indication component 815, a buffer component 820, and an error identification component 825. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0103] The data transfer component 810 can transfer a first data to a memory device. In some instances, the data transfer component 810 can transfer a second data to a memory device. In some instances, transferring the first data to the memory device includes transferring a write command containing the first data, and transferring the second data to the memory device includes transferring a write command containing the second data.

[0104] Error indication component 815 can receive an error indication associated with the second data from the memory device. Buffer component 820 can obtain a copy of the second data and a copy of the first data from a buffer outside the memory device based on the error indication. Data transmission component 810 can transmit a copy of the first data and a copy of the second data to the memory device based on the received error indication.

[0105] The error identification component 825 can receive an indication of address and error size, wherein obtaining a copy of the second data and a copy of the first data is based on the indication of address and error size.

[0106] In some instances, buffer assembly 820 may receive an indication of buffer size from a memory device. In some instances, buffer assembly 820 may configure a buffer to have the indicated size, wherein obtaining a copy of the first data and a copy of the second data is based on configuring the buffer to have the indicated size.

[0107] In some instances, buffer assembly 820 can initialize a memory device, wherein receiving an indication of the buffer size is based on initializing the memory device.

[0108] In some instances, buffer component 820 may write first data into the buffer based on transferring a first data to a memory device. In some instances, buffer component 820 may write second data into the buffer based on transferring a second data to a memory device.

[0109] In some instances, transferring the first data to the memory device includes transferring a write command for the first data, and transferring the second data to the memory device includes transferring a write command for the second data.

[0110] In some cases, the size of the buffer is based on the block size of the memory device, the page size of the memory device, the size of at least a portion of the internal buffers (e.g., RAM buffers) at the memory device, or any combination thereof.

[0111] In some instances, host device 805 may determine the amount of data to be obtained from the buffer based on erroneous indications, wherein obtaining a copy of the first data and a copy of the second data includes obtaining the amount of data from the buffer.

[0112] In some cases, the buffer includes a cyclic buffer (e.g., at the host device).

[0113] Figure 9 The illustration shows a flowchart of a method 900 for data recovery management of a memory, supported by aspects of this disclosure. Operation of method 900 may be implemented by a memory device 100 or its components as described herein. For example, operation of method 900 may be performed by a memory device, as referenced... Figures 2 to 5 As described below. In some instances, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described below. Alternatively, the memory device may use dedicated hardware to perform aspects of the functions described below.

[0114] At 905, the memory device may write first data to a first memory cell page within a first set of memory cell pages at the memory device. The operation at 905 can be performed according to the method described herein. In some instances, aspects of the operation at 905 may be as described in reference... Figure 7 The described write component is executed.

[0115] At 910, the memory device can receive a write command for second data from the host device. The operation of 910 can be performed according to the method described herein. In some instances, aspects of the operation of 910 can be as described in the reference... Figure 7 The described command component is executed.

[0116] At 915, the memory device may attempt to write second data to a second memory cell page within the first set of pages. The operation at 915 can be performed according to the method described herein. In some instances, aspects of the operation at 915 may be as described in the references... Figure 7 The described write component is executed.

[0117] At 920, the memory device can identify an error associated with an attempt to write second data to the second page within the first set of pages. The operation at 920 can be performed according to the method described herein. In some instances, aspects of the operation at 920 may be as described in the references... Figure 7 The described error recognition component is executed.

[0118] At 925, the memory device can indicate an error to the host device. The operation of 925 can be performed according to the method described herein. In some instances, aspects of the operation of 925 can be as described in the reference... Figure 7 The described error indicates that the component is executing.

[0119] At 930, the memory device can receive a copy of the first data and a copy of the second data from the host device after an error is indicated. The operation of 930 can be performed according to the method described herein. In some instances, aspects of the operation of 930 can be derived from, as referenced... Figure 7 The described command component is executed.

[0120] At 935, the memory device may write a copy of the first data to the first memory page within the second set of memory page units at the memory device, and write a copy of the second data to the second memory page within the second set of page units. The operation of 935 can be performed according to the method described herein. In some instances, aspects of the operation of 935 may be as described in the references... Figure 7 The described write component is executed.

[0121] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: writing first data to a first memory cell page within a first set of memory cell pages at a memory device; receiving a write command for second data from a host device; attempting to write the second data to a second memory cell page within the first set of pages; identifying an error associated with the attempt to write the second data to the second page within the first set of pages; indicating the error to the host device; after indicating the error, receiving a copy of the first data and a copy of the second data from the host device; and writing a copy of the first data to a first memory cell page within a second set of memory cell pages at a memory device, and writing a copy of the second data to a second memory cell page within the second set of pages.

[0122] In some instances of method 900 and the devices described herein, indicating an error to the host device may include an address indicating a second page and an error size indicating the number of pages rewritten based on the identified error.

[0123] Method 900 and some instances of the device described herein may further include features, components, and instructions for determining that the first page is affected by an error, and determining the size of the error based at least in part on the determination that the first page is affected by an error.

[0124] Method 900 and some instances of the apparatus described herein may further include operations, features, components, or instructions for: writing third data to a third memory cell page within a first set of memory cell pages after writing the first data and before attempting to write the second data, wherein the page to be rewritten includes the first page, the second page, and the third page; receiving a copy of the third data from the host device after indicating an error; and writing a copy of the third data to a third memory cell page within a second set of pages. In methods 900 and some instances of the apparatus described herein, the third memory cell page is unaffected by errors.

[0125] Method 900 and some instances of the device described herein may further include operations, features, components, or instructions for: determining the size of a buffer to be maintained by the host device based at least in part on the maximum number of pages in the first set of pages whose operations can be affected by a write error of a page in the first set of pages; and instructing the host device on the size of a buffer to be maintained by the host device.

[0126] Method 900 and some instances of the device described herein may further include operations, features, components, or instructions for: writing first data to a portion of an internal buffer at a memory device between writing first data to a first page, wherein the portion of the internal buffer at the memory device is configured to buffer data received from a host device; and writing second data to a portion of an internal buffer at a memory device before attempting to write second data to a second page within a first set of pages, wherein the size of the buffer to be maintained by the host device is at least partially based on the capacity of the portion of the internal buffer.

[0127] Method 900 and some examples of the devices described herein may further include operations, features, components, or instructions for receiving an initialization command for a memory device, wherein the size of a buffer to be maintained by the host device is at least partially based on receiving the initialization command.

[0128] Method 900 and some instances of the device described herein may further include operations, features, components, or instructions for allocating a first page for first data, at least in part based on receiving an initialization command, wherein the first set of pages is empty during the time between allocating the first page and writing the first data to the first page.

[0129] In some instances of method 900 and the device described herein, the memory device includes NAND memory cells, a first set of pages being a first block of NAND memory cells, and a second set of pages being a second block of NAND memory cells.

[0130] Figure 10 The illustration shows a flowchart of a method 1000 for data recovery management of memory, supported by aspects of this disclosure. The operation of method 1000 may be implemented by a host device 305 or components thereof as described herein. In some instances, the host device may execute a set of instructions to control functional elements of the host device to perform the functions described below. Alternatively, the host device may use dedicated hardware to perform aspects of the functions described below.

[0131] At point 1005, the host device can transfer the first data to the memory device. The operation at point 1005 can be performed according to the method described herein. In some instances, aspects of the operation at point 1005 may be as described in the references... Figure 8 The described data transmission component is executed.

[0132] At 1010, the host device can transfer the second data to the memory device. The operation of 1010 can be performed according to the method described herein. In some instances, aspects of the operation of 1010 may be as described in the references... Figure 8 The described data transmission component is executed.

[0133] At point 1015, the host device may receive an indication of an error associated with the second data from the memory device. The operation of point 1015 can be performed according to the method described herein. In some instances, aspects of the operation of point 1015 may be as described in reference... Figure 8 The described error indicates that the component is executing.

[0134] At point 1020, the host device can obtain a copy of the second data and a copy of the first data from a buffer outside the memory device based on an error indication. The operation of point 1020 can be performed according to the method described herein. In some instances, aspects of the operation of point 1020 may be as described in the references... Figure 8 The described buffer component is executed.

[0135] At point 1025, the host device can transfer copies of the first and second data to the memory device based on a received error indication. The operation of point 1025 can be performed according to the method described herein. In some instances, aspects of the operation of point 1025 may be as described in references... Figure 8 The described data transmission component is executed.

[0136] In some instances, the device described herein may perform one or more methods, such as method 1000. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transferring a first data to a memory device; transferring a second data to a memory device; receiving an indication of an error associated with the second data from the memory device; obtaining a copy of the second data and a copy of the first data from a buffer external to the memory device, at least in part based on the error indication; and transferring a copy of the first data and a copy of the second data to the memory device, at least in part based on the received error indication.

[0137] In some instances of method 1000 and the device described herein, the indication of receiving an error includes an indication of the receiving address and the error size, wherein obtaining a copy of the second data and a copy of the first data are based at least in part on the indications of the address and the error size.

[0138] Method 1000 and some instances of the device described herein may further include operations, features, components, or instructions for receiving an indication of a buffer size from a memory device and configuring the buffer to have the indicated size, wherein obtaining a copy of the first data and a copy of the second data is based at least in part on configuring the buffer to have the indicated size.

[0139] Method 1000 and some instances of the device described herein may further include operations, features, components or instructions for initializing a memory device, wherein an indication of the size of a received buffer is based at least in part on initializing the memory device.

[0140] Method 1000 and some instances of the device described herein may further include operations, features, components, or instructions for writing first data to a buffer at least in part based on transferring a first data to a memory device, and writing second data to a buffer at least in part based on transferring a second data to a memory device.

[0141] In some instances of method 1000 and the device described herein, transmitting the first data to the memory device includes transmitting a write command for the first data, and transmitting the second data to the memory device includes transmitting a write command for the second data.

[0142] In some instances of method 1000 and the devices described herein, the size of the buffer is based at least in part on the block size of the memory device, the page size of the memory device, the size of at least a portion of the internal buffer at the memory device, or any combination thereof.

[0143] In some instances of method 1000 and the devices described herein, the buffer is a cyclic buffer (e.g., at the host device).

[0144] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0145] A device is described. The device may include a first set of memory cells, a second set of memory cells, and a controller coupled to the first and second sets of memory cells. The controller is configured to cause the device to: identify an error associated with an attempt to write new data to the first set of memory cells; indicate the error to a host device; receive, at least in part, a copy of the new data and a copy of other data previously written to the first set of memory cells from the host device based on the indicated error; and write the copy of the new data and the copy of the other data to the second set of memory cells.

[0146] In some instances, the controller may further be used to cause the device to perform the following operation: instruct the host device on the size of the buffer that the host device should maintain to support the reception of copies of new data and other data.

[0147] Some instances may further include an internal RAM buffer, wherein the size of the buffer to be maintained by the host device is based at least in part on the maximum number of memory cells that can be affected by write errors associated with the first set of memory cells, the capacity of a portion of the internal RAM buffer, or both.

[0148] Some instances may further include multiple sets of memory cells comprising a first set of memory cells and a second set of memory cells, wherein each of the multiple sets of memory cells includes a block of NAND (e.g., NAND flash) memory cells.

[0149] In some instances, the controller may be further used to enable the device to write new data to a portion of the internal RAM buffer before attempting to write new data to the first set of memory cells.

[0150] In some instances, the controller may further be used to cause the device to: identify an initialization event for the device, wherein the size of the buffer to be maintained by the host device is based at least in part on the identified initialization event.

[0151] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a signal bus, wherein the bus may have various bit widths.

[0152] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" refers to a connection to approximately 0V.

[0153] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be electronically connected (or electrically contacting, connected, or coupled) to each other if there is any conductive path between them that allows the flow of signals at any given time. At any given time, the conductive path between components that are electronically communicating (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0154] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path; in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between other components via conductive paths that were previously not permitted.

[0155] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0156] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0157] The devices containing memory devices discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0158] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0159] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all possible implementations or all instances within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0160] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral.

[0161] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but alternatively, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0162] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. Additionally, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0163] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will become apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: Write the first data into the first memory cell page within the first set of memory cell pages at the memory device; Receive a write command for the second data from the host device; Attempt to write the second data into the second memory cell page within the first group of memory cell pages; An error was identified, the error being associated with an attempt to write the second data into the second memory cell page within the first set of memory cell pages; The error is indicated to the host device; After indicating the error, a copy of the first data and a copy of the second data are received from the host device; and The copy of the first data is written to the first memory cell page within the second group of memory cell pages at the memory device, and the copy of the second data is written to the second memory cell page within the second group of memory cell pages.

2. The method of claim 1, wherein indicating the error to the host device includes indicating the address of the second memory cell page and an error size representing the number of pages rewritten based on the identified error.

3. The method according to claim 2, further comprising: It is determined that the first memory cell page is affected by the error; as well as The size of the error is determined at least in part based on the fact that the first memory cell page is affected by the error.

4. The method of claim 3, further comprising: After writing the first data and before attempting to write the second data, the third data is written to the third memory cell page within the first group of memory cell pages, wherein the pages to be rewritten include the first memory cell page, the second memory cell page, and the third memory cell page; After indicating the error, a copy of the third data is received from the host device; and Write the copy of the third data into the third memory cell page within the second set of memory cell pages.

5. The method of claim 4, wherein the third memory cell page is unaffected by the error.

6. The method of claim 1, further comprising: The size of the buffer that the host device shall maintain is determined at least in part based on the maximum number of operable pages within the first set of memory cell pages that are affected by a write error of one of the pages in the first set of memory cell pages. and Instruct the host device on the size of the buffer that the host device wants to maintain.

7. The method of claim 6, further comprising: Before writing the first data to the first memory cell page, the first data is written to a portion of an internal buffer at the memory device, wherein the portion of the internal buffer at the memory device is configured to buffer data received from the host device; and Before attempting to write the second data to the second memory cell page within the first set of memory cell pages, the second data is written to the portion of the internal buffer at the memory device, wherein... The size of the buffer that the host device is to maintain is at least in part based on the capacity of the portion of the internal buffer.

8. The method of claim 6, further comprising: Receive an initialization command for the memory device, wherein the size of the buffer to be maintained by the host device is at least partially based on receiving the initialization command.

9. The method of claim 8, further comprising: The first memory cell page is allocated to the first data at least in part based on receiving the initialization command, wherein the first set of memory cell pages is empty during the time between allocating the first memory cell page and writing the first data to the first memory cell page.

10. The method according to claim 1, wherein: The memory device includes non-NAND memory cells; The first group of memory cell pages includes a first NAND memory cell block; and The second group of memory cell pages includes a second NAND memory cell block.

11. A method for memory operations, comprising: The first data is transferred to the memory device; The second data is transferred to the memory device; Receive an error indication from the memory device, the error being associated with the second data; At least in part based on the indication of the error, a copy of the second data and a copy of the first data are obtained from a buffer outside the memory device; and The copy of the first data and the copy of the second data are transferred to the memory device, at least in part based on the instruction received regarding the error.

12. The method of claim 11, wherein receiving the indication of the error comprises: The recipient receives an instruction on the address and the error size, wherein the acquisition of the copy of the second data and the copy of the first data is based at least in part on the instruction on the address and the error size.

13. The method of claim 11, further comprising: Receive an indication of the size of the buffer from the memory device; and The buffer is configured to have an indicated size, wherein obtaining the copy of the first data and the copy of the second data is based at least in part on configuring the buffer to have the indicated size.

14. The method of claim 13, further comprising: The memory device is initialized, wherein the indication of the size of the buffer is received is based at least in part on the initialization of the memory device.

15. The method of claim 13, further comprising: The first data is written to the buffer at least in part based on transferring the first data to the memory device; and The second data is written to the buffer at least in part based on transferring the second data to the memory device.

16. The method of claim 13, wherein transmitting the first data to the memory device includes transmitting a write command for the first data, and wherein transmitting the second data to the memory device includes transmitting a write command for the second data.

17. The method of claim 13, wherein: The size of the buffer is based at least in part on the block size of the memory device, the page size of the memory device, the size of at least a portion of the internal buffers in the memory device, or any combination thereof.

18. The method of claim 11, further comprising: The amount of data to be obtained from the buffer is determined at least in part based on the indication of the error, wherein obtaining the copy of the first data and the copy of the second data includes obtaining the amount of data from the buffer.

19. The method of claim 11, wherein the buffer comprises a cyclic buffer.

20. A memory device comprising: First group of memory units The second group of memory units, and A controller, coupled to the first group of memory cells and the second group of memory cells, is configured to cause the memory device to perform the following operations: An error was identified, which was associated with an attempt to write new data to the first set of memory cells; The error is indicated to the host device; At least in part based on the indication of the error, a copy of the new data and a copy of other data previously written to the first set of memory cells are received from the host device; and The copy of the new data and the copies of the other data are written to the second set of memory units.

21. The memory device of claim 20, wherein the controller is further configured to cause the memory device to perform the following operations: The host device is instructed on the size of the buffer it should maintain to support receiving the copy of the new data and the copies of the other data.

22. The memory device of claim 21, further comprising: An internal random access memory (RAM) buffer, wherein the size of the buffer to be maintained by the host device is based at least in part on the maximum number of memory cells that can be affected by write errors associated with the first set of memory cells, the capacity of a portion of the internal RAM buffer, or both.

23. The memory device of claim 22, further comprising: Multiple sets of memory cells, including a first set of memory cells and a second set of memory cells, wherein each set of multiple sets of memory cells includes a block of non-NAND memory cells.

24. The memory device of claim 22, wherein the controller is further configured to cause the memory device to perform the following operations: Before attempting to write the new data to the first set of memory cells, the new data is written to the portion of the internal RAM buffer.

25. The memory device of claim 21, wherein the controller is further configured to cause the memory device to perform the following operations: The initialization event of the memory device is identified, wherein the size of the buffer to be maintained by the host device is based at least in part on the identification of the initialization event.

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